Compensation for horizontal skew between adjacent rows of nozzles on a printhead module

ABSTRACT

A printer controller for supplying dot data to a printhead in a predetermined order, the printhead comprising at least a first printhead module having a plurality of rows of printing nozzles, the printer controller being configured to order and time the supply of the dot data to the first printhead module such that a relative skew between adjacent rows of printing nozzles on the at least one printhead module, in a direction normal to a direction of printing, is at least partially compensated for.

FIELD OF INVENTION

The present invention relates to techniques for compensating forhorizontal displacement between adjacent rows of printhead nozzles thatextend across a printhead.

The invention has primarily been developed for use with a printheadcomprising one or more printhead modules constructed usingmicroelectromechanical systems (MEMS) techniques, and will be describedwith reference to this application. However, it will be appreciated thatthe invention can be applied to other types of printing technologies inwhich analogous problems are faced.

BACKGROUND OF INVENTION

Manufacturing a printhead that has relatively high resolution andprint-speed raises a number of problems.

Difficulties in manufacturing pagewidth printheads of any substantialsize arise due to the relatively small dimensions of standard siliconwafers that are used in printhead (or printhead module) manufacture. Forexample, if it is desired to make an 8 inch wide pagewidth printhead,only one such printhead can be laid out on a standard 8-inch wafer,since such wafers are circular in plan. Manufacturing a pagewidthprinthead from two or more smaller modules can reduce this limitation tosome extent, but raises other problems related to providing a jointbetween adjacent printhead modules that is precise enough to avoidvisible artefacts (which would typically take the form of noticeablelines) when the printhead is used. The problem is exacerbated inrelatively high-resolution applications because of the tight tolerancesdictated by the small spacing between nozzles.

The quality of a joint region between adjacent printhead modules relieson factors including a precision with which the abutting ends of eachmodule can be manufactured, the accuracy with which they can be alignedwhen assembled into a single printhead, and other more practical factorssuch as management of ink channels behind the nozzles. It will beappreciated that the difficulties include relative vertical displacementof the printhead modules with respect to each other.

Whilst some of these issues may be dealt with by careful design andmanufacture, the level of precision required renders it relativelyexpensive to manufacture printheads within the required tolerances. Itwould be desirable to provide a solution to one or more of the problemsassociated with precision manufacture and assembly of multiple printheadmodules to form a printhead, and especially a pagewidth printhead.

In some cases, it is desirable to produce a number of differentprinthead module types or lengths on a substrate to maximise usage ofthe substrate's surface area. However, different sizes and types ofmodules will have different numbers and layouts of print nozzles,potentially including different horizontal and vertical offsets. Wheretwo or more modules are to be joined to form a single printhead, thereis also the problem of dealing with different seam shapes betweenabutting ends of joined modules, which again may incorporate vertical orhorizontal offsets between the modules. Printhead controllers areusually dedicated application specific integrated circuits (ASICs)designed for specific use with a single type of printhead module, thatis used by itself rather than with other modules. It would be desirableto provide a way in which different lengths and types of printheadmodules could be accounted for using a single printer controller.

Printer controllers face other difficulties when two or more printheadmodules are involved, especially if it is desired to send dot data toeach of the printheads directly (rather than via a single printheadconnected to the controller). One concern is that data delivered todifferent length controllers at the same rate will cause the shorter ofthe modules to be ready for printing before any longer modules. Wherethere is little difference involved, the issue may not be of importance,but for large length differences, the result is that the bandwidth of ashared memory from which the dot data is supplied to the modules iseffectively left idle once one of the modules is full and the remainingmodule or modules is still being filled. It would be desirable toprovide a way of improving memory bandwidth usage in a system comprisinga plurality of printhead modules of uneven length.

In any printing system that includes multiple nozzles on a printhead orprinthead module, there is the possibility of one or more of the nozzlesfailing in the field, or being inoperative due to manufacturing defect.Given the relatively large size of a typical printhead module, it wouldbe desirable to provide some form of compensation for one or more “dead”nozzles. Where the printhead also outputs fixative on a per-nozzlebasis, it is also desirable that the fixative is provided in such a waythat dead nozzles are compensated for.

A printer controller can take the form of an integrated circuit,comprising a processor and one or more peripheral hardware units forimplementing specific data manipulation functions. A number of theseunits and the processor may need access to a common resource such asmemory. One way of arbitrating between multiple access requests for acommon resource is timeslot arbitration, in which access to the resourceis guaranteed to a particular requestor during a predetermined timeslot.

One difficulty with this arrangement lies in the fact that not allaccess requests make the same demands on the resource in terms of timingand latency. For example, a memory read requires that data be fetchedfrom memory, which may take a number of cycles, whereas a memory writecan commence immediately. Timeslot arbitration does not take intoaccount these differences, which may result in accesses being performedin a less efficient manner than might otherwise be the case. It would bedesirable to provide a timeslot arbitration scheme that improved thisefficiency as compared with prior art timeslot arbitration schemes.

Also of concern when allocating resources in a timeslot arbitrationscheme is the fact that the priority of an access request may not be thesame for all units. For example, it would be desirable to provide atimeslot arbitration scheme in which one requestor (typically thememory) is granted special priority such that its requests are dealtwith earlier than would be the case in the absence of such priority.

In systems that use a memory and cache, a cache miss (in which anattempt to load data or an instruction from a cache fails) results in amemory access followed by a cache update. It is often desirable whenupdating the cache in this way to update data other than that which wasactually missed. A typical example would be a cache miss for a byteresulting in an entire word or line of the cache associated with thatbyte being updated. However, this can have the effect of tying upbandwidth between the memory (or a memory manager) and the processorwhere the bandwidth is such that several cycles are required to transferthe entire word or line to the cache. It would be desirable to provide amechanism for updating a cache that improved cache update speed and/orefficiency.

Most integrated circuits an externally provided signal as (or togenerate) a clock, often provided from a dedicated clock generationcircuit. This is often due to the difficulties of providing an onboardclock that can operate at a speed that is predictable. Manufacturingtolerances of such on-board clock generation circuitry can result inclock rates that vary by a factor of two, and operating temperatures canincrease this margin by an additional factor of two. In some cases, theparticular rate at which the clock operates is not of particularconcern. However, where the integrated circuit will be writing to aninternal circuit that is sensitive to the time over which a signal isprovided, it may be undesirable to have the signal be applied for toolong or short a time. For example, flash memory is sensitive to beingwritten too for too long a period. It would be desirable to provide amechanism for adjusting a rate of an on-chip system clock to take intoaccount the impact of manufacturing variations on clockspeed.

One form of attacking a secure chip is to induce (usually by increasing)a clock speed that takes the logic outside its rated operatingfrequency. One way of doing this is to reduce the temperature of theintegrated circuit, which can cause the clock to race. Above a certainfrequency, some logic will start malfunctioning. In some cases, themalfunction can be such that information on the chip that wouldotherwise be secure may become available to an external connection. Itwould be desirable to protect an integrated circuit from such attacks.

In an integrated circuit comprising non-volatile memory, a power failurecan result in unintentional behaviour. For example, if an address ordata becomes unreliable due to falling voltage supplied to the circuitbut there is still sufficient power to cause a write, incorrect data canbe written. Even worse, the data (incorrect or not) could be written tothe wrong memory. The problem is exacerbated with multi-word writes. Itwould be desirable to provide a mechanism for reducing or preventingspurious writes when power to an integrated circuit is failing.

In an integrated circuit, it is often desirable to reduce unauthorisedaccess to the contents of memory. This is particularly the case wherethe memory includes a key or some other form of security informationthat allows the integrated circuit to communicate with another entity(such as another integrated circuit, for example) in a secure manner. Itwould be particularly advantageous to prevent attacks involving directprobing of memory addresses by physically investigating the chip (asdistinct from electronic or logical attacks via manipulation of signalsand power supplied to the integrated circuit).

It is also desirable to provide an environment where the manufacturer ofthe integrated circuit (or some other authorised entity) can verify orauthorize code to be run on an integrated circuit.

Another desideratum would be the ability of two or more entities, suchas integrated circuits, to communicate with each other in a securemanner. It would also be desirable to provide a mechanism for securecommunication between a first entity and a second entity, where the twoentities, whilst capable of some form of secure communication, are notable to establish such communication between themselves.

In a system that uses resources (such as a printer, which uses inks) itmay be desirable to monitor and update a record related to resourceusage. Authenticating ink quality can be a major issue, since theattributes of inks used by a given printhead can be quite specific. Useof incorrect ink can result in anything from misfiring or poorperformance to damage or destruction of the printhead. It wouldtherefore be desirable to provide a system that enables authenticationof the correct ink being used, as well as providing various supportsystems secure enabling refilling of ink cartridges.

In a system that prevents unauthorized programs from being loaded ontoor run on an integrated circuit, it can be laborious to allow developersof software to access the circuits during software development. Enablingaccess to integrated circuits of a particular type requiresauthenticating software with a relatively high-level key. Distributingthe key for use by developers is inherently unsafe, since a single leakof the key outside the organization could endanger security of all chipsthat use a related key to authorize programs. Having a small number ofpeople with high-security clearance available to authenticate programsfor testing can be inconvenient, particularly in the case where frequentincremental changes in programs during development require testing. Itwould be desirable to provide a mechanism for allowing access to one ormore integrated circuits without risking the security of otherintegrated circuits in a series of such integrated circuits.

In symmetric key security, a message, denoted by M, is plaintext. Theprocess of transforming M into ciphertext C, where the substance of M ishidden, is called encryption. The process of transforming C back into Mis called decryption. Referring to the encryption function as E, and thedecryption function as D, we have the following identities:E[M]=CD[C]=M

Therefore the following identity is true:D[E[M]]=M

A symmetric encryption algorithm is one where:

-   -   the encryption function E relies on key K₁,    -   the decryption function D relies on key K₂,    -   K₂ can be derived from K₁, and    -   K₁ can be derived from K₂,

In most symmetric algorithms, K₁ equals K₂. However, even if K₁ does notequal K₂, given that one key can be derived from the other, a single keyK can suffice for the mathematical definition. Thus:E_(K)[M]=CD_(K)[C]=M

The security of these algorithms rests very much in the key K. Knowledgeof K allows anyone to encrypt or decrypt. Consequently K must remain asecret for the duration of the value of M. For example, M may be awartime message “My current position is grid position 123-456”. Once thewar is over the value of M is greatly reduced, and if K is made public,the knowledge of the combat unit's position may be of no relevancewhatsoever. The security of the particular symmetric algorithm is afunction of two things: the strength of the algorithm and the length ofthe key.

An asymmetric encryption algorithm is one where:

-   -   the encryption function E relies on key K₁,    -   the decryption function D relies on key K₂,    -   K₂ cannot be derived from K₁ in a reasonable amount of time, and    -   K₁ cannot be derived from K₂ in a reasonable amount of time.

Thus:E_(K1)[M]=CD_(K2)[C]=M

These algorithms are also called public-key because one key K₁ can bemade public. Thus anyone can encrypt a message (using K₁) but only theperson with the corresponding decryption key (K₂) can decrypt and thusread the message.

In most cases, the following identity also holds:E_(K2)[M]=CD_(K1)[C]=M

This identity is very important because it implies that anyone with thepublic key K₁ can see M and know that it came from the owner of K₂.No-one else could have generated C because to do so would implyknowledge of K₂. This gives rise to a different application, unrelatedto encryption - digital signatures.

A number of public key cryptographic algorithms exist. Most areimpractical to implement, and many generate a very large C for a given Mor require enormous keys. Still others, while secure, are far too slowto be practical for several years. Because of this, many public keysystems are hybrid—a public key mechanism is used to transmit asymmetric session key, and then the session key is used for the actualmessages.

All of the algorithms have a problem in terms of key selection. A randomnumber is simply not secure enough. The two large primes p and q must bechosen carefully—there are certain weak combinations that can befactored more easily (some of the weak keys can be tested for). Butnonetheless, key selection is not a simple matter of randomly selecting1024 bits for example. Consequently the key selection process must alsobe secure.

Symmetric and asymmetric schemes both suffer from a difficulty inallowing establishment of multiple relationships between one entity anda two or more others, without the need to provide multiple sets of keys.For example, if a main entity wants to establish secure communicationswith two or more additional entities, it will need to maintain adifferent key for each of the additional entities. For practicalreasons, it is desirable to avoid generating and storing large numbersof keys. To reduce key numbers, two or more of the entities may use thesame key to communicate with the main entity. However, this means thatthe main entity cannot be sure which of the entities it is communicatingwith. Similarly, messages from the main entity to one of the entitiescan be decrypted by any of the other entities with the same key. Itwould be desirable if a mechanism could be provided to allow securecommunication between a main entity and one or more other entities thatovercomes at least some of the shortcomings of prior art.

In a system where a first entity is capable of secure communication ofsome form, it may be desirable to establish a relationship with anotherentity without providing the other entity with any information relatedthe first entity's security features. Typically, the security featuresmight include a key or a cryptographic function. It would be desirableto provide a mechanism for enabling secure communications between afirst and second entity when they do not share the requisite secretfunction, key or other relationship to enable them to establish trust.

A number of other aspects, features, preferences and embodiments aredisclosed in the Detailed Description of the Preferred Embodiment below.

SUMMARY OF INVENTION

In accordance with a first aspect of the invention, there is provided aprinter controller for supplying dot data to a printhead in apredetermined order, the printhead comprising at least a first printheadmodule having a plurality of rows of printing nozzles, the printercontroller being configured to order and time the supply of the dot datato the first printhead module such that a relative skew between adjacentrows of printing nozzles on the at least one printhead module, in adirection normal to a direction of printing, is at least partiallycompensated for.

Preferably, the printer controller is configured to at least partiallycompensate for the relative skew between adjacent rows in each of aplurality of sets of the adjacent rows.

In a preferred embodiment, wherein the relative skew between each of theplurality of the sets of the adjacent rows is the same.

Preferably, the printer controller is configured to compensate for theskew by introducing a relative delay into the dot data destined for atleast one of the rows of printing nozzles. More preferably, theprinthead is configured to print the dots at a predetermined spacingacross its width, and the delay introduced by the printer controllerequates to an integral multiple of the spacing.

It is particularly preferred, that the printhead defines a printableregion between printing boundaries. Nozzles of at least one of the rowsof at least one of the at least one printhead modules are positionedoutside the printable region due to the skew between adjacent rows ofthe nozzles on the at least one printhead module. The printer controlleris configured to introduce a relative delay into the dot data suppliedto at least one of the rows such that the nozzles outside the printableregion do not print.

Preferably, the at least one printhead module includes at least one pairof adjacent rows of the nozzles such that each row of the pair isconfigured to print the same ink. The printhead is configured to providethe dot data to the pair of adjacent rows such that the dot data isshifted serially through the first of the rows then through the secondof the rows, until the dot data has been supplied to all the nozzles.More preferably, the printhead is configured to provide the dot data tothe pair of adjacent rows such that the dot data is shifted seriallythrough the first of the rows in a first direction then looped backthrough the second of the rows in a second direction opposite the first,until the dot data has been supplied to all the nozzles.

Preferably, the printhead is configured to print a series ofprinthead-width rows of the dots, and wherein the first and second rowsare configured to print odd and even dots, respectively, of theprinthead-width rows, the printhead controller being configured tosupply the one or more first rows with odd dot data and the one or moresecond rows with even dot data.

Preferably, the printhead has a plurality of the pairs of rows. Theprinter controller is configured to supply the dot data such that anyrelative skew between the first and second rows of each pair of rows, ina direction normal to a direction of printing, is at least partiallycompensated for.

In one embodiment, each printhead module is configured to print aplurality of independent inks, and the nozzles in each row areconfigured to print in one of the inks. The printhead controller beingconfigured to supply each of the inks to at least one row of at leastone of the printhead modules.

Preferably, at least some of the printhead modules are of mutuallyunequal length, the printer controller being configured to order andtime the supply of the dot data to the compensate for the unequallength.

It is also preferable that the printer controller is configured to atleast partially compensate for any relative skew between adjacent rowsof the nozzles on adjacent ones of the printhead modules.

In a preferred form of the invention, the printer controller isselectively configurable to compensate at least partially for aplurality of potential relative skews.

In one form, the controller is configured to compensate at least partlyfor a fixed amount of the skew.

In accordance with a second aspect, the invention comprises the printerengine comprising a printer controller according to the first aspect anda printhead, wherein the nozzles of the printhead are disposed in aprintable region between printing boundaries of the printhead. Theprinthead includes at least one logical nozzle located outside theprintable zone that can accept data but is not capable of printing. Thelogical nozzles are arranged to introduce a relative delay into the dotdata supplied to at least one of the rows, such that dot data issupplied to the correct nozzles for printing.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred and other embodiments of the invention will now be described,by way of example only, with reference to the accompanying drawings, inwhich:

FIG. 1 is an example of state machine notation

FIG. 2 shows document data flow in a printer

FIG. 3 is an example of a single printer controller (hereinafter“SoPEC”) A4 simplex printer system

FIG. 4 is an example of a dual SoPEC A4 duplex printer system

FIG. 5 is an example of a dual SoPEC A3 simplex printer system

FIG. 6 is an example of a quad SoPEC A3 duplex printer system

FIG. 7 is an example of a SoPEC A4 simplex printing system with an extraSoPEC used as DRAM storage

FIG. 8 is an example of an A3 duplex printing system featuring fourprinting SoPECs

FIG. 9 shows pages containing different numbers of bands

FIG. 10 shows the contents of a page band

FIG. 11 illustrates a page data path from host to SoPEC

FIG. 12 shows a page structure

FIG. 13 shows a SoPEC system top level partition

FIG. 14 shows a SoPEC CPU memory map (not to scale)

FIG. 15 is a block diagram of CPU

FIG. 16 shows CPU bus transactions

FIG. 17 shows a state machine for a CPU subsystem slave

FIG. 18 shows a SoPEC CPU memory map (not to scale)

FIG. 19 shows an external signal view of a memory management unit(hereinafter “MMU”) sub-block partition

FIG. 20 shows an internal signal view of an MMU sub-block partition

FIG. 21 shows a DRAM write buffer

FIG. 22 shows DIU waveforms for multiple transactions

FIG. 23 shows a SoPEC LEON CPU core

FIG. 24 shows a cache data RAM wrapper

FIG. 25 shows a realtime debug unit block diagram

FIG. 26 shows interrupt acknowledge cycles for single and pendinginterrupts

FIG. 27 shows an A3 duplex system featuring four printing SoPECs with asingle SoPEC DRAM device

FIG. 28 is an SCB block diagram

FIG. 29 is a logical view of the SCB of FIG. 28

FIG. 30 shows an ISI configuration with four SoPEC devices

FIG. 31 shows half-duplex interleaved transmission from ISIMaster toISISlave

FIG. 32 shows ISI transactions

FIG. 33 shows an ISI long packet

FIG. 34 shows an ISI ping packet

FIG. 35 shows a short ISI packet

FIG. 36 shows successful transmission of two long packets with sequencebit toggling

FIG. 37 shows sequence bit operation with errored long packet

FIG. 38 shows sequence bit operation with ACK error

FIG. 39 shows an ISI sub-block partition

FIG. 40 shows an ISI serial interface engine functional block diagram

FIG. 41 is an SIE edge detection and data 10 diagram

FIG. 42 is an SIE Rx/Tx state machine Tx cycle state diagram

FIG. 43 shows an SIE Rx/Tx state machine Tx bit stuff ‘0’ cycle statediagram

FIG. 44 shows an SIE Rx/Tx state machine Tx bit stuff ‘1’ cycle statediagram

FIG. 45 shows an SIE Rx/Tx state machine Rx cycle state diagram

FIG. 46 shows an SIE Tx functional timing example

FIG. 47 shows an SIE Rx functional timing example

FIG. 48 shows an SIE Rx/Tx FIFO block diagram

FIG. 49 shows SIE Rx/Tx FIFO control signal gating

FIG. 50 shows an SIE bit stuffing state machine Tx cycle state diagram

FIG. 51 shows an SIE bit stripping state machine Rx cycle state diagram

FIG. 52 shows a CRC16 generation/checking shift register

FIG. 53 shows circular buffer operation

FIG. 54 shows duty cycle select

FIG. 55 shows a GPIO partition

FIG. 56 shows a motor control RTL diagram

FIG. 57 is an input de-glitch RTL diagram

FIG. 58 is a frequency analyser RTL diagram

FIG. 59 shows a brushless DC controller

FIG. 60 shows a period measure unit

FIG. 61 shows line synch generation logic

FIG. 62 shows an ICU partition

FIG. 63 is an interrupt clear state diagram

FIG. 64 is a watchdog timer RTL diagram

FIG. 65 is a generic timer RTL diagram

FIG. 67 is a Pulse generator RTL diagram

FIG. 68 shows a SoPEC clock relationship

FIG. 69 shows a CPR block partition

FIG. 70 shows reset deglitch logic

FIG. 71 shows reset synchronizer logic

FIG. 72 is a clock gate logic diagram

FIG. 73 shows a PLL and Clock divider logic

FIG. 74 shows a PLL control state machine diagram

FIG. 75 shows a LSS master system-level interface

FIG. 76 shows STAR_(T) and STOP conditions

FIG. 77 shows an LSS transfer of 2 data bytes

FIG. 78 is an example of an LSS write to a QA Chip

FIG. 79 is an example of an LSS read from QA Chip

FIG. 80 shows an LSS block diagram

FIG. 81 shows an LSS multi-command transaction

FIG. 82 shows start and stop generation based on previous bus state

FIG. 83 shows an LSS master state machine

FIG. 84 shows LSS master timing

FIG. 85 shows a SoPEC system top level partition

FIG. 86 shows an ead bus with 3 cycle random DRAM read accesses

FIG. 87 shows interleaving of CPU and non-CPU read accesses

FIG. 88 shows interleaving of read and write accesses with 3 cyclerandom DRAM accesses

FIG. 89 shows interleaving of write accesses with 3 cycle random DRAMaccesses

FIG. 90 shows a read protocol for a SoPEC Unit making a single 256-bitaccess

FIG. 91 shows a read protocol for a SoPEC Unit making a single 256-bitaccess

FIG. 92 shows a write protocol for a SoPEC Unit making a single 256-bitaccess

FIG. 93 shows a protocol for a posted, masked, 128-bit write by the CPU

FIG. 94 shows a write protocol shown for CDU making four contiguous64-bit accesses

FIG. 95 shows timeslot-based arbitration

FIG. 96 shows timeslot-based arbitration with separate pointers

FIG. 97 shows a first example (a) of separate read and write arbitration

FIG. 98 shows a second example (b) of separate read and writearbitration

FIG. 99 shows a third example (c) of separate read and write arbitration

FIG. 100 shows a DIU partition

FIG. 101 shows a DIU partition

FIG. 102 shows multiplexing and address translation logic for two memoryinstances

FIG. 103 shows a timing of dau_dcu_valID, dcu_dau_adv and dcu_dau_wadv

FIG. 104 shows a DCU state machine

FIG. 105 shows random read timing

FIG. 106 shows random write timing

FIG. 107 shows refresh timing

FIG. 108 shows page mode write timing

FIG. 109 shows timing of non-CPU DIU read access

FIG. 110 shows timing of CPU DIU read access

FIG. 111 shows a CPU DIU read access

FIG. 112 shows timing of CPU DIU write access

FIG. 113 shows timing of a non-CDU/non-CPU DIU write access

FIG. 114 shows timing of CDU DIU write access

FIG. 115 shows command multiplexor sub-block partition

FIG. 116 shows command multiplexor timing at DIU requesters interface

FIG. 117 shows generation of re_arbitrate and re_arbitrate_wadv

FIG. 118 shows CPU interface and arbitration logic

FIG. 119 shows arbitration timing

FIG. 120 shows setting RotationSync to enable a new rotation.

FIG. 121 shows a timeslot based arbitration

FIG. 122 shows a timeslot based arbitration with separate pointers

FIG. 123 shows a CPU pre-access write lookahead pointer

FIG. 124 shows arbitration hierarchy

FIG. 125 shows hierarchical round-robin priority comparison

FIG. 126 shows a read multiplexor partition

FIG. 127 shows a read command queue (4 deep buffer)

FIG. 128 shows state-machines for shared read bus accesses

FIG. 129 shows a write multiplexor partition

FIG. 130 shows a read multiplexer timing for back-to-back shared readbus transfer

FIG. 131 shows a write multiplexer partition

FIG. 132 shows a block diagram of a PCU

FIG. 133 shows PCU accesses to PEP registers

FIG. 134 shows command arbitration and execution

FIG. 135 shows DRAM command access state machine

FIG. 136 shows an outline of contone data flow with respect to CDU

FIG. 137 shows a DRAM storage arrangement for a single line of JPEG 8×8blocks in 4 colors

FIG. 138 shows a read control unit state machine

FIG. 139 shows a memory arrangement of JPEG blocks

FIG. 140 shows a contone data write state machine

FIG. 141 shows lead-in and lead-out clipping of contone data inmulti-SoPEC environment

FIG. 142 shows a block diagram of CFU

FIG. 143 shows a DRAM storage arrangement for a single line of JPEGblocks in 4 colors

FIG. 144 shows a block diagram of color space converter

FIG. 145 shows a converter/invertor

FIG. 146 shows a high-level block diagram of LBD in context

FIG. 147 shows a schematic outline of the LBD and the SFU

FIG. 148 shows a block diagram of lossless bi-level decoder

FIG. 149 shows a stream decoder block diagram

FIG. 150 shows a command controller block diagram

FIG. 151 shows a state diagram for command controller (CC) state machine

FIG. 152 shows a next edge unit block diagram

FIG. 153 shows a next edge unit buffer diagram

FIG. 154 shows a next edge unit edge detect diagram

FIG. 155 shows a state diagram for the next edge unit state machine

FIG. 156 shows a line fill unit block diagram

FIG. 157 shows a state diagram for the Line Fill Unit (LFU) statemachine

FIG. 158 shows a bi-level DRAM buffer

FIG. 159 shows interfaces between LBD/SFU/HCU

FIG. 160 shows an SFU sub-block partition

FIG. 161 shows an LBDPrevLineFifo sub-block

FIG. 162 shows timing of signals on the LBDPrevLineFIFO interface to DIUand address generator

FIG. 163 shows timing of signals on LBDPrevLineFIFO interface to DIU andaddress generator

FIG. 164 shows LBDNextLineFifo sub-block

FIG. 165 shows timing of signals on LBDNextLineFIFO interface to DIU andaddress generator

FIG. 166 shows LBDNextLineFIFO DIU interface state diagram

FIG. 167 shows an LDB to SFU write interface

FIG. 168 shows an LDB to SFU read interface (within a line)

FIG. 169 shows an HCUReadLineFifo Sub-block

FIG. 170 shows a DIU write Interface

FIG. 171 shows a DIU Read Interface multiplexing by select_hrfplf

FIG. 172 shows DIU read request arbitration logic

FIG. 173 shows address generation

FIG. 174 shows an X scaling control unit

FIG. 175 Y shows a scaling control unit

FIG. 176 shows an overview of X and Y scaling at HCU interface

FIG. 177 shows a high level block diagram of TE in context

FIG. 178 shows a QR Code

FIG. 179 shows Netpage tag structure

FIG. 180 shows a Netpage tag with data rendered at 1600 dpi (magnifiedview)

FIG. 181 shows an example of 2×2 dots for each block of QR code

FIG. 182 shows placement of tags for portrait & landscape printing

FIG. 183 shows agGeneral representation of tag placement

FIG. 184 shows composition of SoPEC's tag format structure

FIG. 185 shows a simple 3×3 tag structure

FIG. 186 shows 3×3 tag redesigned for 21×21 area (not simplereplication)

FIG. 187 shows a TE Block Diagram

FIG. 188 shows a TE Hierarchy

FIG. 189 shows a block diagram of PCU accesses

FIG. 190 shows a tag encoder top-level FSM

FIG. 191 shows generated control signals

FIG. 192 shows logic to combine dot information and encoded data

FIG. 193 shows generation of Lastdotintag/1

FIG. 194 shows generation of Dot Position Valid

FIG. 195 shows generation of write enable to the TFU

FIG. 196 shows generation of Tag Dot Number

FIG. 197 shows TDI Architecture

FIG. 198 shows data flow through the TDI

FIG. 199 shows raw tag data interface block diagram

FIG. 200 shows an RTDI State Flow Diagram

FIG. 201 shows a relationship between TE_endoftagdata,cdu_startofbandstore and cdu_endofbandstore

FIG. 202 shows a TDi State Flow Diagram

FIG. 203 shows mapping of the tag data to codewords 0-7

FIG. 204 shows coding and mapping of uncoded fixed tag data for (15,5)RS encoder

FIG. 205 shows mapping of pre-coded fixed tag data

FIG. 206 shows coding and mapping of variable tag data for (15,7) RSencoder

FIG. 207 shows coding and mapping of uncoded fixed tag data for (15,7)RS encoder

FIG. 208 shows mapping of 2D decoded variable tag data

FIG. 209 shows a simple block diagram for an m=4 Reed Solomon encoder

FIG. 210 shows an RS encoder I/O diagram

FIG. 211 shows a (15,5) & (15,7) RS encoder block diagram

FIG. 212 shows a (15,5) RS encoder timing diagram

FIG. 213 shows a (15,7) RS encoder timing diagram

FIG. 214 shows a circuit for multiplying by alpha³

FIG. 215 shows adding two field elements

FIG. 216 shows an RS encoder implementation

FIG. 217 shows an encoded tag data interface

FIG. 218 shows an encoded fixed tag data interface

FIG. 219 shows an encoded variable tag data interface

FIG. 220 shows an encoded variable tag data sub-buffer

FIG. 221 shows a breakdown of the tag format structure

FIG. 222 shows a TFSI FSM state flow diagram

FIG. 223 shows a TFS block diagram

FIG. 224 shows a table A interface block diagram

FIG. 225 shows a table A address generator

FIG. 226 shows a table C interface block diagram

FIG. 227 shows a table B interface block diagram

FIG. 228 shows interfaces between TE, TFU and HCU

FIG. 229 shows a 16-byte FIFO in TFU

FIG. 230 shows a high level block diagram showing the HCU and itsexternal interfaces

FIG. 231 shows a block diagram of the HCU

FIG. 232 shows a block diagram of the control unit

FIG. 233 shows a block diagram of determine advdot unit

FIG. 234 shows a page structure

FIG. 235 shows a block diagram of a margin unit

FIG. 236 shows a block diagram of a dither matrix table interface

FIG. 237 shows an example of reading lines of dither matrix from DRAM

FIG. 238 shows a state machine to read dither matrix table

FIG. 239 shows a contone dotgen unit

FIG. 240 shows a block diagram of dot reorg unit

FIG. 241 shows an HCU to DNC interface (also used in DNC to DWU, LLU toPHI)

FIG. 242 shows SFU to HCU interface (all feeders to HCU)

FIG. 243 shows representative logic of the SFU to HCU interface

FIG. 244 shows a high-level block diagram of DNC

FIG. 245 shows a dead nozzle table format

FIG. 246 shows set of dots operated on for error diffusion

FIG. 247 shows a block diagram of DNC

FIG. 248 shows a sub-block diagram of ink replacement unit

FIG. 249 shows a dead nozzle table state machine

FIG. 250 shows logic for dead nozzle removal and ink replacement

FIG. 251 shows a sub-block diagram of error diffusion unit

FIG. 252 shows a maximum length 32-bit LFSR used for random bitgeneration

FIG. 253 shows a high-level data flow diagram of DWU in context

FIG. 254 shows a printhead nozzle layout for 36-nozzle bi-lithicprinthead

FIG. 255 shows a printhead nozzle layout for a 36-nozzle bi-lithicprinthead

FIG. 256 shows a dot line store logical representation

FIG. 257 shows a conceptual view of printhead row alignment

FIG. 258 shows a conceptual view of printhead rows (as seen by the LLUand PHI)

FIG. 259 shows a comparison of 1.5×v 2× buffering

FIG. 260 shows an even dot order in DRAM (increasing sense, 13320 dotwide line)

FIG. 261 shows an even dot order in DRAM (decreasing sense, 13320 dotwide line)

FIG. 262 shows a dotline FIFO data structure in DRAM

FIG. 263 shows a DWU partition

FIG. 264 shows a buffer address generator sub-block

FIG. 265 shows a DIU Interface sub-block

FIG. 266 shows an interface controller state diagram

FIG. 267 shows a high level data flow diagram of LLU in context

FIG. 268 shows paper and printhead nozzles relationship (example withD₁=D₂=5)

FIG. 269 shows printhead structure and dot generate order

FIG. 270 shows an order of dot data generation and transmission

FIG. 271 shows a conceptual view of printhead rows

FIG. 272 shows a dotline FIFO data structure in DRAM (LLU specification)

FIG. 273 shows an LLU partition

FIG. 274 shows a dot generator RTL diagram

FIG. 275 shows a DIU interface

FIG. 276 shows an interface controller state diagram

FIG. 277 shows high-level data flow diagram of PHI in context

FIG. 278 is intentionally omitted

FIG. 279 shows printhead data rate equalization

FIG. 280 shows a printhead structure and dot generate order

FIG. 281 shows an order of dot data generation and transmission

FIG. 282 shows an order of dot data generation and transmission (singleprinthead case)

FIG. 283 shows printhead interface timing parameters

FIG. 284 shows printhead timing with margining

FIG. 285 shows a PHI block partition

FIG. 286 shows a sync generator state diagram

FIG. 287 shows a line sync de-glitch RTL diagram

FIG. 288 shows a fire generator state diagram

FIG. 289 shows a PHI controller state machine

FIG. 290 shows a datapath unit partition

FIG. 291 shows a dot order controller state diagram

FIG. 292 shows a data generator state diagram

FIG. 293 shows data serializer timing

FIG. 294 shows a data serializer RTL Diagram

FIG. 295 shows printhead types 0 to 7

FIG. 296 shows an ideal join between two dilithic printhead segments

FIG. 297 shows an example of a join between two bilithic printheadsegments

FIG. 298 shows printable vs non-printable area under new definition(looking at colors as if 1 row only)

FIG. 299 shows identification of printhead nozzles and shift-registersequences for printheads in arrangement 1

FIG. 300 shows demultiplexing of data within the printheads inarrangement 1

FIG. 301 shows double data rate signalling for a type 0 printhead inarrangement 1

FIG. 302 shows double data rate signalling for a type 1 printhead inarrangement 1

FIG. 303 shows identification of printheads nozzles and shift-registersequences for printheads in arrangement 2

FIG. 304 shows demultiplexing of data within the printheads inarrangement 2

FIG. 305 shows double data rate signalling for a type 0 printhead inarrangement 2

FIG. 306 shows double data rate signalling for a type 1 printhead inarrangement 2

FIG. 307 shows all 8 printhead arrangements

FIG. 308 shows a printhead structure

FIG. 309 shows a column Structure

FIG. 310 shows a printhead dot shift register dot mapping to page

FIG. 311 shows data timing during printing

FIG. 312 shows print quality

FIG. 313 shows fire and select shift register setup for printing

FIG. 314 shows a fire pattern across butt end of printhead chips

FIG. 315 shows fire pattern generation

FIG. 316 shows determination of select shift register value

FIG. 317 shows timing for printing signals

FIG. 318 shows initialisation of printheads

FIG. 319 shows a nozzle test latching circuit

FIG. 320 shows nozzle testing

FIG. 321 shows a temperature reading

FIG. 322 shows CMOS testing

FIG. 323 shows a reticle layout

FIG. 324 shows a stepper pattern on Wafer

FIG. 325 shows relationship between datasets

FIG. 326 shows a validation hierarchy

FIG. 327 shows development of operating system code

FIG. 328 shows protocol for directly verifying reads from ChipR

FIG. 329 shows a protocol for signature translation protocol

FIG. 330 shows a protocol for a direct authenticated write

FIG. 331 shows an alternative protocol for a direct authenticated write

FIG. 332 shows a protocol for basic update of permissions

FIG. 333 shows a protocol for a multiple-key update

FIG. 334 shows a protocol for a single-key authenticated read

FIG. 335 shows a protocol for a single-key authenticated write

FIG. 336 shows a protocol for a single-key update of permissions

FIG. 337 shows a protocol for a single-key update

FIG. 338 shows a protocol for a multiple-key single-M authenticated read

FIG. 339 shows a protocol for a multiple-key authenticated write

FIG. 340 shows a protocol for a multiple-key update of permissions

FIG. 341 shows a protocol for a multiple-key update

FIG. 342 shows a protocol for a multiple-key multiple-M authenticatedread

FIG. 343 shows a protocol for a multiple-key authenticated write

FIG. 344 shows a protocol for a multiple-key update of permissions

FIG. 345 shows a protocol for a multiple-key update

FIG. 346 shows relationship of permissions bits to M[n] access bits

FIG. 347 shows 160-bit maximal period LFSR

FIG. 348 shows clock filter

FIG. 349 shows tamper detection line

FIG. 350 shows an oversize nMOS transistor layout of Tamper DetectionLine

FIG. 351 shows a Tamper Detection Line

FIG. 352 shows how Tamper Detection Lines cover the Noise Generator

FIG. 353 shows a prior art FET Implementation of CMOS inverter

FIG. 354 shows non-flashing CMOS

FIG. 355 shows components of a printer-based refill device

FIG. 356 shows refilling of printers by printer-based refill device

FIG. 357 shows components of a home refill station

FIG. 358 shows a three-ink reservoir unit

FIG. 359 shows refill of ink cartridges in a home refill station

FIG. 360 shows components of a commercial refill station

FIG. 361 shows an ink reservoir unit

FIG. 362 shows refill of ink cartridges in a commercial refill station(showing a single refill unit)

FIG. 363 shows equivalent signature generation

FIG. 364 shows a basic field definition

FIG. 365 shows an example of defining field sizes and positions

FIG. 366 shows permissions

FIG. 367 shows a first example of permissions for a field

FIG. 368 shows a second example of permissions for a field

FIG. 369 shows field attributes

FIG. 370 shows an output signature generation data format for Read

FIG. 371 shows an input signature verification data format for Test

FIG. 372 shows an output signature generation data format for Translate

FIG. 373 shows an input signature verification data format for WriteAuth

FIG. 374 shows input signature data format for ReplaceKey

FIG. 375 shows a key replacement map

FIG. 376 shows a key replacement map after K₁ is replaced

FIG. 377 shows a key replacement process

FIG. 378 shows an output signature data format for GetProgramKey

FIG. 379 shows transfer and rollback process

FIG. 380 shows an upgrade flow

FIG. 381 shows authorised ink refill paths in the printing system

FIG. 382 shows an input signature verification data format forXferAmount

FIG. 383 shows a transfer and rollback process

FIG. 384 shows an upgrade flow

FIG. 385 shows authorised upgrade paths in the printing system

FIG. 386 shows a direct signature validation sequence

FIG. 387 shows signature validation using translation

FIG. 388 shows setup of preauth field attributes

FIG. 388A shows setup for multiple preauth fields

FIG. 389 shows a high level block diagram of QA Chip

FIG. 390 shows an analogue unit

FIG. 391 shows a serial bus protocol for trimming

FIG. 392 shows a block diagram of a trim unit

FIG. 393 shows a block diagram of a CPU of the QA chip

FIG. 394 shows block diagram of an MIU

FIG. 395 shows a block diagram of memory components

FIG. 396 shows a first byte sent to an IOU

FIG. 397 shows a block diagram of the IOU

FIG. 398 shows a relationship between external SDa and SClk andgeneration of internal signals

FIG. 399 shows block diagram of ALU

FIG. 400 shows a block diagram of DataSel

FIG. 401 shows a block diagram of ROR

FIG. 402 shows a block diagram of the ALU's IO block

FIG. 403 shows a block diagram of PCU

FIG. 404 shows a block diagram of an Address Generator Unit

FIG. 405 shows a block diagram for a Counter Unit

FIG. 406 shows a block diagram of PMU

FIG. 407 shows a state machine for PMU

FIG. 408 shows a block diagram of MRU

FIG. 409 shows simplified MAU state machine

FIG. 410 shows power-on reset behaviour

FIG. 411 shows a ring oscillator block diagram

FIG. 412 shows a system clock duty cycle

FIG. 413 shows power-on reset

DETAILED DESCRIPTION OF PREFERRED AND OTHER EMBODIMENTS

It will be appreciated that the detailed description that follows takesthe form of a highly detailed design of the invention, includingsupporting hardware and software. A high level of detailed disclosure isprovided to ensure that one skilled in the art will have ample guidancefor implementing the invention.

Imperative phrases such as “must”, “requires”, “necessary” and“important” (and similar language) should be read as being indicative ofbeing necessary only for the preferred embodiment actually beingdescribed. As such, unless the opposite is clear from the context,imperative wording should not be interpreted as such. Nothing in thedetailed description is to be understood as limiting the scope of theinvention, which is intended to be defined as widely as is defined inthe accompanying claims.

Indications of expected rates, frequencies, costs, and otherquantitative values are exemplary and estimated only, and are made ingood faith. Nothing in this specification should be read as implyingthat a particular commercial embodiment is or will be capable of aparticular performance level in any measurable area.

It will be appreciated that the principles, methods and hardwaredescribed throughout this document can be applied to other fields. Muchof the security-related disclosure, for example, can be applied to manyother fields that require secure communications between entities, andcertainly has application far beyond the field of printers.

System Overview

The preferred of the present invention is implemented in a printer usingmicroelectromechanical systems (MEMS) printheads. The printer canreceive data from, for example, a personal computer such as an IBMcompatible PC or Apple computer. In other embodiments, the printer canreceive data directly from, for example, a digital still or videocamera. The particular choice of communication link is not important,and can be based, for example, on USB, Firewire, Bluetooth or any otherwireless or hardwired communications protocol.

Print System Overview

3 Introduction

This document describes the SoPEC (Small office home office Print EngineController) ASIC (Application Specific Integrated Circuit) suitable foruse in, for example, SoHo printer products. The SoPEC ASIC is intendedto be a low cost solution for bi-lithic printhead control, replacing themultichip solutions in larger more professional systems with a singlechIP. The increased cost competitiveness is achieved by integratingseveral systems such as a modified PEC1 printing pipeline, CPU controlsystem, peripherals and memory sub-system onto one SoC ASIC, reducingcomponent count and simplifying board design.

This section will give a general introduction to Memjet printingsystems, introduce the components that make a bi-lithic printheadsystem, describe possible system architectures and show how severalSoPECs can be used to achieve A3 and A4 duplex printing. The section“SoPEC ASIC” describes the SoC SoPEC ASIC, with subsections describingthe CPU, DRAM and Print Engine Pipeline subsystems. Each section gives adetailed description of the blocks used and their operation within theoverall print system. The final section describes the bi-lithicprinthead construction and associated implications to the system due toits makeup.

4 Nomenclature

4.1 Bi-Lithic Printhead Notation

A bi-lithic based printhead is constructed from 2 printhead ICs ofvarying sizes. The notation M:N is used to express the size relationshipof each IC, where M specifies one printhead IC in inches and N specifiesthe remaining printhead IC in inches.

The ‘SoPEC/MoPEC Bilithic Printhead Reference’ document [10] contains adescription of the bilithic printhead and related terminology.

4.2 Definitions

The following terms are used throughout this specification:

-   Bi-lithic printhead Refers to printhead constructed from 2 printhead    ICs-   CPU Refers to CPU core, caching system and MMU.-   ISI-Bridge chip A device with a high speed interface (such as    USB2.0, Ethernet or IEEE1394) and one or more ISI interfaces. The    ISI-Bridge would be the ISIMaster for each of the ISI buses it    interfaces to.-   ISIMaster The ISIMaster is the only device allowed to initiate    communication on the Inter Sopec Interface (ISI) bus. The ISIMaster    interfaces with the host.-   ISISlave Multi-SoPEC systems will contain one or more ISISlave    SoPECs connected to the ISI bus. ISISlaves can only respond to    communication initiated by the ISIMaster.-   LEON Refers to the LEON CPU core.-   LineSyncMaster The LineSyncMaster device generates the line    synchronisation pulse that all SoPECs in the system must synchronise    their line outputs to.-   Multi-SoPEC Refers to SoPEC based print system with multiple SoPEC    devices-   Netpage Refers to page printed with tags (normally in infrared ink).-   PEC1 Refers to Print Engine Controller version 1, precursor to SoPEC    used to control printheads constructed from multiple angled    printhead segments.-   Printhead IC Single MEMS IC used to construct bi-lithic printhead-   PrintMaster The PrintMaster device is responsible for coordinating    all aspects of the print operation. There may only be one    PrintMaster in a system.-   QA Chip Quality Assurance Chip-   Storage SoPEC An ISISlave SoPEC used as a DRAM store and which does    not print.-   Tag Refers to pattern which encodes information about its position    and orientation which allow it to be optically located and its data    contents read.    4.3 Acronym and Abbreviations

The following acronyms and abbreviations are used in this specification

-   CFU Contone FIFO Unit-   CPU Central Processing Unit-   DIU DRAM Interface Unit-   DNC Dead Nozzle Compensator-   DRAM Dynamic Random Access Memory-   DWU DotLine Writer Unit-   GPIO General Purpose Input Output-   HCU Halftoner Compositor Unit-   ICU Interrupt Controller Unit-   ISI Inter SoPEC Interface-   LDB Lossless Bi-level Decoder-   LLU Line Loader Unit-   LSS Low Speed Serial interface-   MEMS Micro Electro Mechanical System-   MMU Memory Management Unit-   PCU SoPEC Controller Unit-   PHI PrintHead Interface-   PSS Power Save Storage Unit-   RDU Real-time Debug Unit-   ROM Read Only Memory-   SCB Serial Communication Block-   SFU Spot FIFO Unit-   SMG4 Silverbrook Modified Group 4.-   SoPEC Small office home office Print Engine-   Controller-   SRAM Static Random Access Memory-   TE Tag Encoder-   TFU Tag FIFO Unit-   TIM Timers Unit-   USB Universal Serial Bus    4.4 Pseudocode Notation

In general the pseudocode examples use C like statements with someexceptions. Symbol and naming convections used for pseudocode. //Comment = Assignment ==, !=, <, > Operator equal, not equal, less than,greater than +, −, *, /, % Operator addition, subtraction, multiply,divide, modulus &, |, {circumflex over ( )}, <<, >>, ˜ Bitwise AND,bitwise OR, bitwise exclusive OR, left shift, right shift, complementAND, OR, NOT Logical AND, Logical OR, Logical inversion [XX:YY]Array/vector specifier {a, b, c} Concatenation operation ++, −−Increment and decrement4.4.1 Register and Signal Naming Conventions

In general register naming uses the C style conventions withcapitalization to denote word delimiters. Signals use RTL style notationwhere underscore denote word delimiters. There is a direct translationbetween both convention. For example the CmdSourceFifo register isequivalent to cmd_source_fifo signal.

4.5 State Machine Notation

State machines should be described using the pseudocode notationoutlined above. State machine descriptions use the convention ofunderline to indicate the cause of a transition from one state toanother and plain text (no underline) to indicate the effect of thetransition i.e. signal transitions which occur when the new state isentered.

A sample state machine is shown in FIG. 1.

5 Printing Considerations

A bi-lithic printhead produces 1600 dpi bi-level dots. On low-diffusionpaper, each ejected drop forms a 22.5 μm diameter dot. Dots are easilyproduced in isolation, allowing dispersed-dot dithering to be exploitedto its fullest. Since the bi-lithic printhead is the width of the pageand operates with a constant paper velocity, color planes are printed inperfect registration, allowing ideal dot-on-dot printing. Dot-on-dotprinting minimizes ‘muddying’ of midtones caused by inter-color bleed. Apage layout may contain a mixture of images, graphics and text.Continuous-tone (contone) images and graphics are reproduced using astochastic dispersed-dot dither. Unlike a clustered-dot (oramplitude-modulated) dither, a dispersed-dot (or frequency-modulated)dither reproduces high spatial frequencies (i.e. image detail) almost tothe limits of the dot resolution, while simultaneously reproducing lowerspatial frequencies to their full color depth, when spatially integratedby the eye. A stochastic dither matrix is carefully designed to be freeof objectionable low-frequency patterns when tiled across the image. Assuch its size typically exceeds the minimum size required to support aparticular number of intensity levels (e.g. 16×16×8 bits for 257intensity levels).

Human contrast sensitivity peaks at a spatial frequency of about 3cycles per degree of visual field and then falls off logarithmically,decreasing by a factor of 100 beyond about 40 cycles per degree andbecoming immeasurable beyond 60 cycles per degree [25][25]. At a normalviewing distance of 12 inches (about 300 mm), this translates roughly to200-300 cycles per inch (cpi) on the printed page, or 400-600 samplesper inch according to Nyquist's theorem.

In practice, contone resolution above about 300 ppi is of limitedutility outside special applications such as medical imaging. Offsetprinting of magazines, for example, uses contone resolutions in therange 150 to 300 ppi. Higher resolutions contribute slightly to colorerror through the dither.

Black text and graphics are reproduced directly using bi-level blackdots, and are therefore not anti-aliased (i.e. low-pass filtered) beforebeing printed. Text should therefore be supersampled beyond theperceptual limits discussed above, to produce smoother edges whenspatially integrated by the eye. Text resolution up to about 1200 dpicontinues to contribute to perceived text sharpness (assuminglow-diffusion paper, of course).

A Netpage printer, for example, may use a contone resolution of 267 ppi(i.e. 1600 dpi/6), and a black text and graphics resolution of 800 dpi.A high end office or departmental printer may use a contone resolutionof 320 ppi (1600 dpi/5) and a black text and graphics resolution of 1600dpi. Both formats are capable of exceeding the quality of commercial(offset) printing and photographic reproduction.

6 Document Data Flow

6.1 Considerations

Because of the page-width nature of the bi-lithic printhead, each pagemust be printed at a constant speed to avoid creating visible artifacts.This means that the printing speed can't be varied to match the inputdata rate. Document rasterization and document printing are thereforedecoupled to ensure the printhead has a constant supply of data. A pageis never printed until it is fully rasterized. This can be achieved bystoring a compressed version of each rasterized page image in memory.This decoupling also allows the RIP(s) to run ahead of the printer whenrasterizing simple pages, buying time to rasterize more complex pages.

Because contone color images are reproduced by stochastic dithering, butblack text and line graphics are reproduced directly using dots, thecompressed page image format contains a separate foreground bi-levelblack layer and background contone color layer. The black layer iscomposited over the contone layer after the contone layer is dithered(although the contone layer has an optional black component). A finallayer of Netpage tags (in infrared or black ink) is optionally added tothe page for printout.

FIG. 2 shows the flow of a document from computer system to printedpage.

At 267 ppi for example, a A4 page (8.26 inches×11.7 inches) of contoneCMYK data has a size of 26.3 MB. At 320 ppi, an A4 page of contone datahas a size of 37.8 MB. Using lossy contone compression algorithms suchas JPEG [27], contone images compress with a ratio up to 10:1 withoutnoticeable loss of quality, giving compressed page sizes of 2.63 MB at267 ppi and 3.78 MB at 320 ppi.

At 800 dpi, a A4 page of bi-level data has a size of 7.4 MB. At 1600dpi, a Letter page of bi-level data has a size of 29.5 MB. Coherent datasuch as text compresses very well. Using lossless bi-level compressionalgorithms such as SMG4 fax as discussed in Section 8.1.2.3.1, ten-pointplain text compresses with a ratio of about 50:1. Lossless bi-levelcompression across an average page is about 20:1 with 10:1 possible forpages which compress poorly. The requirement for SoPEC is to be able toprint text at 10:1 compression. Assuming 10:1 compression givescompressed page sizes of 0.74 MB at 800 dpi, and 2.95 MB at 1600 dpi.

Once dithered, a page of CMYK contone image data consists of 116 MB ofbi-level data. Using lossless bi-level compression algorithms on thisdata is pointless precisely because the optimal dither isstochastic—i.e. since it introduces hard-to-compress disorder.

Netpage tag data is optionally supplied with the page image. Rather thanstoring a compressed bi-level data layer for the Netpage tags, the tagdata is stored in its raw form. Each tag is supplied up to 120 bits ofraw variable data (combined with up to 56 bits of raw fixed data) andcovers up to a 6 mm×6 mm area (at 1600 dpi). The absolute maximum numberof tags on a A4 page is 15,540 when the tag is only 2 mm×2 mm (each tagis 126 dots×126 dots, for a total coverage of 148 tags×105 tags). 15,540tags of 128 bits per tag gives a compressed tag page size of 0.24 MB.

The multi-layer compressed page image format therefore exploits therelative strengths of lossy JPEG contone image compression, losslessbi-level text compression, and tag encoding. The format is compactenough to be storage-efficient, and simple enough to allowstraightforward real-time expansion during printing.

Since text and images normally don't overlap, the normal worst-case pageimage size is image only, while the normal best-case page image size istext only. The addition of worst case Netpage tags adds 0.24 MB to thepage image size. The worst-case page image size is text over image plustags. The average page size assumes a quarter of an average pagecontains images. Table 1 shows data sizes for compressed Letter page forthese different options. TABLE 1 Data sizes for A4 page (8.26 inches ×11.7 inches) 320 ppi contone 267 ppi contone 1600 800 dpi bi-level dpibi-level Image only (contone), 10:1 compression 2.63 MB 3.78 MB Textonly (bi-level), 10:1 compression 0.74 MB 2.95 MB Netpage tags, 1600 dpi0.24 MB 0.24 MB Worst case (text + image + tags) 3.61 MB 6.67 MB Average(text + 25% image + tags) 1.64 MB 4.25 MB6.2 Document Data Flow

The Host PC rasterizes and compresses the incoming document on a page bypage basis. The page is restructured into bands with one or more bandsused to construct a page. The compressed data is then transferred to theSoPEC device via the USB link. A complete band is stored in SoPECembedded memory. Once the band transfer is complete the SoPEC devicereads the compressed data, expands the band, normalizes contone,bi-level and tag data to 1600 dpi and transfers the resultant calculateddots to the bi-lithic printhead.

The document data flow is

-   -   The RIP software rasterizes each page description and compress        the rasterized page image.    -   The infrared layer of the printed page optionally contains        encoded Netpage [5] tags at a programmable density.    -   The compressed page image is transferred to the SoPEC device via        the USB normally on a band by band basis.    -   The print engine takes the compressed page image and starts the        page expansion.    -   The first stage page expansion consists of 3 operations        performed in parallel    -   expansion of the JPEG-compressed contone layer    -   expansion of the SMG4 fax compressed bi-level layer    -   encoding and rendering of the bi-level tag data.    -   The second stage dithers the contone layer using a programmable        dither matrix, producing up to four bi-level layers at        full-resolution.    -   The second stage then composites the bi-level tag data layer,        the bi-level SMG4 fax de-compressed layer and up to four        bi-level JPEG de-compressed layers into the full-resolution page        image.    -   A fixative layer is also generated as required.    -   The last stage formats and prints the bi-level data through the        bi-lithic printhead via the printhead interface.

The SoPEC device can print a full resolution page with 6 color planes.Each of the color planes can be generated from compressed data throughany channel (either JPEG compressed, bi-level SMG4 fax compressed, tagdata generated, or fixative channel created) with a maximum number of 6data channels from page RIP to bi-lithic printhead color planes.

The mapping of data channels to color planes is programmable, thisallows for multiple color planes in the printhead to map to the samedata channel to provide for redundancy in the printhead to assist deadnozzle compensation.

Also a data channel could be used to gate data from another datachannel. For example in stencil mode, data from the bilevel data channelat 1600 dpi can be used to filter the contone data channel at 320 dpi,giving the effect of 1600 dpi contone image.

6.3 Page Considerations Due to SoPEC

The SoPEC device typically stores a complete page of document data onchIP. The amount of storage available for compressed pages is limited to2 Mbytes, imposing a fixed maximum on compressed page size. A comparisonof the compressed image sizes in Table 2 indicates that SoPEC would notbe capable of printing worst case pages unless they are split into bandsand printing commences before all the bands for the page have beendownloaded. The page sizes in the table are shown for comparisonpurposes and would be considered reasonable for a professional levelprinting system. The SoPEC device is aimed at the consumer level andwould not be required to print pages of that complexity. Target documenttypes for the SoPEC device are shown Table 2. TABLE 2 Page contenttargets for SoPEC Size Page Content Description Calculation (MByte) BestCase picture Image, 267 ppi with 3 colors, 8.26 × 11.7 × 267 × 267 × 31.97 A4 size @10:1 Full page text, 800 dpi A4 size 8.26 × 11.7 × 800 ×800 @ 0.74 10:1 Mixed Graphics and Text Image of 6 inches × 4 inches @267 ppi and 3 6 × 4 × 267 × 267 × 3 @ 5:1 1.55 colors Remaining areatext ˜73 inches², 800 dpi 800 × 800 × 73 @ 10:1 Best Case Photo, 3Colors, 6.6 MegaPixel Image 6.6 Mpixel @ 10:1 2.00

If a document with more complex pages is required, the page RIP softwarein the host PC can determine that there is insufficient memory storagein the SoPEC for that document. In such cases the RIP software can taketwo courses of action. It can increase the compression ratio until thecompressed page size will fit in the SoPEC device, at the expense ofdocument quality, or divide the page into bands and allow SoPEC to beginprinting a page band before all bands for that page are downloaded. OnceSoPEC starts printing a page it cannot stop, if SoPEC consumescompressed data faster than the bands can be downloaded a bufferunderrun error could occur causing the print to fail. A buffer underrunoccurs if a line synchronisation pulse is received before a line of datahas been transferred to the printhead.

Other options which can be considered if the page does not fitcompletely into the compressed page store are to slow the printing or touse multiple SoPECs to print parts of the page. A Storage SoPEC (Section7.2.5) could be added to the system to provide guaranteed bandwidth datadelivery. The print system could also be constructed using an ISI-Bridgechip (Section 7.2.6) to provide guaranteed data delivery.

7 Memjet Printer Architecture

The SoPEC device can be used in several printer configurations andarchitectures.

In the general sense every SoPEC based printer architecture willcontain:

-   -   One or more SoPEC devices.    -   One or more bi-lithic printheads.    -   Two or more LSS busses.    -   Two or more QA chips.    -   USB 1.1 connection to host or ISI connection to Bridge ChIP.    -   ISI bus connection between SoPECs (when multiple SoPECs are        used).

Some example printer configurations as outlined in Section 7.2. Thevarious system components are outlined briefly in Section 7.1.

7.1 System Components

7.1.1 SoPEC Print Engine Controller

The SoPEC device contains several system on a chip (SoC) components, aswell as the print engine pipeline control application specific logic.

7.1.1.1 Print Engine Pipeline (PEP) Logic

The PEP reads compressed page store data from the embedded memory,optionally decompresses the data and formats it for sending to theprinthead. The print engine pipeline functionality includes expandingthe page image, dithering the contone layer, compositing the black layerover the contone layer, rendering of Netpage tags, compensation for deadnozzles in the printhead, and sending the resultant image to thebi-lithic printhead.

7.1.1.2 Embedded CPU

SoPEC contains an embedded CPU for general purpose system configurationand management. The CPU performs page and band header processing, motorcontrol and sensor monitoring (via the GPIO) and other system controlfunctions. The CPU can perform buffer management or report buffer statusto the host. The CPU can optionally run vendor application specific codefor general print control such as paper ready monitoring and LED statusupdate.

7.1.1.3 Embedded Memory Buffer

A 2.5 Mbyte embedded memory buffer is integrated onto the SoPEC device,of which approximately 2 Mbytes are available for compressed page storedata. A compressed page is divided into one or more bands, with a numberof bands stored in memory. As a band of the page is consumed by the PEPfor printing a new band can be downloaded. The new band may be for thecurrent page or the next page.

Using banding it is possible to begin printing a page before thecomplete compressed page is downloaded, but care must be taken to ensurethat data is always available for printing or a buffer underrun mayoccur.

An Storage SoPEC acting as a memory buffer (Section 7.2.5) or anISI-Bridge chip with attached DRAM (Section 7.2.6) could be used toprovide guaranteed data delivery.

7.1.1.4 Embedded USB 1.1 Device

The embedded USB 1.1 device accepts compressed page data and controlcommands from the host PC, and facilitates the data transfer to eitherembedded memory or to another SoPEC device in multi-SoPEC systems.

7.1.2 Bi-lithic Printhead

The printhead is constructed by abutting 2 printhead ICs together. Theprinthead ICs can vary in size from 2 inches to 8 inches, so to producean A4 printhead several combinations are possible. For example twoprinthead ICs of 7 inches and 3 inches could be used to create a A4printhead (the notation is 7:3). Similarly 6 and 4 combination (6:4), or5:5 combination. For an A3 printhead it can be constructed from 8:6 oran 7:7 printhead IC combination. For photographic printing smallerprintheads can be constructed.

7.1.3 LSS Interface Bus

Each SoPEC device has 2 LSS system buses for communication with QAdevices for system authentication and ink usage accounting. The numberof QA devices per bus and their position in the system is unrestrictedwith the exception that PRINTER_QA and INK_QA devices should be onseparate LSS busses.

7.1.4 QA Devices

Each SoPEC system can have several QA devices. Normally each printingSoPEC will have an associated PRINTER_QA. Ink cartridges will contain anINK_QA chIP. PRINTER_QA and INK_QA devices should be on separate LSSbusses. All QA chips in the system are physically identical with flashmemory contents defining PRINTER_QA from INK_QA chIP.

7.1.5 ISI Interface

The Inter-SoPEC Interface (ISI) provides a communication channel betweenSoPECs in a multi-SoPEC system. The ISIMaster can be SoPEC device or anISI-Bridge chip depending on the printer configuration. Both compresseddata and control commands are transferred via the interface.

7.1.6 ISI-Bridge Chip

A device, other than a SoPEC with a USB connection, which provides printdata to a number of slave SoPECs. A bridge chip will typically have ahigh bandwidth connection, such as USB2.0, Ethernet or IEEE1394, to ahost and may have an attached external DRAM for compressed page storage.A bridge chip would have one or more ISI interfaces. The use of multipleISI buses would allow the construction of independent print systemswithin the one printer. The ISI-Bridge would be the ISIMaster for eachof the ISI buses it interfaces to.

7.2 Possible SoPEC Systems

Several possible SoPEC based system architectures exist. The followingsections outline some possible architectures. It is possible to haveextra SoPEC devices in the system used for DRAM storage. The QA chipconfigurations shown are indicative of the flexibility of LSS busarchitecture, but not limited to those configurations.

7.2.1 A4 Simplex with 1 SoPEC Device

In FIG. 3, a single SoPEC device can be used to control two printheadICs. The SoPEC receives compressed data through the USB device from thehost. The compressed data is processed and transferred to the printhead.

7.2.2 A4 Duplex with 2 SoPEC Devices

In FIG. 4, two SoPEC devices are used to control two bi-lithicprintheads, each with two printhead ICs. Each bi-lithic printhead printsto opposite sides of the same page to achieve duplex printing. The SoPECconnected to the USB is the ISIMaster SoPEC, the remaining SoPEC is anISISlave. The ISIMaster receives all the compressed page data for bothSoPECs and re-distributes the compressed data over the Inter-SoPECInterface (ISI) bus.

It may not be possible to print an A4 page every 2 seconds in thisconfiguration since the USB 1.1 connection to the host may not haveenough bandwidth. An alternative would be for each SoPEC to have its ownUSB 1.1 connection. This would allow a faster average print speed.

7.2.3 A3 Simplex with 2 SoPEC Devices

In FIG. 5, two SoPEC devices are used to control one A3 bi-lithicprinthead. Each SoPEC controls only one printhead IC (the remaining PHIport typically remains idle). This system uses the SoPEC with the USBconnection as the ISIMaster. In this dual SoPEC configuration thecompressed page store data is split across 2 SoPECs giving a total of 4Mbyte page store, this allows the system to use compression rates as inan A4 architecture, but with the increased page size of A3. TheISIMaster receives all the compressed page data for all SoPECs andre-distributes the compressed data over the Inter-SoPEC Interface (ISI)bus.

It may not be possible to print an A3 page every 2 seconds in thisconfiguration since the USB 1.1 connection to the host will only haveenough bandwidth to supply 2 Mbytes every 2 seconds. Pages which requiremore than 2 MBytes every 2 seconds will therefore print more slowly. Analternative would be for each SoPEC to have its own USB 1.1 connection.This would allow a faster average print speed.

7.2.4 A3 Duplex with 4 SoPEC Devices

In FIG. 6 a 4 SoPEC system is shown. It contains 2 A3 bi-lithicprintheads, one for each side of an A3 page. Each printhead contain 2printhead ICs, each printhead IC is controlled by an independent SoPECdevice, with the remaining PHI port typically unused. Again the SoPECwith USB 1.1 connection is the ISIMaster with the other SoPECs asISISlaves. In total, the system contains 8 Mbytes of compressed pagestore (2 Mbytes per SoPEC), so the increased page size does not degradethe system print quality, from that of an A4 simplex printer. TheISIMaster receives all the compressed page data for all SoPECs andre-distributes the compressed data over the Inter-SoPEC Interface (ISI)bus.

It may not be possible to print an A3 page every 2 seconds in thisconfiguration since the USB 1.1 connection to the host will only haveenough bandwidth to supply 2 Mbytes every 2 seconds. Pages which requiremore than 2 MBytes every 2 seconds will therefore print more slowly. Analternative would be for each SoPEC or set of SoPECs on the same side ofthe page to have their own USB 1.1 connection (as ISISlaves may alsohave direct USB connections to the host). This would allow a fasteraverage print speed.

7.2.5 SoPEC DRAM storage solution: A4 Simplex with 1 printing SoPEC and1 memory SoPEC Extra SoPECs can be used for DRAM storage e.g. in FIG. 7an A4 simplex printer can be built with a single extra SoPEC used forDRAM storage. The DRAM SoPEC can provide guaranteed bandwidth deliveryof data to the printing SoPEC. SoPEC configurations can have multipleextra SoPECs used for DRAM storage.

7.2.6 ISI-Bridge Chip Solution: A3 Duplex System with 4 SoPEC Devices

In FIG. 8, an ISI-Bridge chip provides slave-only ISI connections toSoPEC devices. FIG. 8 shows a ISI-Bridge chip with 2 separate ISI ports.The ISI-Bridge chip is the ISIMaster on each of the ISI busses it isconnected to. All connected SoPECs are ISISlaves. The ISI-Bridge chipwill typically have a high bandwidth connection to a host and may havean attached external DRAM for compressed page storage.

An alternative to having a ISI-Bridge chip would be for each SoPEC oreach set of SoPECs on the same side of a page to have their own USB 1.1connection. This would allow a faster average print speed.

8 Page Format and Printflow

When rendering a page, the RIP produces a page header and a number ofbands (a non-blank page requires at least one band) for a page. The pageheader contains high level rendering parameters, and each band containscompressed page data. The size of the band will depend on the memoryavailable to the RIP, the speed of the RIP, and the amount of memoryremaining in SoPEC while printing the previous band(s). FIG. 9 shows thehigh level data structure of a number of pages with different numbers ofbands in the page.

Each compressed band contains a mandatory band header, an optionalbi-level plane, optional sets of interleaved contone planes, and anoptional tag data plane (for Netpage enabled applications). Since eachof these planes is optional¹, the band header specifies which planes areincluded with the band. FIG. 10 gives a high-level breakdown of thecontents of a page band.

A single SoPEC has maximum rendering restrictions as follows:

-   -   1 bi-level plane    -   1 contone interleaved plane set containing a maximum of 4        contone planes    -   1 tag data plane    -   a bi-lithic printhead with a maximum of 2 printhead ICs

The requirement for single-sided A4 single SoPEC printing is

-   -   average contone JPEG compression ratio of 10:1, with a local        minimum compression ratio of 5:1 for a single line of        interleaved JPEG blocks.    -   average bi-level compression ratio of 10:1, with a local minimum        compression ratio of 1:1 for a single line.

If the page contains rendering parameters that exceed thesespecifications, then the RIP or the Host PC must split the page into aformat that can be handled by a single SoPEC.

In the general case, the SoPEC CPU must analyze the page and bandheaders and generate an appropriate set of register write commands toconfigure the units in SoPEC for that page. The various bands are passedto the destination SoPEC(s) to locations in DRAM determined by the host.

The host keeps a memory map for the DRAM, and ensures that as a band ispassed to a SoPEC, it is stored in a suitable free area in DRAM. EachSoPEC is connected to the ISI bus or USB bus via its Serialcommunication Block (SCB). The SoPEC CPU configures the SCB to allowcompressed data bands to pass from the USB or ISI through the SCB toSoPEC DRAM. FIG. 11 shows an example data flow for a page destined to beprinted by a single SoPEC. Band usage information is generated by theindividual SoPECs and passed back to the host.

SoPEC has an addressing mechanism that permits circular band memoryallocation, thus facilitating easy memory management. However it is notstrictly necessary that all bands be stored together. As long as theappropriate registers in SoPEC are set up for each band, and a givenband is contiguous², the memory can be allocated in any way.¹Although a band must contain at least one plane²Contiguous allocation also includes wrapping around in SoPEC's bandstore memory.

8.1 Print Engine Example Page Format

This section describes a possible format of compressed pages expected bythe embedded CPU in SoPEC. The format is generated by software in thehost PC and interpreted by embedded software in SoPEC. This sectionindicates the type of information in a page format structure, butimplementations need not be limited to this format. The host PC canoptionally perform the majority of the header processing.

The compressed format and the print engines are designed to allowreal-time page expansion during printing, to ensure that printing isnever interrupted in the middle of a page due to data underrun.

The page format described here is for a single black bi-level layer, acontone layer, and a Netpage tag layer. The black bi-level layer isdefined to composite over the contone layer.

The black bi-level layer consists of a bitmap containing a 1-bit opacityfor each pixel. This black layer matte has a resolution which is aninteger or non-integer factor of the printer's dot resolution.

The highest supported resolution is 1600 dpi, i.e. the printer's fulldot resolution.

The contone layer, optionally passed in as YCrCb, consists of a 24-bitCMY or 32-bit CMYK color for each pixel. This contone image has aresolution which is an integer or non-integer factor of the printer'sdot resolution. The requirement for a single SoPEC is to support 1 sideper 2 seconds A4/Letter printing at a resolution of 267 ppi, i.e.one-sixth the printer's dot resolution.

Non-integer scaling can be performed on both the contone and bi-levelimages. Only integer scaling can be performed on the tag data.

The black bi-level layer and the contone layer are both in compressedform for efficient storage in the printer's internal memory.

8.1.1 Page Structure

A single SoPEC is able to print with full edge bleed for Letter and A3via different stitch part combinations of the bi-lithic printhead. Itimposes no margins and so has a printable page area which corresponds tothe size of its paper. The target page size is constrained by theprintable page area, less the explicit (target) left and top marginsspecified in the page description. These relationships are illustratedbelow.

8.1.2 Compressed Page Format

Apart from being implicitly defined in relation to the printable pagearea, each page description is complete and self-contained. There is nodata stored separately from the page description to which the pagedescription refers.³ The page description consists of a page headerwhich describes the size and resolution of the page, followed by one ormore page bands which describe the actual page content.

8.1.2.1 Page Header

Table 3 shows an example format of a page header.³SoPEC relies on dither matrices and tag structures to have already beenset up, but these are not considered to be part of a general pageformat. It is trivial to extend the page format to allow exactspecification of dither matrices and tag structures.TABLE 3 Page header format field format description signature 16-bitinteger Page header format signature. version 16-bit integer Page headerformat version number. structure size 16-bit integer Size of pageheader. band count 16-bit integer Number of bands specified for thispage. target resolution (dpi) 16-bit integer Resolution of target page.This is always 1600 for the Memjet printer. target page width 16-bitinteger Width of target page, in dots. target page height 32-bit integerHeight of target page, in dots. target left margin for black and 16-bitinteger Width of target left margin, in dots, for black contone andcontone. target top margin for black and 16-bit integer Height of targettop margin, in dots, for black contone and contone. target right marginfor black and 16-bit integer Width of target right margin, in dots, forblack contone and contone. target bottom margin for black 16-bit integerHeight of target bottom margin, in dots, for and contone black andcontone. target left margin for tags 16-bit integer Width of target leftmargin, in dots, for tags. target top margin for tags 16-bit integerHeight of target top margin, in dots, for tags. target right margin fortags 16-bit integer Width of target right margin, in dots, for tags.target bottom margin for tags 16-bit integer Height of target bottommargin, in dots, for tags. generate tags 16-bit integer Specifieswhether to generate tags for this page (0 - no, 1 - yes). fixed tag data128-bit integer  This is only valid if generate tags is set. tagvertical scale factor 16-bit integer Scale factor in vertical directionfrom tag data resolution to target resolution. Valid range = 1-511.Integer scaling only tag horizontal scale factor 16-bit integer Scalefactor in horizontal direction from tag data resolution to targetresolution. Valid range = 1-511. Integer scaling only. bi-level layervertical scale factor 16-bit integer Scale factor in vertical directionfrom bi-level resolution to target resolution (must be 1 or greater).May be non-integer. Expressed as a fraction with upper 8-bits thenumerator and the lower 8 bits the denominator. bi-level layerhorizontal scale factor 16-bit integer Scale factor in horizontaldirection from bi- level resolution to target resolution (must be 1 orgreater). May be non-integer. Expressed as a fraction with upper 8-bitsthe numerator and the lower 8 bits the denominator. bi-level layer pagewidth 16-bit integer Width of bi-level layer page, in pixels. bi-levellayer page height 32-bit integer Height of bi-level layer page, inpixels. contone flags 16 bit integer Defines the color conversion thatis required for the JPEG data. Bits 2-0 specify how many contone planesthere are (e.g. 3 for CMY and 4 for CMYK). Bit 3 specifies whether thefirst 3 color planes need to be converted back from YCrCb to CMY. Onlyvalid if b2-0 = 3 or 4. 0 - no conversion, leave JPEG colors alone 1 -color convert. Bits 7-4 specifies whether the YCrCb was generateddirectly from CMY, or whether it was converted to RGB first via thestep: R = 255- C, G = 255-M, B = 255-Y. Each of the color planes can beindividually inverted. Bit 4: 0 - do not invert color plane 0 1 - invertcolor plane 0 Bit 5: 0 - do not invert color plane 1 1 - invert colorplane 1 Bit 6: 0 - do not invert color plane 2 1 - invert color plane 2Bit 7: 0 - do not invert color plane 3 1 - invert color plane 3 Bit 8specifies whether the contone data is JPEG compressed or non-compressed:0 - JPEG compressed 1 - non-compressed The remaining bits are reserved(0). contone vertical scale factor 16-bit integer Scale factor invertical direction from contone channel resolution to target resolution.Valid range = 1-255. May be non-integer. Expressed as a fraction withupper 8-bits the numerator and the lower 8 bits the denominator. contonehorizontal scale factor 16-bit integer Scale factor in horizontaldirection from contone channel resolution to target resolution. Validrange = 1-255. May be non- integer. Expressed as a fraction with upper8-bits the numerator and the lower 8 bits the denominator. contone pagewidth 16-bit integer Width of contone page, in contone pixels. contonepage height 32-bit integer Height of contone page, in contone pixels.reserved up to 128 bytes Reserved and 0 pads out page header to multipleof 128 bytes.

The page header contains a signature and version which allow the CPU toidentify the page header format. If the signature and/or version aremissing or incompatible with the CPU, then the CPU can reject the page.

The contone flags define how many contone layers are present, whichtypically is used for defining whether the contone layer is CMY or CMYK.Additionally, if the color planes are CMY, they can be optionally storedas YCrCb, and further optionally color space converted from CMY directlyor via RGB. Finally the contone data is specified as being either JPEGcompressed or non-compressed. The page header defines the resolution andsize of the target page. The bi-level and contone layers are clipped tothe target page if necessary. This happens whenever the bi-level orcontone scale factors are not factors of the target page width orheight.

The target left, top, right and bottom margins define the positioning ofthe target page within the printable page area.

The tag parameters specify whether or not Netpage tags should beproduced for this page and what orientation the tags should be producedat (landscape or portrait mode). The fixed tag data is also provided.

The contone, bi-level and tag layer parameters define the page size andthe scale factors.

8.1.2.2 Band Format

Table 4 shows the format of the page band header. TABLE 4 Band headerformat field format description signature 16-bit integer Page bandheader format signature. version 16-bit integer Page band header formatversion number. structure size 16-bit integer Size of page band header.bi-level layer band height 16-bit integer Height of bi-level layer band,in black pixels. bi-level layer band data size 32-bit integer Size ofbi-level layer band data, in bytes. contone band height 16-bit integerHeight of contone band, in contone pixels. contone band data size 32-bitinteger Size of contone plane band data, in bytes. tag band height16-bit integer Height of tag band, in dots. tag band data size 32-bitinteger Size of unencoded tag data band, in bytes. Can be 0 whichindicates that no tag data is provided. reserved up to 128 bytesReserved and 0 pads out band header to multiple of 128 bytes.

The bi-level layer parameters define the height of the black band, andthe size of its compressed band data. The variable-size black datafollows the page band header.

The contone layer parameters define the height of the contone band, andthe size of its compressed page data. The variable-size contone datafollows the black data.

The tag band data is the set of variable tag data half-lines as requiredby the tag encoder. The format of the tag data is found in Section26.5.2. The tag band data follows the contone data.

Table 5 shows the format of the variable-size compressed band data whichfollows the page band header. TABLE 5 Page band data format field formatDescription black data Modified G4 Compressed bi-level layer. facsimilebitstream⁴ contone data JPEG bytestream Compressed contone datalayer.tag data map Tag data array Tag data format. See Section 26.5.2.⁴See section 8.1.2.3 on page 36 for note regarding the use of thisstandard

The start of each variable-size segment of band data should be alignedto a 256-bit DRAM word boundary.

The following sections describe the format of the compressed bi-levellayers and the compressed contone layer. section 26.5.1 on page 410describes the format of the tag data structures.

8.1.2.3 Bi-Level Data Compression

The (typically 1600 dpi) black bi-level layer is losslessly compressedusing Silverbrook Modified Group 4 (SMG4) compression which is a versionof Group 4 Facsimile compression [22] without Huffman and withsimplified run length encodings. Typically compression ratIOs exceed10:1. The encoding are listed in Table 6 and Table 7. EncodingDescription same as 1000 Pass Command: a0

b2, skip next two Group 4 edges Facsimile 1 Vertical(0): a0

b1, color = !color 110 Vertical(1): a0

b1 + 1, color = !color 010 Vertical(−1): a0

b1 − 1, color = !color 110000 Vertical(2): a0

b1 + 2, color = !color 010000 Vertical(−2): a0

b1 − 2, color = !color Unique to 100000 Vertical(3): a0

b1 + 3, color = !color this implemen- tation 000000 Vertical(−3): a0

b1 − 3, color = !color <RL><RL>100 Horizontal: a0

a0 + <RL> + <RL>

SMG4 has a pass through mode to cope with local negative compression.Pass through mode is activated by a special run-length code. Passthrough mode continues to either end of line or for a pre-programmednumber of bits, whichever is shorter. The special run-length code isalways executed as a run-length code, followed by pass through. The passthrough escape code is a medium length run-length with a run of lessthan or equal to 31. TABLE 7 Run length (RL) encodings EncodingDescription Unique to this RRRRR1 Short Black Runlength (5 bits)implementation RRRRR1 Short White Runlength (5 bits) RRRRRRRRRR10 MediumBlack Runlength (10 bits) RRRRRRRR10 Medium White Runlength (8 bits)RRRRRRRRRR10 Medium Black Runlength with RRRRRRRRRR <= 31, Enter passthrough RRRRRRRR10 Medium White Runlength with RRRRRRRR <= 31, Enterpass through RRRRRRRRRRRRRRR00 Long Black Runlength (15 bits)RRRRRRRRRRRRRRR00 Long White Runlength (15 bits)

Since the compression is a bitstream, the encodings are read right(least significant bit) to left (most significant bit). The run lengthsgiven as RRRR in Table are read in the same way (least significant bitat the right to most significant bit at the left).

Each band of bi-level data is optionally self contained. The first lineof each band therefore is based on a ‘previous’ blank line or the lastline of the previous band.

8.1.2.3.1 Group 3 and 4 Facsimile Compression

The Group 3 Facsimile compression algorithm [22] losslessly compressesbi-level data for transmission over slow and noisy and noisy telephonelines. The bi-level data represents scanned black text and graphics on awhile background, and the algorithm is tuned for this class of images(it is explicitly not tuned, for example, for halftoned bi-levelimages). The 1D Group 3 algorithm runlength-encodes each scanline andthen Huffman-encodes the resulting runlengths. Runlengths in the range 0to 63 are coded with terminating codes. Runlengths in the range 64 to2623 are coded with make-up codes, each representing a multiple of 64,followed by a terminating code. Runlengths exceeding 2623 are coded withmultiple make-up codes followed by a terminating code. The Huffmantables are fixed, but are separately tuned for black and white runs(except for make-up codes above 1728, which are common). When possible,the 2D Group 3 algorithm encodes a scanline as a set of short edgedeltas (0, +1, +2, +3) with reference to the previous scanline. Thedelta symbols are entropy-encoded (so that the zero delta symbol is onlyone bit long etc.) Edges within a 2D-encoded line which can't bedelta-encoded are runlength-encoded, and are identified by a prefix. 1D-and 2D-encoded lines are marked differently. 1D-encoded lines aregenerated at regular intervals, whether actually required or not, toensure that the decoder can recover from line noise with minimal imagedegradation. 2D Group 3 achieves compression ratIOs of up to 6:1 [32].The Group 4 Facsimile algorithm [22] losslessly compresses bi-level datafor transmission over error-free communications lines (i.e. the linesare truly error-free, or error-correction is done at a lower protocollevel). The Group 4 algorithm is based on the 2D Group 3 algorithm, withthe essential modification that since transmission is assumed to beerror-free, 1D-encoded lines are no longer generated at regularintervals as an aid to error-recovery. Group 4 achieves compressionratIOs ranging from 20:1 to 60:1 for the CCITT set of test images [32].

The design goals and performance of the Group 4 compression algorithmqualify it as a compression algorithm for the bi-level layers. However,its Huffman tables are tuned to a lower scanning resolution (100-400dpi), and it encodes runlengths exceeding 2623 awkwardly.

8.1.2.4 Contone Data Compression

The contone layer (CMYK) is either a non-compressed bytestream or iscompressed to an interleaved JPEG bytestream. The JPEG bytestream iscomplete and self-contained. It contains all data required fordecompression, including quantization and Huffman tables.

The contone data is optionally converted to YCrCb before beingcompressed (there is no specific advantage in color-space converting ifnot compressing). Additionally, the CMY contone pixels are optionallyconverted (on an individual basis) to RGB before color conversion usingR=255-C, G=255-M, B=255-Y. Optional bitwise inversion of the K plane mayalso be performed. Note that this CMY to RGB conversion is not intendedto be accurate for display purposes, but rather for the purposes oflater converting to YCrCb. The inverse transform will be applied beforeprinting.

8.1.2.4.1 JPEG Compression

The JPEG compression algorithm [27] lossily compresses a contone imageat a specified quality level. It introduces imperceptible imagedegradation at compression ratIOs below 5:1, and negligible imagedegradation at compression ratIOs below 10:1 [33].

JPEG typically first transforms the image into a color space whichseparates luminance and chrominance into separate color channels. Thisallows the chrominance channels to be subsampled without appreciableloss because of the human visual system's relatively greater sensitivityto luminance than chrominance. After this first step, each color channelis compressed separately.

The image is divided into 8×8 pixel blocks. Each block is thentransformed into the frequency domain via a discrete cosine transform(DCT). This transformation has the effect of concentrating image energyin relatively lower-frequency coefficients, which allowshigher-frequency coefficients to be more crudely quantized. Thisquantization is the principal source of compression in JPEG. Furthercompression is achieved by ordering coefficients by frequency tomaximize the likelihood of adjacent zero coefficients, and thenrunlength-encoding runs of zeroes. Finally, the runlengths and non-zerofrequency coefficients are entropy coded. Decompression is the inverseprocess of compression.

8.1.2.4.2 Non-Compressed Format

If the contone data is non-compressed, it must be in a block-basedformat bytestream with the same pixel order as would be produced by aJPEG decoder. The bytestream therefore consists of a series of 8×8 blockof the original image, starting with the top left 8×8 block, and workinghorizontally across the page (as it will be printed) until the toprightmost 8×8 block, then the next row of 8×8 blocks (left to right) andso on until the lower row of 8×8 blocks (left to right). Each 8×8 blockconsists of 64 8-bit pixels for color plane 0 (representing 8 rows of 8pixels in the order top left to bottom right) followed by 64 8-bitpixels for color plane 1 and so on for up to a maximum of 4 colorplanes.

If the original image is not a multiple of 8 pixels in X or Y, paddingmust be present (the extra pixel data will be ignored by the setting ofmargins).

8.1.2.4.3 Compressed Format

If the contone data is compressed the first memory band contains JPEGheaders (including tables) plus MCUs (minimum coded units). The ratio ofspace between the various color planes in the JPEG stream is 1:1:1:1. Nosubsampling is permitted. Banding can be completely arbitrary i.e therecan be multiple JPEG images per band or 1 JPEG image divided overmultiple bands. The break between bands is only memory alignment based.

8.1.2.4.4 Conversion of RGB to YCrCb (in RIP)

YCrCb is defined as per CCIR 601-1 [24] except that Y, Cr and Cb arenormalized to occupy all 256 levels of an 8-bit binary encoding and takeaccount of the actual hardware implementation of the inverse transformwithin SoPEC.

The exact color conversion computation is as follows:

-   -   Y*=(9805/32768)R+(19235/32768)G+(3728/32768)B    -   Cr*=(16375/32768)R−(13716/32768)G−(2659/32768)B+128    -   Cb*=−(5529/32768)R−(10846/32768)G+(16375/32768)B+128

Y, Cr and Cb are obtained by rounding to the nearest integer. There isno need for saturation since ranges of Y*, Cr* and Cb* after roundingare [0-255], [1-255] and [1-255] respectively. Note that full accuracyis possible with 24 bits. See [14] for more information.

SoPEC ASIC

9 Overview

The Small Office Home Office Print Engine Controller (SoPEC) is a pagerendering engine ASIC that takes compressed page images as input, andproduces decompressed page images at up to 6 channels of bi-level dotdata as output. The bi-level dot data is generated for the Memjetbi-lithic printhead. The dot generation process takes account ofprinthead construction, dead nozzles, and allows for fixativegeneration.

A single SoPEC can control 2 bi-lithic printheads and up to 6 colorchannels at 10,000 lines/sec⁵, equating to 30 pages per minute. A singleSoPEC can perform full-bleed printing of A3, A4 and Letter pages. The 6channels of colored ink are the expected maximum in a consumer SOHO, oroffice Bi-lithic printing environment:⁵10,000 lines per second equates to 30 A4/Letter pages per minute at1600 dpi

-   -   CMY, for regular color printing.

K, for black text, line graphics and gray-scale printing.

IR (infrared), for Netpage-enabled [5] applications.

F (fixative), to enable printing at high speed. Because the bi-lithicprinter is capable of printing so fast, a fixative may be required toenable the ink to dry before the page touches the page already printed.Otherwise the pages may bleed on each other. In low speed printingenvironments the fixative may not be required.

SoPEC is color space agnostic. Although it can accept contone data asCMYX or RGBX, where X is an optional 4th channel, it also can acceptcontone data in any print color space. Additionally, SoPEC provides amechanism for arbitrary mapping of input channels to output channels,including combining dots for ink optimization, generation of channelsbased on any number of other channels etc. However, inputs are typicallyCMYK for contone input, K for the bi-level input, and the optionalNetpage tag dots are typically rendered to an infra-red layer. Afixative channel is typically generated for fast printing applications.

SoPEC is resolution agnostic. It merely provides a mapping between inputresolutions and output resolutions by means of scale factors. Theexpected output resolution is 1600 dpi, but SoPEC actually has noknowledge of the physical resolution of the Bi-lithic printhead.

SoPEC is page-length agnostic. Successive pages are typically split intobands and downloaded into the page store as each band of information isconsumed and becomes free.

SoPEC provides an interface for synchronization with other SoPECs. Thisallows simple multi-SoPEC solutions for simultaneous A3/A4/Letter duplexprinting. However, SoPEC is also capable of printing only a portion of apage image. Combining synchronization functionality with partial pagerendering allows multiple SoPECs to be readily combined for alternativeprinting requirements including simultaneous duplex printing and wideformat printing.

Table 8 lists some of the features and corresponding benefits of SoPEC.TABLE 8 Features and Benefits of SoPEC Feature Benefits Optimised printarchitecture in 30 ppm full page photographic quality color printingfrom a hardware desktop PC 0.13micron CMOS High speed (>3 milliontransistors) Low cost High functionality 900 Million dots per secondExtremely fast page generation 10,000 lines per second at 1600 dpi 0.5A4/Letter pages per SoPEC chip per second 1 chip drives up to 133,920Low cost page-width printers nozzles 1 chip drives up to 6 color planes99% of SoHo printers can use 1 SoPEC device Integrated DRAM No externalmemory required, leading to low cost systems Power saving sleep modeSoPEC can enter a power saving sleep mode to reduce power dissipationbetween print jobs JPEG expansion Low bandwidth from PC Low memoryrequirements in printer Lossless bitplane expansion High resolution textand line art with low bandwidth from PC (e.g. over USB) Netpage tagexpansion Generates interactive paper Stochastic dispersed dot ditherOptically smooth image quality No moire effects Hardware compositor for6 image Pages composited in real-time planes Dead nozzle compensationExtends printhead life and yield Reduces printhead cost Color spaceagnostic Compatible with all inksets and image sources including RGB,CMYK, spot, CIE L*a*b*, hexachrome, YCrCbK, sRGB and other Color spaceconversion Higher quality/lower bandwidth Computer interface USB1.1interface to host and ISI interface to ISI-Bridge chip thereby allowingconnection to IEEE 1394, Bluetooth etc. Cascadable in resolutionPrinters of any resolution Cascadable in color depth Special color setse.g. hexachrome can be used Cascadable in image size Printers of anywidth up to 16 inches Cascadable in pages Printers can print both sidessimultaneously Cascadable in speed Higher speeds are possible by havingeach SoPEC print one vertical strip of the page. Fixative channel datageneration Extremely fast ink drying without wastage Built-in securityRevenue models are protected Undercolor removal on dot-by-dot Reducedink usage basis Does not require fonts for high No font substitution ormissing fonts speed operation Flexible printhead configuration Manyconfigurations of printheads are supported by one chip type DrivesBi-lithic printheads directly No print driver chips required, results inlower cost Determines dot accurate ink usage Removes need for physicalink monitoring system in ink cartridges9.1 Printing Rates

The required printing rate for SoPEC is 30 sheets per minute with aninter-sheet spacing of 4 cm. To achieve a 30 sheets per minute printrate, this requires:

-   -   300 mm×63 (dot/mm)/2 sec=105.8 μseconds per line, with no        inter-sheet gap.    -   340 mm×63 (dot/mm)/2 sec=93.3 μseconds per line, with a 4 cm        inter-sheet gap.

A printline for an A4 page consists of 13824 nozzles across the page[2]. At a system clock rate of 160 MHz 13824 dots of data can begenerated in 86.4 μseconds. Therefore data can be generated fast enoughto meet the printing speed requirement. It is necessary to deliver thisprint data to the print-heads.

Printheads can be made up of 5:5, 6:4, 7:3 and 8:2 inch printheadcombinations [2]. Print data is transferred to both print heads in apair simultaneously. This means the longest time to print a line isdetermined by the time to transfer print data to the longest printsegment. There are 9744 nozzles across a 7 inch printhead. The printdata is transferred to the printhead at a rate of 106 MHz (2/3 of thesystem clock rate) per color plane. This means that it will take 91.9 μsto transfer a single line for a 7:3 printhead configuration. So we canmeet the requirement of 30 sheets per minute printing with a 4 cm gapwith a 7:3 printhead combination. There are 11160 across an 8 inchprinthead. To transfer the data to the printhead at 106 MHz will take105.3 μs. So an 8:2 printhead combination printing with an inter-sheetgap will print slower than 30 sheets per minute.

9.2 SoPEC Basic Architecture

From the highest point of view the SoPEC device consists of 3 distinctsubsystems

-   -   CPU Subsystem    -   DRAM Subsystem    -   Print Engine Pipeline (PEP) Subsystem

See FIG. 13 for a block level diagram of SoPEC.

9.2.1 CPU Subsystem

The CPU subsystem controls and configures all aspects of the othersubsystems. It provides general support for interfacing andsynchronising the external printer with the internal print engine. Italso controls the low speed communication to the QA chips. The CPUsubsystem contains various peripherals to aid the CPU, such as GPIO(includes motor control), interrupt controller, LSS Master and generaltimers. The Serial Communications Block (SCB) on the CPU subsystemprovides a full speed USB1.1 interface to the host as well as an InterSoPEC Interface (ISI) to other SoPEC devices.

9.2.2 DRAM Subsystem

The DRAM subsystem accepts requests from the CPU, Serial CommunicationsBlock (SCB) and blocks within the PEP subsystem. The DRAM subsystem (inparticular the DIU) arbitrates the various requests and determines whichrequest should win access to the DRAM. The DIU arbitrates based onconfigured parameters, to allow sufficient access to DRAM for allrequesters. The DIU also hides the implementation specifics of the DRAMsuch as page size, number of banks, refresh rates etc.

9.2.3 Print Engine Pipeline (PEP) Subsystem

The Print Engine Pipeline (PEP) subsystem accepts compressed pages fromDRAM and renders them to bi-level dots for a given print line destinedfor a printhead interface that communicates directly with up to 2segments of a bi-lithic printhead.

The first stage of the page expansion pipeline is the CDU, LBD and TE.The CDU expands the JPEG-compressed contone (typically CMYK) layer, theLBD expands the compressed bi-level layer (typically K), and the TEencodes Netpage tags for later rendering (typically in IR or K ink). Theoutput from the first stage is a set of buffers: the CFU, SFU, and TFU.The CFU and SFU buffers are implemented in DRAM.

The second stage is the HCU, which dithers the contone layer, andcomposites position tags and the bi-level spot0 layer over the resultingbi-level dithered layer. A number of options exist for the way in whichcompositing occurs. Up to 6 channels of bi-level data are produced fromthis stage. Note that not all 6 channels may be present on theprinthead. For example, the printhead may be CMY only, with K pushedinto the CMY channels and IR ignored. Alternatively, the position tagsmay be printed in K if IR ink is not available (or for testingpurposes).

The third stage (DNC) compensates for dead nozzles in the printhead bycolor redundancy and error diffusing dead nozzle data into surroundingdots.

The resultant bi-level 6 channel dot-data (typically CMYK-IRF) isbuffered and written out to a set of line buffers stored in DRAM via theDWU.

Finally, the dot-data is loaded back from DRAM, and passed to theprinthead interface via a dot FIFO. The dot FIFO accepts data from theLLU at the system clock rate (pclk), while the PHI removes data from theFIFO and sends it to the printhead at a rate of ⅔ times the system clockrate (see Section 9.1).

9.3 SoPEC Block Description

Looking at FIG. 13, the various units are described here in summaryform: TABLE 9 Units within SoPEC Unit Subsystem Acronym Unit NameDescription DRAM DIU DRAM interface unit Provides the interface for DRAMread and write access for the various SoPEC units, CPU and the SCBblock. The DIU provides arbitration between competing units controlsDRAM access. DRAM Embedded DRAM 20 Mbits of embedded DRAM, CPU CPUCentral Processing CPU for system configuration and control Unit MMUMemory Management Limits access to certain memory address areas Unit inCPU user mode RDU Real-time Debug Unit Facilitates the observation ofthe contents of most of the CPU addressable registers in SoPEC inaddition to some pseudo-registers in realtime. TIM General TimerContains watchdog and general system timers LSS Low Speed Serial Lowlevel controller for interfacing with the QA Interfaces chips GPIOGeneral Purpose IOs General IO controller, with built-in Motor controlunit, LED pulse units and de-glitch circuitry ROM Boot ROM 16 KBytes ofSystem Boot ROM code ICU Interrupt Controller General Purpose interruptcontroller with Unit configurable priority, and masking. CPR Clock,Power and Central Unit for controlling and generating the Reset blocksystem clocks and resets and powerdown mechanisms PSS Power Save StorageStorage retained while system is powered down USB Universal Serial BusUSB device controller for interfacing with the Device host USB. ISIInter-SoPEC Interface ISI controller for data and control communicationwith other SoPEC's in a multi- SoPEC system SCB Serial CommunicationContains both the USB and ISI blocks. Block Print Engine PCU PEPcontroller Provides external CPU with the means to read Pipeline andwrite PEP Unit registers, and read and (PEP) write DRAM in single 32-bitchunks. CDU Contone decoder unit Expands JPEG compressed contone layerand writes decompressed contone to DRAM CFU Contone FIFO Unit Providesline buffering between CDU and HCU LBD Lossless Bi-level Expandscompressed bi-level layer. Decoder SFU Spot FIFO Unit Provides linebuffering between LBD and HCU TE Tag encoder Encodes tag data into lineof tag dots. TFU Tag FIFO Unit Provides tag data storage between TE andHCU HCU Halftoner compositor Dithers contone layer and composites thebi- unit level spot 0 and position tag dots. DNC Dead Nozzle Compensatesfor dead nozzles by color Compensator redundancy and error diffusingdead nozzle data into surrounding dots. DWU Dotline Writer Unit Writesout the 6 channels of dot data for a given printline to the line storeDRAM LLU Line Loader Unit Reads the expanded page image from line store,formatting the data appropriately for the bi-lithic printhead. PHIPrintHead Interface Is responsible for sending dot data to the bi-lithic printheads and for providing line synchronization betweenmultiple SoPECs. Also provides test interface to printhead such astemperature monitoring and Dead Nozzle Identification.9.4 Addressing Scheme in SoPEC

SoPEC must address

-   -   20 Mbit DRAM.    -   PCU addressed registers in PEP.    -   CPU-subsystem addressed registers.

SoPEC has a unified address space with the CPU capable of addressing allCPU-subsystem and PCU-bus accessible registers (in PEP) and alllocations in DRAM. The CPU generates byte-aligned addresses for thewhole of SoPEC.

22 bits are sufficient to byte address the whole SoPEC address space.

9.4.1 DRAM Addressing Scheme

The embedded DRAM is composed of 256-bit words. However theCPU-subsystem may need to write individual bytes of DRAM. Therefore itwas decided to make the DIU byte addressable. 22 bits are required tobyte address 20 Mbits of DRAM. Most blocks read or write 256-bit wordsof DRAM. Therefore only the top 17 bits i.e. bits 21 to 5 are requiredto address 256-bit word aligned locations.

The exceptions are

-   -   CDU which can write 64-bits so only the top 19 address bits i.e.        bits 21-3 are required.    -   The CPU-subsystem always generates a 22-bit byte-aligned DIU        address but it will send flags to the DIU indicating whether it        is an 8, 16 or 32-bit write.

All DIU accesses must be within the same 256-bit aligned DRAM word.

9.4.2 PEP Unit DRAM Addressing

PEP Unit configuration registers which specify DRAM locations shouldspecify 256-bit aligned DRAM addresses i.e. using address bits 21:5.Legacy blocks from PEC1 e.g. the LBD and TE may need to specify 64-bitaligned DRAM addresses if these reused blocks DRAM addressing isdifficult to modify. These 64-bit aligned addresses require address bits21:3. However, these 64-bit aligned addresses should be programmed tostart at a 256-bit DRAM word boundary.

Unlike PEC1, there are no constraints in SoPEC on data organization inDRAM except that all data structures must start on a 256-bit DRAMboundary. If data stored is not a multiple of 256-bits then the lastword should be padded.

9.4.3 CPU Subsystem Bus Addressed Registers

The CPU subsystem bus supports 32-bit word aligned read and writeaccesses with variable access timings. See section 11.4 for more detailsof the access protocol used on this bus. The CPU subsystem bus does notcurrently support byte reads and writes but this can be added at a laterdate if required by imported IP.

9.4.4 PCU Addressed Registers in PEP

The PCU only supports 32-bit register reads and writes for the PEPblocks. As the PEP blocks only occupy a subsection of the overalladdress map and the PCU is explicitly selected by the MMU when a PEPblock is being accessed the PCU does not need to perform a decode of thehigher-order address bits. See Table 11 for the PEP subsystem addressmap.

9.5 SoPEC Memory Map

9.5.1 Main Memory Map

The system wide memory map is shown in FIG. 14 below. The memory map isdiscussed in detail in Section 11 11 Central Processing Unit (CPU).

9.5.2 CPU-Bus Peripherals Address Map

The address mapping for the peripherals attached to the CPU-bus is shownin Table 10 below. The MMU performs the decode of cpu_adr[21:12] togenerate the relevant cpu_block_select signal for each block. Theaddressed blocks decode however many of the lower order bits ofcpu_adr[11:2] are required to address all the registers within theblock. TABLE 10 CPU-bus peripherals address map Block_base AddressROM_base 0x0000_0000 MMU_base 0x0001_0000 TIM_base 0x0001_1000 LSS_base0x0001_2000 GPIO_base 0x0001_3000 SCB_base 0x0001_4000 ICU_base0x0001_5000 CPR_base 0x0001_6000 DIU_base 0x0001_7000 PSS_base0x0001_8000 Reserved 0x0001_9000 to 0x0001_FFFF PCU_base 0x0002_0000 to0x0002_BFFF9.5.3 PCU Mapped Registers (PEP Blocks) Address Map

The PEP blocks are addressed via the PCU. From FIG. 14, the PCU mappedregisters are in the range 0x0002_(—)0000 to 0x0002_BFFF. From Table 11it can be seen that there are 12 sub-blocks within the PCU addressspace. Therefore, only four bits are necessary to address each of thesub-blocks within the PEP part of SoPEC. A further 12 bits may be usedto address any configurable register within a PEP block. This givesscope for 1024 configurable registers per sub-block (the PCU mappedregisters are all 32-bit addressed registers so the upper 10 bits arerequired to individually address them). This address will come eitherfrom the CPU or from a command stored in DRAM. The bus is assembled asfollows:

-   -   address[15:12]=sub-block address,        -   address[n:2]=register address within sub-block, only the            number of bits required to decode the registers within each            sub-block are used,        -   address[1:0]=byte address, unused as PCU mapped registers            are all 32-bit addressed registers.

So for the case of the HCU, its addresses range from 0x7000 to 0x7FFFwithin the PEP subsystem or from 0x0002_(—)7000 to 0x0002_(—)7FFF in theoverall system. TABLE 11 PEP blocks address map Block_base AddressPCU_base 0x0002_0000 CDU_base 0x0002_1000 CFU_base 0x0002_2000 LBD_base0x0002_3000 SFU_base 0x0002_4000 TE_base 0x0002_5000 TFU_base0x0002_6000 HCU_base 0x0002_7000 DNC_base 0x0002_8000 DWU_base0x0002_9000 LLU_base 0x0002_A000 PHI_base 0x0002_B000 to 0x0002_BFFF9.6 Buffer Management in SoPEC

As outlined in Section 9.1, SoPEC has a requirement to print 1 sideevery 2 seconds i.e. 30 sides per minute.

9.6.1 Page Buffering

Approximately 2 Mbytes of DRAM are reserved for compressed pagebuffering in SoPEC. If a page is compressed to fit within 2 Mbyte then acomplete page can be transferred to DRAM before printing. However, thetime to transfer 2 Mbyte using USB 1.1 is approximately 2 seconds. Theworst case cycle time to print a page then approaches 4 seconds. Thisreduces the worst-case print speed to 15 pages per minute.

9.6.2 Band Buffering

The SoPEC page-expansion blocks support the notion of page banding. Thepage can be divided into bands and another band can be sent down toSoPEC while we are printing the current band. Therefore we can startprinting once at least one band has been downloaded.

The band size granularity should be carefully chosen to allow efficientuse of the USB bandwidth and DRAM buffer space. It should be smallenough to allow seamless 30 sides per minute printing but not so smallas to introduce excessive CPU overhead in orchestrating the datatransfer and parsing the band headers. Band-finish interrupts have beenprovided to notify the CPU of free buffer space. It is likely that thehost PC will supervise the band transfer and buffer management insteadof the SoPEC CPU.

If SoPEC starts printing before the complete page has been transferredto memory there is a risk of a buffer underrun occurring if subsequentbands are not transferred to SoPEC in time e.g. due to insufficient USBbandwidth caused by another USB peripheral consuming USB bandwidth. Abuffer underrun occurs if a line synchronisation pulse is receivedbefore a line of data has been transferred to the printhead and causesthe print job to fail at that line. If there is no risk of bufferunderrun then printing can safely start once at least one band has beendownloaded.

If there is a risk of a buffer underrun occurring due to an interruptionof compressed page data transfer, then the safest approach is to onlystart printing once we have loaded up the data for a complete page. Thismeans that a worst case latency in the region of 2 seconds (with USB1.1)will be incurred before printing the first page. Subsequent pages willtake 2 seconds to print giving us the required sustained printing rateof 30 sides per minute.

A Storage SoPEC (Section 7.2.5) could be added to the system to provideguaranteed bandwidth data delivery. The print system could also beconstructed using an ISI-Bridge chip (Section 7.2.6) to provideguaranteed data delivery.

The most efficient page banding strategy is likely to be determined on aper page/print job basis and so SoPEC will support the use of bands ofany size.

10 SoPEC Use Cases

10.1 Introduction

This chapter is intended to give an overview of a representative set ofscenarIOs or use cases which SoPEC can perform. SoPEC is by no meansrestricted to the particular use cases described and not every SoPECsystem is considered here.

In this chapter we discuss SoPEC use cases under four headings:

-   1) Normal operation use cases.-   2) Security use cases.-   3) Miscellaneous use cases.-   4) Failure mode use cases.

Use cases for both single and multi-SoPEC systems are outlined.

Some tasks may be composed of a number of sub-tasks.

The realtime requirements for SoPEC software tasks are discussed in “11Central Processing Unit (CPU)” under Section 11.3 Realtime requirements.

10.2 Normal Operation in a single SoPEC System with USB Host Connection

SoPEC operation is broken up into a number of sections which areoutlined below. Buffer management in a SoPEC system is normallyperformed by the host.

10.2.1 Powerup

Powerup describes SoPEC initialisation following an external reset orthe watchdog timer system reset.

A typical powerup sequence is:

-   1) Execute reset sequence for complete SoPEC.-   2) CPU boot from ROM.-   3) Basic configuration of CPU peripherals, SCB and DIU. DRAM    initialisation. USB Wakeup.-   4) Download and authentication of program (see Section 10.5.2).-   5) Execution of program from DRAM.-   6) Retrieve operating parameters from PRINTER_QA and authenticate    operating parameters.-   7) Download and authenticate any further datasets.    10.2.2 USB Wakeup

The CPU can put different sections of SoPEC into sleep mode by writingto registers in the CPR block (chapter 16). Normally the CPU sub-systemand the DRAM will be put in sleep mode but the SCB and power-safestorage (PSS) will still be enabled.

Wakeup describes SoPEC recovery from sleep mode with the SCB andpower-safe storage (PSS) still enabled. In a single SoPEC system, wakeupcan be initiated following a USB reset from the SCB.

A typical USB wakeup sequence is:

-   1) Execute reset sequence for sections of SoPEC in sleep mode.-   2) CPU boot from ROM, if CPU-subsystem was in sleep mode.-   3) Basic configuration of CPU peripherals and DIU, and DRAM    initialisation, if required.-   4) Download and authentication of program using results in    Power-Safe Storage (PSS) (see Section 10.5.2).-   5) Execution of program from DRAM.-   6) Retrieve operating parameters from PRINTER_QA and authenticate    operating parameters.-   7) Download and authenticate using results in PSS of any further    datasets (programs).    10.2.3 Print Initialization

This sequence is typically performed at the start of a print jobfollowing powerup or wakeup:

-   1) Check amount of ink remaining via QA chips.-   2) Download static data e.g. dither matrices, dead nozzle tables    from host to DRAM.-   3) Check printhead temperature, if required, and configure printhead    with firing pulse profile etc. accordingly.-   4) Initiate printhead pre-heat sequence, if required.    10.2.4 First Page Download

Buffer management in a SoPEC system is normally performed by the host.

First page, first band download and processing:

-   1) The host communicates to the SoPEC CPU over the USB to check that    DRAM space remaining is sufficient to download the first band.-   2) The host downloads the first band (with the page header) to DRAM.-   3) When the complete page header has been downloaded the SoPEC CPU    processes the page header, calculates PEP register commands and    writes directly to PEP registers or to DRAM.-   4) If PEP register commands have been written to DRAM, execute PEP    commands from DRAM via PCU.

Remaining bands download and processing:

-   1) Check DRAM space remaining is sufficient to download the next    band.-   2) Download the next band with the band header to DRAM.-   3) When the complete band header has been downloaded, process the    band header according to whichever band-related register updating    mechanism is being used.    10.2.5 Start Printing-   1) Wait until at least one band of the first page has been    downloaded. One approach is to only start printing once we have    loaded up the data for a complete page. If we start printing before    the complete page has been transferred to memory we run the risk of    a buffer underrun occurring because compressed page data was not    transferred to SoPEC in time e.g. due to insufficient USB bandwidth    caused by another USB peripheral consuming USB bandwidth.

2) Start all the PEP Units by writing to their Go registers, via PCUcommands executed from DRAM or direct CPU writes. A rapid startup orderfor the PEP units is outlined in Table 12. TABLE 12 Typical PEP Unitstartup order for printing a page. Step# Unit 1 DNC 2 DWU 3 HCU 4 PHI 5LLU 6 CFU, SFU, TFU 7 CDU 8 TE, LBD

-   3) Print ready interrupt occurs (from PHI).-   4) Start motor control, if first page, otherwise feed the next page.    This step could occur before the print ready interrupt.-   5) Drive LEDs, monitor paper status.-   6) Wait for page alignment via page sensor(s) GPIO interrupt.-   7) CPU instructs PHI to start producing line syncs and hence    commence printing, or wait for an external device to produce line    syncs.-   8) Continue to download bands and process page and band headers for    next page.    10.2.6 Next Page(s) Download

As for first page download, performed during printing of current page.

10.2.7 Between Bands

When the finished band flags are asserted band related registers in theCDU, LBD, TE need to be re-programmed before the subsequent band can beprinted. This can be via PCU commands from DRAM. Typically only 3-5commands per decompression unit need to be executed. These registers canalso be reprogrammed directly by the CPU or most likely by updating fromshadow registers. The finished band flag interrupts the CPU to tell theCPU that the area of memory associated with the band is now free.

10.2.8 During Page Print

Typically during page printing ink usage is communicated to the QAchips.

-   1) Calculate ink printed (from PHI).-   2) Decrement ink remaining (via QA chips).-   3) Check amount of ink remaining (via QA chips). This operation may    be better performed while the page is being printed rather than at    the end of the page.    10.2.9 Page Finish

These operations are typically performed when the page is finished:

-   1) Page finished interrupt occurs from PHI.-   2) Shutdown the PEP blocks by de-asserting their Go registers. A    typical shutdown order is defined in Table 13. This will set the PEP    Unit state-machines to their idle states without resetting their    configuration registers.

3) Communicate ink usage to QA chips, if required. TABLE 13 End of pageshutdown order for PEP Units. Step# Unit 1 PHI (will shutdown by itselfin the normal case at the end of a page) 2 DWU (shutting this downstalls the DNC and therefore the HCU and above) 3 LLU (should already behalted due to PHI at end of last line of page) 4 TE (this is the onlydot supplier likely to be running, halted by the HCU) 5 CDU (this islikely to already be halted due to end of contone band) 6 CFU, SFU, TFU,LBD (order unimportant, and should already be halted due to end of band)7 HCU, DNC (order unimportant, should already have halted)10.2.10 Start of Next Page

These operations are typically performed before printing the next page:

-   1) Re-program the PEP Units via PCU command processing from DRAM    based on page header.-   2) Go to Start printing.    10.2.11 End of Document-   1) Stop motor control.    10.2.12 Sleep Mode

The CPU can put different sections of SoPEC into sleep mode by writingto registers in the CPR block described in Section 16.

-   1) Instruct host PC via USB that SoPEC is about to sleep.-   2) Store reusable authentication results in Power-Safe Storage    (PSS).-   3) Put SoPEC into defined sleep mode.    10.3 Normal Operation in a Multi-SoPEC System—ISIMaster SoPEC

In a multi-SoPEC system the host generally manages program andcompressed page download to all the SoPECs. Inter-SoPEC communication isover the ISI link which will add a latency. In the case of a multi-SoPECsystem with just one USB 1.1 connection, the SoPEC with the USBconnection is the ISIMaster. The ISI-bridge chip is the ISIMaster in thecase of an ISI-Bridge SoPEC configuration. While it is perfectlypossible for an ISISlave to have a direct USB connection to the host wedo not treat this scenario explicitly here to avoid possible confusion.

In a multi-SoPEC system one of the SoPECs will be the PrintMaster. ThisSoPEC must manage and control sensors and actuators e.g. motor control.These sensors and actuators could be distributed over all the SoPECs inthe system. An ISIMaster SoPEC may also be the PrintMaster SoPEC.

In a multi-SoPEC system each printing SoPEC will generally have its ownPRINTER_QA chip (or at least access to a PRINTER_QA chip that containsthe SoPEC's SoPEC_id_key) to validate operating parameters and inkusage. The results of these operations may be communicated to thePrintMaster SoPEC.

In general the ISIMaster may need to be able to:

Send messages to the ISISlaves which will cause the ISISlaves to sendtheir status to the ISIMaster.

Instruct the ISISlaves to perform certain operations.

As the ISI is an insecure interface commands issued over the ISI areregarded as user mode commands. Supervisor mode code running on theSoPEC CPUs will allow or disallow these commands. The software protocolneeds to be constructed with this in mind.

The ISIMaster will initiate all communication with the ISISlaves.

SoPEC operation is broken up into a number of sections which areoutlined below.

10.3.1 Powerup

Powerup describes SoPEC initialisation following an external reset orthe watchdog timer system reset.

-   1) Execute reset sequence for complete SoPEC.-   2) CPU boot from ROM.-   3) Basic configuration of CPU peripherals, SCB and DIU. DRAM    initialisation USB Wakeup-   4) SoPEC identification by activity on USB end-points 2-4 indicates    it is the ISIMaster (unless the SoPEC CPU has explicitly disabled    this function).-   5) Download and authentication of program (see Section 10.5.3).-   6) Execution of program from DRAM.-   7) Retrieve operating parameters from PRINTER_QA and authenticate    operating parameters.-   8) Download and authenticate any further datasets (programs).-   9) The initial dataset may be broadcast to all the ISISlaves.-   10) ISIMaster master SoPEC then waits for a short time to allow the    authentication to take place on the ISISlave SoPECs.-   11) Each ISISlave SoPEC is polled for the result of its program code    authentication process.-   12) If all ISISlaves report successful authentication the OEM code    module can be distributed and authenticated. OEM code will most    likely reside on one SoPEC.    10.3.2 USB Wakeup

The CPU can put different sections of SoPEC into sleep mode by writingto registers in the CPR block [16]. Normally the CPU sub-system and theDRAM will be put in sleep mode but the SCB and power-safe storage (PSS)will still be enabled.

Wakeup describes SoPEC recovery from sleep mode with the SCB andpower-safe storage (PSS) still enabled. For an ISIMaster SoPEC connectedto the host via USB, wakeup can be initiated following a USB reset fromthe SCB.

A typical USB wakeup sequence is:

-   1) Execute reset sequence for sections of SoPEC in sleep mode.-   2) CPU boot from ROM, if CPU-subsystem was in sleep mode.-   3) Basic configuration of CPU peripherals and DIU, and DRAM    initialisation, if required.-   4) SoPEC identification by activity on USB end-points 2-4 indicates    it is the ISIMaster (unless the SoPEC CPU has explicitly disabled    this function).-   5) Download and authentication of program using results in    Power-Safe Storage (PSS) (see Section 10.5.3).-   6) Execution of program from DRAM.-   7) Retrieve operating parameters from PRINTER_QA and authenticate    operating parameters.-   8) Download and authenticate any further datasets (programs) using    results in Power-Safe Storage (PSS) (see Section 10.5.3).-   9) Following steps as per Powerup.    10.3.3 Print Initialization

This sequence is typically performed at the start of a print jobfollowing powerup or wakeup:

-   1) Check amount of ink remaining via QA chips which may be present    on a ISISlave SoPEC.-   2) Download static data e.g. dither matrices, dead nozzle tables    from host to DRAM.-   3) Check printhead temperature, if required, and configure printhead    with firing pulse profile etc. accordingly. Instruct ISISlaves to    also perform this operation.-   4) Initiate printhead pre-heat sequence, if required. Instruct    ISISlaves to also perform this operation    10.3.4 First Page Download

Buffer management in a SoPEC system is normally performed by the host.

-   1) The host communicates to the SoPEC CPU over the USB to check that    DRAM space remaining is sufficient to download the first band.-   2) The host downloads the first band (with the page header) to DRAM.-   3) When the complete page header has been downloaded the SoPEC CPU    processes the page header, calculates PEP register commands and    write directly to PEP registers or to DRAM.-   4) If PEP register commands have been written to DRAM, execute PEP    commands from DRAM via PCU.

Poll ISISlaves for DRAM status and download compressed data toISISlaves.

Remaining first page bands download and processing:

-   1) Check DRAM space remaining is sufficient to download the next    band.-   2) Download the next band with the band header to DRAM.-   3) When the complete band header has been downloaded, process the    band header according to whichever band-related register updating    mechanism is being used.

Poll ISISlaves for DRAM status and download compressed data toISISlaves.

10.3.5 Start Printing

-   1) Wait until at least one band of the first page has been    downloaded.-   2) Start all the PEP Units by writing to their Go registers, via PCU    commands executed from DRAM or direct CPU writes, in the suggested    order defined in Table.-   3) Print ready interrupt occurs (from PHI). Poll ISISlaves until    print ready interrupt.-   4) Start motor control (which may be on an ISISlave SoPEC), if first    page, otherwise feed the next page. This step could occur before the    print ready interrupt.-   5) Drive LEDS, monitor paper status (which may be on an ISISlave    SoPEC).-   6) Wait for page alignment via page sensor(s) GPIO interrupt (which    may be on an ISISlave SoPEC).-   7) If the LineSyncMaster is a SoPEC its CPU instructs PHI to start    producing master line syncs. Otherwise wait for an external device    to produce line syncs.-   8) Continue to download bands and process page and band headers for    next page.    10.3.6 Next Page(s) Download

As for first page download, performed during printing of current page.

10.3.7 Between Bands

When the finished band flags are asserted band related registers in theCDU, LBD and TE need to be re-programmed. This can be via PCU commandsfrom DRAM. Typically only 3-5 commands per decompression unit need to beexecuted. These registers can also be reprogrammed directly by the CPUor by updating from shadow registers. The finished band flag interruptsto the CPU, tell the CPU that the area of memory associated with theband is now free.

10.3.8 During Page Print

Typically during page printing ink usage is communicated to the QAchips.

-   1) Calculate ink printed (from PHI).-   2) Decrement ink remaining (via QA chips).-   3) Check amount of ink remaining (via QA chips). This operation may    be better performed while the page is being printed rather than at    the end of the page.    10.3.9 Page Finish

These operations are typically performed when the page is finished:

-   1) Page finished interrupt occurs from PHI. Poll ISISlaves for page    finished interrupts.-   2) Shutdown the PEP blocks by de-asserting their Go registers in the    suggested order in Table. This will set the PEP Unit state-machines    to their startup states.-   3) Communicate ink usage to QA chips, if required.    10.3.10 Start of Next Page

These operations are typically performed before printing the next page:

-   1) Re-program the PEP Units via PCU command processing from DRAM    based on page header.-   2) Go to Start printing.    10.3.11 End of Document-   1) Stop motor control. This may be on an ISISlave SoPEC.    10.3.12 Sleep Mode

The CPU can put different sections of SoPEC into sleep mode by writingto registers in the CPR block [16]. This may be as a result of a commandfrom the host or as a result of a timeout.

-   1) Inform host PC of which parts of SoPEC system are about to sleep.-   2) Instruct ISISlaves to enter sleep mode.-   3) Store reusable cryptographic results in Power-Safe Storage (PSS).-   4) Put ISIMaster SoPEC into defined sleep mode.    10.4 Normal Operation in a Multi-SoPEC System—ISISlave SoPEC

This section the outline typical operation of an ISISlave SoPEC in amulti-SoPEC system. The ISIMaster can be another SoPEC or an ISI-BridgechIP. The ISISlave communicates with the host either via the ISIMasteror using a direct connection such as USB. For this use case we consideronly an ISISlave that does not have a direct host connection. Buffermanagement in a SoPEC system is normally performed by the host.

10.4.1 Powerup

Powerup describes SoPEC initialisation following an external reset orthe watchdog timer system reset.

A typical powerup sequence is:

-   1) Execute reset sequence for complete SoPEC.-   2) CPU boot from ROM.-   3) Basic configuration of CPU peripherals, SCB and DIU. DRAM    initialisation.-   4) Download and authentication of program (see Section 10.5.3).-   5) Execution of program from DRAM.-   6) Retrieve operating parameters from PRINTER_QA and authenticate    operating parameters.-   7) SoPEC identification by sampling GPIO pins to determine ISIId.    Communicate ISIId to ISIMaster.-   8) Download and authenticate any further datasets.    10.4.2 ISI Wakeup

The CPU can put different sections of SoPEC into sleep mode by writingto registers in the CPR block [16]. Normally the CPU sub-system and theDRAM will be put in sleep mode but the SCB and power-safe storage (PSS)will still be enabled.

Wakeup describes SoPEC recovery from sleep mode with the SCB andpower-safe storage (PSS) still enabled. In an ISISlave SoPEC, wakeup canbe initiated following an ISI reset from the SCB. A typical ISI wakeupsequence is:

-   1) Execute reset sequence for sections of SoPEC in sleep mode.-   2) CPU boot from ROM, if CPU-subsystem was in sleep mode.-   3) Basic configuration of CPU peripherals and DIU, and DRAM    initialisation, if required.-   4) Download and authentication of program using results in    Power-Safe Storage (PSS) (see Section 10.5.3).-   5) Execution of program from DRAM.-   6) Retrieve operating parameters from PRINTER_QA and authenticate    operating parameters.-   7) SoPEC identification by sampling GPIO pins to determine ISIId.    Communicate ISIId to ISIMaster.-   8) Download and authenticate any further datasets.    10.4.3 Print Initialization

This sequence is typically performed at the start of a print jobfollowing powerup or wakeup:

-   1) Check amount of ink remaining via QA chips.-   2) Download static data e.g. dither matrices, dead nozzle tables    from ISI to DRAM.-   3) Check printhead temperature, if required, and configure printhead    with firing pulse profile etc. accordingly.-   4) Initiate printhead pre-heat sequence, if required.    10.4.4 First Page Download

Buffer management in a SoPEC system is normally performed by the hostvia the ISI.

-   1) Check DRAM space remaining is sufficient to download the first    band.-   2) The host downloads the first band (with the page header) to DRAM    via the ISI.-   3) When the complete page header has been downloaded, process the    page header, calculate PEP register commands and write directly to    PEP registers or to DRAM.-   4) If PEP register commands have been written to DRAM, execute PEP    commands from DRAM via PCU.

Remaining first page bands download and processing:

-   1) Check DRAM space remaining is sufficient to download the next    band.-   2) The host downloads the first band (with the page header) to DRAM    via the ISI.-   3) When the complete band header has been downloaded, process the    band header according to whichever band-related register updating    mechanism is being used.    10.4.5 Start Printing-   1) Wait until at least one band of the first page has been    downloaded.-   2) Start all the PEP Units by writing to their Go registers, via PCU    commands executed from DRAM or direct CPU writes, in the order    defined in Table-   3) Print ready interrupt occurs (from PHI). Communicate to    PrintMaster via ISI.-   4) Start motor control, if attached to this ISISlave, when requested    by PrintMaster, if first page, otherwise feed next page. This step    could occur before the print ready interrupt-   5) Drive LEDS, monitor paper status, if on this ISISlave SoPEC, when    requested by PrintMaster-   6) Wait for page alignment via page sensor(s) GPIO interrupt, if on    this ISISlave SoPEC, and send to PrintMaster.-   7) Wait for line sync and commence printing.-   8) Continue to download bands and process page and band headers for    next page.    10.4.6 Next Page(s) Download

As for first band download, performed during printing of current page.

10.4.7 Between Bands

When the finished band flags are asserted band related registers in theCDU, LBD and TE need to be re-programmed. This can be via PCU commandsfrom DRAM. Typically only 3-5 commands per decompression unit need to beexecuted. These registers can also be reprogrammed directly by the CPUor by updating from shadow registers. The finished band flag interruptsto the CPU tell the CPU that the area of memory associated with the bandis now free.

10.4.8 During Page Print

Typically during page printing ink usage is communicated to the QAchips.

-   1) Calculate ink printed (from PHI).-   2) Decrement ink remaining (via QA chips).-   3) Check amount of ink remaining (via QA chips). This operation may    be better performed while the page is being printed rather than at    the end of the page.    10.4.9 Page Finish

These operations are typically performed when the page is finished:

-   1) Page finished interrupt occurs from PHI. Communicate page    finished interrupt to PrintMaster.-   2) Shutdown the PEP blocks by de-asserting their Go registers in the    suggested order in Table. This will set the PEP Unit state-machines    to their startup states.-   3) Communicate ink usage to QA chips, if required.    10.4.10 Start of Next Page

These operations are typically performed before printing the next page:

-   1) Re-program the PEP Units via PCU command processing from DRAM    based on page header.-   2) Go to Start printing.    10.4.11 End of Document

Stop motor control, if attached to this ISISlave, when requested byPrintMaster.

10.4.12 Powerdown

In this mode SoPEC is no longer powered.

-   1) Powerdown ISISlave SoPEC when instructed by ISIMaster.    10.4.13 Sleep

The CPU can put different sections of SoPEC into sleep mode by writingto registers in the CPR block [16]. This may be as a result of a commandfrom the host or ISIMaster or as a result of a timeout.

-   1) Store reusable cryptographic results in Power-Safe Storage (PSS).-   2) Put SoPEC into defined sleep mode.    10.5 Security Use Cases

Please see the ‘SoPEC Security Overview’ [9] document for a morecomplete description of SoPEC security issues. The SoPEC boot operationis described in the ROM chapter of the SoPEC hardware designspecification, Section 17.2.

10.5.1 Communication with the QA Chips

Communication between SoPEC and the QA chips (i.e. INK_QA andPRINTER_QA) will take place on at least a per power cycle and per pagebasis. Communication with the QA chips has three principal purposes:validating the presence of genuine QA chips (i.e the printer is usingapproved consumables), validation of the amount of ink remaining in thecartridge and authenticating the operating parameters for the printer.After each page has been printed, SoPEC is expected to communicate thenumber of dots fired per ink plane to the QA chipset. SoPEC may alsoinitiate decoy communications with the QA chips from time to time.

Process:

-   -   When validating ink consumption SoPEC is expected to principally        act as a conduit between the PRINTER_QA and INK_QA chips and to        take certain actions (basically enable or disable printing and        report status to host PC) based on the result. The communication        channels are insecure but all traffic is signed to guarantee        authenticity.        Known Weaknesses    -   All communication to the QA chips is over the LSS interfaces        using a serial communication protocol. This is open to        observation and so the communication protocol could be reverse        engineered. In this case both the PRINTER_QA and INK_QA chips        could be replaced by impostor devices (e.g. a single FPGA) that        successfully emulated the communication protocol. As this would        require physical modification of each printer this is considered        to be an acceptably low risk. Any messages that are not signed        by one of the symmetric keys (such as the SoPEC_id_key) could be        reverse engineered. The imposter device must also have access to        the appropriate keys to crack the system.    -   If the secret keys in the QA chips are exposed or cracked then        the system, or parts of it, is compromised.        Assumptions:

-   [1] The QA chips are not involved in the authentication of    downloaded SoPEC code

-   [2] The QA chip in the ink cartridge (INK_QA) does not directly    affect the operation of the cartridge in any way i.e. it does not    inhibit the flow of ink etc.

-   [3] The INK_QA and PRINTER_QA chips are identical in their virgin    state. They only become a INK_QA or PRINTER_QA after their FlashROM    has been programmed.    10.5.2 Authentication of Downloaded Code in a Single SoPEC System    Process:

-   1) SoPEC identification by activity on USB end-points 2-4 indicates    it is the ISIMaster (unless the SoPEC CPU has explicitly disabled    this function).

-   2) The program is downloaded to the embedded DRAM.

-   3) The CPU calculates a SHA-1 hash digest of the downloaded program.

-   4) The ResetSrc register in the CPR block is read to determine    whether or not a power-on reset occurred.

-   5) If a power-on reset occurred the signature of the downloaded code    (which needs to be in a known location such as the first or last N    bytes of the downloaded code) is decrypted using the Silverbrook    public boot0key stored in ROM. This decrypted signature is the    expected SHA-1 hash of the accompanying program. The encryption    algorithm is likely to be a public key algorithm such as RSA. If a    power-on reset did not occur then the expected SHA-1 hash is    retrieved from the PSS and the compute intensive decryption is not    required.

-   6) The calculated and expected hash values are compared and if they    match then the programs authenticity has been verified.

-   7) If the hash values do not match then the host PC is notified of    the failure and the SoPEC will await a new program download.

-   8) If the hash values match then the CPU starts executing the    downloaded program.

-   9) If, as is very likely, the downloaded program wishes to download    subsequent programs (such as OEM code) it is responsible for    ensuring the authenticity of everything it downloads. The downloaded    program may contain public keys that are used to authenticate    subsequent downloads, thus forming a hierarchy of authentication.    The SoPEC ROM does not control these authentications—it is solely    concerned with verifying that the first program downloaded has come    from a trusted source.

-   10) At some subsequent point OEM code starts executing. The    Silverbrook supervisor code acts as an O/S to the OEM user mode    code. The OEM code must access most SoPEC functionality via system    calls to the Silverbrook code.

-   11) The OEM code is expected to perform some simple ‘turn on the    lights’ tasks after which the host PC is informed that the printer    is ready to print and the Start Printing use case comes into play.    Known Weaknesses:    -   If the Silverbrook private boot0key is exposed or cracked then        the system is seriously compromised. A ROM mask change would be        required to reprogram the boot0key.        10.5.3 Authentication of Downloaded Code in a Multi-SoPEC System        10.5.3.1 ISIMaster SoPEC Process:

-   1) SoPEC identification by activity on USB end-points 2-4 indicates    it is the ISIMaster.

-   2) The SCB is configured to broadcast the data received from the    host PC.

-   3) The program is downloaded to the embedded DRAM and broadcasted to    all ISISlave SoPECs over the ISI.

-   4) The CPU calculates a SHA-1 hash digest of the downloaded program.

-   5) The ResetSrc register in the CPR block is read to determine    whether or not a power-on reset occurred.

-   6) If a power-on reset occurred the signature of the downloaded code    (which needs to be in a known location such as the first or last N    bytes of the downloaded code) is decrypted using the Silverbrook    public boot0key stored in ROM. This decrypted signature is the    expected SHA-1 hash of the accompanying program. The encryption    algorithm is likely to be a public key algorithm such as RSA. If a    power-on reset did not occur then the expected SHA-1 hash is    retrieved from the PSS and the compute intensive decryption is not    required.

-   7) The calculated and expected hash values are compared and if they    match then the programs authenticity has been verified.

-   8) If the hash values do not match then the host PC is notified of    the failure and the SoPEC will await a new program download.

-   9) If the hash values match then the CPU starts executing the    downloaded program.

-   10) It is likely that the downloaded program will poll each ISISlave    SoPEC for the result of its authentication process and to determine    the number of slaves present and their ISIIds.

-   11) If any ISISlave SoPEC reports a failed authentication then the    ISIMaster communicates this to the host PC and the SoPEC will await    a new program download.

-   12) If all ISISlaves report successful authentication then the    downloaded program is responsible for the downloading,    authentication and distribution of subsequent programs within the    multi-SoPEC system.

-   13) At some subsequent point OEM code starts executing. The    Silverbrook supervisor code acts as an O/S to the OEM user mode    code. The OEM code must access most SoPEC functionality via system    calls to the Silverbrook code.

-   14) The OEM code is expected to perform some simple ‘turn on the    lights’ tasks after which the master SoPEC determines that all    SoPECs are ready to print. The host PC is informed that the printer    is ready to print and the Start Printing use case comes into play.    10.5.3.2 ISISlave SoPEC Process:

-   1) When the CPU comes out of reset the SCB will be in slave mode,    and the SCB is already configured to receive data from both the ISI    and USB.

-   2) The program is downloaded (via ISI or USB) to embedded DRAM.

-   3) The CPU calculates a SHA-1 hash digest of the downloaded program.

-   4) The ResetSrc register in the CPR block is read to determine    whether or not a power-on reset occurred.

-   5) If a power-on reset occurred the signature of the downloaded code    (which needs to be in a known location such as the first or last N    bytes of the downloaded code) is decrypted using the Silverbrook    public boot0key stored in ROM. This decrypted signature is the    expected SHA-1 hash of the accompanying program. The encryption    algorithm is likely to be a public key algorithm such as RSA. If a    power-on reset did not occur then the expected SHA-1 hash is    retrieved from the PSS and the compute intensive decryption is not    required.

-   6) The calculated and expected hash values are compared and if they    match then the programs authenticity has been verified.

-   7) If the hash values do not match, then the ISISlave device will    await a new program again

-   8) If the hash values match then the CPU starts executing the    downloaded program.

-   9) It is likely that the downloaded program will communicate the    result of its authentication process to the ISIMaster. The    downloaded program is responsible for determining the SoPECs ISIID,    receiving and authenticating any subsequent programs.

-   10) At some subsequent point OEM code starts executing. The    Silverbrook supervisor code acts as an O/S to the OEM user mode    code. The OEM code must access most SoPEC functionality via system    calls to the Silverbrook code.

-   11) The OEM code is expected to perform some simple ‘turn on the    lights’ tasks after which the master SoPEC is informed that this    slave is ready to print. The Start Printing use case then comes into    play.    Known Weaknesses    -   If the Silverbrook private boot0key is exposed or cracked then        the system is seriously compromised.    -   ISI is an open interface i.e. messages sent over the ISI are in        the clear. The communication channels are insecure but all        traffic is signed to guarantee authenticity. As all        communication over the ISI is controlled by Supervisor code on        both the ISIMaster and ISISlave then this also provides some        protection against software attacks.        10.5.4 Authentication and Upgrade of Operating Parameters for a        Printer

The SoPEC IC will be used in a range of printers with differentcapabilities (e.g. A3/A4 printing, printing speed, resolution etc.). Itis expected that some printers will also have a software upgradecapability which would allow a user to purchase a license that enablesan upgrade in their printer's capabilities (such as print speed). Tofacilitate this it must be possible to securely store the operatingparameters in the PRINTER_QA chip, to securely communicate theseparameters to the SoPEC and to securely reprogram the parameters in theevent of an upgrade. Note that each printing SoPEC (as opposed to aSoPEC that is only used for the storage of data) will have its ownPRINTER_QA chip (or at least access to a PRINTER_QA that contains theSoPEC's SoPEC_id_key). Therefore both ISIMaster and ISISlave SoPECs willneed to authenticate operating parameters.

Process:

-   1) Program code is downloaded and authenticated as described in    sections 10.5.2 and 10.5.3 above.-   2) The program code has a function to create the SoPEC_id_key from    the unique SoPEC_id that was programmed when the SoPEC was    manufactured.-   3) The SoPEC retrieves the signed operating parameters from its    PRINTER_QA chIP. The PRINTER_QA chip uses the SoPEC_id_key (which is    stored as part of the pairing process executed during printhead    assembly manufacture & test) to sign the operating parameters which    are appended with a random number to thwart replay attacks.-   4) The SoPEC checks the signature of the operating parameters using    its SoPEC_id_-key. If this signature authentication process is    successful then the operating parameters are considered valid and    the overall boot process continues. If not the error is reported to    the host PC.-   5) Operating parameters may also be set or upgraded using a second    key, the PrintEngineLicense_key, which is stored on the PRINTER_QA    and used to authenticate the change in operating parameters.    Known Weaknesses:    -   It may be possible to retrieve the unique SoPEC_id by placing        the SoPEC in test mode and scanning it out. It is certainly        possible to obtain it by reverse engineering the device. Either        way the SoPEC_id (and by extension the SoPEC_id_key) so obtained        is valid only for that specific SoPEC and so printers may only        be compromised one at a time by parties with the appropriate        specialised equipment. Furthermore even if the SoPEC_id is        compromised, the other keys in the system, which protect the        authentication of consumables and of program code, are        unaffected.        10.6 Miscellaneous Use Cases

There are many miscellaneous use cases such as the following examples.Software running on the SoPEC CPU or host will decide on what actions totake in these scenarios.

10.6.1 Disconnect/Re-Connect of QA Chips.

-   1) Disconnect of a QA chip between documents or if ink runs out    mid-document.-   2) Re-connect of a QA chip once authenticated e.g. ink cartridge    replacement should allow the system to resume and print the next    document    10.6.2 Page Arrives Before Print Ready Interrupt.-   1) Engage clutch to stop paper until print ready interrupt occurs.    10.6.3 Dead-Nozzle Table Upgrade

This sequence is typically performed when dead nozzle information needsto be updated by performing a printhead dead nozzle test.

-   1) Run printhead nozzle test sequence-   2) Either host or SoPEC CPU converts dead nozzle information into    dead nozzle table.-   3) Store dead nozzle table on host.-   4) Write dead nozzle table to SoPEC DRAM.    10.7 Failure Mode Use Cases    10.7.1 System Errors and Security Violations

System errors and security violations are reported to the SoPEC CPU andhost. Software running on the SoPEC CPU or host will then decide whatactions to take.

Silverbrook code authentication failure.

-   1) Notify host PC of authentication failure.-   2) Abort print run.

OEM code authentication failure.

-   1) Notify host PC of authentication failure.-   2) Abort print run.

Invalid QA chip(s).

-   1) Report to host PC.-   2) Abort print run.

MMU security violation interrupt.

-   1) This is handled by exception handler.-   2) Report to host PC-   3) Abort print run.

Invalid address interrupt from PCU.

-   1) This is handled by exception handler.-   2) Report to host PC.-   3) Abort print run.

Watchdog timer interrupt.

-   1) This is handled by exception handler.-   2) Report to host PC.-   3) Abort print run.

Host PC does not acknowledge message that SoPEC is about to power down.

-   1) Power down anyway.    10.7.2 Printing Errors

Printing errors are reported to the SoPEC CPU and host. Software runningon the host or SoPEC CPU will then decide what actions to take.

Insufficient space available in SoPEC compressed band-store to downloada band.

-   1) Report to the host PC.

Insufficient ink to print.

-   1) Report to host PC.

Page not downloaded in time while printing.

-   1) Buffer underrun interrupt will occur.-   2) Report to host PC and abort print run.

JPEG decoder error interrupt.

-   1) Report to host PC.    CPU Subsystem    11 Central Processing Unit (CPU)    11.1 Overview

The CPU block consists of the CPU core, MMU, cache and associated logic.The principal tasks for the program running on the CPU to fulfill in thesystem are:

Communications:

-   -   Control the flow of data from the USB interface to the DRAM and        ISI    -   Communication with the host via USB or ISI    -   Running the USB device driver        PEP Subsystem Control:    -   Page and band header processing (may possibly be performed on        host PC)    -   Configure printing options on a per band, per page, per job or        per power cycle basis    -   Initiate page printing operation in the PEP subsystem    -   Retrieve dead nozzle information from the printhead interface        (PHI) and forward to the host PC    -   Select the appropriate firing pulse profile from a set of        predefined profiles based on the printhead characteristics    -   Retrieve printhead temperature via the PHI        Security:    -   Authenticate downloaded program code    -   Authenticate printer operating parameters    -   Authenticate consumables via the PRINTER_QA and INK_QA chips    -   Monitor ink usage    -   Isolation of OEM code from direct access to the system resources        Other:    -   Drive the printer motors using the GPIO pins    -   Monitoring the status of the printer (paper jam, tray empty        etc.)    -   Driving front panel LEDs    -   Perform post-boot initialisation of the SoPEC device    -   Memory management (likely to be in conjunction with the host PC)    -   Miscellaneous housekeeping tasks

To control the Print Engine Pipeline the CPU is required to provide alevel of performance at least equivalent to a 16-bit Hitachi H8-3664microcontroller running at 16 MHz. An as yet undetermined amount ofadditional CPU performance is needed to perform the other tasks, as wellas to provide the potential for such activity as Netpage page assemblyand processing, RIPing etc. The extra performance required is dominatedby the signature verification task and the SCB (including the USB)management task. An operating system is not required at present. Anumber of CPU cores have been evaluated and the LEON P1754 is consideredto be the most appropriate solution. A diagram of the CPU block is shownin FIG. 15 below.

11.2 Definitions of I/Os TABLE 14 CPU Subsystem I/Os Port name Pins I/ODescription Clocks and Resets prst_n 1 In Global reset. Synchronous topclk, active low. Pclk 1 In Global clock CPU to DIU DRAM interfacecpu_adr[21:2] 20 Out Address bus for both DRAM and peripheral accesscpu_dataout[31:0] 32 Out Data out to both DRAM and peripheral devices.This should be driven at the same time as the cpu_adr and requestsignals. dram_cpu_data[255:0] 256 In Read data from the DRAMcpu_diu_rreq 1 Out Read request to the DIU DRAM diu_cpu_rack 1 InAcknowledge from DIU that read request has been accepted. diu_cpu_rvalid1 In Signal from DIU telling SoPEC Unit that valid read data is on thedram_cpu_data bus cpu_diu_wdatavalid 1 Out Signal from the CPU to theDIU indicating that the data currently on the cpu_diu_wdata bus is validand should be committed to the DIU posted write buffer diu_cpu_write_rdy1 In Signal from the DIU indicating that the posted write buffer isempty cpu_diu_wdadr[21:4] 18 Out Write address bus to the DIUcpu_diu_wdata[127:0] 128 Out Write data bus to the DIUcpu_diu_wmask[15:0] 16 Out Write mask for the cpu_diu_wdata bus. Eachbit corresponds to a byte of the 128-bit cpu_diu_wdata bus. CPU toperipheral blocks cpu_rwn 1 Out Common read/not-write signal from theCPU cpu_acode[1:0] 2 Out CPU access code signals. cpu_acode[0] - Program(0)/Data (1) access cpu_acode[1] - User (0)/Supervisor (1) accesscpu_cpr_sel 1 Out CPR block select. cpr_cpu_rdy 1 In Ready signal to theCPU. When cpr_cpu_rdy is high it indicates the last cycle of the access.For a write cycle this means cpu_dataout has been registered by the CPRblock and for a read cycle this means the data on cpr_cpu_data is valid.cpr_cpu_berr 1 In CPR bus error signal to the CPU. cpr_cpu_data[31:0] 32In Read data bus from the CPR block cpu_gpio_sel 1 Out GPIO blockselect. gpio_cpu_rdy 1 In GPIO ready signal to the CPU. gpio_cpu_berr 1In GPIO bus error signal to the CPU. gpio_cpu_data[31:0] 32 In Read databus from the GPIO block cpu_icu_sel 1 Out ICU block select. icu_cpu_rdy1 In ICU ready signal to the CPU. icu_cpu_berr 1 In ICU bus error signalto the CPU. icu_cpu_data[31:0] 32 In Read data bus from the ICU blockcpu_lss_sel 1 Out LSS block select. lss_cpu_rdy 1 In LSS ready signal tothe CPU. lss_cpu_berr 1 In LSS bus error signal to the CPU.lss_cpu_data[31:0] 32 In Read data bus from the LSS block cpu_pcu_sel 1Out PCU block select. pcu_cpu_rdy 1 In PCU ready signal to the CPU.pcu_cpu_berr 1 In PCU bus error signal to the CPU. pcu_cpu_data[31:0] 32In Read data bus from the PCU block cpu_scb_sel 1 Out SCB block select.scb_cpu_rdy 1 In SCB ready signal to the CPU. scb_cpu_berr 1 In SCB buserror signal to the CPU. scb_cpu_data[31:0] 32 In Read data bus from theSCB block cpu_tim_sel 1 Out Timers block select. tim_cpu_rdy 1 In Timersblock ready signal to the CPU. tim_cpu_berr 1 In Timers bus error signalto the CPU. tim_cpu_data[31:0] 32 In Read data bus from the Timers blockcpu_rom_sel 1 Out ROM block select. rom_cpu_rdy 1 In ROM block readysignal to the CPU. rom_cpu_berr 1 In ROM bus error signal to the CPU.rom_cpu_data[31:0] 32 In Read data bus from the ROM block cpu_pss_sel 1Out PSS block select. pss_cpu_rdy 1 In PSS block ready signal to theCPU. pss_cpu_berr 1 In PSS bus error signal to the CPU.pss_cpu_data[31:0] 32 In Read data bus from the PSS block cpu_diu_sel 1Out DIU register block select. diu_cpu_rdy 1 In DIU register block readysignal to the CPU. diu_cpu_berr 1 In DIU bus error signal to the CPU.diu_cpu_data[31:0] 32 In Read data bus from the DIU block Interruptsignals icu_cpu_ilevel[3:0] 3 In An interrupt is asserted by driving theappropriate priority level on icu_cpu_ilevel. These signals must remainasserted until the CPU executes an interrupt acknowledge cycle. 3 OutIndicates the level of the interrupt the CPU is acknowledging whencpu_iack is high cpu_iack 1 Out Interrupt acknowledge signal. The exacttiming depends on the CPU core implementation Debug signalsdiu_cpu_debug_valid 1 In Signal indicating the data on the diu_cpu_databus is valid debug data. tim_cpu_debug_valid 1 In Signal indicating thedata on the tim_cpu_data bus is valid debug data. scb_cpu_debug_valid 1In Signal indicating the data on the scb_cpu_data bus is valid debugdata. pcu_cpu_debug_valid 1 In Signal indicating the data on thepcu_cpu_data bus is valid debug data. lss_cpu_debug_valid 1 In Signalindicating the data on the lss_cpu_data bus is valid debug data.icu_cpu_debug_valid 1 In Signal indicating the data on the icu_cpu_databus is valid debug data. gpio_cpu_debug_valid 1 In Signal indicating thedata on the gpio_cpu_data bus is valid debug data. cpr_cpu_debug_valid 1In Signal indicating the data on the cpr_cpu_data bus is valid debugdata. debug_data_out 32 Out Output debug data to be muxed on to the GPIO& PHI pins debug_data_valid 1 Out Debug valid signal indicating thevalidity of the data on debug_data_out. This signal is used in all debugconfigurations debug_cntrl 33 Out Control signal for each PHI bounddebug data line indicating whether or not the debug data should beselected by the pin mux11.3 Realtime Requirements

The SoPEC realtime requirements have yet to be fully determined but theymay be split into three categories: hard, firm and soft

11.3.1 Hard Realtime Requirements

Hard requirements are tasks that must be completed before a certaindeadline or failure to do so will result in an error perceptible to theuser (printing stops or functions incorrectly). There are three hardrealtime tasks:

-   -   Motor control: The motors which feed the paper through the        printer at a constant speed during printing are driven directly        by the SoPEC device. Four periodic signals with different phase        relationships need to be generated to ensure the paper travels        smoothly through the printer. The generation of these signals is        handled by the GPIO hardware (see section 13.2 for more details)        but the CPU is responsible for enabling these signals (i.e. to        start or stop the motors) and coordinating the movement of the        paper with the printing operation of the printhead.    -   Buffer management: Data enters the SoPEC via the SCB at an        uneven rate and is consumed by the PEP subsystem at a different        rate. The CPU is responsible for managing the DRAM buffers to        ensure that neither overrun nor underrun occur. This buffer        management is likely to be performed under the direction of the        host.    -   Band processing: In certain cases PEP registers may need to be        updated between bands. As the timing requirements are most        likely too stringent to be met by direct CPU writes to the PCU a        more likely scenario is that a set of shadow registers will        programmed in the compressed page units before the current band        is finished, copied to band related registers by the finished        band signals and the processing of the next band will continue        immediately. An alternative solution is that the CPU will        construct a DRAM based set of commands (see section 21.8.5 for        more details) that can be executed by the PCU. The task for the        CPU here is to parse the band headers stored in DRAM and        generate a DRAM based set of commands for the next number of        bands. The location of the DRAM based set of commands must then        be written to the PCU before the current band has been processed        by the PEP subsystem. It is also conceivable (but currently        considered unlikely) that the host PC could create the DRAM        based commands. In this case the CPU will only be required to        point the PCU to the correct location in DRAM to execute        commands from.        11.3.2 Firm Requirements

Firm requirements are tasks that should be completed by a certain timeor failure to do so will result in a degradation of performance but notan error. The majority of the CPU tasks for SoPEC fall into thiscategory including all interactions with the QA chips, programauthentication, page feeding, configuring PEP registers for a page orjob, determining the firing pulse profile, communication of printerstatus to the host over the USB and the monitoring of ink usage. Theauthentication of downloaded programs and messages will be the mostcompute intensive operation the CPU will be required to perform. Initialinvestigations indicate that the LEON processor, running at 160 MHz,will easily perform three authentications in under a second. TABLE 15Expected firm requirements Requirement Duration Power-on to start ofprinting first page [USB   ˜8 secs ?? and slave SoPEC enumeration, 3 ormore RSA signature verifications, code and compressed page data downloadand chip initialisation] Wake-up from sleep mode to start printing [3 ormore   ˜2 secs SHA-1/RSA operations, code and compressed page datadownload and chip re-initialisation Authenticate ink usage in theprinter ˜0.5 secs Determining firing pulse profile ˜0.1 secs Pagefeeding, gap between pages OEM dependent Communication of printer statusto host PC  ˜10 ms Configuring PEP registers ??11.3.3 Soft Requirements

Soft requirements are tasks that need to be done but there are onlylight time constraints on when they need to be done. These tasks areperformed by the CPU when there are no pending higher priority tasks. Asthe SoPEC CPU is expected to be lightly loaded these tasks will mostlybe executed soon after they are scheduled.

11.4 Bus Protocols

As can be seen from FIG. 15 above there are different buses in the CPUblock and different protocols are used for each bus. There are threebuses in operation:

11.4.1 AHB Bus

The LEON CPU core uses an AMBA2.0 AHB bus to communicate with memory andperipherals (usually via an APB bridge). See the AMBA specification[38], section 5 of the LEON users manual [37] and section 11.6.6.1 ofthis document for more details.

11.4.2 CPU to DIU Bus

This bus conforms to the DIU bus protocol described in Section 20.14.8.Note that the address bus used for DIU reads (i.e. cpu_adr(21:2)) isalso that used for CPU subsystem with bus accesses while the writeaddress bus (cpu_diu_wadr) and the read and write data buses(dram_cpu_data and cpu_diu_wdata) are private buses between the CPU andthe DIU. The effective bus width differs between a read (256 bits) and awrite (128 bits). As certain CPU instructions may require byte writeaccess this will need to be supported by both the DRAM write buffer (inthe AHB bridge) and the DIU. See section 11.6.6.1 for more details.

11.4.3 CPU Subsystem Bus

For access to the on-chip peripherals a simple bus protocol is used. TheMMU must first determine which particular block is being addressed (andthat the access is a valid one) so that the appropriate block selectsignal can be generated. During a write access CPU write data is drivenout with the address and block select signals in the first cycle of anaccess. The addressed slave peripheral responds by asserting its readysignal indicating that it has registered the write data and the accesscan complete. The write data bus is common to all peripherals and isalso used for CPU writes to the embedded DRAM. A read access isinitiated by driving the address and select signals during the firstcycle of an access. The addressed slave responds by placing the readdata on its bus and asserting its ready signal to indicate to the CPUthat the read data is valid. Each block has a separate point-to-pointdata bus for read accesses to avoid the need for a tri-stateable bus.All peripheral accesses are 32-bit (Programming note: char or short Ctypes should not be used to access peripheral registers). The use of theready signal allows the accesses to be of variable length. In most casesaccesses will complete in two cycles but three or four (or more) cyclesaccesses are likely for PEP blocks or IP blocks with a different nativebus interface. All PEP blocks are accessed via the PCU which acts as abridge. The PCU bus uses a similar protocol to the CPU subsystem bus butwith the PCU as the bus master.

The duration of accesses to the PEP blocks is influenced by whether ornot the PCU is executing commands from DRAM. As these commands areessentially register writes the CPU access will need to wait until thePCU bus becomes available when a register access has been completed.This could lead to the CPU being stalled for up to 4 cycles if itattempts to access PEP blocks while the PCU is executing a command. Thesize and probability of this penalty is sufficiently small to have anysignificant impact on performance.

In order to support user mode (i.e. OEM code) access to certainperipherals the CPU subsystem bus propagates the CPU function codesignals (cpu_acode[1:0]). These signals indicate the type of addressspace (i.e. User/Supervisor and Program/Data) being accessed by the CPUfor each access. Each peripheral must determine whether or not the CPUis in the correct mode to be granted access to its registers and in somecases (e.g. Timers and GPIO blocks) different access permissions canapply to different registers within the block. If the CPU is not in thecorrect mode then the violation is flagged by asserting the block's buserror signal (block_cpu_berr) with the same timing as its ready signal(block_cpu_rdy) which remains deasserted. When this occurs invalid readaccesses should return 0 and write accesses should have no effect.

FIG. 16 shows two examples of the peripheral bus protocol in action. Awrite to the LSS block from code running in supervisor mode issuccessfully completed. This is immediately followed by a read from aPEP block via the PCU from code running in user mode. As this type ofaccess is not permitted the access is terminated with a bus error. Thebus error exception processing then starts directly after this—nofurther accesses to the peripheral should be required as the exceptionhandler should be located in the DRAM.

Each peripheral acts as a slave on the CPU subsystem bus and itsbehavior is described by the state machine in section 11.4.3.1

11.4.3.1 CPU Subsystem Bus Slave State Machine

CPU subsystem bus slave operation is described by the state machine inFIG. 17. This state machine will be implemented in each CPU subsystembus slave. The only new signals mentioned here are the valid_access andreg_available signals. The valid_access is determined by comparing thecpu_acode value with the block or register (in the case of a block thatallow user access on a per register basis such as the GPIO block) accesspermissions and asserting valid_access if the permissions agree with theCPU mode. The reg_available signal is only required in the PCU or inblocks that are not capable of two-cycle access (e.g. blocks containingimported IP with different bus protocols). In these blocks thereg_available signal is an internal signal used to insert wait states(by delaying the assertion of block_cpu_rdy) until the CPU bus slaveinterface can gain access to the register.

When reading from a register that is less than 32 bits wide the CPUsubsystems bus slave should return zeroes on the unused upper bits ofthe block_cpu_data bus.

To support debug mode the contents of the register selected for debugobservation, debug_reg, are always output on the block_cpu_data buswhenever a read access is not taking place. See section

11.8 for More Details of Debug Operation.

11.5 LEON CPU

The LEON processor is an open-source implementation of the IEEE-1754standard (SPARC V8) instruction set. LEON is available from and activelysupported by Gaisler Research (www.gaisler.com).

The following features of the LEON-2 processor will be utilised onSoPEC:

-   -   IEEE-1754 (SPARC V8) compatible integer unit with 5-stage        pipeline    -   Separate instruction and data cache (Harvard architecture). 1        kbyte direct mapped caches will be used for both.    -   Full implementation of AMBA-2.0 AHB on-chip bus

The standard release of LEON incorporates a number of peripherals andsupport blocks which will not be included on SoPEC. The LEON core asused on SoPEC will consist of: 1) the LEON integer unit, 2) theinstruction and data caches (currently 1 kB each), 3) the cache controllogic, 4) the AHB interface and 5) possibly the AHB controller (althoughthis functionality may be implemented in the LEON AHB bridge).

The version of the LEON database that the SoPEC LEON components will besourced from is LEON2-1.0.7 although later versions may be used if theyoffer worthwhile functionality or bug fixes that affect the SoPECdesign.

The LEON core will be clocked using the system clock, pclk, and resetusing the prst_n_section[1] signal. The ICU will assert all the hardwareinterrupts using the protocol described in section 11.9. The LEONhardware multipliers and floating-point unit are not required. SoPECwill use the recommended 8 register window configuration.

Further details of the SPARC V8 instruction set and the LEON processorcan be found in [36] and [37] respectively.

11.5.1 LEON Registers

Only two of the registers described in the LEON manual are implementedon SoPEC—the LEON configuration register and the Cache Control Register(CCR). The addresses of these registers are shown in Table 16. Theconfiguration register bit fields are described below and the CCR isdescribed in section 11.7.1.1.

11.5.1.1 LEON Configuration Register

The LEON configuration register allows runtime software to determine thesettings of LEONs various configuration options. This is a read-onlyregister whose value for the SoPEC ASIC will be 0x1071_(—)8C00. Furtherdescriptions of many of the bitfileds can be found in the LEON manual.The values used for SoPEC are highlighted in bold for clarity. TABLE 16LEON Configuration Register Field Name bit(s) DescriptionWriteProtection 1:0 Write protection type. 00 - none 01 - standardPCICore 3:2 PCI core type 00 - none 01 - InSilicon 10 - ESA 11 - OtherFPUType 5:4 FPU type. 00 - none 01 - Meiko MemStatus 6 0 - No memorystatus and failing address register present 1 - Memory status andfailing address register present Watchdog 7 0 - Watchdog timer notpresent (Note this refers to the LEON watchdog timer in the LEON timerblock). 1 - Watchdog timer present UMUL/SMUL 8 0 - UMUL/SMULinstructions are not implemented 1 - UMUL/SMUL instructions areimplemented UDIV/SDIV 9 0 - UMUL/SMUL instructions are not implemented1 - UMUL/SMUL instructions are implemented DLSZ 11:10 Data cache linesize in 32-bit words: 00 - 1 word 01 - 2 words 10 - 4 words 11 - 8 wordsDCSZ 14:12 Data cache size in kBbytes = 2^(DCSZ). SoPEC DCSZ = 0. ILSZ16:15 Instruction cache line size in 32-bit words: 00 - 1 word 01 - 2words 10 - 4 words 11 - 8 words ICSZ 19:17 Instruction cache size inkBbytes = 2^(ICSZ). SoPEC ICSZ = 0. RegWin 24:20 The implemented numberof SPARC register windows −1. SoPEC value = 7. UMAC/SMAC 25  0 -UMAC/SMAC instructions are not implemented 1 - UMAC/SMAC instructionsare implemented Watchpoints 28:26 The implemented number of hardwarewatchpoints. SoPEC value = 4. SDRAM 29  0 - SDRAM controller not present1 - SDRAM controller present DSU 30  0 - Debug Support Unit not present1 - Debug Support Unit present Reserved 31  Reserved. SoPEC value = 0.11.6 Memory Management Unit (MMU)

Memory Management Units are typically used to protect certain regions ofmemory from invalid accesses, to perform address translation for avirtual memory system and to maintain memory page status (swapped-in,swapped-out or unmapped)

The SoPEC MMU is a much simpler affair whose function is to ensure thatall regions of the SoPEC memory map are adequately protected. The MMUdoes not support virtual memory and physical addresses are used at alltimes. The SoPEC MMU supports a full 32-bit address space. The SoPECmemory map is depicted in FIG. 18 below.

The MMU selects the relevant bus protocol and generates the appropriatecontrol signals depending on the area of memory being accessed. The MMUis responsible for performing the address decode and generation of theappropriate block select signal as well as the selection of the correctblock read bus during a read access. The MMU will need to support all ofthe bus transactions the CPU can produce including interrupt acknowledgecycles, aborted transactions etc. When an MMU error occurs (such as anattempt to access a supervisor mode only region when in user mode) a buserror is generated. While the LEON can recognise different types of buserror (e.g. data store error, instruction access error) it handles themin the same manner as it handles all traps i.e it will transfer controlto a trap handler. No extra state information is be stored because ofthe nature of the trap. The location of the trap handler is contained inthe TBR (Trap Base Register). This is the same mechanism as is used tohandle interrupts.

11.6.1 CPU-Bus Peripherals Address Map

The address mapping for the peripherals attached to the CPU-bus is shownin Table 17 below. The MMU performs the decode of the high order bits togenerate the relevant cpu_block_select signal. Apart from the PCU, whichdecodes the address space for the PEP blocks, each block only needs todecode as many bits of cpu_adr[1 1:2] as required to address all theregisters within the block. TABLE 17 CPU-bus peripherals address mapBlock_base Address ROM_base 0x0000_0000 MMU_base 0x0001_0000 TIM_base0x0001_1000 LSS_base 0x0001_2000 GPIO_base 0x0001_3000 SCB_base0x0001_4000 ICU_base 0x0001_5000 CPR_base 0x0001_6000 DIU_base0x0001_7000 PSS_base 0x0001_8000 Reserved 0x0001_9000 to 0x0001_FFFFPCU_base 0x0002_000011.6.2 DRAM Region Mapping

The embedded DRAM is broken into 8 regions, with each region defined bya lower and upper bound address and with its own access permissions.

The association of an area in the DRAM address space with a MMU regionis completely under software control. Table 18 below gives one possibleregion mapping. Regions should be defined according to their accessrequirements and position in memory. Regions that share the same accessrequirements and that are contiguous in memory may be combined into asingle region. The example below is purely for indicative purposes—realmappings are likely to differ significantly from this. Note that theRegionBottom and RegionTop fields in this example include the DRAM baseaddress offset (0x4000_(—)0000) which is not required when programmingthe RegionNTop and RegionNBottom registers. For more details, see11.6.5.1 and 11.6.5.2. TABLE 18 Example region mapping RegionRegionBottom RegionTop Description 0 0x4000_0000 0x4000_0FFF SilverbrookOS (supervisor) data 1 0x4000_1000 0x4000_BFFF Silverbrook OS(supervisor) code 2 0x4000_C000 0x4000_C3FF Silverbrook(supervisor/user) data 3 0x4000_C400 0x4000_CFFF Silverbrook(supervisor/user) code 4 0x4026_D000 0x4026_D3FF OEM (user) data 50x4026_D400 0x4026_DFFF OEM (user) code 6 0x4027_E000 0x4027_FFFF SharedSilverbrook/OEM space 7 0x4000_D000 0x4026_CFFF Compressed page store(supervisor data)11.6.3 Non-DRAM Regions

As shown in FIG. 18 the DRAM occupies only 2.5 MBytes of the total 4 GBSoPEC address space. The non-DRAM regions of SoPEC are handled by theMMU as follows:

ROM (1x0000_(—)000 to 1x0000_FFFF): The ROM block will control theaccess types allowed. The cpu_acode[1:0] signals will indicate the CPUmode and access type and the ROM block will assert rom_cpu_berr if anattempted access is forbidden. The protocol is described in more detailin section 11.4.3. The ROM block access permissions are hard wired toallow all read accesses except to the FuseChipID registers which mayonly be read in supervisor mode.

MMU Internal Registers (0x0001_(—)0000 to 1x0001_(—)0FFF): The MMU isresponsible for controlling the accesses to its own internal registersand will only allow data reads and writes (no instruction fetches) fromsupervisor data space. All other accesses will result in themmu_cpu_berr signal being asserted in accordance with the CPU native busprotocol.

CPU Subsystem Peripheral Registers (1x0001_(—)1000 to 1x0001_FFFF): Eachperipheral block will control the access types allowed. Every peripheralwill allow supervisor data accesses (both read and write) and someblocks (e.g. Timers and GPIO) will also allow user data space accessesas outlined in the relevant chapters of this specification. Neithersupervisor nor user instruction fetch accesses are allowed to any blockas it is not possible to execute code from peripheral registers. The busprotocol is described in section 11.4.3.

PCU Mapped Registers (0x0002_(—)0000 to 0x0002_BFFF): All of the PEPblocks registers which are accessed by the CPU via the PCU will inheritthe access permissions of the PCU. These access permissions are hardwired to allow supervisor data accesses only and the protocol used isthe same as for the CPU peripherals.

Unused address space (0x0002_C000 to 0x3FFF_FFFF and 0x4028_(—)0000 to1xFFFF_FFFF): All accesses to the unused portion of the address spacewill result in the mmu_cpu_berr signal being asserted in accordance withthe CPU native bus protocol. These accesses will not propagate outsideof the MMU i.e. no external access will be initiated.

11.6.4 Reset Exception Vector and Reference Zero Traps

When a reset occurs the LEON processor starts executing code fromaddress 0x0000_(—)0000. A common software bug is zero-referencing ornull pointer de-referencing (where the program attempts to access thecontents of address 0x0000_(—)0000). To assist software debug the MMUwill assert a bus error every time the locations 0x0000_(—)0000 to0x0000_(—)000F (i.e. the first 4 words of the reset trap) are accessedafter the reset trap handler has legitimately been retrieved immediatelyafter reset.

11.6.5 MMU Configuration Registers

The MMU configuration registers include the RDU configuration registersand two LEON registers. Note that all the MMU configuration registersmay only be accessed when the CPU is running in supervisor mode. TABLE19 MMU Configuration Registers Address offset from MMU_base Register#bits Reset Description 0x00 Region0Bottom[21:5] 17 0x0_0000 Thisregister contains the physical address that marks the bottom of region 00x04 Region0Top[21:5] 17 0xF_FFFF This register contains the physicaladdress that marks the top of region 0. Region 0 covers the entireaddress space after reset whereas all other regions are zero-sizedinitially. 0x08 Region1Bottom[21:5] 17 0xF_FFFF This register containsthe physical address that marks the bottom of region 1 0x0CRegion1Top[21:5] 17 0x0_0000 This register contains the physical addressthat marks the top of region 1 0x10 Region2Bottom[21:5] 17 0xF_FFFF Thisregister contains the physical address that marks the bottom of region 20x14 Region3Top[21:5] 17 0x0_0000 This register contains the physicaladdress that marks the top of region 2 0x18 Region3Bottom[21:5] 170xF_FFFF This register contains the physical address that marks thebottom of region 3 0x1C Region3Top[21:5] 17 0x0_0000 This registercontains the physical address that marks the top of region 3 0x20Region4Bottom[21:5] 17 0xF_FFFF This register contains the physicaladdress that marks the bottom of region 4 0x24 Region4Top[21:5] 170x0_0000 This register contains the physical address that marks the topof region 4 0x28 Region5Bottom[21:5] 17 0xF_FFFF This register containsthe physical address that marks the bottom of region 5 0x2CRegion5Top[21:5] 17 0x0_0000 This register contains the physical addressthat marks the top of region 5 0x30 Region6Bottom[21:5] 17 0xF_FFFF Thisregister contains the physical address that marks the bottom of region 60x34 Region6Top[21:5] 17 0x0_0000 This register contains the physicaladdress that marks the top of region 6 0x38 Region7Bottom[21:5] 170xF_FFFF This register contains the physical address that marks thebottom of region 7 0x3C Region7Top[21:5] 17 0x0_0000 This registercontains the physical address that marks the top of region 7 0x40Region0Control 6 0x07 Control register for region 0 0x44 Region1Control6 0x07 Control register for region 1 0x48 Region2Control 6 0x07 Controlregister for region 2 0x4C Region3Control 6 0x07 Control register forregion 3 0x50 Region4Control 6 0x07 Control register for region 4 0x54Region5Control 6 0x07 Control register for region 5 0x58 Region6Control6 0x07 Control register for region 6 0x5C Region7Control 6 0x07 Controlregister for region 7 0x60 RegionLock 8 0x00 Writing a 1 to a bit in theRegionLock register locks the value of the corresponding Region- Top,RegionBottom and RegionControl registers. The lock can only be clearedby a reset and any attempt to write to a locked register will result ina bus error. 0x64 BusTimeout 8 0xFF This register should be set to thenumber of pclk cycles to wait after an access has started beforeaborting the access with a bus error. Writing 0 to this registerdisables the bus time- out feature. 0x68 ExceptionSource 6 0x00 Thisregister identifies the source of the last exception. See Section11.6.5.3 for details. 0x6C DebugSelect 7 0x00 Contains address of theregister selected for debug observation. It is expected that a number ofpseudo-registers will be made available for debug observation and thesewill be outlined during the implementation phase. 0x80 to RDU RegistersSee Table for details. 0x108 0x140 LEON Configuration 32 0x1071_8 TheLEON configuration register is used by Register C00 software todetermine the configuration of this LEON implementation. See section11.5.1.1 for details. This register is ReadOnly. 0x144 LEON Cache 320x0000_0 The LEON Cache Control Register is used to Control Register 000control the operation of the caches. See section 11.6 for details.11.6.5.1 RegionTop and RegionBottom Registers

The 20 Mbit of embedded DRAM on SoPEC is arranged as 81920 words of 256bits each. All region boundaries need to align with a 256-bit word. Thusonly 17 bits are required for the RegionNTop and RegionNBottomregisters. Note that the bottom 5 bits of the RegionNTop andRegionNBottom registers cannot be written to and read as ‘0’ i.e. theRegionNTop and RegionNBottom registers represent byte-aligned DRAMaddresses

Both the RegionNTop and RegionNBottom registers are inclusive i.e. theaddresses in the registers are included in the region. Thus the size ofa region is (RegionNTop—RegionNBottom)+1 DRAM words.

If DRAM regions overlap (there is no reason for this to be the case butthere is nothing to prohibit it either) then only accesses allowed byall overlapping regions are permitted. That is if a DRAM address appearsin both Region1 and Region3 (for example) the cpu_acode of an access ischecked against the access permissions of both regions. If both regionspermit the access then it will proceed but if either or both regions donot permit the access then it will not be allowed. The MMU does notsupport negatively sized regions i.e. the value of the RegionNTopregister should always be greater than or equal to the value of theRegionNBottom register. If RegionNTop is lower in the address map thanRegionNTop then the region is considered to be zero-sized and isignored.

When both the RegionNTop and RegionNBottom registers for a regioncontain the same value the region is then simply one 256-bit word inlength and this corresponds to the smallest possible active region.

11.6.5.2 Region Control Registers

Each memory region has a control register associated with it. TheRegionNControl register is used to set the access conditions for thememory region bounded by the RegionNTop and RegionNBottom registers.Table 20 describes the function of each bit field in the RegionNControlregisters. All bits in a RegionNControl register are both readable andwritable by design. However, like all registers in the MMU, theRegionNControl registers can only be accessed by code running insupervisor mode. TABLE 20 Region Control Register Field Name bit(s)Description SupervisorAccess 2:0 Denotes the type of access allowed whenthe CPU is running in Supervisor mode. For each access type a 1indicates the access is permitted and a 0 indicates the access is notpermitted. bit0 - Data read access permission bit1 - Data write accesspermission bit2 - Instruction fetch access permission UserAccess 5:3Denotes the type of access allowed when the CPU is running in User mode.For each access type a 1 indicates the access is permitted and a 0indicates the access is not permitted. bit3 - Data read accesspermission bit4 - Data write access permission bit5 - Instruction fetchaccess permission11.6.5.3 ExceptionSource Register

The SPARC V8 architecture allows for a number of types of memory accesserror to be trapped. These trap types and trap handling in general aredescribed in chapter 7 of the SPARC architecture manual [36]. However onthe LEON processor only data_store_error and data_access_exception traptypes will result from an external (to LEON) bus error. According to theSPARC architecture manual the processor will automatically move to thenext register window (i.e. it decrements the current window pointer) andcopies the program counters (PC and nPC) to two local registers in thenew window. The supervisor bit in the PSR is also set and the PSR can besaved to another local register by the trap handler (this does nothappen automatically in hardware). The ExceptionSource register aids thetrap handler by identifying the source of an exception. Each bit in theExceptionSource register is set when the relevant trap condition andshould be cleared by the trap handler by writing a ‘1’ to that bitposition. TABLE 21 ExceptionSource Register Field Name bit(s)Description DramAccessExcptn 0 The permissions of an access did notmatch those of the DRAM region it was attempting to access. This bitwill also be set if an attempt is made to access an undefined DRAMregion (i.e. a location that is not within the bounds of anyRegionTop/RegionBottom pair) PeriAccessExcptn 1 An access violationoccurred when accessing a CPU subsystem block. This occurs when theaccess permissions disagree with those set by the block.UnusedAreaExcptn 2 An attempt was made to access an unused part of thememory map LockedWriteExcptn 3 An attempt was made to write to a regionsregisters (RegionTop/ Bottom/Control) after they had been locked.ResetHandlerExcptn 4 An attempt was made to access a ROM locationbetween 0x0000_0000 and 0x0000_000F after the reset handler wasexecuted. The most likely cause of such an access is the use of anuninitialised pointer or structure. TimeoutExcptn 5 A bus timeoutcondition occurred.11.6.6 MMU Sub-Block Partition

As can be seen from FIG. 19 and FIG. 20 the MMU consists of threeprincipal sub-blocks. For clarity the connections between thesesub-blocks and other SoPEC blocks and between each of the sub-blocks areshown in two separate diagrams.

11.6.6.1 LEON AHB Bridge

The LEON AHB bridge consists of an AHB bridge to DIU and an AHB to CPUsubsystem bus bridge. The AHB bridge will convert between the AHB andthe DIU and CPU subsystem bus protocols but the address decoding andenabling of an access happens elsewhere in the MMU. The AHB bridge willalways be a slave on the AHB. Note that the AMBA signals from the LEONcore are contained within the ahbso and ahbsi records. The LEON recordsare described in more detail in section 11.7. Glue logic may be requiredto assist with enabling memory accesses, endianness coherency,interrupts and other miscellaneous signalling. TABLE 22 LEON AHB bridgeI/Os Port name Pins I/O Description Global SoPEC signals prst_n 1 InGlobal reset. Synchronous to pclk, active low. pclk 1 In Global clockLEON core to LEON AHB signals (ahbsi and ahbso records)ahbsi.haddr[31:0] 32 In AHB address bus ahbsi.hwdata[31:0] 32 In AHBwrite data bus ahbso.hrdata[31:0] 32 Out AHB read data bus ahbsi.hsel 1In AHB slave select signal ahbsi.hwrite 1 In AHB write signal: 1 - Writeaccess 0 - Read access ahbsi.htrans 2 In Indicates the type of thecurrent transfer: 00 - IDLE 01 - BUSY 10 - NONSEQ 11 - SEQ ahbsi.hsize 3In Indicates the size of the current transfer: 000 - Byte transfer 001 -Halfword transfer 010 - Word transfer 011 - 64-bit transfer(unsupported?) 1xx - Unsupported larger wordsizes ahbsi.hburst 3 InIndicates if the current transfer forms part of a burst and the type ofburst: 000 - SINGLE 001 - INCR 010 - WRAP4 011 - INCR4 100 - WRAP8 101 -INCR8 110 - WRAP16 111 - INCR16 ahbsi.hprot 4 In Protection controlsignals pertaining to the current access: hprot[0] - Opcode(0)/Data(1)access hprot[1] - User(0)/Supervisor access hprot[2] -Non-bufferable(0)/Bufferable(1) access (unsupported) hprot[3] -Non-cacheable(0)/Cacheable access ahbsi.hmaster 4 In Indicates theidentity of the current bus master. This will always be the LEON core.ahbsi.hmastlock 1 In Indicates that the current master is performing alocked sequence of transfers. ahbso.hready 1 Out Active high readysignal indicating the access has completed ahbso.hresp 2 Out Indicatesthe status of the transfer: 00 - OKAY 01 - ERROR 10 - RETRY 11 - SPLITahbso.hsplit[15:0] 16 Out This 16-bit split bus is used by a slave toindicate to the arbiter which bus masters should be allowed attempt asplit transaction. This feature will be unsupported on the AHB bridgeToplevel/Common LEON AHB bridge signals cpu_dataout[31:0] 32 Out Dataout bus to both DRAM and peripheral devices. cpu_rwn 1 Out Read/NotWritesignal. 1 = Current access is a read access, 0 = Current access is awrite access icu_cpu_ilevel[3:0] 4 In An interrupt is asserted bydriving the appropriate priority level on icu_cpu_ilevel. These signalsmust remain asserted until the CPU executes an interrupt acknowledgecycle. cpu_icu_ilevel[3:0] 4 In Indicates the level of the interrupt theCPU is acknowledging when cpu_iack is high cpu_iack 1 Out Interruptacknowledge signal. The exact timing depends on the CPU coreimplementation cpu_start_access 1 Out Start Access signal indicating thestart of a data transfer and that the cpu_adr, cpu_dataout, cpu_rwn andcpu_acode signals are all valid. This signal is only asserted during thefirst cycle of an access. cpu_ben[1:0] 2 Out Byte enable signals.dram_cpu_data[255:0] 256 In Read data from the DRAM. diu_cpu_rreq 1 OutRead request to the DIU. diu_cpu_rack 1 In Acknowledge from DIU thatread request has been accepted. diu_cpu_rvalid 1 In Signal from DIUindicating that valid read data is on the dram_cpu_data buscpu_diu_wdatavalid 1 Out Signal from the CPU to the DIU indicating thatthe data currently on the cpu_diu_wdata bus is valid and should becommitted to the DIU posted write buffer diu_cpu_write_rdy 1 In Signalfrom the DIU indicating that the posted write buffer is emptycpu_diu_wdadr[21:4] 18 Out Write address bus to the DIUcpu_diu_wdata[127:0] 128 Out Write data bus to the DIUcpu_diu_wmask[15:0] 16 Out Write mask for the cpu_diu_wdata bus. Eachbit corresponds to a byte of the 128-bit cpu_diu_wdata bus. LEON AHBbridge to MMU Control Block signals cpu_mmu_adr 32 Out CPU Address Bus.mmu_cpu_data 32 In Data bus from the MMU mmu_cpu_rdy 1 In Ready signalfrom the MMU cpu_mmu_acode 2 Out Access code signals to the MMUmmu_cpu_berr 1 In Bus error signal from the MMU dram_access_en 1 In DRAMaccess enable signal. A DRAM access cannot be initiated unless it hasbeen enabled by the MMU control unit.Description:

The LEON AHB bridge must ensure that all CPU bus transactions arefunctionally correct and that the timing requirements are met. The AHBbridge also implements a 128-bit DRAM write buffer to improve theefficiency of DRAM writes, particularly for multiple successive writesto DRAM. The AHB bridge is also responsible for ensuring endiannesscoherency i.e. guaranteeing that the correct data appears in the correctposition on the data buses (hrdata, cpu_dataout and cpu_mmu_wdata) forevery type of access. This is a requirement because the LEON usesbig-endian addressing while the rest of SoPEC is little-endian.

The LEON AHB bridge will assert request signals to the DIU if the MMUcontrol block deems the access to be a legal access. The validity (i.e.is the CPU running in the correct mode for the address space beingaccessed) of an access is determined by the contents of the relevantRegionNControl register. As the SPARC standard requires that allaccesses are aligned to their word size (i.e. byte, half-word, word ordouble-word) and so it is not possible for an access to traverse a256-bit boundary (as required by the DIU). Invalid DRAM accesses are notpropagated to the DIU and will result in an error response(ahbso.hresp=‘01’) on the AHB. The DIU bus protocol is described in moredetail in section 20.9. The DIU will return a 256-bit dataword ondram_cpu_data[255:0] for every read access.

The CPU subsystem bus protocol is described in section 11.4.3. While theLEON AHB bridge performs the protocol translation between AHB and theCPU subsystem bus the select signals for each block are generated byaddress decoding in the CPU subsystem bus interface. The CPU subsystembus interface also selects the correct read data bus, ready and errorsignals for the block being addressed and passes these to the LEON AHBbridge which puts them on the AHB bus. It is expected that some signals(especially those external to the CPU block) will need to be registeredhere to meet the timing requirements. Careful thought will be requiredto ensure that overall CPU access times are not excessively degraded bythe use of too many register stages.

11.6.6.1.1 DRAM Write Buffer

The DRAM write buffer improves the efficiency of DRAM writes byaggregating a number of CPU write accesses into a single DIU writeaccess. This is achieved by checking to see if a CPU write is to anaddress already in the write buffer and if so the write is immediatelyacknowledged (i.e. the ahbsi.hready signal is asserted without any waitstates) and the DRAM write buffer updated accordingly. When the CPUwrite is to a DRAM address other than that in the write buffer then thecurrent contents of the write buffer are sent to the DIU (where they areplaced in the posted write buffer) and the DRAM write buffer is updatedwith the address and data of the CPU write. The DRAM write bufferconsists of a 128-bit data buffer, an 18-bit write address tag and a16-bit write mask. Each bit of the write mask indicates the validity ofthe corresponding byte of the write buffer as shown in FIG. 21 below.

The operation of the DRAM write buffer is summarised by the followingset of rules:

-   1) The DRAM write buffer only contains DRAM write data i.e.    peripheral writes go directly to the addressed peripheral.-   2) CPU writes to locations within the DRAM write buffer or to an    empty write buffer (i.e. the write mask bits are all 0) complete    with zero wait states regardless of the size of the write    (byte/half-word/word/ double-word).-   3) The contents of the DRAM write buffer are flushed to DRAM    whenever a CPU write to a location outside the write buffer occurs,    whenever a CPU read from a location within the write buffer occurs    or whenever a write to a peripheral register occurs.-   4) A flush resulting from a peripheral write will not cause any    extra wait states to be inserted in the peripheral write access.-   5) Flushes resulting from a DRAM accesses will cause wait states to    be inserted until the DIU posted write buffer is empty. If the DIU    posted write buffer is empty at the time the flush is required then    no wait states will be inserted for a flush resulting from a CPU    write or one wait state will be inserted for a flush resulting from    a CPU read (this is to ensure that the DIU sees the write request    ahead of the read request). Note that in this case further wait    states will also be inserted as a result of the delay in servicing    the read request by the DIU.    11.6.6.1.2 DIU Interface Waveforms

FIG. 22 below depicts the operation of the AHB bridge over a samplesequence of DRAM transactions consisting of a read into the DCache, adouble-word store to an address other than that currently in the DRAMwrite buffer followed by an ICache line refill. To avoid clutter anumber of AHB control signals that are inputs to the MMU have beengrouped together as ahbsi.CONTROL and only the ahbso.HREADY is shown ofthe output AHB control signals.

The first transaction is a single word load (‘LD’). The MMU(specifically the MMU control block) uses the first cycle of everyaccess (i.e. the address phase of an AHB transaction) to determinewhether or not the access is a legal access. The read request to the DIUis then asserted in the following cycle (assuming the access is a validone) and is acknowledged by the DIU a cycle later. Note that the timefrom cpu_diu_rreq being asserted and diu_cpu_rack being asserted isvariable as it depends on the DIU configuration and access patterns ofDIU requestors. The AHB bridge will insert wait states until it sees thediu_cpu_rvalid signal is high, indicating the data (‘LD1’) on thedram_cpu_data bus is valid. The AHB bridge terminates the read access inthe same cycle by asserting the ahbso.HREADY signal (together with an‘OKAY’ HRESP code). The AHB bridge also selects the appropriate 32 bits(‘RD1’) from the 256-bit DRAM line data (‘LD1’) returned by the DIUcorresponding to the word address given by A1.

The second transaction is an AHB two-beat incrementing burst issued bythe LEON acache block in response to the execution of a double-wordstore instruction. As LEON is a big endian processor the address issued(‘A2’) during the address phase of the first beat of this transaction isthe address of the most significant word of the double-word while theaddress for the second beat (‘A3’) is that of the least significant wordi.e. A3=A2+4. The presence of the DRAM write buffer allows these writesto complete without the insertion of any wait states. This is true evenwhen, as shown here, the DRAM write buffer needs to be flushed into theDIU posted write buffer, provided the DIU posted write buffer is empty.If the DIU posted write buffer is not empty (as would be signified bydiu_cpu_write_rdy being low) then wait states would be inserted until itbecame empty. The cpu_diu_wdata buffer builds up the data to be writtento the DIU over a number of transactions (‘BD1’ and ‘BD2’ here) whilethe cpu_dui_wmask records every byte that has been written to since thelast flush—in this case the lowest word and then the second lowest wordare written to as a result of the double-word store operation.

The final transaction shown here is a DRAM read caused by an ICachemiss. Note that the pipelined nature of the AHB bus allows the addressphase of this transaction to overlap with the final data phase of theprevious transaction. All ICache misses appear as single word loads(‘LD’) on the AHB bus. In this case we can see that the DIU is slower torespond to this read request than to the first read request because itis processing the write access caused by the DRAM write buffer flush.The ICache refill will complete just after the window shown in FIG. 22.

11.6.6.2 CPU Subsystem Bus Interface

The CPU Subsystem Interface block handles all valid accesses to theperipheral blocks that comprise the CPU Subsystem. TABLE 23 CPUSubsystem Bus Interface I/Os Port name Pins I/O Description Global SoPECsignals prst_n 1 In Global reset. Synchronous to pclk, active low. pclk1 In Global clock Toplevel/Common CPU Subsystem Bus Interface signalscpu_cpr_sel 1 Out CPR block select. cpu_gpio_sel 1 Out GPIO blockselect. cpu_icu_sel 1 Out ICU block select. cpu_lss_sel 1 Out LSS blockselect. cpu_pcu_sel 1 Out PCU block select. cpu_scb_sel 1 Out SCB blockselect. cpu_tim_sel 1 Out Timers block select. cpu_rom_sel 1 Out ROMblock select. cpu_pss_sel 1 Out PSS block select. cpu_diu_sel 1 Out DIUblock select. cpr_cpu_data[31:0] 32 In Read data bus from the CPR blockgpio_cpu_data[31:0] 32 In Read data bus from the GPIO blockicu_cpu_data[31:0] 32 In Read data bus from the ICU blocklss_cpu_data[31:0] 32 In Read data bus from the LSS blockpcu_cpu_data[31:0] 32 In Read data bus from the PCU blockscb_cpu_data[31:0] 32 In Read data bus from the SCB blocktim_cpu_data[31:0] 32 In Read data bus from the Timers blockrom_cpu_data[31:0] 32 In Read data bus from the ROM blockpss_cpu_data[31:0] 32 In Read data bus from the PSS blockdiu_cpu_data[31:0] 32 In Read data bus from the DIU block cpr_cpu_rdy 1In Ready signal to the CPU. When cpr_cpu_rdy is high it indicates thelast cycle of the access. For a write cycle this means cpu_dataout hasbeen registered by the CPR block and for a read cycle this means thedata on cpr_cpu_data is valid. gpio_cpu_rdy 1 In GPIO ready signal tothe CPU. icu_cpu_rdy 1 In ICU ready signal to the CPU. lss_cpu_rdy 1 InLSS ready signal to the CPU. pcu_cpu_rdy 1 In PCU ready signal to theCPU. scb_cpu_rdy 1 In SCB ready signal to the CPU. tim_cpu_rdy 1 InTimers block ready signal to the CPU. rom_cpu_rdy 1 In ROM block readysignal to the CPU. pss_cpu_rdy 1 In PSS block ready signal to the CPU.diu_cpu_rdy 1 In DIU register block ready signal to the CPU.cpr_cpu_berr 1 In Bus Error signal from the CPR block gpio_cpu_berr 1 InBus Error signal from the GPIO block icu_cpu_berr 1 In Bus Error signalfrom the ICU block lss_cpu_berr 1 In Bus Error signal from the LSS blockpcu_cpu_berr 1 In Bus Error signal from the PCU block scb_cpu_berr 1 InBus Error signal from the SCB block tim_cpu_berr 1 In Bus Error signalfrom the Timers block rom_cpu_berr 1 In Bus Error signal from the ROMblock pss_cpu_berr 1 In Bus Error signal from the PSS block diu_cpu_berr1 In Bus Error signal from the DIU block CPU Subsystem Bus Interface toMMU Control Block signals cpu_adr[19:12] 8 In Toplevel CPU Address bus.Only bits 19-12 are required to decode the peripherals address spaceperi_access_en 1 In Enable Access signal. A peripheral access cannot beinitiated unless it has been enabled by the MMU Control Unitperi_mmu_data[31:0] 32 Out Data bus from the selected peripheralperi_mmu_rdy 1 Out Data Ready signal. Indicates the data on theperi_mmu_data bus is valid for a read cycle or that the data wassuccessfully written to the peripheral for a write cycle. peri_mmu_berr1 Out Bus Error signal. Indicates a bus error has occurred in accessingthe selected peripheral CPU Subsystem Bus Interface to LEON AHB bridgesignals cpu_start_access 1 In Start Access signal from the LEON AHBbridge indicating the start of a data transfer and that the cpu_adr,cpu_dataout, cpu_rwn and cpu_acode signals are all valid. This signal isonly asserted during the first cycle of an access.Description:

The CPU Subsystem Bus Interface block performs simple address decodingto select a peripheral and multiplexing of the returned signals from thevarious peripheral blocks. The base addresses used for the decodeoperation are defined in Table. Note that access to the MMUconfiguration registers are handled by the MMU Control Block rather thanthe CPU Subsystem Bus Interface block. The CPU Subsystem Bus Interfaceblock operation is described by the following pseudocode: masked_cpu_adr = cpu_adr[17:12]  case (masked_cpu_adr)  whenTIM_base[17:12]   cpu_tim_sel = peri_access_en    // The peri_access_ensignal will have the   peri_mmu_data = tim_cpu_data   // timing requiredfor block selects   peri_mmu_rdy = tim_cpu_rdy   peri_mmu_berr =tim_cpu_berr   all_other_selects = 0  // Shorthand to ensure othercpu_block_sel signals             // remain deasserted  whenLSS_base[17:12]   cpu_lss_sel = peri_access_en   peri_mmu_data =lss_cpu_data   peri_mmu_rdy = lss_cpu_rdy   peri_mmu_berr = lss_cpu_berr  all_other_selects = 0  when GPIO_base[17:12]   cpu_gpio_sel =peri_access_en   peri_mmu_data = gpio_cpu_data   peri_mmu_rdy =gpio_cpu_rdy   peri_mmu_berr = gpio_cpu_berr   all_other_selects = 0 when SCB_base[17:12]   cpu_scb_sel = peri_access_en   peri_mmu_data =scb_cpu_data   peri_mmu_rdy = scb_cpu_rdy   peri_mmu_berr = scb_cpu_berr  all_other_selects = 0  when ICU_base[17:12]   cpu_icu_sel =peri_access_en   peri_mmu_data = icu_cpu_data   peri_mmu_rdy =icu_cpu_rdy   peri_mmu_berr = icu_cpu_berr   all_other_selects = 0  whenCPR_base[17:12]   cpu_cpr_sel = peri_access_en   peri_mmu_data =cpr_cpu_data   peri_mmu_rdy = cpr_cpu_rdy   peri_mmu_berr = cpr_cpu_berr  all_other_selects = 0  when ROM_base[17:12]   cpu_rom_sel =peri_access_en   peri_mmu_data = rom_cpu_data   peri_mmu_rdy =rom_cpu_rdy   peri_mmu_berr = rom_cpu_berr   all_other_selects = 0  whenPSS_base[17:12]   cpu_pss_sel = peri_access_en   peri_mmu_data =pss_cpu_data   peri_mmu_rdy = pss_cpu_rdy   peri_mmu_berr = pss_cpu_berr  all_other_selects = 0  when DIU_base[17:12]   cpu_diu_sel =peri_access_en   peri_mmu_data = diu_cpu_data   peri_mmu_rdy =diu_cpu_rdy   peri_mmu_berr = diu_cpu_berr   all_other_selects = 0  whenPCU_base[17:12]   cpu_pcu_sel = peri_access_en   peri_mmu_data =pcu_cpu_data   peri_mmu_rdy = pcu_cpu_rdy   peri_mmu_berr = pcu_cpu_berr  all_other_selects = 0  when others   all_block_selects = 0  peri_mmu_data = 0x00000000   peri_mmu_rdy = 0   peri_mmu_berr = 1  endcase11.6.6.3 MMU Control Block

The MMU Control Block determines whether every CPU access is a validaccess. No more than one cycle is to be consumed in determining thevalidity of an access and all accesses must terminate with the assertionof either mmu_cpu_rdy or mmu_cpu_berr. To safeguard against stalling theCPU a simple bus timeout mechanism will be supported. TABLE 24 MMUControl Block I/Os Port name Pins I/O Description Global SoPEC signalsprst_n 1 In Global reset. Synchronous to pclk, active low. pclk 1 InGlobal clock Toplevel/Common MMU Control Block signals cpu_adr[21:2] 22Out Address bus for both DRAM and peripheral access. cpu_acode[1:0] 2Out CPU access code signals (cpu_mmu_acode) retimed to meet the CPUSubsystem Bus timing requirements dram_access_en 1 Out DRAM AccessEnable signal. Indicates that the current CPU access is a valid DRAMaccess. MMU Control Block to LEON AHB bridge signals cpu_mmu_adr[31:0]32 In CPU core address bus. cpu_dataout[31:0] 32 In Toplevel CPU databus mmu_cpu_data[31:0] 32 Out Data bus to the CPU core. Carries the datafor all CPU read operations cpu_rwn 1 In Toplevel CPU Read/notWritesignal. cpu_mmu_acode[1:0] 2 In CPU access code signals mmu_cpu_rdy 1Out Ready signal to the CPU core. Indicates the completion of all validCPU accesses. mmu_cpu_berr 1 Out Bus Error signal to the CPU core. Thissignal is asserted to terminate an invalid access. cpu_start_access 1 InStart Access signal from the LEON AHB bridge indicating the start of adata transfer and that the cpu_adr, cpu_dataout, cpu_rwn and cpu_acodesignals are all valid. This signal is only asserted during the firstcycle of an access. cpu_iack 1 In Interrupt Acknowledge signal from theCPU. This signal is only asserted during an interrupt acknowledge cycle.cpu_ben[1:0] 2 In Byte enable signals indicating which bytes of the 32-bit bus are being accessed. MMU Control Block to CPU Subsystem BusInterface signals cpu_adr[17:12] 8 Out Toplevel CPU Address bus. Onlybits 17-12 are required to decode the peripherals address spaceperi_access_en 1 Out Enable Access signal. A peripheral access cannot beinitiated unless it has been enabled by the MMU Control Unitperi_mmu_data[31:0] 32 In Data bus from the selected peripheralperi_mmu_rdy 1 In Data Ready signal. Indicates the data on theperi_mmu_data bus is valid for a read cycle or that the data wassuccessfully written to the peripheral for a write cycle. peri_mmu_berr1 In Bus Error signal. Indicates a bus error has occurred in accessingthe selected peripheralDescription:

The MMU Control Block is responsible for the MMU's core functionality,namely determining whether or not an access to any part of the addressmap is valid. An access is considered valid if it is to a mapped area ofthe address space and if the CPU is running in the appropriate mode forthat address space. Furthermore the MMU control block must correctlyhandle the special cases that are: an interrupt acknowledge cycle, areset exception vector fetch, an access that crosses a 256-bit DRAM wordboundary and a bus timeout condition. The following pseudocode shows thelogic required to implement the MMU Control Block functionality. It doesnot deal with the timing relationships of the various signals—it is thedesigner's responsibility to ensure that these relationships are correctand comply with the different bus protocols. For simplicity thepseudocode is split up into numbered sections so that the functionalitymay be seen more easily.

It is important to note that the style used for the pseudocode willdiffer from the actual coding style used in the RTL implementation. Thepseudocode is only intended to capture the required functionality, toclearly show the criteria that need to be tested rather than to describehow the implementation should be performed. In particular the differentcomparisons of the address used to determine which part of the memorymap, which DRAM region (if applicable) and the permission checkingshould all be performed in parallel (with results ORed together whereappropriate) rather than sequentially as the pseudocode implies.

PS0 Description: This first segment of code defines a number ofconstants and variables that are used elsewhere in this description.Most signals have been defined in the I/O descriptions of the MMUsub-blocks that precede this section of the document. Thepost_reset_state variable is used later (in section PS4) to determine ifwe should trap a null pointer access. PS0:  const UnusedBottom =0x002AC000  const DRAMTop = 0x4027FFFF  const UserDataSpace = b01  constUserProgramSpace = b00  const SupervisorDataSpace = b11  constSupervisorProgramSpace = b10  const ResetExceptionCycles = 0x2 cpu_adr_peri_masked[5:0] = cpu_mmu_adr[17:12] cpu_adr_dram_masked[16:0] = cpu_mmu_adr & 0x003FFFE0  if (prst_n == 0)then    // Initialise everything   cpu_adr = cpu_mmu_adr[21:2]  peri_access_en = 0   dram_access_en = 0   mmu_cpu_data = peri_mmu_data  mmu_cpu_rdy = 0   mmu_cpu_berr = 0   post_reset_state = TRUE  access_initiated = FALSE   cpu_access_cnt = 0  // The following isused to determine if we are coming out of reset for the purposes of  //reset exception vector redirection. There may be a convenient signal inthe CPU core  // that we could use instead of this. if ((cpu_start_access  == 1)  AND  (cpu_access_cnt  <ResetExceptionCycles) AND    (clock_tick == TRUE)) then   cpu_access_cnt= cpu_access_cnt +1  else   post_reset_state = FALSE

PS1 Description: This section is at the top of the hierarchy thatdetermines the validity of an access. The address is tested to see whichmacro-region (i.e. Unused, CPU Subsystem or DRAM) it falls into orwhether the reset exception vector is being accessed. PS1:  if(cpu_mmu_adr >= UnusedBottom) then    // The access is to an invalidarea of the address space. See section PS2  elsif  ((cpu_mmu_adr > DRAMTop)  AND  (cpu_mmu_adr  < UnusedBottom)) then   // We are in theCPU Subsystem/PEP Subsystem address space. See section PS3  // Onlyremaining possibility is an access to DRAM address space  // First weneed to intercept the special case for the reset exception vector  elsif(cpu_mmu_adr < 0x00000010) then   // The reset exception is beingaccessed. See section PS4  elsif  ((cpu_adr_dram_masked >= Region0Bottom)  AND (cpu_adr_dram_masked <=     Region0Top) ) then   // We are in Region0. See section PS5  elsif  ((cpu_adr_dram_masked >= RegionNBottom)  AND (cpu_adr_dram_masked <=      RegionNTop) ) then// we are in RegionN      // Repeat the Region0 (i.e. section PS5) logicfor each of Region1 to Region7  else  // We could end up here if therewere gaps in the DRAM regions   peri_access_en = 0   dram_access_en = 0  mmu_cpu_berr = 1  // we have an unknown access error, most likely dueto hitting   mmu_cpu_rdy = 0  // a gap in the DRAM regions  // Onlything remaining is to implement a bus timeout function. This is done inPS6  end

PS2 Description: Accesses to the large unused area of the address spaceare trapped by this section. No bus transactions are initiated and themmu_cpu_berr signal is asserted. PS2:  elsif (cpu_mmu_adr >=UnusedBottom) then   peri_access_en = 0  // The access is to an invalidarea of the address space   dram_access_en = 0   mmu_cpu_berr = 1  mmu_cpu_rdy = 0

PS3 Description: This section deals with accesses to CPU Subsystemperipherals, including the MMU itself. If the MMU registers are beingaccessed then no external bus transactions are required. Access to theMMU registers is only permitted if the CPU is making a data access fromsupervisor mode, otherwise a bus error is asserted and the accessterminated. For non-MMU accesses then transactions occur over the CPUSubsystem Bus and each peripheral is responsible for determining whetheror not the CPU is in the correct mode (based on the cpu_acode signals)to be permitted access to its registers. Note that all of the PEPregisters are accessed via the PCU which is on the CPU Subsystem Bus.PS3:  elsif  ((cpu_mmu_adr  > DRAMTop)  AND  (cpu_mmu_adr  <UnusedBottom)) then   // We are in the CPU Subsystem/PEP Subsystemaddress space   cpu_adr = cpu_mmu_adr[21:2]   if (cpu_adr_peri_masked ==MMU_base) then  // access is to local registers    peri_access_en = 0   dram_access_en = 0    if (cpu_acode == SupervisorDataSpace) then    for (i=0; i<26; i++) {      if ((i == cpu_mmu_adr[6:2]) then  //selects the addressed register       if (cpu_rwn == 1) then       mmu_cpu_data[16:0] = MMUReg[i] // MMUReg[i] is one of the       mmu_cpu_rdy = 1      // registers in Table        mmu_cpu_berr =0       else // write cycle        MMUReg[i] = cpu_dataout[16:0]       mmu_cpu_rdy = 1        mmu_cpu_berr = 0      else // there is noregister mapped to this address       mmu_cpu_berr = 1  // do we reallywant a bus_error here as registers       mmu_cpu_rdy = 0  // are justmirrored in other blocks    else // we have an access violation    mmu_cpu_berr = 1     mmu_cpu_rdy = 0   else // access is tosomething else on the CPU Subsystem Bus    peri_access_en = 1   dram_access_en = 0    mmu_cpu_data = peri_mmu_data    mmu_cpu_rdy =peri_mmu_rdy    mmu_cpu_berr = peri_mmu_berr

PS4 Description: The only correct accesses to the locations beneath0x00000010 are fetches of the reset trap handling routine and theseshould be the first accesses after reset. Here we trap all otheraccesses to these locations regardless of the CPU mode. The most likelycause of such an access will be the use of a null pointer in the programexecuting on the CPU. PS4:  elsif (cpu_mmu_adr < 0x00000010) then   if(post_reset_state == TRUE)) then    cpu adr = cpu mmu adr[21:2]   peri_access_en = 1    dram_access_en = 0    mmu_cpu_data =peri_mmu_data    mmu_cpu_rdy = peri_mmu_rdy    mmu_cpu_berr =peri_mmu_berr   else // we have a problem (almost certainly a nullpointer)    peri_access_en = 0    dram_access_en = 0    mmu_cpu_berr = 1   mmu_cpu_rdy = 0

PS5 Description: This large section of pseudocode simply checks whetherthe access is within the bounds of DRAM Region0 and if so whether or notthe access is of a type permitted by the Region0Control register. If theaccess is permitted then a DRAM access is initiated. If the access isnot of a type permitted by the Region0Control register then the accessis terminated with a bus error. PS5:  elsif  ((cpu_adr_dram_masked >= Region0Bottom)  AND (cpu_adr_dram_masked <=      Region0Top) ) then// we are in Region0   cpu_adr = cpu_mmu_adr[21:2]   if (cpu_rwn == 1)then    if  ((cpu_acode  == SupervisorProgramSpace  ANDRegion0Control[2] == 1))      OR  (cpu_acode  == UserProgramSpace  ANDRegion0Control[5] == 1)) then        // this is a valid instructionfetch from Region0        // The dram_cpu_data bus goes directly to theLEON        // AHB bridge which also handles the hready generation    peri_access_en = 0     dram_access_en = 1     mmu_cpu_berr = 0   elsif  ((cpu_acode  == SupervisorDataSpace  AND Region0Control[0]== 1)     OR  (cpu_acode  == UserDataSpace  AND Region0Control[3] == 1))then            // this is a valid read access from Region0    peri_access_en = 0     dram_access_en = 1     mmu_cpu_berr = 0   else         // we have an access violation     peri_access_en = 0    dram_access_en = 0     mmu_cpu_berr = 1     mmu_cpu_rdy = 0   else         // it is a write access    if  ((cpu_acode == SupervisorDataSpace  AND Region0Control[1] == 1)      OR  (cpu_acode == UserDataSpace  AND Region0Control[4] == 1)) then              //this is a valid write access to Region0     peri_access_en = 0    dram_access_en = 1     mmu_cpu_berr = 0    else          // we havean access violation     peri_access_en = 0     dram_access_en = 0    mmu_cpu_berr = 1     mmu_cpu_rdy = 0

PS6 Description: This final section of pseudocode deals with the specialcase of a bus timeout. This occurs when an access has been initiated buthas not completed before the BusTimeout number of pclk cycles. Whileaccess to both DRAM and CPU/PEP Subsystem registers will take a variablenumber of cycles (due to DRAM traffic, PCU command execution or thedifferent timing required to access registers in imported IP) eachaccess should complete before a timeout occurs. Therefore it should notbe possible to stall the CPU by locking either the CPU Subsystem or DIUbuses. However given the fatal effect such a stall would have it isconsidered prudent to implement bus timeout detection. PS6:  // Onlything remaining is to implement a bus timeout function.  if((cpu_start_access == 1) then   access_initiated = TRUE  timeout_countdown = BusTimeout  if ((mmu_cpu_rdy == 1 ) OR(mmu_cpu_berr ==1 )) then   access_initiated = FALSE   peri_access_en =0   dram_access_en = 0  if ((clock_tick == TRUE) AND (access_initiated== TRUE) AND (BusTimeout != 0))   if (timeout_countdown > 0) then   timeout_countdown−−   else // timeout has occurred    peri_access_en= 0     // abort the access    dram_access_en = 0    mmu_cpu_berr = 1   mmu_cpu_rdy = 011.7 LEON Caches

The version of LEON implemented on SoPEC features 1 kB of ICache and 1kB of DCache. Both caches are direct mapped and feature 8 word lines sotheir data RAMs are arranged as 32×256-bit and their tag RAMs as32×30-bit (itag) or 32×32-bit (dtag). Like most of the rest of the LEONcode used on SoPEC the cache controllers are taken from the leon2-1.0.7release. The LEON cache controllers and cache RAMs have been modified toensure that an entire 256-bit line is refilled at a time to make maximumuse out of the memory bandwidth offered by the embedded DRAMorganization (DRAM lines are also 256-bit). The data cache controllerhas also been modified to ensure that user mode code cannot access theDCache contents unless it is authorised to do so. A block diagram of theLEON CPU core as implemented on SoPEC is shown in FIG. 23 below.

In this diagram dotted lines are used to indicate hierarchy and reditems represent signals or wrappers added as part of the SoPECmodifications. LEON makes heavy use of VHDL records and the records usedin the CPU core are described in Table 25. Unless otherwise stated therecords are defined in the iface.vhd file (part of the LEON release) andthis should be consulted for a complete breakdown of the recordelements. TABLE 25 Relevant LEON records Record Name Description rfiRegister File Input record. Contains address, datain and control signalsfor the register file. rfo Register File Output record. Contains thedata out of the dual read port register file. ici Instruction Cache Inrecord. Contains program counters from different stages of the pipelineand various control signals ico Instruction Cache Out record. Containsthe fetched instruction data and various control signals. This record isalso sent to the DCache (i.e. icol) so that diagnostic accesses (e.g.lda/sta) can be serviced. dci Data Cache In record. Contains address anddata buses from different stages of the pipeline (execute & memory) andvarious control signals dco Data Cache Out record. Contains the dataretrieved from either memory or the caches and various control signals.This record is also sent to the ICache (i.e. dcol) so that diagnosticaccesses (e.g. lda/sta) can be serviced. iui Integer Unit In record.This record contains the interrupt request level and a record for usewith LEONs Debug Support Unit (DSU) iuo Integer Unit Out record. Thisrecord contains the acknowledged interrupt request level with controlsignals and a record for use with LEONs Debug Support Unit (DSU) mciiMemory to Cache Icache In record. Contains the address of an Icache missand various control signals mcio Memory to Cache Icache Out record.Contains the returned data from memory and various control signals mcdiMemory to Cache Dcache In record. Contains the address and data of aDcache miss or write and various control signals mcdo Memory to CacheDcache Out record. Contains the returned data from memory and variouscontrol signals ahbi AHB In record. This is the input record for an AHBmaster and contains the data bus and AHB control signals. Thedestination for the signals in this record is the AHB controller. Thisrecord is defined in the amba.vhd file ahbo AHB Out record. This is theoutput record for an AHB master and contains the address and data busesand AHB control signals. The AHB controller drives the signals in thisrecord. This record is defined in the amba.vhd file ahbsi AHB Slave Inrecord. This is the input record for an AHB slave and contains theaddress and data buses and AHB control signals. It is used by the DCacheto facilitate cache snooping (this feature is not enabled in SoPEC).This record is defined in the amba.vhd file crami Cache RAM In record.This record is composed of records of records which contain the address,data and tag entries with associated control signals for both the ICacheRAM and DCache RAM cramo Cache RAM Out record. This record is composedof records of records which contain the data and tag entries withassociated control signals for both the ICache RAM and DCache RAMiline_rdy Control signal from the ICache controller to the instructioncache memory. This signal is active (high) when a full 256-bit line (ondram_cpu_data) is to be written to cache memory. dline_rdy Controlsignal from the DCache controller to the data cache memory. This signalis active (high) when a full 256-bit line (on dram_cpu_data) is to bewritten to cache memory. dram_cpu_data 256-bit data bus from theembedded DRAM11.7.1 Cache Controllers

The LEON cache module consists of three components: the ICachecontroller (icache.vhd), the DCache controller (dcache.vhd) and the AHBbridge (acache.vhd) which translates all cache misses into memoryrequests on the AHB bus.

In order to enable full line refill operation a few changes had to bemade to the cache controllers. The ICache controller was modified toensure that whenever a location in the cache was updated (i.e. the cachewas enabled and was being refilled from DRAM) all locations on thatcache line had their valid bits set to reflect the fact that the fullline was updated. The iline_rdy signal is asserted by the ICachecontroller when this happens and this informs the cache wrappers toupdate all locations in the idata RAM for that line.

A similar change was made to the DCache controller except that theentire line was only updated following a read miss and that existingwrite through operation was preserved. The DCache controller uses thedline_rdy signal to instruct the cache wrapper to update all locationsin the ddata RAM for a line. An additional modification was also made toensure that a double-word load instruction from a non-cached locationwould only result in one read access to the DIU i.e. the second readwould be serviced by the data cache. Note that if the DCache is turnedoff then a double-word load instruction will cause two DIU read accessesto occur even though they will both be to the same 256-bit DRAM line.

The DCache controller was further modified to ensure that user mode codecannot access cached data to which it does not have permission (asdetermined by the relevant RegionNControl register settings at the timethe cache line was loaded). This required an extra 2 bits of taginformation to record the user read and write permissions for each cacheline. These user access permissions can be updated in the same manner asthe other tag fields (i.e. address and valid bits) namely by linerefill, STA instruction or cache flush. The user access permission bitsare checked every time user code attempts to access the data cache andif the permissions of the access do not agree with the permissionsreturned from the tag RAM then a cache miss occurs. As the MMU evaluatesthe access permissions for every cache miss it will generate theappropriate exception for the forced cache miss caused by the errantuser code. In the case of a prohibited read access the trap will beimmediate while a prohibited write access will result in a deferredtrap. The deferred trap results from the fact that the prohibited writeis committed to a write buffer in the DCache controller and programexecution continues until the prohibited write is detected by the MMUwhich may be several cycles later. Because the errant write was treatedas a write miss by the DCache controller (as it did not match the storeduser access permissions) the cache contents were not updated and soremain coherent with the DRAM contents (which do not get updated becausethe MMU intercepted the prohibited write). Supervisor mode code is notsubject to such checks and so has free access to the contents of thedata cache.

In addition to AHB bridging, the ACache component also performsarbitration between ICache and DCache misses when simultaneous missesoccur (the DCache always wins) and implements the Cache Control Register(CCR). The leon2-1.0.7 release is inconsistent in how it handlescacheability: For instruction fetches the cacheability (i.e. is theaccess to an area of memory that is cacheable) is determined by theICache controller while the ACache determines whether or not a dataaccess is cacheable. To further complicate matters the DCache controllerdoes determine if an access resulting from a cache snoop by another AHBmaster is cacheable (Note that the SoPEC ASIC does not implement cachesnooping as it has no need to do so). This inconsistency has beencleaned up in more recent LEON releases but is preserved here tominimise the number of changes to the LEON RTL. The cache controllerswere modified to ensure that only DRAM accesses (as defined by the SoPECmemory map) are cached.

The only functionality removed as a result of the modifications wassupport for burst fills of the ICache. When enabled burst fills wouldrefill an ICache line from the location where a miss occurred up to theend of the line. As the entire line is now refilled at once (whenexecuting from DRAM) this functionality is no longer required.Furthermore more substantial modifications to the ICache controllerwould be needed if we wished to preserve this function without adverselyaffecting full line refills. The CCR was therefore modified to ensurethat the instruction burst fetch bit (bit16) was tied low and could notbe written to.

11.7.1.1 LEON Cache Control Register

The CCR controls the operation of both the I and D caches. Note that thebitfields used on the SoPEC implementation of this register are based onthe LEON v1.0.7 implementation and some bits have their values tied off.See section 4 of the LEON manual for a description of the LEON cachecontrollers. TABLE 26 LEON Cache Control Register Field Name bit(s)Description ICS 1:0 Instruction cache state: 00 - disabled 01 - frozen10 - disabled 11 - enabled Reserved 13:6  Reserved. Reads as 0. DCS 3:2Data cache state: 00 - disabled 01 - frozen 10 - disabled 11 - enabledIF 4 ICache freeze on interrupt 0 - Do not freeze the ICache contents ontaking an interrupt 1 - Freeze the ICache contents on taking aninterrupt DF 5 DCache freeze on interrupt 0 - Do not freeze the DCachecontents on taking an interrupt 1 - Freeze the DCache contents on takingan interrupt Reserved 13:6  Reserved. Reads as 0. DP 14 Data cache flushpending. 0 - No DCache flush in progress 1 - DCache flush in progressThis bit is ReadOnly. IP 15 Instruction cache flush pending. 0 - NoICache flush in progress 1 - ICache flush in progress This bit isReadOnly. IB 16 Instruction burst fetch enable. This bit is tied low onSoPEC because it would interfere with the operation of the cachewrappers. Burst refill functionality is automatically provided in SoPECby the cache wrappers. Reserved 20:17 Reserved. Reads as 0. FI 21 Flushinstruction cache. Writing a 1 this bit will flush the ICache. Reads as0. FD 22 Flush data cache. Writing a 1 this bit will flush the DCache.Reads as 0. DS 23 Data cache snoop enable. This bit is tied low in SoPECas there is no requirement to snoop the data cache. Reserved 31:24Reserved. Reads as 0.11.7.2 Cache Wrappers

The cache RAMs used in the leon2-1.0.7 release needed to be modified tosupport full line refills and the correct IBM macros also needed to beinstantiated. Although they are described as RAMs throughout thisdocument (for consistency), register arrays are actually used toimplement the cache RAMs. This is because IBM SRAMs were not availablein suitable configurations (offered configurations were too big) toimplement either the tag or data cache RAMs. Both instruction and datatag RAMs are implemented using dual port (1 Read & 1 Write) registerarrays and the clocked write-through versions of the register arrayswere used as they most closely approximate the single port SRAM LEONexpects to see.

11.7.2.1 Cache Tag RAM Wrappers

The itag and dtag RAMs differ only in their width—the itag is a 32×30array while the dtag is a 32×32 array with the extra 2 bits being usedto record the user access permissions for each line. When read using aLDA instruction both tags return 32-bit words. The tag fields aredescribed in Table 27 and Table 28 below. Using the IBM namingconventions the register arrays used for the tag RAMs are calledRA032X30D2P2W1R1M3 for the itag and RA032X32D2P2W1R1M3 for the dtag. Theibm_syncram wrapper used for the tag RAMs is a simple affair that justmaps the wrapper ports on to the appropriate ports of the IBM registerarray and ensures the output data has the correct timing by registeringit. The tag RAMs do not require any special modifications to handle fullline refills. TABLE 27 LEON Instruction Cache Tag Field Name bit(s)Description Valid 7:0 Each valid bit indicates whether or not thecorresponding word of the cache line contains valid data Reserved 9:8Reserved - these bits do not exist in the itag RAM. Reads as 0. Address31:10 The tag address of the cache line

TABLE 28 LEON Data Cache Tag Field Name bit(s) Description Valid 7:0Each valid bit indicates whether or not the corresponding word of thecache line contains valid data URP 8 User read permission. 0 - User modereads will force a refill of this line 1 - User mode code can read fromthis cache line. UWP 9 User write permission. 0 - User mode writes willnot be written to the cache 1 - User mode code can write to this cacheline. Address 31:10 The tag address of the cache line11.7.2.2 Cache Data RAM Wrappers

The cache data RAM contains the actual cached data and nothing else.Both the instruction and data cache data RAMs are implemented using 832×32-bit register arrays and some additional logic to support full linerefills. Using the IBM naming conventions the register arrays used forthe tag RAMs are called RA032X32D2P2W1R1M3. The ibm_cdram_wrap wrapperused for the tag RAMs is shown in FIG. 24 below.

To the cache controllers the cache data RAM wrapper looks like a 256×32single port SRAM (which is what they expect to see) with an input toindicate when a full line refill is taking place (the line_rdy signal).Internally the 8-bit address bus is split into a 5-bit lineaddress,which selects one of the 32 256-bit cache lines, and a 3-bit wordaddresswhich selects one of the 8 32-bit words on the cache line. Thus each ofthe 8 32×32 register arrays contains one 32-bit word of each cache line.When a full line is being refilled (indicated by both the line rdy andwrite signals being high) every register array is written to with theappropriate 32 bits from the linedatain bus which contains the 256-bitline returned by the DIU after a cache miss. When just one word of thecache line is to be written (indicated by the write signal being highwhile the line_rdy is low) then the wordaddress is used to enable thewrite signal to the selected register array only—all other write enablesignals are kept low. The data cache controller handles byte andhalf-word write by means of a read-modify-write operation so writes tothe cache data RAM are always 32-bit.

The wordaddress is also used to select the correct 32-bit word from thecache line to return to the LEON integer unit.

11.8 Realtime Debug Unit (RDU)

The RDU facilitates the observation of the contents of most of the CPUaddressable registers in the SoPEC device in addition to somepseudo-registers in realtime. The contents of pseudo-registers, i.e.registers that are collections of otherwise unobservable signals andthat do not affect the functionality of a circuit, are defined in eachblock as required. Many blocks do not have pseudo-registers and someblocks (e.g. ROM, PSS) do not make debug information available to theRDU as it would be of little value in realtime debug.

Each block that supports realtime debug observation features aDebugSelect register that controls a local mux to determine whichregister is output on the block's data bus (i.e. block_cpu_data). Onesmall drawback with reusing the blocks data bus is that the debug datacannot be present on the same bus during a CPU read from the block. Anaccompanying active high block_cpu_debug_valid signal is used toindicate when the data bus contains valid debug data and when the bus isbeing used by the CPU. There is no arbitration for the bus as the CPUwill always have access when required. A block diagram of the RDU isshown in FIG. 25. TABLE 29 RDU I/Os Port name Pins I/O Descriptiondiu_cpu_data 32 In Read data bus from the DIU block cpr_cpu_data 32 InRead data bus from the CPR block gpio_cpu_data 32 In Read data bus fromthe GPIO block icu_cpu_data 32 In Read data bus from the ICU blocklss_cpu_data 32 In Read data bus from the LSS block pcu_cpu_debug_data32 In Read data bus from the PCU block scb_cpu_data 32 In Read data busfrom the SCB block tim_cpu_data 32 In Read data bus from the TIM blockdiu_cpu_debug_valid 1 In Signal indicating the data on the diu_cpu_databus is valid debug data. tim_cpu_debug_valid 1 In Signal indicating thedata on the tim_cpu_data bus is valid debug data. scb_cpu_debug_valid 1In Signal indicating the data on the scb_cpu_data bus is valid debugdata. pcu_cpu_debug_valid 1 In Signal indicating the data on thepcu_cpu_data bus is valid debug data. lss_cpu_debug_valid 1 In Signalindicating the data on the lss_cpu_data bus is valid debug data.icu_cpu_debug_valid 1 In Signal indicating the data on the icu_cpu_databus is valid debug data. gpio_cpu_debug_valid 1 In Signal indicating thedata on the gpio_cpu_data bus is valid debug data. cpr_cpu_debug_valid 1In Signal indicating the data on the cpr_cpu_data bus is valid debugdata. debug_data_out 32 Out Output debug data to be muxed on to thePHI/GPIO/other pins debug_data_valid 1 Out Debug valid signal indicatingthe validity of the data on debug_data_out. This signal is used in alldebug configurations debug_cntrl 33 Out Control signal for each debugdata line indicating whether or not the debug data should be selected bythe pin mux

As there are no spare pins that can be used to output the debug data toan external capture device some of the existing I/Os will have a debugmultiplexer placed in front of them to allow them be used as debug pins.Furthermore not every pin that has a debug mux will always be availableto carry the debug data as they may be engaged in their primary purposee.g. as a GPIO pin. The RDU therefore outputs a debug_cntrl signal witheach debug data bit to indicate whether the mux associated with eachdebug pin should select the debug data or the normal data for the pin.The DebugPinSel1 and DebugPinSel2 registers are used to determine whichof the 33 potential debug pins are enabled for debug at any particulartime.

As it may not always be possible to output a full 32-bit debug wordevery cycle the RDU supports the outputting of an n-bit sub-word everycycle to the enabled debug pins. Each debug test would then need to bere-run a number of times with a different portion of the debug wordbeing output on the n-bit sub-word each time. The data from each runshould then be correlated to create a full 32-bit (or whatever size isneeded) debug word for every cycle. The debug_data_valid and pclk_outsignals will accompany every sub-word to allow the data to be sampledcorrectly. The pclk_out signal is sourced close to its output pad ratherthan in the RDU to minimise the skew between the rising edge of thedebug data signals (which should be registered close to their outputpads) and the rising edge of pclk_out.

As multiple debug runs will be needed to obtain a complete set of debugdata the n-bit sub-word will need to contain a different bit pattern foreach run. For maximum flexibility each debug pin has an associatedDebugDataSrc register that allows any of the 32 bits of the debug dataword to be output on that particular debug data pin. The debug data pinmust be enabled for debug operation by having its corresponding bit inthe DebugPinSel registers set for the selected debug data bit to appearon the pin.

The size of the sub-word is determined by the number of enabled debugpins which is controlled by the DebugPinSel registers. Note that thedebug_data_valid signal is always output. Furthermore debug_cntrl[0](which is configured by DebugPinSel1) controls the mux for both thedebug_data_valid and pclk_out signals as both of these must be enabledfor any debug operation. The mapping of debug_data_out[n] signals ontoindividual pins will take place outside the RDU. This mapping isdescribed in Table 30 below. TABLE 30 DebugPinSel mapping bit # PinDebugPinSel1 phi_frclk. The debug_data_valid signal will appear on thispin when enabled. Enabling this pin also automatically enables thephi_readl pin which will output the pclk_out signal DebugPinSel2(0-31)gpio[0...31]

TABLE 31 RDU Configuration Registers Address offset from MMU_baseRegister #bits Reset Description 0x80 DebugSrc 4 0x00 Denotes whichblock is supplying the debug data. The encoding of this block is givenbelow. 0 - MMU 1 - TIM 2 - LSS 3- GPIO 4 - SCB 5 - ICU 6 - CPR 7 - DIU8 - PCU 0x84 DebugPinSel1 1 0x0 Determines whether the phi_frclk andphi_readl pins are used for debug output. 1 - Pin outputs debug data 0 -Normal pin function 0x88 DebugPinSel2 32  0x0000_0000 Determines whethera pin is used for debug data output. 1 - Pin outputs debug data 0 -Normal pin function 0x8C to 0x108 DebugDataSrc[31:0] 32x5 0x00 Selectswhich bit of the 32-bit debug data word will be output ondebug_data_out[N]11.9 Interrupt Operation

The interrupt controller unit (see chapter 14) generates an interruptrequest by driving interrupt request lines with the appropriateinterrupt level. LEON supports 15 levels of interrupt with level 15 asthe highest level (the SPARC architecture manual [36] states that level15 is non-maskable but we have the freedom to mask this if desired). TheCPU will begin processing an interrupt exception when execution of thecurrent instruction has completed and it will only do so if theinterrupt level is higher than the current processor priority. If asecond interrupt request arrives with the same level as an executinginterrupt service routine then the exception will not be processed untilthe executing routine has completed.

When an interrupt trap occurs the LEON hardware will place the programcounters (PC and nPC) into two local registers. The interrupt handlerroutine is expected, as a minimum, to place the PSR register in anotherlocal register to ensure that the LEON can correctly return to itspre-interrupt state. The 4-bit interrupt level (irl) is also written tothe trap type (tt) field of the TBR (Trap Base Register) by hardware.The TBR then contains the vector of the trap handler routine theprocessor will then jump. The TBA (Trap Base Address) field of the TBRmust have a valid value before any interrupt processing can occur so itshould be configured at an early stage.

Interrupt pre-emption is supported while ET (Enable Traps) bit of thePSR is set. This bit is cleared during the initial trap processing. Ininitial simulations the ET bit was observed to be cleared for up to 30cycles. This causes significant additional interrupt latency in theworst case where a higher priority interrupt arrives just as a lowerpriority one is taken.

The interrupt acknowledge cycles shown in FIG. 26 below are derived fromsimulations of the LEON processor. The SoPEC toplevel interrupt signalsused in this diagram map directly to the LEON interrupt signals in theiui and iuo records. An interrupt is asserted by driving its (encoded)level on the icu_cpu_ilevel[3:0] signals (which map to iui.irl[3:0]).The LEON core responds to this, with variable timing, by reflecting thelevel of the taken interrupt on the cpu_icu_ilevel[3:0] signals (mappedto iuo.irl[3:0]) and asserting the acknowledge signal cpu_iack(iuo.intack). The interrupt controller then removes the interrupt levelone cycle after it has seen the level been acknowledged by the core. Ifthere is another pending interrupt (of lower priority) then this shouldbe driven on icu_cpu_ilevel[3:0] and the CPU will take that interrupt(the level 9 interrupt in the example below) once it has finishedprocessing the higher priority interrupt. The cpu_icu_ilevel[3:0]signals always reflect the level of the last taken interrupt, even whenthe CPU has finished processing all interrupts.

11.10 Boot Operation

See section 17.2 for a description of the SoPEC boot operation.

11.11 Software Debug

Software debug mechanisms are discussed in the “SoPEC Software Debug”document [15].

12 Serial Communications Block (SCB)

12.1 Overview

The Serial Communications Block (SCB) handles the movement of all databetween the SoPEC and the host device (e.g. PC) and between master andslave SoPEC devices. The main components of the SCB are a Full-Speed(FS) USB Device Core, a FS USB Host Core, a Inter-SoPEC Interface (ISI),a DMA manager, the SCB Map and associated control logic. The need forthese components and the various types of communication they provide isevident in a multi-SoPEC printer configuration.

12.1.1 Multi-SoPEC Systems

While single SoPEC systems are expected to form the majority of SoPECsystems the SoPEC device must also support its use in multi-SoPECsystems such as that shown in FIG. 27. A SoPEC may be assigned any oneof a number of identities in a multi-SoPEC system. A SoPEC may be one ormore of a PrintMaster, a LineSyncMaster, an ISIMaster, a StorageSoPEC oran ISISlave SoPEC.

12.1.1.1 ISIMaster Device

The ISIMaster is the only device that controls the common ISI lines (seeFIG. 30) and typically interfaces directly with the host. In mostsystems the ISIMaster will simply be the SoPEC connected to the USB bus.Future systems, however, may employ an ISI-Bridge chip to interfacebetween the host and the ISI bus and in such systems the ISI-Bridge chipwill be the ISIMaster. There can only be one ISIMaster on an ISI bus.

Systems with multiple SoPECs may have more than one host connection, forexample there could be two SoPECs communicating with the external hostover their FS USB links (this would of course require two USB cables tobe connected), but still only one ISIMaster.

While it is not expected to be required, it is possible for a device tohand over its role as the ISIMaster to another device on the ISI i.e.the ISIMaster is not necessarily fixed.

12.1.1.2 PrintMaster Device

The PrintMaster device is responsible for coordinating all aspects ofthe print operation. This includes starting the print operation in allprinting SoPECs and communicating status back to the external host. Whenthe ISIMaster is a SoPEC device it is also likely to be the PrintMasteras well. There may only be one PrintMaster in a system and it is mostlikely to be a SoPEC device.

12.1.1.3 LineSyncMaster Device

The LineSyncMaster device generates the lsync pulse that all SoPECs inthe system must synchronize their line outputs with. Any SoPEC in thesystem could act as a LineSyncMaster although the PrintMaster isprobably the most likely candidate. It is possible that theLineSyncMaster may not be a SoPEC device at all—it could, for example,come from some OEM motor control circuitry. There may only be oneLineSyncMaster in a system.

12.1.1.4 Storage Device

For certain printer types it may be realistic to use one SoPEC as astorage device without using its print engine capability—that is toeffectively use it as an ISI-attached DRAM. A storage SoPEC wouldreceive data from the ISIMaster (most likely to be an ISI-Bridge chIP)and then distribute it to the other SoPECs as required. No other type ofdata flow (e.g. ISISlave->storage SoPEC->ISISlave) would need to besupported in such a scenario. The SCB supports this functionality at noadditional cost because the CPU handles the task of transferringoutbound data from the embedded DRAM to the ISI transmit buffer. The CPUin a storage SoPEC will have almost nothing else to do.

12.1.1.5 ISISlave Device

Multi-SoPEC systems will contain one or more ISISlave SoPECs. AnISISlave SoPEC is primarily used to generate dot data for the printheadIC it is driving. An ISISlave will not transmit messages on the ISIwithout first receiving permission to do so, via a ping packet (seesection 12.4.4.6), from the ISIMaster

12.1.1.6 ISI-Bridge Device

SoPEC is targeted at the low-cost small office/home office (SoHo)market. It may also be used in future systems that target differentmarket segments which are likely to have a high speed interfacecapability. A future device, known as an ISI-Bridge chip, is envisagedwhich will feature both a high speed interface (such as High-Speed (HS)USB, Ethernet or IEEE1394) and one or more ISI interfaces. The use ofmultiple ISI buses would allow the construction of independent printsystems within the one printer. The ISI-Bridge would be the ISIMasterfor each of the ISI buses it interfaces to.

12.1.1.7 External Host

The external host is most likely (but is not required) to be, a PC. Anysystem that can act as a USB host or that can interface to an ISI-Bridgechip could be the external host. In particular, with the development ofUSB On-The-Go (USB OTG), it is possible that a number of USB OTG enabledproducts such as PDAs or digital cameras will be able to directlyinterface with a SoPEC printer.

12.1.1.8 External USB Device

The external USB device is most likely (but is not required) to be, adigital camera. Any system that can act as a USB device could beconnected as an external USB device. This is to facilitate printing inthe absence of a PC.

12.1.2 Types of Communication

12.1.2.1 Communications with External Host

The external host communicates directly with the ISIMaster in order toprint pages. When the ISIMaster is a SoPEC, the communications channelis FS USB.

12.1.2.1.1 External Host to ISIMaster Communication

The external host will need to communicate the following information tothe ISIMaster device:

-   -   Communications channel configuration and maintenance information    -   Most data destined for PrintMaster, ISISlave or storage SoPEC        devices. This data is simply relayed by the ISIMaster    -   Mapping of virtual communications channels, such as USB        endpoints, to ISI destination        12.1.2.1.2 ISIMaster to External Host Communication

The ISIMaster will need to communicate the following information to theexternal host:

-   -   Communications channel configuration and maintenance information    -   All data originating from the PrintMaster, ISISlave or storage        SoPEC devices and destined for the external host. This data is        simply relayed by the ISIMaster        12.1.2.1.3 External Host to PrintMaster Communication

The external host will need to communicate the following information tothe PrintMaster device:

-   -   Program code for the PrintMaster    -   Compressed page data for the PrintMaster    -   Control messages to the PrintMaster    -   Tables and static data required for printing e.g. dead nozzle        tables, dither matrices etc.    -   Authenticatable messages to upgrade the printer's capabilities        12.1.2.1.4 PrintMaster to External Host Communication

The PrintMaster will need to communicate the following information tothe external host:

-   -   Printer status information (i.e. authentication results, paper        empty/jammed etc.)    -   Dead nozzle information    -   Memory buffer status information    -   Power management status    -   Encrypted SoPEC_id for use in the generation of PRINTER_QA keys        during factory programming        12.1.2.1.5 External Host to ISISlave Communication

All communication between the external host and ISISlave SoPEC devicesmust be direct (via a dedicated connection between the external host andthe ISISlave) or must take place via the ISIMaster. In the case of aSoPEC ISIMaster it is possible to configure each individual USB endpointto act as a control channel to an ISISlave SoPEC if desired, althoughthe endpoints will be more usually used to transport data. The externalhost will need to communicate the following information to ISISlavedevices over the comms/lSI:

-   -   Program code for ISISlave SoPEC devices    -   Compressed page data for ISISlave SoPEC devices    -   Control messages to the ISISlave SoPEC (where a control channel        is supported)    -   Tables and static data required for printing e.g. dead nozzle        tables, dither matrices etc.    -   Authenticatable messages to upgrade the printer's capabilities        12.1.2.1.6 ISISlave to External Host Communication

All communication between the ISISlave SoPEC devices and the externalhost must take place via the ISIMaster. The ISISlave will need tocommunicate the following information to the external host over thecomms/ISI:

-   -   Responses to the external host's control messages (where a        control channel is supported)    -   Dead nozzle information from the ISISlave SoPEC.    -   Encrypted SoPEC_id for use in the generation of PRINTER_QA keys        during factory programming        12.1.2.2 Communication with External USB Device        12.1.2.2.1 ISIMaster to External USB Device Communication    -   Communications channel configuration and maintenance        information.        12.1.2.2.2 External USB Device to ISIMaster Communication    -   Print data from a function on the external USB device.        12.1.2.3 Communication Over ISI        12.1.2.3.1 ISIMaster to PrintMaster Communication

The ISIMaster and PrintMaster will often be the same physical device.When they are different devices then the following information needs tobe exchanged over the ISI:

-   -   All data from the external host destined for the PrintMaster        (see section 12.1.2.1.4).

This data is simply relayed by the ISIMaster

12.1.2.3.2 PrintMaster to ISIMaster Communication

The ISIMaster and PrintMaster will often be the same physical device.When they are different devices then the following information needs tobe exchanged over the ISI:

-   -   All data from the PrintMaster destined for the external host        (see section 12.1.2.1.4).

This data is simply relayed by the ISIMaster

12.1.2.3.3 ISIMaster to ISISlave Communication

The ISIMaster may wish to communicate the following information to theISISlaves:

-   -   All data (including program code such as ISIId enumeration)        originating from the external host and destined for the ISISlave        (see section 12.1.2.1.5). This data is simply relayed by the        ISIMaster    -   wake up from sleep mode        12.1.2.3.4 ISISlave to ISIMaster Communication

The ISISlave may wish to communicate the following information to theISIMaster:

-   -   All data originating from the ISISlave and destined for the        external host (see section 12.1.2.1.6). This data is simply        relayed by the ISIMaster        12.1.2.3.5 PrintMaster to ISISlave Communication

When the PrintMaster is not the ISIMaster all ISI communication is donein response to ISI ping packets (see 12.4.4.6). When the PrintMaster isthe ISIMaster then it will of course communicate directly with theISISlaves. The PrintMaster SoPEC may wish to communicate the followinginformation to the ISISlaves:

-   -   Ink status e.g. requests for dotCount data i.e. the number of        dots in each color fired by the printheads connected to the        ISISlaves    -   configuration of GPIO ports e.g. for clutch control and lid open        detect    -   power down command telling the ISISlave to enter sleep mode    -   ink cartridge fail information

This list is not complete and the time constraints associated with theserequirements have yet to be determined.

In general the PrintMaster may need to be able to:

-   -   send messages to an ISISlave which will cause the ISISlave to        return the contents of ISISlave registers to the PrintMaster or    -   to program ISISlave registers with values sent by the        PrintMaster

This should be under the control of software running on the CPU whichwrites messages to the ISI/SCB interface.

12.1.2.3.6 ISISlave to PrintMaster Communication

ISISlaves may need to communicate the following information to thePrintMaster:

-   -   ink status e.g. dotCount data i.e. the number of dots in each        color fired by the printheads connected to the ISISlaves    -   band related information e.g. finished band interrupts    -   page related information i.e. buffer underrun, page finished        interrupts    -   MMU security violation interrupts    -   GPIO interrupts and status e.g. clutch control and lid open        detect    -   printhead temperature    -   printhead dead nozzle information from SoPEC printhead nozzle        tests    -   power management status

This list is not complete and the time constraints associated with theserequirements have yet to be determined.

As the ISI is an insecure interface commands issued over the ISI shouldbe of limited capability e.g. only limited register writes allowed. Thesoftware protocol needs to be constructed with this in mind. In generalISISlaves may need to return register or status messages to thePrintMaster or ISIMaster. They may also need to indicate to thePrintMaster or ISIMaster that a particular interrupt has occurred on theISISlave. This should be under the control of software running on theCPU which writes messages to the ISI block.

12.1.2.3.7 ISISlave to ISISlave Communication

The amount of information that will need to be communicated betweenISISlaves will vary considerably depending on the printer configuration.In some systems ISISlave devices will only need to exchange smallamounts of control information with each other while in other systems(such as those employing a storage SoPEC or extra USB connection) largeamounts of compressed page data may be moved between ISISlaves.ScenarIOs where ISISlave to ISISlave communication is required include:(a) when the PrintMaster is not the ISIMaster, (b) QA Chip ink usageprotocols, (c) data transmission from data storage SoPECs, (d) whenthere are multiple external host connections supplying data to theprinter.

12.1.3 SCB Block Diagram

The SCB consists of four main sub-blocks, as shown in the basic blockdiagram of FIG. 28.

12.1.4 Definitions of I/Os

The toplevel I/Os of the SCB are listed in Table 32. A more detaileddescription of their functionality will be given in the relevantsub-block sections. TABLE 32 SCB I/O Port name s I/O Description Clocksand Resets prst_n 1 In System reset signal. Active low. Pclk 1 In Systemclock. usbclk 1 In 48 MHz clock for the USB device and host cores. Thecores also require a 12 MHz clock, which will be generated locally bydividing the 48 MHz clock by 4. isi_cpr_reset_n 1 Out Signal from theISI indicating that ISI activity has been detected while in sleep modeand so the chip should be reset. Active low. usbd_cpr_reset_n 1 OutSignal from the USB device that a USB reset has occurred. Active low.USB device IO transceiver signals usbd_ts 1 Out USB device IOtransceiver (BUSB2_PM) driver three-state control. Active high enable.usbd_a 1 Out USB device IO transceiver (BUSB2_PM) driver data input.usbd_se0 1 Out USB device IO transceiver (BUSB2_PM) single-ended zeroinput. Active high. usbd_zp 1 In USB device IO transceiver (BUSB2_PM) D+receiver output. usbd_zm 1 In USB device IO transceiver (BUSB2_PM) D−receiver output. usbd_z 1 In USB device IO transceiver (BUSB2_PM)differential receiver output. usbd_pull_up_en 1 Out USB device pull-upresistor enable. Switches power to the external pull-up resistor,connected to the D+ line that is required for device identification tothe USB. Active high. usbd_vbus_sense 1 In USB device VBUS power sense.Used to detect power on VBUS. NOTE: The IBM Cu11 PADS are 3.3 V, VBUS is5 V. An external voltage conversion will be necessary, e.g. resistordivider network. Active high. USB host IO transceiver signals usbh_ts 1Out USB host IO transceiver (BUSB2_PM) driver three-state control.Active high enable usbh_a 1 Out USB host IO transceiver (BUSB2_PM)driver data input. usbh_se0 1 Out USB host IO transceiver (BUSB2_PM)single- ended zero input. Active high. usbh_zp 1 In USB host IOtransceiver (BUSB2_PM) D+ receiver output. usbh_zm 1 In USB host IOtransceiver (BUSB2_PM) D− receiver output. usbh_z 1 In USB host IOtransceiver (BUSB2_PM) differential receiver output. usbh_over_current 1In USB host port power over current indicator. Active high.usbh_power_en 1 Out USB host VBUS power enable. Used for port powerswitching. Active high. CPU Interface cpu_adr[n:2] n−1 In CPU addressbus. cpu_dataout[31:0] 32 In Shared write data bus from the CPUscb_cpu_data[31:0] 32 Out Read data bus to the CPU cpu_rwn 1 In Commonread/not-write signal from the CPU cpu_acode[1:0] 2 In CPU Access Codesignals. These decode as follows: 00 - User program access 01 - Userdata access 10 - Supervisor program access 11 - Supervisor data accesscpu_scb_sel 1 In Block select from the CPU. When cpu_scb_sel is highboth cpu_adr and cpu_dataout are valid scb_cpu_rdy 1 Out Ready signal tothe CPU. When scb_cpu_rdy is high it indicates the last cycle of theaccess. For a write cycle this means cpu_dataout has been registered bythe SCB and for a read cycle this means the data on scb_cpu_data isvalid. scb_cpu_berr 1 Out Bus error signal to the CPU indicating aninvalid access. scb_cpu_debug_valid 1 Out Signal indicating that thedata currently on scb_cpu_data is valid debug data Interrupt signalsdma_icu_irq 1 Out DMA interrupt signal to the interrupt controllerblock. isi_icu_irq 1 Out ISI interrupt signal to the interruptcontroller block. usb_icu_irq[1:0] 2 Out USB host and device interruptsignals to the ICU. Bit 0 - USB Host interrupt Bit 1 - USB Deviceinterrupt DIU interface scb_diu_wadr[21:5] 17 Out Write address bus tothe DIU scb_diu_data[63:0] 64 Out Data bus to the DIU. scb_diu_wreq 1Out Write request to the DIU diu_scb_wack 1 In Acknowledge from the DIUthat the write request was accepted. scb_diu_wvalid 1 Out Signal fromthe SCB to the DIU indicating that the data currently on thescb_diu_data[63:0] bus is valid scb_diu_wmask[7:0] 7 Out Byte alignedwrite mask. A “1” in a bit field of “scb_diu_wmask[7:0]” means that thecorresponding byte will be written to DRAM. scb_diu_rreq 1 Out Readrequest to the DIU. scb_diu_radr[21:5] 17 Out Read address bus to theDIU diu_scb_rack 1 In Acknowledge from the DIU that the read request wasaccepted. diu_scb_rvalid 1 In Signal from the DIU to the SCB indicatingthat the data currently on the diu_data[63:0] bus is validdiu_data[63:0] 64 In Common DIU data bus. GPIO interfaceisi_gpio_dout[3:0] 4 Out ISI output data to GPIO pins isi_gpio_e[3:0] 4Out ISI output enable to GPIO pins gpio_isi_din[3:0] 4 In Input datafrom GPIO pins to ISI12.1.5 SCB Data Flow

A logical view of the SCB is shown in FIG. 29, depicting the transfer ofdata within the SCB.

12.2 USBD (USB Device Sub-Block)

12.2.1 Overview

The FS USB device controller core and associated SCB logic are referredto as the USB Device (USBD).

A SoPEC printer has FS USB device capability to facilitate communicationbetween an external USB host and a SoPEC printer. The USBD isself-powered. It connects to an external USB host via a dedicated USBinterface on the SoPEC printer, comprising a USB connector, thenecessary discretes for USB signalling and the associated SoPEC ASICI/Os.

The FS USB device core will be third party IP from Synopsys: TymeWare™USB1.1 Device Controller (UDCVCI). Refer to the UDCVCI User Manual [20]for a description of the core.

The device core does not support LS USB operation. Control and bulktransfers are supported by the device. Interrupt transfers are notconsidered necessary because the required interrupt-type functionalitycan be achieved by sending query messages over the control channel on ascheduled basis. There is no requirement to support isochronoustransfers.

The device core is configured to support 6 USB endpoints (EPs): thedefault control EP (EP0), 4 bulk OUT EPs (EP1, EP2, EP3, EP4) and 1 bulkIN EP (EP5). It should be noted that the direction of each EP is withrespect to the USB host, i.e. IN refers to data transferred to theexternal host and OUT refers to data transferred from the external host.The 4 bulk OUT EPs will be used for the transfer of data from theexternal host to SoPEC, e.g. compressed page data, program data orcontrol messages. Each bulk OUT EP can be mapped on to any targetdestination in a multi-SoPEC system, via the SCB Map configurationregisters. The bulk IN EP is used for the transfer of data from SoPEC tothe external host, e.g. a print image downloaded from a digital camerathat requires processing on the external host system. Any feedback datawill be returned to the external host on EP0, e.g. status information.

The device core does not provide internal buffering for any of its EPs(with the exception of the 8 byte setup data payload for controltransfers). All EP buffers are provided in the SCB. Buffers will begrouped according to EP direction and associated packet destination. TheSCB Map configuration registers contain a DestISIId and DestISISubId foreach OUT EP, defining their EP mapping and therefore their packetdestination. Refer to section Section 12.4 ISI (Inter SoPEC InterfaceSub-block) for further details on ISIId and ISISubId. Refer to sectionSection 12.5 CTRL (Control Sub-block) for further details on the mappingof OUT EPs.

12.2.2 USBD Effective Bandwidth

The effective bandwidth between an external USB host and the printerwill be influenced by:

-   -   Amount of activity from other devices that share the USB with        the printer.    -   Throughput of the device controller core.    -   EP buffering implementation.    -   Responsiveness of the external host system CPU in handling USB        interrupts.

To maximize bandwidth to the printer it is recommended that no otherdevices are active on the USB between the printer and the external host.If the printer is connected to a HS USB external host or hub it maylimit the bandwidth available to other devices connected to the same hubbut it would not significantly affect the bandwidth available to otherdevices upstream of the hub. The EP buffering should not limit the USBdevice core throughput, under normal operating conditions. Used in therecommended configuration, under ideal operating conditions, it isexpected that an effective bandwidth of 8-9 Mbit/s will be achieved withbulk transfers between the external host and the printer.

12.2.3 IN EP Packet Buffer

The IN EP packet buffer stores packets originating from the LEON CPUthat are destined for transmission over the USB to the external USBhost. CPU writes to the buffer are 32 bits wide. USB device core readsfrom the buffer 32 bits wide.

128 bytes of local memory are required in total for EP0-IN and EP5-INbuffering. The IN EP buffer is a single, 2-port local memory instance,with a dedicated read port and a dedicated write port. Both ports are 32bits wide. Each IN EP has a dedicated 64 byte packet location availablein the memory array to buffer a single USB packet (maximum USB packetsize is 64 bytes). Each individual 64 byte packet location is structuredas 16×32 bit words and is read/written in a FIFO manner. When the devicecore reads a packet entry from the IN EP packet buffer, the buffer mustretain the packet until the device core performs a status write,informing the SCB that the packet has been accepted by the external USBhost and can be flushed. The CPU can therefore only write a singlepacket at a time to each IN EP. Any subsequent CPU write request to abuffer location containing a valid packet will be refused, until thatpacket has been successfully transmitted.

12.2.4 OUT EP Packet Buffer

The OUT EP packet buffer stores packets originating from the externalUSB host that are destined for transmission over DMAChannel0,DMAChannel1 or the ISI. The SCB control logic is responsible for routingthe OUT EP packets from the OUT EP packet buffer to DMA or to the ISITxBuffer, based on the SCB Map configuration register settings. USB corewrites to the buffer are 32 bits wide. DMA and ISI associated reads fromthe buffer are both 64 bits wide.

512 bytes of local memory are required in total for EP0-OUT, EP1-OUT,EP2-OUT, EP3-OUT and EP4-OUT buffering. The OUT EP packet buffer is asingle, 2-port local memory instance, with a dedicated read port and adedicated write port. Both ports are 64 bits wide. Byte enables are usedfor the 32 bit wide USB device core writes to the buffer. Each OUT EPcan be mapped to DMAChannel0, DMAChannel1 or the ISI.

The OUT EP packet buffer is partitioned accordingly, resulting in threedistinct packet FIFOs:

-   -   USBDDMA0FIFO, for USB packets destined for DMAChannel0 on the        local SoPEC.    -   USBDDMA1 FIFO, for USB packets destined for DMAChannel1 on the        local SoPEC.    -   USBDISIFIFO, for USB packets destined for transmission over the        ISI.        12.2.4.1 USBDDMAnFIFO

This description applies to USBDDMA0FIFO and USBDDMA1 FIFO, where ‘n’represents the respective DMA channel, i.e. n=0 for USBDDMA0FIFO, n=1for USBDDMA1 FIFO. USBDDMAnFIFO services any EPs mapped to DMAChannelnon the local SoPEC device. This implies that a packet originating froman EP with an associated ISIId that matches the local SoPEC ISIId and anISISubId=n will be written to USBDDMAnFIFO, if there is space availablefor that packet.

USBDDMAnFIFO has a capacity of 2×64 byte packet entries, and cantherefore buffer up to 2 USB packets. It can be considered as a 2 packetentry FIFO. Packets will be read from it in the same order in which theywere written, i.e. the first packet written will be the first packetread and the second packet written will be the second packet read. Eachindividual 64 byte packet location is structured as 8×64 bit words andis read/written in a FIFO manner.

The USBDDMAnFIFO has a write granularity of 64 bytes, to allow for themaximum USB packet size. The USBDDMAnFIFO will have a read granularityof 32 bytes to allow for the DMA write access bursts of 4×64 bit words,i.e. the DMA Manager will read 32 byte chunks at a time from theUSBDDMAnFIFO 64 byte packet entries, for transfer to the DIU.

It is conceivable that a packet which is not a multiple 32 bytes in sizemay be written to the USBDDMAnFIFO. When this event occurs, the DMAManager will read the contents of the remaining address locationsassociated with the 32 byte chunk in the USBDDMAnFIFO, transferring thepacket plus whatever data is present in those locations, resulting in a32 byte packet (a burst of 4×64 bit words) transfer to the DIU.

The DMA channels should achieve an effective bandwidth of 160 Mbits/sec(1 bit/cycle) and should never become blocked, under normal operatingconditions. As the USB bandwidth is considerably less, a 2 entry packetFIFO for each DMA channel should be sufficient.

12.2.4.2 USBDISIFIFO

USBDISIFIFO services any EPs mapped to ISI. This implies that a packetoriginating from an EP with an associated ISId that does not match thelocal SoPEC ISId will be written to USBDISIFIFO if there is spaceavailable for that packet.

USBDISIFIFO has a capacity of 4×64 byte packet entries, and cantherefore buffer up to 4 USB packets. It can be considered as a 4 packetentry FIFO. Packets will be read from it in the same order in which theywere written, i.e. the first packet written will be the first packetread and the second packet written will be the second packet read, etc.Each individual 64 byte packet location is structured as 8×64 bit wordsand is read/written in a FIFO manner.

The ISI long packet format will be used to transfer data across the ISI.Each ISI long packet data payload is 32 bytes. The USBDISIFIFO has awrite granularity of 64 bytes, to allow for the maximum USB packet size.The USBDISIFIFO will have a read granularity of 32 bytes to allow forthe ISI packet size, i.e. the SCB will read 32 byte chunks at a timefrom the USBDISIFIFO 64 byte packet entries, for transfer to the ISI.

It is conceivable that a packet which is not a multiple 32 bytes in sizemay be written to the USBDISIFIFO, either intentionally or due to asoftware error. A maskable interrupt per EP is provided to flag thisevent. There will be 2 options for dealing with this scenario on a perEP basis:

-   -   Discard the packet.    -   Read the contents of the remaining address locations associated        with the 32 byte chunk in the USBDISIFIFO, transferring the        irregular size packet plus whatever data is present in those        locations, resulting in a 32 byte packet transfer to the        ISITxBuffer.

The ISI should achieve an effective bandwidth of 100 Mbits/sec (4 wireconfiguration). It is possible to encounter a number of retries whentransmitting an ISI packet and the LEON CPU will require access to theISI transmit buffer. However, considering the relatively low bandwidthof the USB, a 4 packet entry FIFO should be sufficient.

12.2.5 Wake-Up From Sleep Mode

The SoPEC will be placed in sleep mode after a suspend command isreceived by the USB device core. The USB device core will continue to bepowered and clocked in sleep mode. A USB reset, as opposed to a deviceresume, will be required to bring SoPEC out of its sleep state as thesleep state is hoped to be logically equivalent to the power down state.

The USB reset signal originating from the USB controller will bepropagated to the CPR (as usb_cpr_reset_n) if the USBWakeupEnable bit ofthe WakeupEnable register (see Table) has been set. The USBWakeupEnablebit should therefore be set just prior to entering sleep mode. There isa scenario that would require SoPEC to initiate a USB remote wake-up(i.e. where SoPEC signals resume to the external USB host after beingsuspended by the external USB host). A digital camera (or othersupported external USB device) could be connected to SoPEC via theinternal SoPEC USB host controller core interface. There may be a needto transfer data from this external USB device, via SoPEC, to theexternal USB host system for processing. If the USB connecting theexternal host system and SoPEC was suspended, then SoPEC would need toinitiate a USB remote wake-up.

12.2.6 Implementation

12.2.6.1 USBD Sub-Block Partition

-   -   Block diagram    -   Definition of I/Os        12.2.6.2 USB Device IP Core        12.2.6.3 PVCI Target        12.2.6.4 IN EP Buffer        12.2.6.5 OUT EP Buffer        12.3 USBH (USB Host Sub-Block)        12.3.1 Overview

The SoPEC USB Host Controller (HC) core, associated SCB logic andassociated SoPEC ASIC I/Os are referred to as the USB Host (USBH).

A SoPEC printer has FS USB host capability, to facilitate communicationbetween an external USB device and a SoPEC printer. The USBH connects toan external USB device via a dedicated USB interface on the SoPECprinter, comprising a USB connector, the necessary discretes for USBsignalling and the associated SoPEC ASIC I/Os.

The FS USB HC core are third party IP from Synopsys: DesignWare^(R)USB1.1 OHCI Host Controller with PVCI (UHOSTC_PVCI). Refer to theUHOSTC_PVCI User Manual [18] for details of the core. Refer to the OpenHost Controller Interface (OHCI) Specification Release [19] for detailsof OHCI operation.

The HC core supports Low-Speed (LS) USB devices, although compatibleexternal USB devices are most likely to be FS devices. It is expectedthat communication between an external USB device and a SoPEC printerwill be achieved with control and bulk transfers. However, isochronousand interrupt transfers are also supported by the HC core.

There will be 2 communication channels between the Host ControllerDriver (HCD) software running on the LEON CPU and the HC core:

-   -   OHCI operational registers in the HC core. These registers are        control, status, list pointers and a pointer to the Host        Controller Communications Area (HCCA) in shared memory. A target        Peripheral Virtual Component Interface (PCVI) on the HC core        will provide LEON with direct read/write access to the        operational registers. Refer to the OHCI Specification for        details of these registers.        -   HCCA in SoPEC eDRAM. An initiator Peripheral Virtual            Component Interface (PCVI) on the HC core will provide the            HC with DMA read/write access to an address space in eDRAM.            The HCD running on LEON will have read/write access to the            same address space. Refer to the OHCI Specification for            details of the HCCA.

The target PVCI interface is a 32 bit word aligned interface, with byteenables for write access. All read/write access to the target PVCIinterface by the LEON CPU will be 32 bit word aligned. The byte enableswill not be used, as all registers will be read and written as 32 bitwords.

The initiator PVCI interface is a 32 bit word aligned interface withbyte enables for write access. All DMA read/write accesses are 256 bitword aligned, in bursts of 4×64 bit words. As there is no guarantee thatthe read/write requests from the HC core will start at a 256 bitboundary or be 256 bits long, it is necessary to provide 8 byte enablesfor each of the 64 bit words in a write burst form the HC core to DMA.The signal scb_diu_wmask serves this purpose.

Configuration of the HC core will be performed by the HCD.

12.3.2 Read/Write Buffering

The HC core maximum burst size for a read/write access is 4×32 bitwords. This implies that the minimum buffering requirements for the HCcore will be a 1 entry deep address register and a 4 entry deep dataregister. It will be necessary to provide data and address mappingfunctionality to convert the 4×32 bit word HC core read/write burstsinto 4×64 bit word DMA read/write bursts. This will meet the minimumbuffering requirements.

12.3.3 USBH Effective Bandwidth

The effective bandwidth between an external USB device and a SoPECprinter will be influenced by:

-   -   Amount of activity from other devices that share the USB with        the external USB device.    -   Throughput of the HC core.    -   HC read/write buffering implementation.    -   Responsiveness of the LEON CPU in handling USB interrupts.

Effective bandwidth between an external USB device and a SoPEC printeris not an issue. The primary application of this connectivity is thedownload of a print image from a digital camera. Printing speed is notimportant for this type of print operation. However, to maximizebandwidth to the printer it is recommended that no other devices areactive on the USB between the printer and the external USB device. TheHC read/write buffering in the SCB should not limit the USB HC corethroughput, under normal operating conditions.

Used in the recommended configuration, under ideal operating conditions,it is expected that an effective bandwidth of 8-9 Mbit/s will beachieved with bulk transfers between the external USB device and theSoPEC printer.

12.3.4 Implementation

12.3.5 USBH Sub-Block Partition

-   -   USBH Block Diagram    -   Definition of I/Os.        12.3.5.1 USB Host IP Core        12.3.5.2 PVCI Target        12.3.5.3 PVCI Initiator        12.3.5.4 Read/Write Buffer        12.4 ISI (Inter SoPEC Interface Sub-Block)        12.4.1 Overview

The ISI is utilised in all system configurations requiring more than oneSoPEC. An example of such a system which requires four SoPECs for duplexA3 printing and an additional SoPEC used as a storage device is shown inFIG. 27.

The ISI performs much the same function between an ISISlave SoPEC andthe ISIMaster as the USB connection performs between the ISIMaster andthe external host. This includes the transfer of all program data,compressed page data and message (i.e. commands or status information)passing between the ISIMaster and the ISISlave SoPECs. The ISIMasterinitiates all communication with the ISISlaves.

12.4.2 ISI Effective Bandwidth

The ISI will need to run at a speed that will allow error freetransmission on the PCB while minimising the buffering and hardwarerequirements on SoPEC. While an ISI speed of 10 Mbit/s is adequate tomatch the effective FS USB bandwidth it would limit the systemperformance when a high-speed connection (e.g. USB2.0, IEEE1394) is usedto attach the printer to the PC. Although they would require the use ofan extra ISI-Bridge chip such systems are envisaged for more expensiveprinters (compared to the low-cost basic SoPEC powered printers that areinitially being targeted) in the future.

An ISI line speed (i.e. the speed of each individual ISI wire) of 32Mbit/s is therefore proposed as it will allow ISI data to beover-sampled 5 times (at a pclk frequency of 160 MHz). The totalbandwidth of the ISI will depend on the number of pins used to implementthe interface. The ISI protocol will work equally well if 2 or 4 pinsare used for transmission/reception. The ISINumPins register is used toselect between a 2 or 4 wire ISI, giving peak raw bandwidths of 64Mbit/s and 128 Mbit/s respectively. Using either a 2 or 4 wire ISIsolution would allow the movement of data in to and out of a storageSoPEC (as described in 12.1.1.4 above), which is the most bandwidthhungry ISI use, in a timely fashion.

The ISINumPins register is used to select between a 2 or 4 wire ISI. A 2wire ISI is the default setting for ISINumPins and this may be changedto a 4 wire ISI after initial communication has been established betweenthe ISIMaster and all ISISlaves. Software needs to ensure that theswitch from 2 to 4 wires is handled in a controlled and coordinatedfashion so that nothing is transmitted on the ISI during the switch overperiod.

The maximum effective bandwidth of a two wire ISI, after allowing forprotocol overheads and bus turnaround times, is expected to be approx.50 Mbit/s.

12.4.3 ISI Device Identification and Enumeration

The ISIMasterSel bit of the ISICntrl register (see section Table)determines whether a SoPEC is an ISIMaster (ISIMasterSel=1), or anISISlave (ISIMasterSel=0).

SoPEC defaults to being an ISISlave (ISIMasterSel=0) after a power-onreset—i.e. it will not transmit data on the ISI without first receivinga ping. If a SoPEC's ISIMasterSel bit is changed to 1, then that SoPECwill become the ISIMaster, transmitting data without requiring a ping,and generating pings as appropriately programmed.

ISIMasterSel can be set to 1 explicitly by the CPU writing directly tothe ISICntrl register. ISIMasterSel can also be automatically set to 1when activity occurs on any of USB endpoints 2-4 and theAutoMasterEnable bit of the ISICntrl register is also 1 (the defaultreset condition). Note that if AutoMasterEnable is 0, then activity onUSB endpoints 2-4 will not result in ISIMasterSel being set to 1. USBendpoints 2-4 are chosen for the automatic detection since thepower-on-reset condition has USB endpoints 0 and 1 pointing to ISIId 0(which matches the local SoPEC's ISIId after power-on reset). Thus anytransmission on USB endpoints 2-4 indicate a desire to transmit on theISI which would usually indicate ISIMaster status. The automatic settingof ISIMasterSel can be disabled by clearing AutoMasterEnable, therebyallowing the SoPEC to remain an ISISlave while still making use of theUSB endpoints 2-4 as external destinations.

Thus the setting of a SoPEC being ISIMaster or ISISlave can becompletely under software control, or can be completely automatic.

The ISIId is established by software downloaded over the ISI (inbroadcast mode) which looks at the input levels on a number of GPIO pinsto determine the ISIId. For any given printer that uses a multi-SoPECconfiguration it is expected that there will always be enough free GPIOpins on the ISISlaves to support this enumeration mechanism.

12.4.4 ISI Protocol

The ISI is a serial interface utilizing a 2/4 wire half-duplexconfiguration such as the 2-wire system shown in FIG. 30 below. AnISIMaster must always be present and a variable number of ISISlaves mayalso be on the ISI bus. The ISI protocol supports up to 14 addressableslaves, however to simplify electrical issues the ISI drivers need onlyallow for 5-6 ISI devices on a particular ISI bus. The ISI bus enablesbroadcasting of data, ISIMaster to ISISlave communication, ISISlave toISIMaster communication and ISISlave to ISISlave communication. Flowcontrol, error detection and retransmission of errored packets is alsosupported. ISI transmission is asynchronous and a Start field is presentin every transmitted packet to ensure synchronization for the durationof the packet.

To maximize the effective ISI bandwidth while minimising pinrequirements a half-duplex interleaved transmission scheme is used. FIG.31 below shows how a 16-bit word is transmitted from an ISIMaster to anISISlave over a 2-wire ISI bus. Since data will be interleaved over thewires and a 4-wire ISI is also supported, all ISI packets should be amultiple of 4 bits.

All ISI transactions are initiated by the ISIMaster and everynon-broadcast data packet needs to be acknowledged by the addressedrecipient. An ISISlave may only transmit when it receives a ping packet(see section 12.4.4.6) addressed to it. To avoid bus contention all ISIdevices must wait ISITurnAround bit-times (5 pclk cycles per bit) afterdetecting the end of a packet before transmitting a packet (assumingthey are required to transmit). All non-transmitting ISI devices musttristate their Tx drivers to avoid line contention. The ISI protocol isdefined to avoid devices driving out of order (e.g. when an ISISlave isno longer being addressed). As the ISI uses standard I/O pads there isno physical collision detection mechanism.

There are three types of ISI packet: a long packet (used for datatransmission), a ping packet (used by the ISIMaster to prompt ISISlavesfor packets) and a short packet (used to acknowledge receipt of apacket). All ISI packets are delineated by a Start and Stop fields andtransmission is atomic i.e. an ISI packet may not be split or haltedonce transmission has started.

12.4.4.1 ISI Transactions

The different types of ISI transactions are outlined in FIG. 32 below.As described later all NAKs are inferred and ACK_(S) are not addressedto any particular ISI device.

12.4.4.2 Start Field Description

The Start field serves two purposes: To allow the start of a packet beunambiguously identified and to allow the receiving device synchroniseto the data stream. The symbol, or data value, used to identify a Startfield must not legitimately occur in the ensuing packet. Bit stuffing isused to guarantee that the Start symbol will be unique in any valid(i.e. error free) packet. The ISI needs to see a valid Start symbolbefore packet reception can commence i.e. the receive logic constantlylooks for a Start symbol in the incoming data and will reject all datauntil it sees a Start symbol. Furthermore if a Start symbol occurs(incorrectly) during a data packet it will be treated as the start of anew packet. In this case the partially received packet will bediscarded.

The data value of the Start symbol should guarantee that an adequatenumber of transitions occur on the physical ISI lines to allow thereceiving ISI device to determine the best sampling window for thetransmitted data. The Start symbol should also be sufficiently long toensure that the bit stuffing overhead is low but should still be shortenough to reduce its own contribution to the packet overhead. A Startsymbol of b01010101 is therefore used as it is an effective compromisebetween these constraints.

Each SoPEC in a multi-SoPEC system will derive its system clock from aunique (i.e. one per SoPEC) crystal. The system clocks of each devicewill drift relative to each other over any period of time. The systemclocks are used for generation and sampling of the ISI data. Thereforethe sampling window can drift and could result in incorrect data valuesbeing sampled at a later point in time. To overcome this problem the ISIreceive circuitry tracks the sampling window against the incoming datato ensure that the data is sampled in the centre of the bit period.

12.4.4.3 Stop Field Description

A 1 bit-time Stop field of b1 per ISI line ensures that all ISI linesreturn to the high state before the next packet is transmitted. The stopfield is driven on to each ISI line simultaneously, i.e. b11 for a2-wire ISI and b1111 for a 4-wire ISI would be interleaved over therespective ISI lines. Each ISI line is driven high for 1 bit-time. Thisis necessary because the first bit of the Start field is b0.

12.4.4.4 Bit Stuffing

This involves the insertion of bits into the bitstream at thetransmitting SoPEC to avoid certain data patterns. The receiving SoPECwill strip these inserted bits from the bitstream.

Bit-stuffing will be performed when the Start symbol appears at alocation other than the start field of any packet, i.e. when the bitpattern b0101010 occurs at the transmitter, a 0 will be inserted toescape the Start symbol, resulting in the bit pattern b01010100.Conversely, when the bit pattern b0101010 occurs at the receiver, if thenext bit is a ‘0’ it will be stripped, if it is a ‘1’ then a Startsymbol is detected.

If the frequency variations in the quartz crystal were large enough, itis conceivable that the resultant frequency drift over a large number ofconsecutive 1s or 0s could cause the receiving SoPEC to loosesynchronisation.⁶ The quartz crystal that will be used in SoPEC systemsis rated for 32 MHz @ 100 ppm. In a multi-SoPEC system with a 32 MHz+100ppm crystal and a 32 MHz-100 ppm crystal, it would take approximately5000 pclk cycles to cause a drift of 1 pclk cycle. This means that wewould only need to bit-stuff somewhere before 1000 ISI bits ofconsecutive 1s or consecutive 0s, to ensure adequate synchronization. Asthe maximum number of bits transmitted per ISI line in a packet is 145,it should not be necessary to perform bit-stuffing for consecutive 1s or0s. We may wish to constrain the spec of xtalin and also xtalin for theISI-Bridge chip to ensure the ISI cannot drift out of sync during packetreception.⁶Current max packet size˜=290 bits=145 bits per ISI line (on a 2 wireISI)=725 160 MHz cycles. Thus the pclks in the two communicating ISIdevices should not drift by more than one cycle in 725 i.e. 1379 ppm.Careful analysis of the crystal, PLL and oscillator specs and the syncdetection circuit is needed here to ensure our solution is robust.

Note that any violation of bit stuffing will result in theRxFrameErrorSticky status bit being set and the incoming packet will betreated as an errored packet.

12.4.4.5 ISI Long Packet

The format of a long ISI packet is shown in FIG. 33 below. Data may onlybe transferred between ISI devices using a long packet as both the shortand ping packets have no payload field. Except in the case of abroadcast packet, the receiving ISI device will always reply to a longpacket with an explicit ACK (if no error is detected in the receivedpacket) or will not reply at all (e.g. an error is detected in thereceived packet), leaving the transmitter to infer a NAK. As with allISI packets the bitstream of a long packet is transmitted with its lsb(the leftmost bit in FIG. 33) first. Note that the total length (inbits) of an ISI long packet differs slightly between a 2 and 4-wire ISIsystem due to the different number of bits required for the Start andStop fields.

All long packets begin with the Start field as described earlier. ThePktDesc field is described in Table 33. TABLE 33 PktDesc fielddescription Bit Description 0:1 00 - Long packet 01 - Reserved 10 - Pingpacket 11 - Reserved 2 Sequence bit value. Only valid for long packets.See section 12.4.4.9 for a description of sequence bit operation

Any ISI device in the system may transmit a long packet but only theISIMaster may initiate an ISI transaction using a long packet. AnISISlave may only send a long packet in reply to a ping message from theISIMaster. A long packet from an ISISlave may be addressed to any ISIdevice in the system.

The Address field is straightforward and complies with the ISI namingconvention described in section 12.5.

The payload field is exactly what is in the transmit buffer of thetransmitting ISI device and gets copied into the receive buffer of theaddressed ISI device(s). When present the payload field is always 256bits.

To ensure strong error detection a 16-bit CRC is appended.

12.4.4.6 ISI Ping Packet

The ISI ping packet is used to allow ISISlaves to transmit on the ISIbus. As can be seen from FIG. 34 below the ping packet can be viewed asa special case of the long packet. In other words it is a long packetwithout any payload. Therefore the PktDesc field is the same as a longpacket PktDesc, with the exception of the sequence bit, which is notvalid for a ping packet. Both the ISISubId and the sequence bit arefixed at 1 for all ping packets. These values were chosen to maximizethe hamming distance from an ACK symbol and to minimize the likelihoodof bit stuffing. The ISISubId is unused in ping packets because theISIMaster is addressing the ISI device rather than one of the DMAchannels in the device. The ISISlave may address any ISIId.ISISubId inresponse if it wishes. The ISISlave will respond to a ping packet witheither an explicit ACK (if it has nothing to send), an inferred NAK (ifit detected an error in the ping packet) or a long packet (containingthe data it wishes to send). Note that inferred NAK_(S) do not result inthe retransmission of a ping packet. This is because the ping packetwill be retransmitted on a predetermined schedule (see 12.4.4.11 formore details).

An ISISlave should never respond to a ping message to the broadcastISIId as this must have been sent in error. An ISI ping packet willnever be sent in response to any packet and may only originate from anISIMaster.

12.4.4.7 ISI Short Packet

The ISI short packet is only 17 bits long, including the Start and Stopfields. A value of b11101011 is proposed for the ACK symbol. As a 16-bitCRC is inappropriate for such a short packet it is not used. In factthere is only one valid value for a short ACK packet as the Start, ACKand Stop symbols all have fixed values. Short packets are only used foracknowledgements (i.e. explicit ACKs). The format of a short ISI packetis shown in FIG. 35 below. The ACK value is chosen to ensure that no bitstuffing is required in the packet and to minimize its hamming distancefrom ping and long ISI packets.

12.4.4.8 Error Detection and Retransmission

The 16-bit CRC will provide a high degree of error detection and theprobability of transmission errors occurring is very low as thetransmission channel (i.e. PCB traces) will have a low inherent biterror rate. The number of undetected errors should therefore be minute.

The HDLC standard CRC-16 (i.e. G(x)=x¹⁶+x¹²+x⁵+1) is to be used for thiscalculation, which is to be performed serially. It is calculated overthe entire packet (excluding the Start and Stop fields). A simpleretransmission mechanism frees the CPU from getting involved in errorrecovery for most errors because the probability of a transmission erroroccurring more than once in succession is very, very low in normalcircumstances.

After each non-short ISI packet is transmitted the transmitting devicewill open a reply window. The size of the reply window will beISIShortReplyWin bit times when a short packet is expected in reply,i.e. the size of a short packet, allowing for worst case bit stuffing,bus turnarounds and timing differences. The size of the reply windowwill be ISILongReplyWin bit times when a long packet is expected inreply, i.e. this will be the max size of a long packet, allowing forworst case bit stuffing, bus turnarounds and timing differences. In bothcases if an ACK is received the window will close and another packet canbe transmitted but if an ACK is not received then the full length of thewindow must be waited out.

As no reply should be sent to a broadcast packet, no reply window shouldbe required however all other long packets open a reply window inanticipation of an ACK. While the desire is to minimize the time betweenbroadcast transmissions the simplest solution should be employed. Thiswould imply the same size reply window as other long packets.

When a packet has been received without any errors the receiving ISIdevice must transmit its acknowledge packet (which may be either a longor short packet) before the reply window closes. When detected errors dooccur the receiving ISI device will not send any response. Thetransmitting ISI device interprets this lack of response as a NAKindicating that errors were detected in the transmitted packet or thatthe receiving device was unable to receive the packet for some reason(e.g. its buffers are full). If a long packet was transmitted thetransmitting ISI device will keep the transmitted packet in its transmitbuffer for retransmission. If the transmitting device is the ISIMasterit will retransmit the packet immediately while if the transmittingdevice is an ISISlave it will retransmit the packet in response to thenext ping it receives from the ISIMaster.

The transmitting ISI device will continue retransmitting the packet whenit receives a NAK until it either receives an ACK or the number ofretransmission attempts equals the value of the NumRetries register. Ifthe transmission was unsuccessful then the transmitting device sets theTxErrorSticky bit in its ISIIntStatus register. The receiving devicealso sets the RxErrorSticky bit in its ISIIntStatus register whenever itdetects a CRC error in an incoming packet and is not required to takeany further action, as it is up to the transmitting device to detect andrectify the problem. The NumRetries registers in all ISI devices shouldbe set to the same value for consistent operation. Note that successfultransmission or reception of ping packets do not affect retransmissionoperation.

Note that a transmit error will cause the ISI to stop transmitting. CPUintervention will be required to resolve the source of the problem andto restart the ISI transmit operation. Receive errors however do notaffect receive operation and they are collected to facilitate problemdebug and to monitor the quality of the ISI physical channel. Transmitor receive errors should be extremely rare and their occurrence willmost likely indicate a serious problem.

Note that broadcast packets are never acknowledged to avoid contentionon the common ISI lines. If an ISISlave detects an error in a broadcastpacket it should use the message passing mechanism described earlier toalert the ISIMaster to the error if it so wishes.

12.4.4.9 Sequence Bit Operation

To ensure that communication between transmitting and receiving ISIdevices is correctly ordered a sequence bit is included in every longpacket to keep both devices in step with each other. The sequence bitfield is a constant for short or ping packets as they are not used fordata transmission. In addition to the transmitted sequence bit all ISIdevices keep two local sequence bits, one for each ISISubId. Furthermoreeach ISI device maintains a transmit sequence bit for each ISIId andISISubId it is in communication with. For packets sourced from theexternal host (via USB) the transmit sequence bit is contained in therelevant USBEPnDest register while for packets sourced from the CPU thetransmit sequence bit is contained in the CPUISITxBuffCntrl register.The sequence bits for received packets are stored in ISISubId0Seq andISISubId1Seq registers. All ISI devices will initialize their sequencebits to 0 after reset. It is-the responsibility of software to ensurethat the sequence bits of the transmitting and receiving ISI devices arecorrectly initialized each time a new source is selected for anyISIId.ISISubId channel.

Sequence bits are ignored by the receiving ISI device for broadcastpackets. However the broadcasting ISI device is free to toggle thesequence in the broadcast packets since they will not affect operation.The SCB will do this for all USB source data so that there is no specialtreatment for the sequence bit of a broadcast packet in the transmittingdevice. CPU sourced broadcasts will have sequence bits toggled at thediscretion of the program code.

Each SoPEC may also ignore the sequence bit on either of its ISISubIdchannels by setting the appropriate bit in the ISISubIdSeqMask register.The sequence bit should be ignored for ISISubId channels that will carrydata that can originate from more than one source and is self orderinge.g. control messages.

A receiving ISI device will toggle its sequence bit addressed by theISISubId only when the receiver is able to accept data and receives anerror-free data packet addressed to it. The transmitting ISI device willtoggle its sequence bit for that ISIId.ISISubId channel only when itreceives a valid ACK handshake from the addressed ISI device.

FIG. 36 shows the transmission of two long packets with the sequence bitin both the transmitting and receiving devices toggling from 0 to 1 andback to 0 again. The toggling operation will continue in this manner inevery subsequent transmission until an error condition is encountered.

When the receiving ISI device detects an error in the transmitted longpacket or is unable to accept the packet (because of full buffers forexample) it will not return any packet and it will not toggle its localsequence bit. An example of this is depicted in FIG. 37. The absence ofany response prompts the transmitting device to retransmit the original(seq=0) packet. This time the packet is received without any errors (orbuffer space may have been freed) so the receiving ISI device togglesits local sequence bit and responds with an ACK. The transmitting devicethen toggles its local sequence bit to a 1 upon correct receipt of theACK.

However it is also possible for the ACK packet from the receiving ISIdevice to be corrupted and this scenario is shown in FIG. 38. In thiscase the receiving device toggles its local sequence bit to 1 when thelong packet is received without error and replies with an ACK to thetransmitting device. The transmitting device does not receive the ACKcorrectly and so does not change its local sequence bit. It thenretransmits the seq=0 long packet. When the receiving device finds thatthere is a mismatch between the transmitted sequence bit and theexpected (local) sequence bit is discards the long packet and replieswith an ACK. When the transmitting ISI device correctly receives the ACKit updates its local sequence bit to a 1, thus restoringsynchronization. Note that when the ISISubIdSeqMask bit for theaddressed ISISubId is set then the retransmitted packet is not discardedand so a duplicate packet will be received. The data contained in thepacket should be self-ordering and so the software handling thesepackets (most likely control messages) is expected to deal with thiseventuality.

12.4.4.10 Flow Control

The ISI also supports flow control by treating it in exactly the samemanner as an error in the received packet. Because the SCB enjoysgreater guaranteed bandwidth to DRAM than both the ISI and USB cansupply flow control should not be required during normal operation. Anyblockage on a DMA channel will soon result in the NumRetries value beingexceeded and transmission from that SoPEC being halted. If a SoPECNAK_(S) a packet because its RxBuffer is full it will flag an overflowcondition. This condition can potentially cause a CPU interrupt, if thecorresponding interrupt is enabled. The RxOverflowSticky bit of itsISIIntStatus register reflects this condition. Because flow control istreated in the same manner as an error the transmitting ISI device willnot be able to differentiate a flow control condition from an error inthe transmitted packet.

12.4.4.11 Auto-Ping Operation

While the CPU of the ISIMaster could send a ping packet by writing theappropriate header to the CPUISITxBuffCntrl register it is expected thatall ping packets will be generated in the ISI itself. The use ofautomatically generated ping packets ensures that ISISlaves will begiven access to the ISI bus with a programmable minimum guaranteedfrequency in addition to whenever it would otherwise be idle. Fiveregisters facilitate the automatic generation of ping messages withinthe ISI: PingSchedule0, PingSchedule1, PingSchedule2, ISITotalPeriod andISILocalPeriod. Auto-pinging will be enabled if any bit of any of thePingScheduleN registers is set and disabled if all PingScheduleNregisters are 0x0000.

Each bit of the 15-bit PingScheduleN register corresponds to an ISIIdthat is used in the Address field of the ping packet and a 1 in the bitposition indicates that a ping packet is to be generated for that ISIId.A 0 in any bit position will ensure that no ping packet is generated forthat ISIId. As ISISlaves may differ in their bandwidth requirement(particularly if a storage SoPEC is present) three differentPingSchedule registers are used to allow an ISISlave receive up to threetimes the number of pings as another active ISISlave. When the ISIMasteris not sending long packets (sourced from either the CPU or USB in thecase of a SoPEC ISIMaster) ISI ping packets will be transmittedaccording to the pattern given by the three PingScheduleN registers. TheISI will start with the lsb of PingSchedule0 register and work its wayfrom lsb through msb of each of the PingScheduleN registers. When themsb of PingSchedule2 is reached the ISI returns to the lsb ofPingSchedule0 and continues to cycle through each bit position of eachPingScheduleN register. The ISI has more than enough time to work outthe destination of the next ping packet while a ping or long packet isbeing transmitted.

With the addition of auto-ping operation we now have three potentialsources of packets in an ISIMaster SoPEC: USB, CPU and auto-ping.Arbitration between the CPU and USB for access to the ISI is handledoutside the ISI. To ensure that local packets get priority wheneverpossible and that ping packets can have some guaranteed access to theISI we use two 4-bit counters whose reload value is contained in theISITotalPeriod and ISILocalPeriod registers. As we saw in section12.4.4.1 every ISI transaction is initiated by the ISIMastertransmitting either a long packet or a ping packet. The ISITotalPeriodcounter is decremented for every ISI transaction (i.e. either long orping) when its value is non-zero. The ISILocalPeriod counter isdecremented for every local packet that is transmitted. Neither counteris decremented by a retransmitted packet. If the ISITotalPeriod counteris zero then ping packets will not change its value from zero. Both theISITotalPeriod and ISILocalPeriod counters are reloaded by the nextlocal packet transmit request after the ISITotalPeriod counter hasreached zero and this local packet has priority over pings.

The amount of guaranteed ISI bandwidth allocated to both local and pingpackets is determined by the values of the ISITotalPeriod andISILocalPeriod registers. Local packets will always be given prioritywhen the ISILocalPeriod counter is non-zero. Ping packets will be givenpriority when the ISILocalPeriod counter is zero and the ISITotalPeriodcounter is still non-zero.

Note that ping packets are very likely to get more than their guaranteedbandwidth as they will be transmitted whenever the ISI bus wouldotherwise be idle (i.e. no pending local packets). In particular whenthe ISITotalPeriod counter is zero it will not be reloaded until anotherlocal packet is pending and so ping packets transmitted when theISITotalPeriod counter is zero will be in addition to the guaranteedbandwidth. Local packets on the other hand will never get more thantheir guaranteed bandwidth because each local packet transmitteddecrements both counters and will cause the counters to be reloaded whenthe ISITotalPeriod counter is zero. The difference between the values ofthe ISITotalPeriod and ISILocalPeriod registers determines the number ofautomatically generated ping packets that are guaranteed to betransmitted every ISITotalPeriod number of ISI transactions. If theISITotalPeriod and ISILocalPeriod values are the same then the localpackets will always get priority and could totally exclude ping packetsif the CPU always has packets to send.

For example if ISITotalPeriod=0xC; ISILocalPeriod=0x8;PingSchedule0=0x0E; PingSchedule1=0x0C and PingSchedule2=0x08 then fourping messages are guaranteed to be sent in every 12 ISI transactions.Furthermore ISIId3 will receive 3 times the number of ping packets asISId1 and ISId2 will receive twice as many as ISId1. Thus over a periodof 36 contended ISI transactions (allowing for two full rotationsthrough the three PingScheduleN registers) when local packets are alwayspending 24 local packets will be sent, ISId1 will receive 2 pingpackets, ISId2 will receive 4 pings and ISId3 will receive 6 pingpackets. If local traffic is less frequent then the ping frequency willautomatically adjust upwards to consume all remaining ISI bandwidth.

12.4.5 Wake-Up From Sleep Mode

Either the PrintMaster SoPEC or the external host may place any of theISISlave SoPECs in sleep mode prior to going into sleep mode itself. TheISISlave device should then ensure that its ISIWakeupEnable bit of theWakeupEnable register (see Table 34) is set prior to entering sleepmode. In an ISISlave device the ISI block will continue to receive powerand clock during sleep mode so that it may monitor the gpio_isi_dinlines for activity. When ISI activity is detected during sleep mode andthe ISIWakeupEnable bit is set the ISI asserts the isi_cpr_reset_nsignal. This will bring the rest of the chip out of sleep mode by meansof a wakeup reset. See chapter 16 for more details of reset propagation.

12.4.6 Implementation

Although the ISI consists of either 2 or 4 ISI data lines over which aserial data stream is demultiplexed, each ISI line is treated as aseparate serial link at the physical layer. This permits a certainamount of skew between the ISI lines that could not be tolerated if thelines were treated as a parallel bus. A lower Bit Error Rate (BER) canbe achieved if the serial data recovery is performed separately on eachserial link. FIG. 39 illustrates the ISI sub block partitioning.

12.4.6.1 ISI Sub-Block Partition

Definition of I/Os. TABLE 34 ISI I/O Port name Pins I/O DescriptionClock and Reset isi_pclk 1 In ISI primary clock. isi_reset_n 1 In ISIreset. Active low. Asserting isi_reset_n will reset all ISI logic.Synchronous to isi_pclk. Configuration isi_go 1 In ISI GO. Active high.When GO is de-asserted, all ISI statemachines are reset to their idlestates, all ISI output signals are de- asserted, but all ISI countersretain their values. When GO is asserted, all ISI counters are reset andall ISI statemachines and output signals will return to their normalmode of operation. isi_master_select 1 In ISI master select. Determineswhether the SoPEC is an ISIMaster or not 1 = ISIMaster 0 = ISISlaveisi_id[3:0] 4 In ISI ID for this device. isi_retries[3:0] 4 In ISInumber of retries. Number of times a transmitting ISI device willattempt retransmission of a NAK'd packet before aborting thetransmission and flagging an error. The value of this configurationsignal should not be changed while there are valid packets in the Txbuffer. isi_ping_schedule0[14:0] 15 In ISI auto ping schedule #0.Denotes which ISIIds will be receive ping packets. Note that bit0 refersto ISIId0, bit1 to ISIId1...bit14 to ISIId14. Setting a bit in thisschedule will enable auto ping generation for the corresponding ISI ID.The ISI will start from the bit 0 of isi_ping_schedule0 and cyclethrough to bit 14, generating pings for each bit that is set. Thisoperation will be performed in sequence from isi_ping_schedule0 throughisi_ping_schedule2. isi_ping_schedule1[14:0] 15 In As perisi_ping_schedule0. isi_ping_schedule2[14:0] 15 In As perisi_ping_schedule0. isi_total_period[3:0] 4 In Reload value of the ISITotal Period Counter. isi_local_period[3:0] 4 In Reload value of the ISILocal Period Counter. isi_number_pins 1 In Number of active ISI datapins. Used to select how many serial data pins will be used to transmitand receive data. Should reflect the number of ISI device data pins thatare in use. 1 = isi_data[3:0] active 0 = isi_data[1:0] activeisi_turn_around[3:0] 4 In ISI bus turn around time in ISI clock cycles(32 MHz). isi_short_reply_win[4:0] 5 In ISI long packet reply window inISI clock cycles (32 MHz). isi_long_reply_win[8:0] 9 In ISI long packetreply window in ISI clock cycles (32 MHz). isi_tx_enable 1 In ISItransmit enable. Active high. Enables ISI transmission of long or pingpackets. ACKs may still be transmitted when this bit is 0. The value ofthis configuration signal should not be changed while there are validpackets in the Tx buffer. isi_rx_enable 1 In ISI receive enable. Activehigh. Enables ISI packet reception. Any activity on the ISI bus will beignored when this signal is de-asserted. This signal should only bede-asserted if the ISI block is not required for use in the design.isi_bit_stuff_rate[3:0] 1 In ISI bit stuffing limit. Allows the bitstuffing counter value to be programmed. Is loaded into the 4 upper bitsof the 7bit wide bit stuffing counter. The lower bits are always loadedwith b111, to prevent bit stuffing for less than 7 consecutive ones orzeroes. E.g. b000: stuff_count = b0000111: bit stuff after 7 consecutive0/1 b111: stuff_count = b1111111: bit stuff after127 consecutive 0/1Serial Link Signals isi_ser_data_in[3:0] 4 In ISI Serial data inputs.Each bit corresponds to a separate serial link. isi_ser_data_out[3:0] 4Out ISI Serial data outputs. Each bit corresponds to a separate seriallink. isi_ser_data_en[3:0] 4 Out ISI Serial data driver enables. Activehigh. Each bit corresponds to a separate serial link. Tx Packet Bufferisi_tx_wr_en 1 In ISI Tx FIFO write enable. Active high. Assertingisi_tx_wr_en will write the 64 bit data on isi_tx_wr_data to the FIFO,providing that space is available in the FIFO. If isi_tx_wr_en remainsasserted after the last entry in the current packet is written, thewrite operation will wrap around to the start of the next packet,providing that space is available for a second packet in the FIFO.isi_tx_wr_data[63:0] 64 In ISI Tx FIFO write data. isi_tx_ping 1 In ISITx FIFO ping packet select. Active high. Asserting isi_tx_ping willqueue a ping packet for transmission, as opposed to a long packet.Although there is no data payload for a ping packet, a packet locationin the FIFO is used as a ‘place holder’ for the ping packet. Any datawritten to the associated packet location in the FIFO will be discardedwhen the ping packet is transmitted. isi_tx_id[3:0] 5 In ISI Tx FIFOpacket ID. ISI ID for each packet written to the FIFO. Registered whenthe last entry of the packet is written. isi_tx_sub_id 1 In ISI Tx FIFOpacket sub ID. ISI sub ID for each packet written to the FIFO.Registered when the last entry of the packet is written.isi_tx_pkt_count[1:0] 2 Out ISI Tx FIFO packet count. Indicates thenumber of packets contained in the FIFO. The FIFO has a capacity of 2 ×256 bit packets. Range is b00->b10. isi_tx_word_count[2:0] 3 Out ISI TxFIFO current packet word count. Indicates the number of words containedin the current Tx packet location of the Tx FIFO. Each packet locationhas a capacity of 4 × 64 bit words. Range is b000->b100. isi_tx_empty 1Out ISI Tx FIFO empty. Active high. Indicates that no packets arepresent in the FIFO. isi_tx_full 1 Out ISI Tx FIFO full. Active high.Indicates that 2 packets are present in the FIFO, therefore no morepackets can be transmitted. isi_tx_over_flow 1 Out ISI Tx FIFO overflow. Active high. Indicates that a write operation was performed on afull FIFO. The write operation will have no effect on the contents ofthe FIFO or the write pointer. isi_tx_error 1 Out ISI Tx FIFO error.Active high. Indicates that an error occurred while transmitting thepacket currently at the head of the FIFO. This will happen if the numberof transmission attempts exceeds isi_tx_retries. isi_tx_desc[2:0] 3 OutISI Tx packet descriptor field. ISI packet descriptor field for thepacket currently at the head of the FIFO. See Table for details. Onlyvalid when isi_tx_empty = 0, i.e. when there is a valid packet in theFIFO. isi_tx_addr[4:0] 5 Out ISI Tx packet address field. ISI addressfield for the packet currently at the head of the FIFO. See Table fordetails. Only valid when isi_tx_empty = 0, i.e. when there is a validpacket in the FIFO. Rx Packet FIFO isi_rx_rd_en 1 In ISI Rx FIFO readenable. Active high. Asserting isi_rx_rd_en will drive isi_rx_rd_datawith valid data, from the Rx packet at the head of the FIFO, providingthat data is available in the FIFO. If isi_rx_rd_en remains assertedafter the last entry is read from the current packet, the read operationwill wrap around to the start of the next packet, providing that asecond packet is available in the FIFO. isi_rx_rd_data[63:0] 64 Out ISIRx FIFO read data. isi_rx_sub_id 1 Out ISI Rx packet sub ID. Indicatesthe ISI sub ID associated with the packet at the head of the Rx FIFO.isi_rx_pkt_count[1:0] 2 Out ISI Rx FIFO packet count. Indicates thenumber of packets contained in the FIFO. The FIFO has a capacity of 2 ×256 bit packets. Range is b00->b10. isi_rx_word_count[2:0] 3 Out ISI RxFIFO current packet word count. Indicates the number of words containedin the Rx packet location at the head of the FIFO. Each packet locationhas a capacity of 4 × 64 bit words. Range is b000->b100. isi_rx_empty 1Out ISI Rx FIFO empty. Active high. Indicates that no packets arepresent in the FIFO. isi_rx_full 1 Out ISI Rx FIFO full. Active high.Indicates that 2 packets are present in the FIFO, therefore no morepackets can be received. isi_rx_over_flow 1 Out ISI Rx FIFO over flow.Active high. Indicates that a packet was addressed to the local ISIdevice, but the Rx FIFO was full, resulting in a NAK. isi_rx_under_run 1Out ISI Rx FIFO under run. Active high. Indicates that a read operationwas performed on an empty FIFO. The invalid read will return thecontents of the memory location currently addressed by the FIFO readpointer and will have no effect on the read pointer. isi_rx_frame_error1 Out ISI Rx framing error. Active high. Asserted by the ISI when aframing error is detected in the received packet, which can be caused byan incorrect Start or Stop field or by bit stuffing errors. Theassociated packet will be dropped. isi_rx_crc_error 1 Out ISI Rx CRCerror. Active high. Asserted by the ISI when a CRC error is detected inan incoming packet. Other than dropping the errored packet ISI receptionis unaffected by a CRC Error.12.4.6.2 ISI Serial Interface Engine (isi_sie)

There are 4 instantiations of the isi_sie sub block in the ISI, 1 perISI serial link. The isi_sie is responsible for Rx serial data sampling,Tx serial data output and bit stuffing.

Data is sampled based on a phase detection mechanism. The incoming ISIserial data stream is over sampled 5 times per ISI bit period. The phaseof the incoming data is determined by detecting transitions in the ISIserial data stream, which indicates the ISI bit boundaries. An ISI bitboundary is defined as the sample phase at which a transition wasdetected.

The basic functional components of the isi_sie are detailed in FIG. 40.These components are simply a grouping of logical functionality and donot necessarily represent hierarchy in the design.

12.4.6.2.1 SIE Edge Detection and Data I/O

The basic structure of the data I/O and edge detection mechanism isdetailed in FIG. 41.

NOTE: Serial data from the receiver in the pad MUST be synchronized tothe isi_pclk domain with a 2 stage shift register external to the ISI,to reduce the risk of metastability. ser_data_out and ser_data_en shouldbe registered externally to the ISI.

The Rx/Tx statemachine drives ser_data_en, stuff_(—)1_en andstuff_(—)0_en. The signals stuff_(—)1_en and stuff_(—)0_en cause a oneor a zero to be driven on ser_data_out when they are asserted, otherwisefifo_rd_data is selected.

12.4.6.2.2 SIE Rx/Tx Statemachine

The Rx/Tx statemachine is responsible for the transmission of ISI Txdata and the sampling of ISI Rx data. Each ISI bit period is 5 isi_pclkcycles in duration.

The Tx cycle of the Rx/Tx statemachine is illustrated in FIG. 42. Itgenerates each ISI bit that is transmitted. States tx0->tx4 representeach of the 5 isi_pclk phases that constitute a Tx ISI bit period.ser_data_en controls the tristate enable for the ISI line driver in thebidirectional pad, as shown in FIG. 41. rx_tx_cycle is asserted duringboth Rx and Tx states to indicate an active Rx or Tx cycle. It isprimarily used to enable bit stuffing.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwisestated.

The Tx cycle for Tx bit stuffing when the Rx/Tx statemachine inserts a‘0’ into the bitstream can be seen in FIG. 43.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwisestated

The Tx cycle for Tx bit stuffing when the RxTx statemachine inserts a‘1’ into the bitstream can be seen in FIG. 44.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwisestated

The tx* and stuff* states are detailed separately for clarity. Theycould be easily combined when coding the statemachine, however it wouldbe better for verification and debugging if they were kept separate.

The Rx cycle of the ISI Rx/Tx statemachine is detailed in FIG. 45. TheRx cycle of the Rx/Tx Statemachine, samples each ISI bit that isreceived. States rx0->rx4 represent each of the 5 isi_pclk phases thatconstitute a Rx ISI bit period.

The optimum sample position for an ideal ISI bit period is 2 isi_pclkcycles after the ISI bit boundary sample, which should result in a datasample close to the centre of the ISI bit period. rx_sample is assertedduring the rx2 state to indicate a valid ISI data sample on rx_bit,unless the bit should be stripped when flagged by the bit stuffingstatemachine, in which case rx_sample is not asserted during rx2 and thebit is not written to the FIFO. When edge is asserted, it resets the Rxcycle to the rx0 state, from any rx state. This is how the isi_sietracks the phase of the incoming data. The Rx cycle will cycle throughstates rx0->rx4 until edge is asserted to reset the sample phase, or atx_req is asserted indicating that the ISI needs to transmit.

Due to the 5 times oversampling a maximum phase error of 0.4 of an ISIbit period (2 isi_pclk cycles out of 5) can be tolerated.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwisestated.

An example of the Tx data generation mechanism is detailed in FIG. 46.tx_req and fifo_wr_tx are driven by the framer block.

An example of the Rx data sampling functional timing is detailed in FIG.47. The dashed lines on the ser_data_in_ff signal indicate where theRx/Tx statemachine perceived the bit boundary to be, based on the phaseof the last ISI bit boundary. It can be seen that data is sampled duringthe same phase as the previous bit was, in the absence of a transition.

12.4.6.2.3 SIE Rx/Tx FIFO

The Rx/Tx FIFO is a 7×1 bit synchronous look-ahead FIFO that is sharedfor Tx and Rx operations. It is required to absorb any Rx/Tx latencycaused by bit stripping/stuffing on a per ISI line basis, i.e. some ISIlines may require bit stripping/stuffing during an ISI bit period whilethe others may not, which would lead to a loss of synchronizationbetween the data of the different ISI lines, if a FIFO were not presentin each isi_sie.

The basic functional components of the FIFO are detailed in FIG. 48.tx_ready is driven by the Rx/Tx statemachine and selects which signalscontrol the read and write operations. tx_ready=1 during ISItransmission and selects the fifo_*tx control and data signals.tx_ready=0 during ISI reception and selects the fifo_*rx control anddata signals. fifo_reset is driven by the Rx/Tx statemachine. It isactive high and resets the FIFO and associated logic before/aftertransmitting a packet to discard any residual data.

The size of the FIFO is based on the maximum bit stuffing frequency andthe size of the shift register used to segment/re-assemble the multipleserial streams in the ISI framing logic. The maximum bit stuffingfrequency is every 7 consecutive ones or zeroes. The shift register usedis 32 bits wide. This implies that the maximum number of stuffed bitsencountered in the time it takes to fill/empty the shift register if 4.This would suggest that 4×1 bit would be the minimum ideal size of theFIFO. However it is necessary to allow for different skew and phaseerror between the ISI lines, hence a 7×1 bit FIFO.

The FIFO is controlled by the isi_sie during packet reception and iscontrolled by the isi_frame block during packet transmission. This isillustrated in FIG. 49. The signal tx_ready selects which mode the FIFOcontrol signals operate in. When tx_ready=0, i.e. Rx mode, the isi_siecontrol signals rx_sample, fifo_rd_rx and ser_data_in_ff are selected.When tx_ready=1, i.e. Tx mode, the sie_frame control signals fifo_wr_tx,fifo_rd_tx and fifo_wr_data_tx are selected.

12.4.6.3 Bit Stuffing

Programmable bit stuffing is implemented in the isi_sie. This is toallow the system to determine the amount of bit stuffing necessary for aspecific ISI system devices. It is unlikely that bit stuffing would berequired in a system using a 100 ppm rated crystal. However, aprogrammable bit stuffing implementation is much more versatile androbust.

The bit stuffing logic consists of a counter and a statemachine thattrack the number of consecutive ones or zeroes that are transmitted orreceived and flags the Rx/Tx statemachine when the bit stuffing limithas been reached. The counter, stuff count, is a 7 bit counter, whichdecrements when rx_sample is asserted on a Rx cycle or when fifo_rd_txis asserted on a Tx cycle. The upper 4 bits of stuff_count are loadedwith isi_bit_stuff_rate. The lower 3 bits of stuff_count are alwaysloaded with b111, i.e. for isi_bit_stuff_rate=b000, the counter would beloaded with b0000111. This is to prevent bit stuffing for less than 7consecutive ones or zeroes. This allows the bit stuffing limit to be setin the range 7->127 consecutive ones or zeroes.

NOTE: It is extremely important that a change in the bit stuffing rate,isi_bit_stuff_rate, is carefully coordinated between ISI devices in asystem. It is obvious that ISI devices will not be able to communicatereliably with each other with different bit stuffing settings. It isrecommended that all ISI devices in a system default to the safest bitstuffing rate (isi_bit_stuff_rate=b000) at reset. The system can thenco-ordinate the change to an optimum bit stuffing rate.

The ISI bit stuffing statemachine Tx cycle is shown in FIG. 50. Thecounter is loaded when stuff_count_load is asserted.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwisestated.

The ISI bit stuffing statemachine Rx cycle is shown in FIG. 51. Itshould be noted that the statemachine enters the strip state whenstuff_count=0x2. This is because the statemachine can only transition torx0 or rx1 when rx_sample is asserted as it needs to be synchronized tochanges in sampling phase introduced by the Rx/Tx statemachine.Therefore a one or a zero has already been sampled by the time it entersrx0 or rx1. This is not the case for the Tx cycle, as it will alwayshave a stable 5 isi_pclk cycles per bit period and relies purely on thedata value when entering tx0 or tx1. The Tx cycle therefore entersstuff1 or stuff0 when stuff_count=0x1.

NOTE: All statemachine signals are assumed to be ‘0’ unless otherwisestated.

12.4.6.4 ISI Framing and CRC Sub-Block (isi_frame)

12.4.6.4.1 CRC Generation/Checking

A Cyclic Redundancy Checksum (CRC) is calculated over all fields exceptthe start and stop fields for each long or ping packet transmitted. Thereceiving ISI device will perform the same calculation on the receivedpacket to verify the integrity of the packet. The procedure used in theCRC generation/checking is the same as the Frame Checking Sequence (FCS)procedure used in HDLC, detailed in ITU-T Recommendation T30[39].

For generation/checking of the CRC field, the shift register illustratedin FIG. 52 is used to perform the modulo 2 division on the packetcontents by the polynomial G(x)=x¹⁶+x¹²+x⁵+1.

To generate the CRC for a transmitted packet, where T(x)=[PacketDescriptor field, Address field, Data Payload field] (a ping packet willnot contain a data payload field).

-   -   Set the shift register to 0xFFFF.    -   Shift T(x) through the shift register, LSB first. This can occur        in parallel with the packet transmission.    -   Once the each bit of T(x) has been shifted through the register,        it will contain the remainder of the modulo 2 division        T(x)/G(x).    -   Perform a ones complement of the register contents, giving the        CRC field which is transmitted MSB first, immediately following        the last bit of M(x        -   To check the CRC for a received packet, where R(x)=[Packet            Descriptor field, Address field, Data Payload field, CRC            field] (a ping packet will not contain a data payload            field).        -   Set the shift register to 0xFFFF.        -   Shift R(x) through the shift register, LSB first. This can            occur in parallel with the packet reception.        -   Once each bit of the packet has been shifted through the            register, it will contain the remainder of the modulo 2            division R(x)/G(x).        -   The remainder should equal b0001110100001111, for a packet            without errors.            12.5 CTRL (Control Sub-Block)            12.5.1 Overview

The CTRL is responsible for high level control of the SCB sub-blocks andcoordinating access between them. All control and status registers forthe SCB are contained within the CTRL and are accessed via the CPUinterface. The other major components of the CTRL are the SCB Map logicand the DMA Manager logic.

12.5.2 SCB Mapping

In order to support maximum flexibility when moving data through amulti-SoPEC system it is possible to map any USB endpoint onto eitherDMAChannel within any SoPEC in the system. The SCB map, and indeed theSCB itself is based around the concept of an ISIId and an ISISubId. EachSoPEC in the system has a unique ISIId and two ISISubIds, namelyISISubId0 and ISISubId1. We use the convention that ISISubId0corresponds to DMAChannel0 in each SoPEC and ISISubId1 corresponds toDMAChannel1. The naming convention for the ISIId is shown in Table 35below and this would correspond to a multi-SoPEC system such as thatshown in FIG. 27. We use the term ISIId instead of SoPECId to avoidconfusion with the unique ChipID used to create the SoPEC_id andSoPEC_id_key (see chapter 17 and [9] for more details). TABLE 35 ISIIdnaming convention ISIId SoPEC to which it refers 0-14 Standard deviceISIIds (0 is the power-on reset value) 15 Broadcast ISIId

The combined ISIId and ISISubId therefore allows the ISI to addressDMAChannel0 or DMAChannel1 on any SoPEC device in the system. The ISI,DMA manager and SCB map hardware use the ISIId and ISISubId to handlethe different data streams that are active in a multi-SoPEC system asdoes the software running on the CPU of each SoPEC. In this document wewill identify DMAChannels as ISIx.y where x is the ISIId and y is theISISubId. Thus ISI2.1 refers to DMAChannel1 of ISISlave2. Any data sentto a broadcast channel, i.e. ISI15.0 or ISI15.1, are received by everyISI device in the system including the ISIMaster (which may be anISI-Bridge). The USB device controller and software stacks however haveno understanding of the ISIId and ISISubId but the Silverbrook printerdriver software running on the external host does make use of the ISIIdand ISISubId. USB is simply used as a data transport—the mapping of USBdevice endpoints onto ISIId and SubId is communicated from the externalhost Silverbrook code to the SoPEC Silverbrook code through USB control(or possibly bulk data) messages i.e. the mapping information is simplydata payload as far as USB is concerned. The code running on SoPEC isresponsible for parsing these messages and configuring the SCBaccordingly.

The use of just two DMAChannels places some limitations on what can beachieved without software intervention. For every SoPEC in the systemthere are more potential sources of data than there are sinks. Forexample an ISISlave could receive both control and data messages fromthe ISIMaster SoPEC in addition to control and data from the externalhost, either specifically addressed to that particular ISISlave or overthe broadcast ISI channel. However all ISISlaves only have two possibledata sinks, i.e. DMAChannelz0 and DMAChannel1. Another example is theISIMaster in a multi-SoPEC system which may receive control messagesfrom each SoPEC in addition to control and data information from theexternal host (e.g. over USB). In this case all of the control messagesare in contention for access to DMAChannel0. We resolve these potentialconflicts by adopting the following conventions:

1) Control messages may be interleaved in a memory buffer: The memorybuffer that the DMAChannel0 points to should be regarded as a centralpool of control messages. Every control message must contain fields thatidentify the size of the message, the source and the destination of thecontrol message. Control messages may therefore be multiplexed over aDMAChannel which allows several control message sources to address thesame DMAChannel. Furthermore, if SoPEC-type control messages containsource and destination fields it is possible for the external host tosend control messages to individual SoPECs over the ISI15.0 broadcastchannel.

2) Data messages should not be interleaved in a memory buffer: As datamessages are typically part of a much larger block of data that is beingtransferred it is not possible to control their contents in the samemanner as is possible with the control messages. Furthermore we do notwant the CPU to have to perform reassembly of data blocks. Data messagesfrom different sources cannot be interleaved over the sameDMAChannel—the SCB map must be reconfigured each time a different datasource is given access to the DMAChannel.

3) Every reconfiguration of the SCB map requires the exchange of controlmessages: SoPEC's SCB map reset state is shown in Table and anysubsequent modifications to this map require the exchange of controlmessages between the SoPEC and the external host. As the external hostis expected to control the movement of data in any SoPEC system it isanticipated that all changes to the SCB map will be performed inresponse to a request from the external host. While the SoPEC couldautonomously reconfigure the SCB map (this is entirely up to thesoftware running on the SoPEC) it should not do so without informing theexternal host in order to avoid data being misrouted.

An example of the above conventions in operation is worked through insection 12.5.2.3.

12.5.2.1 SCB Map Rules

The operation of the SCB map is described by these 2 rules:

Rule 1: A packet is routed to the DMA manager if it originates from theUSB device core and has an ISIId that matches the local SoPEC ISIId.

Rule 2: A packet is routed to the ISI if it originates from the CPU orhas an ISIId that does not match the local SoPEC ISIId.

If the CPU erroneously addresses a packet to the ISIId contained in theISIId register (i.e. the ISIId of the local SoPEC) then that packet willbe transmitted on the ISI rather than be sent to the DMA manager. Whilethis will usually cause an error on the ISI there is one situation whereit could be beneficial, namely for initial dialog in a 2 SoPEC system asboth devices come out of reset with an ISIId of 0.

12.5.2.2 External Host to ISIMaster SoPEC Communication

Although the SCB map configuration is independent of ISIMaster status,the following discussion on SCB map configurations assumes the ISIMasteris a SoPEC device rather than an ISI bridge chip, and that only a singleUSB connection to the external host is present. The information shouldapply broadly to an ISI-Bridge but we focus here on an ISIMaster SoPECfor clarity.

As the ISIMaster SoPEC represents the printer device on the PC USB busit is required by the USB specification to have a dedicated controlendpoint, EP0. At boot time the ISIMaster SoPEC will also require a bulkdata endpoint to facilitate the transfer of program code from theexternal host. The simplest SCB map configuration, i.e. for a singlestand-alone SoPEC, is sufficient for external host to ISIMaster SoPECcommunication and is shown in Table 36. TABLE 36 Single SoPEC SCB mapconfiguration Source Sink EP0 ISI0.0 EP1 ISI0.1 EP2 nc EP3 nc EP4 nc

In this configuration all USB control information exchanged between theexternal host and SoPEC over EP0 (which is the only bidirectional USBendpoint). SoPEC specific control information (printer status, DNC infoetc.) is also exchanged over EP0.

All packets sent to the external host from SoPEC over EP0 must bewritten into the DMA mapped EP buffer by the CPU (LEON-PC dataflow inFIG. 29). All packets sent from the external host to SoPEC are placed inDRAM by the DMA Manager, where they can be read by the CPU (PC-DIUdataflow in FIG. 29). This asymmetry is because in a multi-SoPECenvironment the CPU will need to examine all incoming control messages(i.e. messages that have arrived over DMAChannel0) to ascertain theirsource and destination (i.e. they could be from an ISISlave and destinedfor the external host) and so the additional overhead in having the CPUmove the short control messages to the EP0 FIFO is relatively small.Furthermore we wish to avoid making the SCB more complicated thannecessary, particularly when there is no significant performance gain tobe had as the control traffic will be relatively low bandwidth.

The above mechanisms are appropriate for the types of communicationoutlined in sections 12.1.2.1.1 through 12.1.2.1.4

12.5.2.3 Broadcast Communication

The SCB configuration for broadcast communication is also the default,post power-on reset, configuration for SoPEC and is shown in Table 37.TABLE 37 Default SoPEC SCB map configuration Source Sink EP0 ISI0.0 EP1ISI0.1 EP2 ISI15.0 EP3 ISI15.1 EP4 ISI1.1

USB endpoints EP2 and EP3 are mapped onto ISISubID0 and ISISubId1 ofISIId15 (the broadcast ISIId channel). EP0 is used for control messagesas before and EP1 is a bulk data endpoint for the ISIMaster SoPEC.Depending on what is convenient for the boot loader software, EP1 may ormay not be used during the initial program download, but EP1 is highlylikely to be used for compressed page or other program downloads later.For this reason it is part of the default configuration. In this setupthe USB device configuration will take place, as it always must, byexchanging messages over the control channel (EP0).

One possible boot mechanism is where the external host sends thebootloader1 program code to all SoPECs by broadcasting it over EP3. EachSoPEC in the system then authenticates and executes the bootloader1program. The ISIMaster SoPEC then polls each ISISlave (over the ISIx.0channel). Each ISISlave ascertains its ISIId by sampling the particularGPIO pins required by the bootloader1 and reporting its presence andstatus back to the ISIMaster. The ISIMaster then passes this informationback to the external host over EP0. Thus both the external host and theISIMaster have knowledge of the number of SoPECs, and their ISIIds, inthe system. The external host may then reconfigure the SCB map to betteroptimise the SCB resources for the particular multi-SoPEC system. Thiscould involve simplifying the default configuration to a single SoPECsystem or remapping the broadcast channels onto DMAChannels inindividual ISISlaves.

The following steps are required to reconfigure the SCB map from theconfiguration depicted in Table to one where EP3 is mapped onto ISI1.0:

-   -   1) The external host sends a control message(s) to the ISIMaster        SoPEC requesting that USB EP3 be remapped to ISI1.0    -   2) The ISIMaster SoPEC sends a control message to the external        host informing it that EP3 has now been mapped to ISI1.0 (and        therefore the external host knows that the previous mapping of        ISI15.1 is no longer available through EP3).    -   3) The external host may now send control messages directly to        ISISlave1 without requiring any CPU intervention on the        ISIMaster SoPEC        12.5.2.4 External Host to ISISlave SoPEC Communication

If the ISIMaster is configured correctly (e.g. when the ISIMaster is aSoPEC, and that SoPEC's SCB map is configured correctly) then data sentfrom the external host destined for an ISISlave will be transmitted onthe ISI with the correct address. The ISI automatically forwards anydata addressed to it (including broadcast data) to the DMA channel withthe appropriate ISISubId. If the ISISlave has data to send to theexternal host it must do so by sending a control message to theISIMaster identifying the external host as the intended recipient. It isthen the ISIMaster's responsibility to forward this message to theexternal host.

With this configuration the external host can communicate with theISISlave via broadcast messages only and this is the mechanism by whichthe bootloader1 program is downloaded. The ISISlave is unable tocommunicate with the external host (or the ISIMaster) until thebootloader1 program has successfully executed and the ISISlave hasdetermined what its ISIId is. After the bootloader1 program (andpossibly other programs) has executed the SCB map of the ISIMaster maybe reconfigured to reflect the most appropriate topology for theparticular multi-SoPEC system it is part of.

All communication from an ISISlave to external host is either achieveddirectly (if there is a direct USB connection present for example) or bysending messages via the ISIMaster. The ISISlave can never initiatecommunication to the external host. If an ISISlave wishes to send amessage to the external host via the ISIMaster it must wait until it ispinged by the ISIMaster and then send a the message in a long packetaddressed to the ISIMaster. When the ISIMaster receives the message fromthe ISISlave it first examines it to determine the intended destinationand will then copy it into the EP0 FIFO for transmission to the externalhost. The software running on the ISIMaster is responsible for anyarbitration between messages from different sources (including itself)that are all destined for the external host.

The above mechanisms are appropriate for the types of communicationoutlined in sections 12.1.2.1.5 and 12.1.2.1.6.

12.5.2.5 ISIMaster to ISISlave Communication

All ISIMaster to ISISlave communication takes place over the ISI.Immediately after reset this can only be by means of broadcast messages.Once the bootloader1 program has successfully executed on all SoPECs ina multi-SoPEC system the ISIMaster can communicate with each SoPEC on anindividual basis.

If an ISISlave wishes to send a message to the ISIMaster it may do so inresponse to a ping packet from the ISIMaster. When the ISIMasterreceives the message from the ISISlave it must interpret the message todetermine if the message contains information required to be sent to theexternal host. In the case of the ISIMaster being a SoPEC, software willtransfer the appropriate information into the EP0 FIFO for transmissionto the external host.

The above mechanisms are appropriate for the types of communicationoutlined in sections 12.1.2.3.3 and 12.1.2.3.4.

12.5.2.6 ISISlave to ISISlave Communication

ISISlave to ISISlave communication is expected to be limited to twospecial cases: (a) when the PrintMaster is not the ISIMaster and (b)when a storage SoPEC is used. When the PrintMaster is not the ISIMasterthen it will need to send control messages (and receive responses tothese messages) to other ISISlaves. When a storage SoPEC is present itmay need to send data to each SoPEC in the system. All ISISlave toISISlave communication will take place in response to ping messages fromthe ISIMaster.

12.5.2.7 Use of the SCB Map in an ISISlave with a External HostConnection

After reset any SoPEC (regardless of ISIMaster/Slave status) with anactive USB connection will route packets from EP0,1 to DMA channels 0,1because the default SCB map is to map EP0 to ISIId0.0 and EP1 toISIId0.1 and the default ISIId is 0. At some later time the SoPEC learnsits true ISIId for the system it is in and re-configures its ISIId andSCB map registers accordingly. Thus if the true ISIId is 3 the externalhost could reconfigure the SCB map so that EP0 and EP1 (or any otherendpoints for that matter) map to ISIId3.0 and 3.1 respectively. Theco-ordination of the updating of the ISIId registers and the SCB map isa matter for software to take care of. While the AutoMasterEnable bit ofthe ISICntrl register is set the external host must not send packetsdown EP2-4 of the USB connection to the device intended to be anISISlave. When AutoMasterEnable has been cleared the external host maysend data down any endpoint of the USB connection to the ISISlave.

The SCB map of an ISISlave can be configured to route packets from anyEP to any ISIId.ISISubId oust as an ISIMaster can). As with an ISIMasterthese packets will end up in the SCBTxBuffer but while an ISIMasterwould just transmit them when it got a local access slot (from pingarbitration) the ISISlave can only transmit them in response to a ping.All this would happen without CPU intervention on the ISISlave (orISIMaster) and as long as the ping frequency is sufficiently high itwould enable maximum use of the bandwidth on both USB buses.

12.5.3 DMA Manager

The DMA manager manages the flow of data between the SCB and theembedded DRAM. Whilst the CPU could be used for the movement of data inSoPEC, a DMA manager is a more efficient solution as it will handle datain a more predictable fashion with less latency and requiring lessbuffering. Furthermore a DMA manager is required to support the ISItransfer speed and to ensure that the SoPEC could be used with a highspeed ISI-Bridge chip in the future.

The DMA manager utilizes 2 write channels (DMAChannel0, DMAChannel1) and1 read/write channel (DMAChannel2) to provide 2 independent modes ofaccess to DRAM via the DIU interface:

-   -   USBD/ISI type access.    -   USBH type access.

DIU read and write access is in bursts of 4×64 bit words. Byte alignedwrite enables are provided for write access. Data for DIU write accesseswill be read directly from the buffers contained in the respective SCBsub-blocks. There is no internal SCB DMA buffer. The DMA manager handlesall issues relating to byte/word/longword address alignment, dataendianness and transaction scheduling. If a DMA channel is disabledduring a DMA access, the access will be completed. Arbitration will beperformed between the following DIU access requests:

-   -   USBD write request.    -   ISI write request.    -   USBH write request.    -   USBH read request.

DMAChannel0 will have absolute priority over any DMA requesters. In theabsence of DMAChannel0 DMA requests, arbitration will be performed in around robin manner, on a per cycle basis over the other channels.

12.5.3.1 DMA Effective Bandwidth

The DIU bandwidth available to the DMA manager must be set to ensureadequate bandwidth for all data sources, to avoid back pressure on theUSB and the ISI. This is achieved by setting the output (i.e. DIU)bandwidth to be greater than the combined input bandwidths (i.e.USBD+USBH+ISI). The required bandwidth is expected to be 160 Mbits/s (1bit/cycle @ 160 MHz). The guaranteed DIU bandwidth for the SCB isprogrammable and may need further analysis once there is betterknowledge of the data throughput from the USB IP cores.

12.5.3.2 USBDIISI DMA Access

The DMA manager uses the two independent unidirectional write channelsfor this type of DMA access, one for each ISISubID, to control themovement of data. Both DMAChannel0 and DMAChannel1 only support writeoperation and can transfer data from any USB device DMA mapped EP bufferand from the ISI receive buffer to separate circular buffers in DRAM,corresponding to each DMA channel.

While the DMA manager performs the work of moving data the CPU controlsthe destination and relative timing of data flows to and from the DRAM.The management of the DRAM data buffers requires the CPU to haveaccurate and timely visibility of both the DMA and PEP memory usage. Inother words when the PEP has completed processing of a page band the CPUneeds to be aware of the fact that an area of memory has been freed upto receive incoming data. The management of these buffers may also beperformed by the external host.

12.5.3.2.1 Circular Buffer Operation

The DMA manager supports the use of circular buffers for bothDMAChannels. Each circular buffer is controlled by 5 registers:DMAnBottomAdr, DMAnTopAdr, DMAnMaxAdr, DMAnCurrWPtr and DMAnIntAdr. Theoperation of the circular buffers is shown in FIG. 53 below.

Here we see two snapshots of the status of a circular buffer with (b)occurring sometime after (a) and some CPU writes to the registersoccurring in between (a) and (b). These CPU writes are most likely to beas a result of a finished band interrupt (which frees up buffer space)but could also have occurred in a DMA interrupt service routineresulting from DMAnIntAdr being hit. The DMA manager will continuefilling the free buffer space depicted in (a), advancing theDMAnCurrWPtr after each write to the DIU. Note that the DMACurrWPtrregister always points to the next address the DMA manager will writeto. When the DMA manager reaches the address in DMAnIntAdr (i.e.DMACurrWPtr=DMAnIntAdr) it will generate an interrupt if theDMAnIntAdrMask bit in the DMAMask register is set. The purpose of theDMAnintAdr register is to alert the CPU that data (such as a controlmessage or a page or band header) has arrived that it needs to process.The interrupt routine servicing the DMA interrupt will change theDMAnintAdr value to the next location that data of interest to the CPUwill have arrived by.

In the scenario shown in FIG. 53 the CPU has determined (most likely asa result of a finished band interrupt) that the filled buffer space in(a) has been freed up and is therefore available to receive more data.The CPU therefore moves the DMAnMaxAdr to the end of the section thathas been freed up and moves the DMAnIntAdr address to an appropriateoffset from the DMAnMaxAdr address. The DMA manager continues to fillthe free buffer space and when it reaches the address in DMAnTopAdr itwraps around to the address in DMAnBottomAdr and continues from there.DMA transfers will continue indefinitely in this fashion until the DMAmanager reaches the address in the DMAnMaxAdr register.

The circular buffer is initialized by writing the top and bottomaddresses to the DMAnTopAdr and DMAnBottomAdr registers, writing thestart address (which does not have to be the same as the DMAnBottomAdreven though it usually will be) to the DMAnCurrWPtr register andappropriate addresses to the DMAnIntAdr and DMAnMaxAdr registers. TheDMA operation will not commence until a 1 has been written to therelevant bit of the DMAChanEn register.

While it is possible to modify the DMAnTopAdr and DMAnBottomAdrregisters after the DMA has started it should be done with caution. TheDMAnCurrWPtr register should not be written to while the DMAChannel isin operation. DMA operation may be stalled at any time by clearing theappropriate bit of the DMAChanEn register or by disabling an SCB mappingor ISI receive operation.

12.5.3.2.2 Non-Standard Buffer Operation

The DMA manager was designed primarily for use with a circular buffer.However because the DMA pointers are tested for equality (i.e.interrupts generated when DMAnCurrWPtr=DMAIntAdr orDMAnCurrWPtr=DMAMaxAdr) and no bounds checking is performed on theirvalues (i e. neither DMAnIntAdr nor DMAnMaxAdr are checked to see ifthey lie between DMAnBottomAdr and DMAnTopAdr) a number of non-standardbuffer arrangements are possible. These include:

-   -   Dustbin buffer: If DMAnBottomAdr, DMAnTopAdr and DMAnCurrWPtr        all point to the same location and both DMAnIntAdr and        DMAnMaxAdr point to anywhere else then all data for that DMA        channel will be dumped into the same location without ever        generating an interrupt. This is the equivalent to writing to        /dev/null on Unix systems.    -   Linear buffer: If DMAnMaxAdr and DMAnTopAdr have the same value        then the DMA manager will simply fill from DMAnBottomAdr to        DMAnTopAdr and then stop. DMAnIntAdr should be outside this        buffer or have its interrupt disabled.        12.5.3.3 USBH DMA Access

The USBH requires DMA access to DRAM in to provide a communicationchannel between the USB HC and the USB HCD via a shared memory resource.The DMA manager uses two independent channels for this type of DMAaccess, one for reads and one for writes. The DRAM addresses provided tothe DIU interface are generated based on addresses defined in the USB HCcore operational registers, in USBH section 12.3.

12.5.3.4 Cache Coherency

As the CPU will be processing some of the data transferred (particularlycontrol messages and page/band headers) into DRAM by the DMA manager,care needs to be taken to ensure that the data it uses is the mostrecently transferred data. Because the DMA manager will be updating thecircular buffers in DRAM without the knowledge of the cache controllerlogic in the LEON CPU core the contents of the cache can becomeoutdated. This situation can be easily handled by software, for exampleby flushing the relevant cache lines, and so there is no hardwaresupport to enforce cache coherency.

12.5.4 ISI Transmit Buffer Arbitration

The SCB control logic will arbitrate access to the ISI transmit buffer(ISITxBuffer) interface on the ISI block. There are two sources of ISITx packets:

-   -   CPUISITxBuffer, contained in the SCB control block.    -   ISI mapped USB EP OUT buffers, contained in the USB device        block.

This arbitration is controlled by the ISITxBuffArb register whichcontains a high priority bit for both the CPU and the USB. If only oneof these bits is set then the corresponding source always has priority.Note that if the CPU is given absolute priority over the USB, then thesoftware filling the ISI transmit buffer needs to ensure that sufficientUSB traffic is allowed through. If both bits of the ISITxBufferArb havethe same value then arbitration will take place on a round robin basis.The control logic will use the USBEPnDest registers, as it will use theCPUISITxBuffCntrl register, to determine the destination of the packetsin these buffers. When the ISITxBuffer has space for a packet, the SCBcontrol logic will immediately seek to refill it. Data will betransferred directly from the CPUISITxBuffer and the ISI mapped USB EPOUT buffers to the ISITxBuffer without any intermediate buffering.

As the speed at which the ISITxBuffer can be emptied is at least 5 timesgreater than it can be filled by USB traffic, the ISI mapped USB EP OUTbuffers should not overflow using the above scheme in normal operation.There are a number of scenarIOs which could lead to the USB EPs beingtemporarily blocked such as the CPU having priority, retransmissions onthe ISI bus, channels being enabled (ChannelEn bit of the USBEPnDestregister) with data already in their associated endpoint buffers orshort packets being sent on the USB. Care should be taken to ensure thatthe USB bandwidth is efficiently utilised at all times.

12.5.5 Implementation

12.5.5.1 CTRL Sub-Block Partition

-   -   Block Diagram    -   Definition of I/Os        12.5.5.2 SCB Configuration Registers

The SCB register map is listed in Table 38. Registers are groupedaccording to which SCB sub-block their functionality is associated. Allconfiguration registers reside in the CTRL sub-block. The Reset valuesin the table indicates the 32 bit hex value that will be returned whenthe CPU reads the associated address location after reset. All Registerspre-fixed with Hc refer to Host Controller Operational Registers, asdefined in the OHCI Spec[19].

The SCB will only allow supervisor mode accesses to data space (i.e.cpu_acode[1:0]=b11). All other accesses will result in scb_cpu_berrbeing asserted.

TDB: Is read access necessary for ISI Rx/Tx buffers? Could implement theISI interface as simple FIFOs as opposed to a memory interface. TABLE 38SCB control block configuration registers Address Offset from SCB_baseRegister #Bits Reset Description CTRL 0x000 SCBResetN 4 0x0000000F SCBsoftware reset. Allows individual sub-blocks to be reset separately ortogether. Once a reset for a block has been initiated, by writing a 0 tothe relevant register field, it can not be suppressed. Each field willbe set after reset. Writing 0x0 to the SCBReset register will have thesame effect as CPR generated hardware reset. 0x004 SCBGo 2 0x00000000SCB Go. Allows the ISI and CTRL sub-blocks to be selected separately ortogether. When go is de-asserted for a particular sub-block, itsstatemachines are reset to their idle states and its interface signalsare de-asserted. The sub-block counters and configuration registersretain their values. When go is asserted for a particular sub-block, itscounters are reset. The sub-block configuration registers retain theirvalues, i.e. they don't get reset. The sub-block statemachines andinterface signals will return to their normal mode of operation. TheCTRL field should be de-asserted before disabling the clock from anypart of the SCB to avoid erroneous SCB DMA requests when the clock isenabled again. NOTE: This functionality has not been provided for theUSBH and USBD sub- blocks because of the USB IP cores that they contain.We do not have direct control over the IP core statemachines andcounters, and it would cause unpredictable behaviour if the cores weredisabled in this way during operation. 0x008 SCBWakeupEn 2 0x00000000USB/ISI WakeUpEnable register 0x00C SCBISITxBufferArb 2 0x00000000 ISItransmit buffer access priority register. 0x010 SCBDebugSel[11:2] 100x00000000 SCB Debug select register. 0x014 USBEP0Dest 7 0x00000020 Thisregister determines which of the data sinks the data arriving in EP0should be routed to. 0x018 USBEP1Dest 7 0x00000021 Data sink mapping forUSB EP1 0x01C USBEP2Dest 7 0x0000003E Data sink mapping for USB EP20x020 USBEP3Dest 7 0x0000003F Data sink mapping for USB EP3 0x024USBEP4Dest 7 0x00000023 Data sink mapping for USB EP4 0x028DMA0BottomAdr[21:5] 17 DMAChannel0 bottom address register. 0x02CDMA0TopAdr[21:5] 17 DMAChannel0 top address register. 0x030DMA0CurrWPtr[21:5] 17 DMAChannel0 current write pointer. 0x034DMA0IntAdr[21:5] 17 DMAChannel0 interrupt address register. 0x038DMA0MaxAdr[21:5] 17 DMAChannel0 max address register. 0x03CDMA1BottomAdr[21:5] 17 As per DMA0BottomAdr. 0x040 DMA1TopAdr[21:5] 17As per DMA0TopAdr. 0x044 DMA1CurrWPtr[21:5] 17 As per DMA0CurrWPtr.0x048 DMA1IntAdr[21:5] 17 As per DMA0IntAdr. 0x04C DMA1MaxAdr[21:5] 17As per DMA0MaxAdr. 0x050 DMAAccessEn 3 0x00000003 DMA access enable.0x054 DMAStatus 4 0x00000000 DMA status register. 0x058 DMAMask 40x00000000 DMA mask register. 0x05C-0x098 CPUISITxBuff[7:0] 32x8 n/a CPUISI transmit buffer. 32-byte packet buffer, containing the payload of aCPU sourced packet destined for transmission over the ISI. The CPU hasfull write access to the CPUISITxBuff. NOTE: The CPU does not have readaccess to CPUISITxBuff. This is because the CPU is the source of thedata and to avoid arbitrating read access between the CPU and the CTRLsub-block. Any CPU reads from this address space will return 0x00000000.0x09C CPUISITxBuffCtrl 9 0x00000000 CPU ISI transmit buffer controlregister. USBD 0x100 USBDIntStatus 19 0x00000000 USBD Interrupt eventstatus register. 0x104 USBDISIFIFOStatus 16 0x00000000 USBD ISI mappedOUT EP packet FIFO status register. 0x108 USBDDMA0FIFO 8 0x00000000 USBDDMAChannel0 mapped OUT EP Status packet FIFO status register. 0x10CUSBDDMA1FIFO 8 0x00000000 USBD DMAChannel1 mapped OUT EP Status packetFIFO status register. 0x110 USBDResume 1 0x00000000 USBD core resumeregister. 0x114 USBDSetup 4 0x00000000 USBD setup/configurationregister. 0x118-0x154 USBDEp0InBuff[15:0] 32x16 n/a USBD EP0-IN buffer.64-byte packet buffer in the, containing the payload of a USB packetdestined for EP0-IN. The CPU has full write access to the USBDEp0InBuff.NOTE: The CPU does not have read access to USBDEp0InBuff. This isbecause the CPU is the source of the data and to avoid arbitrating readaccess between the CPU and the USB device core. Any CPU reads from thisaddress space will return 0x00000000. 0x158 USBDEp0InBuffCtrl 10x00000000 USBD EP0-IN buffer control register. 0x15C-0x198USBDEp5InBuff[15:0] 32x16 n/a USBD EP5-IN buffer. As per USBDEp0InBuff.0x19C USBDEp5InBuffCtrl 1 0x00000000 USBD EP5-IN buffer controlregister. 0x1A0 USBDMask 19 0x00000000 USBD interrupt mask register.0x1A4 USBDDebug 30 0x00000000 USBD debug register. USBH 0x200 HcRevisionRefer to [19] for #Bits, Reset, Description. 0x204 HcControl Refer to[19] for #Bits, Reset, Description. 0x208 HcCommandStatus Refer to [19]for #Bits, Reset, Description. 0x20C HcInterruptStatus Refer to [19] for#Bits, Reset, Description. 0x210 HcInterruptEnable Refer to [19] for#Bits, Reset, Description. 0x214 HcInterruptDisable Refer to [19] for#Bits, Reset, Description. 0x218 HcHCCA Refer to [19] for #Bits, Reset,Description. 0x21C HcPeriodCurrentED Refer to [19] for #Bits, Reset,Description. 0x220 HcControlHeadED Refer to [19] for #Bits, Reset,Description. 0x224 HcControlCurrent Refer to [19] for #Bits, Reset, EDDescription. 0x228 HcBulkHeadED Refer to [19] for #Bits, Reset,Description. 0x22C HcBulkCurrentED Refer to [19] for #Bits, Reset,Description. 0x230 HcDoneHead Refer to [19] for #Bits, Reset,Description. 0x234 HcFmInterval Refer to [19] for #Bits, Reset,Description. 0x238 HcFmRemaining Refer to [19] for #Bits, Reset,Description. 0x23C HcFmNumber Refer to [19] for #Bits, Reset,Description. 0x240 HcPeriodicStart Refer to [19] for #Bits, Reset,Description. 0x244 HcLSTheshold Refer to [19] for #Bits, Reset,Description. 0x248 HcRhDescriptorA Refer to [19] for #Bits, Reset,Description. 0x24C HcRhDescriptorB Refer to [19] for #Bits, Reset,Description. 0x250 HcRhStatus Refer to [19] for #Bits, Reset,Description. 0x254 HcRhPortStatus[1] Refer to [19] for #Bits, Reset,Description. 0x258 USBHStatus 3 0x00000000 USBH status register. 0x25CUSBHMask 2 0x00000000 USBH interrupt mask register. 0x260 USBHDebug 20x00000000 USBH debug register. ISI 0x300 ISICntrl 4 0x0000000B ISIControl register 0x304 ISIId 4 0x00000000 ISIId for this SoPEC. 0x308ISINumRetries 4 0x00000002 Number of ISI retransmissions register. 0x30CISIPingSchedule0 15 0x00000000 ISI Ping schedule 0 register. 0x310ISIPingSchedule1 15 0x00000000 ISI Ping schedule 1 register. 0x314ISIPingSchedule2 15 0x00000000 ISI Ping schedule 2 register. 0x318ISITotalPeriod 4 0x0000000F Reload value of the ISITotalPeriod counter.0x31C ISILocalPeriod 4 0x0000000F Reload value of the ISILocalPeriodcounter. 0x320 ISIIntStatus 4 0x00000000 ISI interrupt status register.0x324 ISITxBuffStatus 27 0x00000000 ISI Tx buffer status register. 0x328ISIRxBuffStatus 27 0x00000000 ISI Rx buffer status register. 0x32CISIMask 4 0x00000000 ISI Interrupt mask register. 0x330-0x34CISITxBuffEntry0[7:0] 32x8 n/a ISI transmit Buff, packet entry #0.32-byte packet entry in the ISITxBuff, containing the payload of an ISITx packet. CPU read access to ISITxBuffEntry0 is provided forobservability only i.e. CPU reads of the ISITxBuffEntry0 do not alterthe state of the buffer. The CPU does not have write access to theISITxBuffEntry0. 0x350-0x36C ISITxBuffEntry1[7:0] 32x8 n/a ISI transmitBuff, packet entry #1. As per ISITxBuffEntry0. 0x370-0x38CISIRxBuffEntry0[7:0] 32x8 n/a ISI receive Buff, packet entry #0. 32-bytepacket entry in the ISIRxBuff, containing the payload of an ISI Rxpacket. Note that the only error-free long packets are placed in theISIRxBuffEntry0. Both ping and ACKs are consumed in the ISI. CPU accessto ISIRxBuffEntry0 is provided for observability only i.e. CPU reads ofthe ISIRxBuffEntry0 do not alter the state of the buffer. 0x390-0x3ACISIRxBuffEntry1[7:0] 32x8 n/a ISI receive Buff, packet entry #1. As perISIRxBuffEntry0. 0x3B0 ISISubId0Seq 1 0x00000000 ISI sub ID 0 sequencebit register. 0x3B4 ISISubId1Seq 1 0x00000000 ISI sub ID 1 sequence bitregister. 0x3B8 ISISubIdSeqMask 2 0x00000000 ISI sub ID sequence bitmask register. 0x3BC ISINumPins 1 0x00000000 ISI number of pinsregister. 0x3C0 ISITurnAround 4 0x0000000F ISI bus turn around register.0x3C4 ISITShortReplyWin 5 0x0000001F ISI short packet reply window.0x3C8 ISITLongReplyWin 9 0x000001FF ISI long packet reply window. 0x3CCISIDebug 4 0x00000000 ISI debug register.

A detailed description of each register format follows. The CPU has fullread access to all registers. Write access to the fields of eachregister is defined as:

-   -   Full: The CPU has full write access to the field, i.e. the CPU        can write a 1 or a 0 to each bit.    -   Clear: The CPU can clear the field by writing a 1 to each bit.        Writing a 0 to this type of field will have no effect.    -   None: The CPU has no write access to the field, i.e. a CPU write        will have no effect on the field.

12.5.5.2.1 SCBResetN TABLE 39 SCBResetN register format Field NameBit(s) write access Description CTRL 0 Full scb_ctrl sub-block reset.Setting this field will reset the SCB control sub-block logic, includingall configuration registers. 0 = reset 1 = default state ISI 1 Fullscb_isi sub-block reset. Setting this field will reset the ISI sub-blocklogic. 0 = reset 1 = default state USBH 2 Full scb_usbh sub-block reset.Setting this field will reset the USB host controller core andassociated logic. 0 = reset 1 = default state USBD 3 Full scb_usbdsub-block reset. Setting this field will reset the USB device controllercore and associated logic. 0 = reset 1 = default state

12.5.5.2.2 SCBGo TABLE 40 SCBGo register format Field Name Bit(s) writeaccess Description CTRL 0 Full scb_ctrl sub-block go. 0 = halted 1 =running ISI 1 Full scb_isi sub-block go. 0 = halted 1 = running12.5.5.2.3 SCBWakeUpEn

This register is used to gate the propagation of the USB and ISI resetsignals to the CPR block. TABLE 41 SCBWakeUpEn register format FieldName Bit(s) write access Description USBWakeUpEn 0 Full usb_cpr_reset_npropagation enable. 1 = enable 0 = disable ISIWakeUpEn 1 Fullisi_cpr_reset_n propagation enable. 1 = enable 0 = disable12.5.5.2.4 SCBISITxBufferArb

This register determines which source has priority at the ISITxBufferinterface on the ISI block. When a bit is set priority is given to therelevant source. When both bits have the same value, arbitration will beperformed in a round-robin manner. TABLE 42 SCBISITxBufferArb registerformat write Field Name Bit(s) access Description CPUPriority 0 Full CPUPriority 1 = high priority 0 = low priority USBPriority 1 Full USBPriority 1 = high priority 0 = low priority12.5.5.2.5 SCBDebugSel

Contains address of the register selected for debug observation as itwould appear on cpu_adr. The contents of the selected register areoutput in the scb_cpu_data bus while cpu_scb_sel is low andscb_cpu_debug_valid is asserted to indicate the debug data is valid. Itis expected that a number of pseudo-registers will be made available fordebug observation and these will be outlined with the implementationdetails. TABLE 43 SCBDebugSel register format write Field Name Bit(s)access Description CPUAdr 11:2 Full cpu_adr register address.12.5.5.2.6 USBEPnDest

This register description applies to USBEP0Dest, USBEP1Dest, USBEP2Dest,USBEP3Dest, USBEP4Dest. The SCB has two routing options for each packetreceived, based on the DestISIId associated with the packets source EP:

-   -   To the DMA Manager    -   To the ISI

The SCB map therefore does not need special fields to identify theDMAChannels on the ISIMaster SoPEC as this is taken care of by the SCBhardware. Thus the USBEP0Dest and USBEP1Dest registers should beprogrammed with 0x20 and 0x21 (for ISI0.0 and ISI0.1) respectively toensure data arriving on these endpoints is moved directly to DRAM. TABLE44 USBEPnDest register format Field Name Bit(s) Write access DescriptionSequenceBit 0 Full Sequence bit for packets going from USBEPn toDestISIId.DestISISubId. Every CPU write to this register initialises thevalue of the sequence bit and this is subsequently updated by the ISIafter every successful long packet transmission. DestISIId 4:1 FullDestination ISI ID. Denotes the ISIId of the target SoPEC as per TableDestISISubId 5 Full Destination ISI sub ID. Indicates which DMAChannelof the target SoPEC the endpoint is mapped onto: 0 = DMAChannel0 1 =DMAChannel1 ChannelEn 6 Full Communication channel enable bit for EPn.This enables/disables the communication channel for EPn. When disabled,the SCB will not accept USB packets addressed to EPn. 0 = Channeldisabled 1 = Channel enabled

If the local SoPEC is connected to an external USB host, it isrecommended that the EP0 communication channel should always remainenabled and mapped to DMAChannel0 on the local SoPEC, as this isintended as the primary control communication channel between theexternal USB host and the local SoPEC.

A SoPEC ISIMaster should map as many USB endpoints, under the control ofthe external host, as are required for the multi-SoPEC system it is partof. As already mentioned this mapping may be dynamically reconfigured.

12.5.5.2.7 DMAnBottomAdr

This register description applies to DMA0BottomAdr and DMA1BottomAdr.TABLE 45 DMAnBottomAdr register format Field Name Bit(s) Write accessDescription DMAnBottomAdr 21:5 Full The 256-bit aligned DRAM address ofthe bottom of the circular buffer (inclusive) serviced by DMAChanneln12.5.5.2.8 DMAnTopAdr

This register description applies to DMA0TopAdr and DMA 1 TopAdr. TABLE46 DMAnTopAdr register format Write Field Name Bit(s) access DescriptionDMAnTopAdr 21:5 Full The 256-bit aligned DRAM address of the top of thecircular buffer (inclusive) serviced by DMAChanneln12.5.5.2.9 DMAnCurrWPtr

This register description applies to DMA0CurrWPtr and DMA1CurrWPtr.TABLE 47 DMAnCurrWptr register format Write Field Name Bit(s) accessDescription DMAnCurrWPtr 21:5 Full The 256-bit aligned DRAM address ofthe next location DMAChannel0 will write to. This register is set by theCPU at the start of a DMA operation and dynamically updated managerduring the operation. by the DMA12.5.5.2.10 DMAIntAdr

This register description applies to DMA0IntAdr and DMA1IntAdr. TABLE 48DMAnIntAdr register format Write Bit(s) access Description DMAnIntAdr21:5 Full The 256-bit aligned DRAM address of the location that willtrigger an interrupt when reached by DMAChanneln buffer.12.5.5.2.11 DMAnMaxAdr

This register description applies to DMA0MaxAdr and DMA1MaxAdr. TABLE 49DMAnMaxAdr register format Write Field Name Bit(s) access DescriptionDMAnMaxAdr 21:5 Full The 256-bit aligned DRAM address of the last freelocation that in the DMAChanneln circular buffer. DMAChannel0 transferswill stop when it reaches this address.12.5.5.2.12 DMAAccessEn

This register enables DMA access for the various requesters, on a perchannel basis. TABLE 50 DMAAccessEn register format Write Field NameBit(s) access Description DMAChannel0En 0 Full DMA Channel #0 accessenable. This uni-directional write channel is used by the USBD and theISI. 1 = enable 0 = disable DMAChannel1En 1 Full As per USBDISI0En.DMAChannel2En 2 Full DMA Channel #2 access enable. This bi-directionalread/write channel is used by the USBH. 1 = enable 0 = disable12.5.5.2.13 DMAStatus

The status bits are not sticky bits i.e. they reflect the ‘live’ statusof the channel. DMAChannelNntAdrHit and DMAChannelNMaxAdrHit status bitsmay only be cleared by writing to the relevant DMAnintAdr or DMAnMaxAdrregister. TABLE 51 DMAStatus register format Write Field Name Bit(s)access Description DMAChannel0IntAdrHit 0 None DMA channel #0 interruptaddress hit. 1 = DMAChannel0 has reached the address contained in theDMA0IntAdr register. 0 = default state DMAChannel0MaxAdrHit 1 None DMAchannel #0 max address hit. 1 = DMAChannel0 has reached the addresscontained in the DMA0MaxAdr register. 0 = default stateDMAChannel1IntAdrHit 3 None As per DMAChannel0IntAdrHit.DMAChannel1MaxAdrHit 4 None As per DMAChannel0MaxAdrHit.12.5.5.2.14 DMAMask Register

All bits of the DMAMask are both readable and writable by the CPU. TheDMA manager cannot alter the value of this register. All interrupts aregenerated in an edge sensitive manner i.e. the DMA manager will generatea dma_icu_irq pulse each time a status bit goes high and itscorresponding mask bit is enabled. TABLE 52 DMAMask register formatWrite Field Name Bit(s) access Description DMAChannel0IntAdrHitIntEn 0Full DMAChannel0IntAdrHit status interrupt enable. 1 = enable 0 =disable DMAChannel0MaxAdrHitIntEn 1 Full DMAChannel0MaxAdrHit statusinterrupt enable. 1 = enable 0 = disable DMAChannel1IntAdrHitIntEn 2Full As per DMAChannel0IntAdrHitIntEn DMAChannel1MaxAdrHitIntEn 3 FullAs per DMAChannel0MaxAdrHitIntEn

12.5.5.2.15 CPUISITxBuffCtrl Register TABLE 53 CPUISITxBuffCtrl registerformat Write Field Name Bit(s) access Description PktValid 0 full Thisfield should be set by the CPU to indicate the validity of theCPUISITxBuff contents. This field will be cleared by the SCB once thecontents of the CPUISITxBuff has been copied to the ISITxBuff. NOTE: TheCPU should not clear this field under normal operation. If the CPUclears this field during a packet transfer to the ISITxBuff, thetransfer will be aborted - this is not recommended. 1 = valid packet. 0= default state. PktDesc 3:1 full PktDesc field, as per Table, of thepacket contained in the CPUISITxBuff. The CPU is responsible formaintaining the correct sequence bit value for each ISIId.ISISubIdchannel it communicates with. Only valid when CPU-ISITxBuffCtrl.PktValid = 1. DestISIId 7:4 full Denotes the ISIId of thetarget SoPEC as per Table DestISISubId 8 full Indicates which DMAChannelof the target SoPEC the packet in the CPUISITxBuff is destined for. 1 =DMAChannel1 0 = DMAChannel012.5.5.2.16 USBDIntStatus

The USBDIntStatus register contains status bits that are related toconditions that can cause an interrupt to the CPU, if the correspondinginterrupt enable bits are set in the USBDMask register. The field nameextension Sticky implies that the status condition will remainregistered until cleared by a CPU write of 1 to each bit of the field.

NOTE: There is no Ep0IrregPktSticky field because the default control EPwill frequently receive packets that are not multiples of 32 bytesduring normal operation. TABLE 54 USBDIntStatus register format WriteField Name Bit(s) access Description CoreSuspendSticky 0 Clear Devicecore USB suspend flag. Sticky. 1 = USB suspend state. Set when devicecore udcvci_suspend signal transitions from 1 -> 0. 0 = default value.CoreUSBResetSticky 1 Clear Device core USB reset flag. Sticky. 1 = USBreset. Set when device core udcvci_reset signal transitions from 1 -> 0.0 = default value. CoreUSBSOFSticky 2 Clear Device core USB Start OfFrame (SOF) flag. Sticky. 1 = USB SOF. Set when device core udcvci_sofsignal transitions from 1 -> 0 0 = default value.CPUISITxBuffEmptySticky 3 Clear CPU ISI transmit buffer empty flag.Sticky. 1 = empty. 0 = default value. CPUEp0InBuffEmptySticky 4 ClearCPU EP0 IN buffer empty flag. Sticky. 1 = empty. 0 = default value.CPUEp5InBuffEmptySticky 5 Clear CPU EP5 IN buffer empty flag. Sticky. 1= empty. 0 = default value. Ep0InNAKSticky 6 clear EP0-IN NAK flag.Sticky This flag is set if the USB device core issues a read request forEP0-IN and there is not a valid packet present in the EP0-IN buffer. Thecore will therefore send a NAK response to the IN token that wasreceived from external USB host. This is an indicator of any back-pressure on the USB caused by EP0-IN. 1 = NAK sent. 0 = default valueEp5InNAKSticky 7 Clear As per Ep0InNAK. Ep0OutNAKSticky 8 Clear EP0-OUTNAK flag. Sticky This flag is set if the USB device core issues a writerequest for EP0-OUT and there is no space in the OUT EP buffer for a thepacket. The core will therefore send a NAK response to the OUT tokenthat was received from external USB host. This is an indicator of anyback-pressure on the USB caused by EP0- OUT. 1 = NAK sent. 0 = defaultvalue Ep1OutNAKSticky 9 Clear As per Ep0OutNAK. Ep2OutNAKSticky 10 ClearAs per Ep0OutNAK. Ep3OutNAKSticky 11 Clear As per Ep0OutNAK.Ep4OutNAKSticky 12 Clear As per Ep0OutNAK. Ep1IrregPktSticky 13 ClearEP1-OUT irregular sized packet flag. Sticky. Indicates a packet that isnot a multiple of 32 bytes in size was received by EP1-OUT. 1 =irregular sized packet received. 0 = default value. Ep2IrregPktSticky 14Clear As per Ep1IrregPktSticky. Ep3IrregPktSticky 15 Clear As perEp1IrregPktSticky. Ep4IrregPktSticky 16 Clear As per Ep1IrregPktSticky.OutBuffOverFlowSticky 17 Clear OUT EP buffer overflow flag. Sticky. Thisflag is set if the USB device core attempted to write a packet of morethan 64 bytes to the OUT EP buffer. This is a fatal error, suggesting aproblem in the USB device IP core. The SCB will take no further action.1 = overflow condition detected. 0 = default value. InBuffUnderRunSticky18 clear IN EP buffer underrun flag. Sticky. This flag is set if the USBdevice core attempted to read more data than was present from the IN EPbuffer. This is a fatal error, suggesting a problem in the USB device IPcore. The SCB will take no further action. 1 = underrun conditiondetected. 0 = default value.12.5.5.2.17 USBDISIFIFOStatus

This register contains the status of the ISI mapped OUT EP packet FIFO.This is a secondary status register and will not cause any interrupts tothe CPU. TABLE 55 USBDISIFIFOStatus register format Write Field NameBit(s) access Description Entry0Valid 0 none FIFO entry #0 valid field.This flag will be set by the USBD when the USB device core indicates thevalidity of packet entry #0 in the FIFO. 1 = valid USB packet in ISI OUTEP buffer 0. 0 = default value. Entry0Source 3:1 none FIFO entry #0source field. Contains the EP associated with packet entry #0 in theFIFO. Binary Coded Decimal. Only valid when ISIBuff0PktValid = 1.Entry1Valid 4 none As per Entry0Valid. Entry1Source 7:5 none As perEntry0Source. Entry2Valid 8 none As per Entry0Valid. Entry2Source 11:9 none As per Entry0Source. Entry3Valid 12  none As per Entry0Valid.Entry3Source 15:13 none As per Entry0Source.12.5.5.2.18 USBDDMAOFIFOStatus

This register description applies to USBDDMAOFIFOStatus andUSBDDMA1FIFOStatus. This register contains the status of the DMAChannelNmapped OUT EP packet FIFO. This is a secondary status register and willnot cause any interrupts to the CPU. TABLE 56 USBDDMANFIFOStatusregister format Write Field Name Bit(s) access Description Entry0Valid 0none FIFO entry #0 valid field. This flag will be set by the USBD whenthe USB device core indicates the validity of packet entry #0 in theFIFO. 1 = valid USB packet in ISI OUT EP buffer 0. 0 = default value.Entry0Source 3:1 none FIFO entry #0 source field. Contains the EPassociated with packet entry #0 in the FIFO. Binary Coded Decimal. Onlyvalid when Entry0Valid = 1. Entry1Valid 4 none As per Entry0Valid.Entry1Source 7:5 none As per Entry0Source.12.5.5.2.19 USBDResume

This register causes the USB device core to initiate resume signallingto the external USB host. Only applicable when the device core is in thesuspend state. TABLE 57 USBDResume register format Field Name Bit(s)Write access Description USBDResume 0 full USBD core resume register.The USBD will clear this register upon resume notification from thedevice core. 1 = generate resume signalling. 0 = default value.12.5.5.2.20 USBDSetup

This register controls the general setup/configuration of the USBD.TABLE 58 USBDSetup register format write Field Name Bit(s) accessDescription Ep1IrregPktCntrl 0 full EP 1 OUT irregular sized packetcontrol. An irregular sized packet is defined as a packet that is not amultiple of 32 bytes. 1 = discard irregular sized packets. 0 = read 32bytes from buffer, regardless of packet size. Ep2IrregPktCntrl 1 full Asper Ep1IrregPktDiscard Ep3IrregPktCntrl 2 full As per Ep1IrregPktDiscardEp4IrregPktCntrl 3 full As per Ep1IrregPktDiscard12.5.5.2.21 USBDEpNInBuffCtrl Register

This register description applies to USBDEp0InBuffCtrl andUSBDEp5InBuffCtrl. TABLE 59 USBDEpNInBuffCtrl register format WriteField Name Bit(s) access Description PktValid 0 full Setting thisregister validates the contents of USBDEpNInBuff. This field will becleared by the SCB once the packet has been successfully transmitted tothe external USB host. NOTE: The CPU should not clear this field undernormal operation. If the CPU clears this field during a packet transferto the USB, the transfer will be aborted - this is not recommended. 1 =valid packet. 0 = default state.12.5.5.2.22 USBDMask

This register serves as an interrupt mask for all USBD status conditionsthat can cause a CPU interrupt. Setting a field enables interruptgeneration for the associated status event. Clearing a field disablesinterrupt generation for the associated status event. All interruptswill be generated in an edge sensitive manner, i.e. when the associatedstatus register transitions from 0->1. TABLE 60 USBDMask register formatWrite Field Name Bit(s) access Description CoreSuspendStickyEn 0 fullCoreSuspendSticky status interrupt enable. CoreUSBResetStickyEn 1 fullCoreUSBResetSticky status interrupt enable. CoreUSBSOFStickyEn 2 fullCoreUSBSOFSticky status interrupt enable. CPUISITxBuffEmptyStickyEn 3full CPUISITxBuffEmptySticky status interrupt enable.CPUEp0InBuffEmptyStickyEn 4 full CPUEp0InBuffEmptySticky statusinterrupt enable. CPUEp5InBuffEmptyStickyEn 5 fullCPUEp5InBuffEmptySticky status interrupt enable. Ep0InNAKStickyEn 6 fullEp0InNAKSticky status interrupt enable. Ep5InNAKStickyEn 7 fullEp5InNAKSticky status interrupt enable. Ep0OutNAKStickyEn 8 fullEp0OutNAKSticky status interrupt enable. Ep1OutNAKStickyEn 9 fullEp1OutNAKSticky status interrupt enable. Ep2OutNAKStickyEn 10 fullEp2OutNAkSticky status interrupt enable. Ep3OutNAKStickyEn 11 fullEp3OutNAKSticky status interrupt enable. Ep4OutNAKStickyEn 12 fullEp4OutNAKSticky status interrupt enable. Ep1IrregPktStickyEn 13 fullEp1IrregPktSticky status interrupt enable. Ep2IrregPktStickyEn 14 fullEp2IrregPktSticky status interrupt enable. Ep3IrregPktStickyEn 15 fullEp3IrregPktSticky status interrupt enable. Ep4IrregPktStickyEn 16 fullEp4IrregPktSticky status interrupt enable. OutBuffOverFlowStickyEn 17full OutBuffOverFlowSticky status interrupt enable.InBuffUnderRunStickyEn 18 full InBuffUnderRunSticky status interruptenable.12.5.5.2.23 USBDDebug

This register is intended for debug purposes only. Contains non-stickyversions of all interrupt capable status bits, which are referred to asdynamic in the table. TABLE 61 USBDDebug register format write FieldName Bit(s) access Description CoreTimeStamp 10:0 none USB device coreframe number. CoreSuspend 11 none Dynamic version of CoreSuspendSticky.CoreUSBRest 12 none Dynamic version of CoreUSBResetSticky. CoreUSBSOF 13none Dynamic version of CoreUSBSOFSticky. CPUISITxBuffEmpty 14 noneDynamic version of CPUISITxBuffEmptySticky. CPUEp0InBuffEmpty 15 noneDynamic version of CPUEp0InBuffEmptySticky. CPUEp5InBuffEmpty 16 noneDynamic version of CPUEp5InBuffEmptySticky. Ep0InNAK 17 none Dynamicversion of Ep0InNAKSticky. Ep5InNAK 18 none Dynamic version ofEp5InNAKSticky. Ep0OutNAK 19 none Dynamic version of Ep0OutNAKSticky.Ep1OutNAK 20 none Dynamic version of Ep1OutNAKSticky. Ep2OutNAK 21 noneDynamic version of Ep2OutNAKSticky. Ep3OutNAK 22 none Dynamic version ofEp3OutNAKSticky. Ep4OutNAK 23 none Dynamic version of Ep4OutNAKSticky.Ep1IrregPkt 24 none Dynamic version of Ep1IrregPktSticky. Ep2IrregPkt 25none Dynamic version of Ep2IrregPktSticky. Ep3IrregPkt 26 none Dynamicversion of Ep3IrregPktSticky. Ep4IrregPkt 27 none Dynamic version ofEp4IrregPktSticky. OutBuffOverFlow 28 none Dynamic version ofOutBuffOverFlowSticky. InBuffUnderRun 29 none Dynamic version ofInBuffUnderRunSticky.12.5.5.2.24 USBHStatus

This register contains all status bits associated with the USBH. Thefield name extension Sticky implies that the status condition willremain registered until cleared by a CPU write. TABLE 62 USBHStatusregister format Write Field Name Bit(s) access Description CoreIRQSticky0 clear HC core IRQ interrupt flag. Sticky Set when HC core UHOSTC_IrqNoutput signal transitions from 0 -> 1. Refer to OHCI spec for details onHC interrupt processing. 1 = IRQ interrupt from core. 0 = default value.CoreSMISticky 1 clear HC core SMI interrupt flag. Sticky Set when HCcore UHOSTC_SmiN output signal transitions from 0 -> 1. Refer to OHCIspec for details on HC interrupt processing. 1 = SMI interrupt from HC.0 = default value. CoreBuffAcc 2 none HC core buffer access flag. HCcore UHOSTC_BufAcc output signal. Indicates whether the HC is accessinga descriptor or a buffer in shared system memory. 1 = buffer access 0 =descriptor access.12.5.5.2.25 USBHMask

This register serves as an interrupt mask for all USBH status conditionsthat can cause a CPU interrupt. All interrupts will be generated in anedge sensitive manner, i.e. when the associated status registertransitions from 0->1. TABLE 63 USBHMask register format Write FieldName Bit(s) access Description CoreIRQIntEn 0 full CoreIRQSticky statusinterrupt enable 1 = enable. 0 = disable. CoreSMIIntEn 1 fullCoreSMISticky status interrupt enable. 1 = enable. 0 = disable.12.5.5.2.26 USBHDebug

This register is intended for debug purposes only. Contains non-stickyversions of all interrupt capable status bits, which are referred to asdynamic in the table. Field Name Bit(s) write access Description CoreIRQ0 none Dynamic version of CoreIRQSticky. CoreSMI 1 None Dynamic versionof CoreSMISticky.12.5.5.2.27 ISICntrl

This register controls the general setup/configuration of the ISI.

Note that the reset value of this register allows the SoPEC toautomatically become an ISIMaster (AutoMasterEnable=1) if any USBpackets are received on endpoints 24. On becoming an ISIMaster theISIMasterSel bit is set and any USB or CPU packets destined for otherISI devices are transmitted. The CPU can override this capability at anytime by clearing the AutoMasterEnable bit. TABLE 65 ISICntrl registerformat Write Field Name Bit(s) access Description TxEnable 0 Full ISItransmit enable. Enables ISI transmission of long or ping packets. ACKsmay still be transmitted when this bit is 0. This is cleared by transmiterrors and needs to be restarted by the CPU. 1 = Transmission enabled 0= Transmission disabled RxEnable 1 Full ISI receive enable. Enables ISIreception. This is can only be cleared by the CPU and it is onlyanticipated that reception will be disabled when the ISI in not in useand the ISI pins are being used by the GPIO for another purpose. 1 =Reception enabled 0 = Reception disabled ISIMasterSel 2 Full ISI masterselect. Determines whether the SoPEC is an ISIMaster or not 1 =ISIMaster 0 = ISISlave AutoMasterEnable 3 Full ISI auto master enable.Enables the device to automatically become the ISIMaster if activity isdetected on USB endpoints2-4. 1 = auto-master operation enabled 0 =auto-master operation disabled

12.5.5.2.28 ISIId TABLE 66 ISIId register format Write Field Name Bit(s)access Description ISIId 3:0 Full ISIId for this SoPEC. SoPEC resets tobeing an ISISlave with ISIId0. 0xF (the broadcast ISIId) is an illegalvalue and should not be written to this register.

12.5.5.2.29 ISINumRetries TABLE 67 ISINumRetries register format WriteField Name Bit(s) access Description ISINumRetries 3:0 Full Number ofISI retransmissions to attempt in response to an inferred NAK beforeaborting a long packet transmission12.5.5.2.30 ISIPingScheduleN

This register description applies to ISIPingSchedule0, ISIPingSchedule1and ISIPingSchedule2. TABLE 68 ISIPingScheduleN register format WriteField Name Bit(s) access Description ISIPingSchedule 14:0 Full Denoteswhich ISIIds will be receive ping packets. Note that bit0 refers toISIId0, bit1 to ISIId1 ...bit14 to ISIId14.

12.5.5.2.31 ISITotalPeriod TABLE 69 ISITotalPeriod register format FieldName Bit(s) Write access Description ISITotalPeriod 3:0 Full Reloadvalue of the ISITotalPeriod counter

12.5.5.2.32 ISILocalPeriod TABLE 70 ISILocalPeriod register format FieldName Bit(s) Write access Description ISILocalPeriod 3:0 Full Reloadvalue of the ISILocalPeriod counter12.5.5.2.33 ISIIntStatus

The ISIIntStatus register contains status bits that are related toconditions that can cause an interrupt to the CPU, if the correspondinginterrupt enable bits are set in the ISIMask register. TABLE 71ISIIntStatus register Write Field Name Bit(s) access DescriptionTxErrorSticky 0 None ISI transmit error flag. Sticky. Receiving ISIdevice would not accept the transmitted packet. Only set afterNumRetries unsuccessful retransmissions. (excluding ping packets). Thisbit is cleared by the ISI after transmission has been re-enabled by theCPU setting the TxEnable bit of the ISICntrl register. 1 = transmiterror. 0 = default state. RxFrameErrorSticky 1 Clear ISI receive framingerror flag. Sticky. This bit is set by the ISI when a framing errordetected in the received packet, which can be caused by an incorrectStart or Stop field or by bit stuffing errors. 1 = framing errordetected. 0 = default state. RxCRCErrorSticky 2 Clear ISI receive CRCerror flag. This bit is set by the ISI when a CRC error is detected inan incoming packet. Other than dropping the errored packet ISI receptionis unaffected by a CRC Error. 1 = CRC error 0 = default state.RxBuffOverFlowSticky 3 Clear ISI receive buffer over flow flag. Sticky.An overflow has occurred in the ISI receive buffer and a packet had tobe dropped. 1 = over flow condition detected. 0 = default state.12.5.5.2.34 ISITxBuffStatus

The ISITxBuffStatus register contains status bits that are related tothe ISI Tx buffer. This is a secondary status register and will notcause any interrupts to the CPU. TABLE 72 ISITxBuffStatus registerformat Write Field Name Bit(s) access Description Entry0PktValid 0 NoneISI Tx buffer entry #0 packet valid flag. This flag will be set by theISI when a valid ISI packet is written to entry #0 in the ISITxBuff fortransmission over the ISI bus. A Tx packet is considered valid when itis 32 bytes in size and the ISI has written the packet headerinformation to Entry0PktDesc, Entry0DestISIId and Entry0DestISISubId. 1= packet valid. 0 = default value. Entry0PktDesc 3:1 None ISI Tx bufferentry #0 packet descriptor. PktDesc field as per Table for the packetentry #0 in the ISITxBuff. Only valid when Entry0PktValid = 1.Entry0DestISIId 7:4 None ISI Tx buffer entry #0 destination ISI ID.Denotes the ISIId of the target SoPEC as per Table . Only valid whenEntry0PktValid = 1. Entry0DestISISubId 8 None ISI Tx buffer entry #0destination ISI sub ID. Indicates which DMAChannel on the target SoPECthat packet entry #0 in the ISITxBuff is destined for. Only valid whenEntry0PktValid = 1. 1 = DMAChannel1 0 = DMAChannel0 Entry1PktValid 9None As per Entry0PktValid. Entry1PktDesc 12:10 None As perEntry0PktDesc. Entry1DestISIId 16:13 None As per Entry0DestISIId.Entry1DestISISubId 17  None As per Entry0DestISISubId.12.5.5.2.35 ISIRxBuffStatus

The ISIRxBuffStatus register contains status bits that are related tothe ISI Rx buffer. This is a secondary status register and will notcause any interrupts to the CPU. TABLE 73 ISIRxBuffStatus registerformat Write Field Name Bit(s) access Description Entry0PktValid 0 NoneISI Rx buffer entry #0 packet valid flag. This flag will be set by theISI when a valid ISI packet is received and written to entry #0 of theISIRxBuff. A Rx packet is considered valid when it is 32 bytes in sizeand no framing or CRC errors were detected. 1 = valid packet 0 = defaultvalue Entry0PktDesc 3:1 None ISI Rx buffer entry #0 packet descriptor.PktDesc field as per Table for packet entry #0 of the ISIRxBuff. Onlyvalid when Entry0PktValid = 1. Entry0DestISIId 7:4 None ISI Rx buffer 0destination ISI ID. Denotes the ISIId of the target SoPEC as per Table .This should always correspond to the local SoPEC ISIId. Only valid whenEntry0PktValid = 1. Entry0DestISISubId 8 None ISI Rx buffer 0destination ISI sub ID. Indicates which DMAChannel on the target SoPECthat entry #0 of the ISIRxBuff is destined for. Only valid whenEntry0PktValid = 1. 1 = DMAChannel1 0 = DMAChannel0 Entry1PktValid 9None As per Entry0PktValid. Entry1PktDesc 12:10 None As perEntry0PktDesc. Entry1DestISIId 16:13 None As per Entry0DestISIId.Entry1DestISISubId 17  None As per Entry0DestISISubId.12.5.5.2.36 ISIMask Register

An interrupt will be generated in an edge sensitive manner i.e. the ISIwill generate an isi_icu_irq pulse each time a status bit goes high andthe corresponding bit of the ISIMask register is enabled. TABLE 74ISIMask register Write Field Name Bit(s) access Description TxErrorIntEn0 Full TxErrorSticky status interrupt enable. 1 = enable. 0 = disable.RxFrameErrorIntEn 1 Full RxFrameErrorSticky status interrupt enable. 1 =enable. 0 = disable. RxCRCErrorIntEn 2 Full RxCRCErrorSticky statusinterrupt enable. 1 = enable. 0 = disable. RxBuffOverFlowIntEn 3 FullRxBuffOverFlowSticky status interrupt enable. 1 = enable. 0 = disable.12.5.5.2.37 ISISubIdNSeq

This register description applies to ISISubId0Seq and ISISubId0Seq.TABLE 75 ISISubIdNSeq register format Write Field Name Bit(s) accessDescription ISISubIdNSeq 0 Full ISI sub ID channel N sequence bit. Thisbit may be initialised by the CPU but is updated by the ISI each time anerror-free long packet is received.

12.5.5.2.38 ISISubIdSeqMask TABLE 76 ISISubIdSeqMask register formatWrite Field Name Bit(s) access Description ISISubIdSeq0Mask 0 Full ISIsub ID channel 0 sequence bit mask. Setting this bit ensures that thesequence bit will be ignored for incoming packets for the ISISubId. 1 =ignore sequence bit. 0 = default state. ISISubIdSeq1Mask 1 Full As perISISubIdSeq0Mask.

12.5.5.2.39 ISINumPins TABLE 77 ISINumPins register format Field NameBit(s) Write access Description ISINumPins 0 Full Select number ofactive ISI pins. 1 = 4 pins 0 = 2 pins12.5.5.2.40 ISITurnAround

The ISI bus turnaround time will reset to its maximum value of 0xF toprovide a safer starting mode for the ISI bus. This value should be setto a value that is suitable for the physical implementation of the ISIbus, i.e. the lowest turn around time that the physical implementationwill allow without significant degradation of signal integrity. TABLE 78ISITurnAround register format Field Name Bit(s) Write access DescriptionISITurnAround 3:0 Full ISI bus turn around time in ISI clock cycles (32MHz).12.5.5.2.41 ISIShortReplyWin

The ISI short packet reply window time will reset to its maximum valueof 0x1F to provide a safer starting mode for the ISI bus. This valueshould be set to a value that will allow for expected frequency of bitstuffing and receiver response timing. TABLE 79 ISIShortReplyWinregister format Field Name Bit(s) Write access DescriptionISIShortReplyWin 4:0 Full ISI long packet reply window in ISI clockcycles (32 MHz).12.5.5.2.42 ISILongReplyWin

The ISI long packet reply window time will reset to its maximum value of0x1FF to provide a safer starting mode for the ISI bus. This valueshould be set to a value that will allow for expected frequency of bitstuffing and receiver response timing. TABLE 80 ISILongReplyWin registerformat Write Field Name Bit(s) access Description ISILongReplyWin 8:0Full ISI long packet reply window in ISI clock cycles (32 MHz).12.5.5.2.43 ISIDebug

This register is intended for debug purposes only. Contains non-stickyversions of all interrupt capable status bits, which are referred to asdynamic in the table. TABLE 81 ISIDebug register format Field NameBit(s) Write access Description TxError 0 None Dynamic version ofTxErrorSticky. RxFrameError 1 None Dynamic version ofRxFrameErrorSticky. RxCRCError 2 None Dynamic version ofRxCRCErrorSticky. RxBuffOverFlow 3 None Dynamic version ofRxBuffOverFlowSticky.12.5.5.3 CPU Bus Interface12.5.5.4 Control Core Logic12.5.5.5 DIU Bus Interface12.6 DMA Regs

All of the circular buffer registers are 256-bit word aligned asrequired by the DIU. The DMAnBottomAdr and DMAnTopAdr registers areinclusive i.e. the addresses contained in those registers form part ofthe circular buffer. The DMAnCurrWPtr always points to the next locationthe DMA manager will write to so interrupts are generated whenever theDMA manager reaches the address in either the DMAnIntAdr or DMAnMaxAdrregisters rather than when it actually writes to these locations. Ittherefore can not write to the location in the DMAnMaxAdr register.

SCB Map Regs

The SCB map is configured by mapping a USB endpoint on to a data sink.This is performed on a endpoint basis i.e. each endpoint has aconfiguration register to allow its data sink be selected. Mapping anendpoint on to a data sink does not initiate any data flow—eachendpoint/data sink needs to be enabled by writing to the appropriateconfiguration registers for the USBD, ISI and DMA manager.

13. General Purpose IO (GPIO)

13.1 Overview

The General Purpose IO block (GPIO) is responsible for control andinterfacing of GPIO pins to the rest of the SoPEC system. It provideseasily programmable control logic to simplify control of GPIO functions.In all there are 32 GPIO pins of which any pin can assume any output orinput function. Possible output functions are

-   -   4 Stepper Motor control Outputs    -   12 Brushless DC Motor Control Output (total of 2 different        controllers each with 6 outputs)    -   4 General purpose high drive pulsed outputs capable of driving        LEDs.    -   4 Open drain IOs used for LSS interfaces    -   4 Normal drive low impedance IOs used for the ISI interface in        Multi-SoPEC mode

Each of the pins can be configured in either input or output mode, eachpin is independently controlled. A programmable de-glitching circuitexists for a fixed number of input pins. Each input is a schmidt triggerto increase noise immunity should the input be used without thede-glitch circuit. The mapping of the above functions and theiralternate use in a slave SoPEC to GPIO pins is shown in Table 82 below.TABLE 82 GPIO pin type GPIO pin(s) Pin IO Type Default Functiongpio[3:0] Normal drive, low impedance IO Pins 1 and 0 in ISI (35 Ohm),Integrated pull-up Mode, pins 2 and 3 in resistor input mode gpio[7:4]High drive, normal impedance IO Input Mode (65 Ohm), intended for LEDdrivers gpio[31:8] Normal drive, normal impedance Input Mode IO (65Ohm), no pull-up13.2 Stepper Motor Control

The motor control pins can be directly controlled by the CPU or themotor control logic can be used to generate the phase pulses for thestepper motors. The controller consists of two central counters fromwhich the control pins are derived. The central counters have severalregisters (see Table) used to configure the cycle period, the phase, theduty cycle, and counter granularity.

There are two motor master counters (0 and 1) with identical features.The period of the master counters are defined by theMotorMasterClkPeriod[1:0] and MotorMasterClkSrc registers i.e. bothmaster counters are derived from the same MotorMasterClkSrc. TheMotorMasterClkSrc defines the timing pulses used by the master countersto determine the timing period. The MotorMasterClkSrc can select clocksources of 1 μs, 100 μs, 10 ms and pclk timing pulses.

The MotorMasterClkPeriod[1:0] registers are set to the number of timingpulses required before the timing period re-starts. Each master counteris set to the relevant MotorMasterClkPeriod value and counts down a uniteach time a timing pulse is received.

The master counters reset to MotorMasterClkPeriod value and count down.Once the value hits zero a new value is reloaded from theMotorMasterClkPeriod[1:0] registers. This ensures that no master clockglitch is generated when changing the clock period.

Each of the IO pins for the motor controller are derived from the mastercounters. Each pin has independent configuration registers. TheMotorMasterClkSelect[3:0] registers define which of the two mastercounters to use as the source for each motor control pin. The mastercounter value is compared with the configured MotorCtrlLow andMotorCtrlHigh registers (bit fields of the MotorCtrlConfig register). Ifthe count is equal to MotorCtrlHigh value the motor control is set to 1,if the count is equal to MotorCtrlLow value the motor control pin is setto 0.

This allows the phase and duty cycle of the motor control pins to bevaried at pclk granularity. The motor control generators keep a workingcopy of the MotorCtrlLow, MotorCtrlHigh values and update the configuredvalue to the working copy when it is safe to do so. This allows thephase or duty cycle of a motor control pin to be safely adjusted by theCPU without causing a glitch on the output pin.

Note that when reprogramming the MotorCtrlLow, MotorCtrlHigh registersto reorder the sequence of the transition points (e.g changing from lowpoint less than high point to low point greater than high point and viceversa) care must still taken to avoid introducing glitching on theoutput pin.

13.3 LED Control

LED lifetime and brightness can be improved and power consumptionreduced by driving the LEDs with a pulsed rather than a DC signal. Thesource clock for each of the LED pins is a 7.8 kHz (128 μs period) clockgenerated from the 1 μs clock pulse from the Timers block. TheLEDDutySelect registers are used to create a signal with the desiredwaveform. Unpulsed operation of the LED pins can be achieved by usingCPU IO direct control, or setting LEDDutySelect to 0. By default the LEDpins are controlled by the LED control logic.

13.4 LSS Interface via GPIO

In some SoPEC system configurations one or more of the LSS interfacesmay not be used. Unused LSS interface pins can be reused as general IOpins by configuring the IOModeSelect registers. When a mode selectregister for a particular GPIO pin is set to 23,22,21,20 the GPIO pin isconnected to LSS control IOs 3 to 0 respectively.

13.5 ISI Interface via GPIO

In Multi-SoPEC mode the SCB block (in particular the ISI sub-block)requires direct access to and from the GPIO pins. Control of the ISIinterface pins is determined by the IOModeSelect registers. When a modeselect register for a particular GPIO pin is set to 27,26,25,24 the GPIOpin connected to the ISI control bits 3 to 0 respectively. By defaultthe GPIO pins 1 to 0 are directly controlled by the ISI block.

In single SoPEC systems the pins can be re-used by the GPIO.

13.6 CPU GPIO Control

The CPU can assume direct control of any (or all) of the IO pinsindividually. On a per pin basis the CPU can turn on direct access tothe pin by configuring the IOModeSelect register to CPU direct mode.Once set the IO pin assumes the direction specified by theCpuIODirection register. When in output mode the value in registerCpuIOOut will be directly reflected to the output driver. When in inputmode the status of the input pin can be read by reading CpuIOInregister. When writing to the CpuIOOut register the value being writtenis XORed with the current value in CpuIOOut. The CPU can also read thestatus of the 10 selected de-glitched inputs by reading theCpuIOInDeGlitch register.

13.7 Programmable De-Glitching Logic

Each IO pin can be filtered through a de-glitching logic circuit, thepin that the de-glitching logic is connected to is configured by theInputPinSelect registers. There are IO de-glitching circuits, so amaximum of IO input pin can be de-glitched at anytime.

The de-glitch circuit can be configured to sample the IO pin for apredetermined time before concluding that a pin is in a particularstate. The exact sampling length is configurable, but each de-glitchcircuit must use one of two possible configured values (selected byDeGlitchSelect). The sampling length is the same for both high and lowstates. The DeGlitchCount is programmed to the number of system timeunits that a state must be valid for before the state is passed on. Thetime units are selected by DeGlitchClkSel and can be one of 1 μs, 100μs, 10 ms and pclk pulses.

For example if DeGlitchCount is set to 10 and DeGlitchClkSel set to 3,then the selected input pin must consistently retain its value for 10system clock cycles (pclk) before the input state will be propagatedfrom CpuIOIn to CpuIOInDeglitch.

13.8 Interrupt Generation

Any of the selected input pins (selected by InputPinSelect) can generatean interrupt from the raw or deglitched version of the input pin. Thereare IO possible interrupt sources from the GPIO to the interruptcontroller, one interrupt per input pin. The InterruptSrcSelect registerdetermines whether the raw input or the deglitched version is used asthe interrupt source.

The interrupt type, masking and priority can be programmed in theinterrupt controller.

13.9 Frequency Analyser

The frequency analyser measures the duration between successive positiveedges on a selected input pin (selected by InputPinSelect) and reportsthe last period measured (FreqAnaLastPeriod) and a running averageperiod (FreqAnaAverage).

The running average is updated each time a new positive edge is detectedand is calculated byFreqAnaAverage=(FreqAnaAverage/8)*7+FreqAnaLastPeriod/8.

The analyser can be used with any selected input pin (or its deglitchedform), but only one input at a time can be selected. The input isselected by the FreqAnaPinSelect (range of 0 to 9) and its deglitchedform can be selected by FreqAnaPinFormSelect.

13.10 Brushless DC (BLDC) Motor Controllers

The GPIO contains 2 brushless DC (BLDC) motor controllers. Eachcontroller consists of 3 hall inputs, a direction input, and sixpossible outputs. The outputs are derived from the input state and apulse width modulated (PWM) input from the Stepper Motor controller, andis given by the truth table in Table 83. TABLE 83 Truth Table for BLDCMotor Controllers direction hc hb ha q6 q5 q4 q3 q2 q1 0 0 0 1 0 0 0 1PWM 0 0 0 1 1 PWM 0 0 1 0 0 0 0 1 0 PWM 0 0 0 0 1 0 1 1 0 0 0 PWM 0 0 10 1 0 0 0 1 PWM 0 0 0 0 1 0 1 0 1 0 0 PWM 0 0 0 0 0 0 0 0 0 0 0 0 1 1 10 0 0 0 0 0 1 0 0 1 0 0 PWM 0 0 1 1 0 1 1 PWM 0 0 0 0 1 1 0 1 0 PWM 0 01 0 0 1 1 1 0 0 0 0 1 PWM 0 1 1 0 0 0 1 0 0 PWM 0 1 1 0 1 0 1 PWM 0 0 01 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0

All inputs to a BLDC controller must be de-glitched. Each controller hasits inputs hardwired to de-glitch circuits. Controller 1 hall inputs arede-glitched by circuits 2 to 0, and its direction input is de-glitchedby circuit 3. Controller 2 inputs are de-glitched by circuits 6 to 4 forhall inputs and 7 for direction input.

Each controller also requires a PWM input. The stepper motor controlleroutputs are reused, output 0 is connected to BLDC controller 1, andoutput 1 to BLDC controller 2.

The controllers have two modes of operation, internal and externaldirection control (configured by BLDCMode). If a controller is inexternal direction mode the direction input is taken from a de-glitchedcircuit, if it is in internal direction mode the direction input isconfigured by the BLDCDirection register.

The BLDC controller outputs are connected to the GPIO output pins byconfiguring the IOModeSelect register for each pin. e.g Setting the moderegister to 8 will connect q1 Controller 1 to drive the pin.

13.11 Implementation

13.11.1 Definitions of I/O TABLE 84 I/O definition Port name Pins I/ODescription Clocks and Resets Pclk 1 In System Clock prst_n 1 In Systemreset, synchronous active low tim_pulse[2:0] 3 In Timers block generatedtiming pulses. 0 - 1 μs pulse 1 - 100 μs pulse 2 - 10 ms pulse CPUInterface cpu_adr[8:2] 8 In CPU address bus. Only 7 bits are required todecode the address space for this block cpu_dataout[31:0] 32 In Sharedwrite data bus from the CPU gpio_cpu_data[31:0] 32 Out Read data bus tothe CPU cpu_rwn 1 In Common read/not-write signal from the CPUcpu_gpio_sel 1 In Block select from the CPU. When cpu_gpio_sel is highboth cpu_adr and cpu_dataout are valid gpio_cpu_rdy 1 Out Ready signalto the CPU. When gpio_cpu_rdy is high it indicates the last cycle of theaccess. For a write cycle this means cpu_dataout has been registered bythe GPIO block and for a read cycle this means the data on gpio_cpu_datais valid. gpio_cpu_berr 1 Out Bus error signal to the CPU indicating aninvalid access. gpio_cpu_debug_valid 1 Out Debug Data valid ongpio_cpu_data bus. Active high cpu_acode[1:0] 2 In CPU Access Codesignals. These decode as follows: 00 - User program access 01 - Userdata access 10 - Supervisor program access 11 - Supervisor data accessIO Pins gpio_o[31:0] 32 Out General purpose IO output to IO drivergpio_i[31:0] 32 In General purpose IO input from IO receivergpio_e[31:0] 32 Out General purpose IO output control. Active highdriving GPIO to LSS lss_gpio_dout[1:0] 2 In LSS bus data output Bit 0 -LSS bus 0 Bit 1 - LSS bus 1 gpio_lss_din[1:0] 2 Out LSS bus data inputBit 0 - LSS bus 0 Bit 1 - LSS bus 1 lss_gpio_e[1:0] 2 In LSS bus dataoutput enable, active high Bit 0 - LSS bus 0 Bit 1 - LSS bus 1lss_gpio_clk[1:0] 2 In LSS bus clock output Bit 0 - LSS bus 0 Bit 1 -LSS bus 1 GPIO to ISI gpio_isi_din[1:0] 2 Out Input data from IOreceivers to ISI. isi_gpio_dout[1:0] 2 In Data output from ISI to IOdrivers isi_gpio_e[1:0] 2 In GPIO ISI pins output enable (active high)from ISI interface usbh_gpio_power_en 1 In Port Power enable from theUSB host core, active high gpio_usbh_over_current 1 Out Over currentdetect to the USB host core, active high Miscellaneous gpio_icu_irq[9:0]10 Out GPIO pin interrupts gpio_cpr_wakeup 1 Out SoPEC wakeup to the CPRblock active high. Debug debug_data_out[31:0] 32 In Output debug data tobe muxed on to the GPIO pins debug_cntrl[31:0] 32 In Control signal foreach GPIO bound debug data line indicating whether or not the debug datashould be selected by the pin mux13.11.2 Configuration Registers

The configuration registers in the GPIO are programmed via the CPUinterface. Refer to section 11.4.3 on page 69 for a description of theprotocol and timing diagrams for reading and writing registers in theGPIO. Note that since addresses in SoPEC are byte aligned and the CPUonly supports 32-bit register reads and writes, the lower 2 bits of theCPU address bus are not required to decode the address space for theGPIO. When reading a register that is less than 32 bits wide zerosshould be returned on the upper unused bit(s) of gpio_cpu_data. Table 85lists the configuration registers in the GPIO block TABLE 85 GPIORegister Definition Address GPIO_base+ Register #bits Reset Description0x000-0x07C IOModeSelect[31:0] 32x5 See Specifies the mode of operationfor each Table for GPIO pin. One 5 bit bus per pin. default valuesPossible assignment values and correspond controller outputs are asfollows Value - Controlled by 3 to 0 - Output, LED controller 4 to 1 7to 4 - Output Stepper Motor control 4-1 13 to 8 - Output BLDC 1 Motorcontrol 6-1 19 to 14 - Output BLDC 2 Motor control 6-1 23 to 20 - LSScontrol 4-1 27 to 24 - ISI control 4-1 28 - CPU Direct Control 29 - USBpower enable output 30 - Input Mode 0x080-0xA4 InputPinSelect[9:0] 10x50x00 Specifies which pins should be selected as inputs. Used to selectthe pin source to the DeGlitch Circuits. CPU IO Control 0x0B0CpuIOUserModeMask 32 0x0000_0000 User Mode Access Mask to CPU GPIOcontrol register. When 1 user access is enabled. One bit per gpio pin.Enables access to CpuIODirection, CpuIOOut and CpuIOIn in user mode.0x0B4 CpuIOSuperModeMask 32 0xFFFF_FFFF Supervisor Mode Access Mask toCPU GPIO control register. When 1 supervisor access is enabled. One bitper gpio pin. Enables access to CpuIODirection, CpuIOOut and CpuIOIn insupervisor mode. 0x0B8 CpuIODirection 32 0x0000_0000 Indicates thedirection of each IO pin, when controlled by the CPU 0 - Indicates InputMode 1 - Indicates Output Mode 0x0BC CpuIOOut 32 0x0000_0000 Value usedto drive output pin in CPU direct mode. bits31:0 - Value to drive onoutput GPIO pins When written to the register assumes the new valueXORed with the current value. 0x0C0 CpuIOIn 32 External pin Valuereceived on each input pin regardless value of mode. Read Only register.0x0C4 CpuDeGlitchUserModeMask 10 0x000 User Mode Access Mask toCpuIOInDeglitch control register. When 1 user access is enabled,otherwise bit reads as zero. 0x0C8 CpuIOInDeglitch 10 0x000 Deglitchedversion of selected input pins. The input pins are selected by theInputPinSelect register. Note that after reset this register willreflect the external pin values 256 pclk cycles after they havestabilized. Read Only register. Deglitch control 0x0D0-0x0D4DeGlitchCount[1:0] 2x8 0xFF Deglitch circuit sample count inDeGlitchClkSrc selected units. 0x0D8-0x0DC DeGlitchClkSrc 2x2 0x3Specifies the unit use of the GPIO deglitch [1:0] circuits: 0 - 1 μspulse 1 - 100 μs pulse 2 - 10 ms pulse 3 - pclk 0x0E0 DeGlitchSelect 100x000 Specifies which deglitch count (DeGlitchCount) and unit select(DeGlitchClkSrc) should be used with each de-glitch circuit 0 -Specifies DeGlitchCount[0] and DeGlitchClkSrc[0] 1 - SpecifiesDeGlitchCount[1] and DeGlitchClkSrc[1] Motor Control 0x0E4 MotorCtrlUser1 0x0 User Mode Access enable to Motor control ModeEnable configurationregisters. When 1 user access is enabled. Enables user access toMotorMasterClkPeriod, MotorMasterClkSrc, MotorDutySelect,MotorPhaseSelect, MotorMasterClockEnable, Motor- MasterClkSelect,BLDCMode and BLDCDirection registers 0x0E8-0x0ECMotorMasterClkPeriod[1:0] 2x16 0x0000 Specifies the motor controllermaster clock periods in MotorMasterClkSrc selected units 0x0F0MotorMasterClkSrc 2 0x0 Specifies the unit use by the motor controllermaster clock generator: 0 - 1 μs pulse 1 - 100 μs pulse 2 - 10 ms pulse3 - pclk 0x0F4-0x100 MotorCtrlConfig 4x32 0x0000_0000 Specifies thetransition points in the clock [3:0] period for each motor control pin.One register per pin bits 15:0 - MotorCtrlLow, high to low transitionpoint bits 31:16 - MotorCtrlHigh, low to high transition point 0x104MotorMasterClkSelect 4 0x0 Specifies which motor master clock should beused as a pin generator source 0 - Clock derived fromMotorMasterClockPeriod [0] 1 - Clock derived from MotorMasterClockPeriod[1] 0x108 MotorMasterClockEnable 2 0x0 Enable the motor master clockcounter. When 1 count is enabled Bit 0 - Enable motor master clock 0 Bit1 - Enable motor master clock 1 BLDC Motor Controllers 0x10C BLDCMode 20x0 Specifies the Mode of operation of the BLDC Controller. One bit perController. 0- External direction control 1- Internal direction control0x110 BLDCDirection 2 0x0 Specifies the direction input of the BLDCcontroller. Only used when BLDC controller is an internal directioncontrol mode. One bit per controller. LED control 0x114LEDCtrlUserModeEnable 4 0x0 User Mode Access enable to LED controlconfiguration registers. When 1 user access is enabled. One bit perLEDDutySelect select register. 0x118-0x124 LEDDutySelect 4x3 0x0Specifies the duty cycle for each LED [3:0] control output. See FIG. 54for encoding details. The LEDDutySelect[3:0] registers determine theduty cycle of the LED controller outputs Frequency Analyser 0x130FreqAnaUserModeEnable 1 0x0 User Mode Access enable to Frequencyanalyser configuration registers. When 1 user access is enabled.Controls access to FreqAnaPinFormSelect, FreqAnaLastPeriod,FreqAnaAverage and FreqAnaCountInc. 0x134 FreqAnaPinSelect 4 0x00Selects which selected input should be used for the frequency analyses.0x138 FreqAnaPinFormSelect 1 0x0 Selects if the frequency analysershould use the raw input or the deglitched form. 0 - Deglitched form ofinput pin 1 - Raw form of input pin 0x13C FreqAnaLastPeriod 16 0x0000Frequency Analyser last period of selected input pin. 0x140FreqAnaAverage 16 0x0000 Frequency Analyser average period of selectedinput pin. 0x144 FreqAnaCountInc 20 0x0000 0 Frequency Analyser counterincrement amount. For each clock cycle no edge is detected on theselected input pin the accumulator is incremented by this amount. 0x148FreqAnaCount 32 0x0000_0000 Frequency Analyser running counter (Workingregister) Miscellaneous 0x150 InterruptSrcSelect 10 0x3FF Interruptsource select.1 bit per selected input. Determines whether the interruptsource is direct form the selected input pin or the deglitched version.Input pins are selected by the DeGlitchPinSelect register. 0 - Selectedinput direct 1 - Deglitched selected input 0x154 DebugSelect[8:2] 7 0x00Debug address select. Indicates the address of the register to report onthe gpio_cpu_data bus when it is not otherwise being used. 0x158-0x15CMotorMasterCount[1:0] 2x16 0x0000 Motor master clock counter values. Bus0 - Master clock count 0 Bus 1 - Master clock count 1 Read Onlyregisters 0x160 WakeUpInputMask 10 0x000 Indicates which deglitchedinputs should be considered to generate the CPR wakeup. Active high0x164 WakeUpLevel 1 0 Defines the level to detect on the masked GPIOinputs to generate a wakeup to the CPR 0 - Level 0 1 - Level 1 0x168USBOverCurrentPinSelect 4 0x00 Selects which deglitched input should beused for the USB over current detect.13.11.2.1 Supervisor and User Mode Access

The configuration registers block examines the CPU access type(cpu_acode signal) and determines if the access is allowed to thatparticular register, based on configured user access registers. If anaccess is not allowed the GPIO will issue a bus error by asserting thegpio_cpu_berr signal.

All supervisor and user program mode accesses will result in a buserror.

Access to the CpuIODirection, CpuIOOut and CpuIOIn is filtered by theCpuIOUserModeMask and CpuIOSuperModeMask registers. Each bit masksaccess to the corresponding bits in the CpuIO* registers for each mode,with CpuIOUserModeMask filtering user data mode access andCpuIOSuperModeMask filtering supervisor data mode access.

The addition of the CpuIOSuperModeMask register helps prevent potentialconflicts between user and supervisor code read modify write operations.For example a conflict could exist if the user code is interruptedduring a read modify write operation by a supervisor ISR which alsomodifies the CpuIO* registers.

An attempt to write to a disabled bit in user or supervisor mode will beignored, and an attempt to read a disabled bit returns zero. If thereare no user mode enabled bits then access is not allowed in user modeand a bus error will result. Similarly for supervisor mode.

When writing to the CpuIOOut register, the value being written is XORedwith the current value in the CpuIOOut register, and the result isreflected on the GPIO pins.

The pseudocode for determining access to the CpuIOOut register is shownbelow. Similar code could be shown for the CpuIODirection and CpuIOInregisters. Note that when writing to CpuIODirection data is depositeddirectly and not XORed with the existing data (as in the CpuIOOut case).if (cpu_acode == SUPERVISOR_DATA_MODE) then  // supervisor mode  if(CpuIOSuperModeMask[31:0] == 0 ) then   // access is denied, and buserror   gpio_cpu_berr = 1  elsif (cpu_rwn == 1) then   // read mode (nofiltering needed)   gpio_cpu_data[31:0] = CpuIOOut[31:0]  else   //write mode,filtered by mask   mask[31:0]      =  (cpu_dataout[31:0]  &CpuIOSuperModeMask[31:0])   CpuIOOut[31:0] = (cpu_dataout[31:0] {circumflex over ( )}  mask[31:0] ) //bitwise XOR operator elsif(cpu_acode == USER_DATA_MODE) then  // user datamode  if(CpuIOUserModeMask[31:0] == 0 ) then   // access is denied, and buserror   gpio_cpu_berr = 1  elsif (cpu_rwn == 1) then   // read mode,filtered by mask   gpio_cpu_data      =  ( CpuIOOut[31:0]  &CpuIOUserModeMask[31:0])  else   // write mode,filtered by mask  mask[31:0]      =  (cpu_dataout[31:0]  & CpuIOUserModeMask[31:0])  CpuIOOut[31:0] = (cpu_dataout[31:0]  {circumflex over ( )}  mask[31:0]) //bitwise XOR operator else  // access is denied, bus error gpio_cpu_berr = 1

Table 86 details the access modes allowed for registers in the GPIOblock. In supervisor mode all registers are accessible. In user modeforbidden accesses will result in a bus error (gpio_cpu_berr asserted).TABLE 86 GPIO supervisor and user access modes Register AddressRegisters Access Permitted 0x000-0x07C IOModeSelect[31:0] Supervisordata mode only 0x080-0x94 InputPinSelect[9:0] Supervisor data mode onlyCPU IO Control 0x0B0 CpuIOUserModeMask Supervisor data mode only 0x0B4CpuIOSuperModeMask Supervisor data mode only 0x0B8 CpuIODirectionCpuIOUserModeMask and CpuIOSuperModeMask filtered 0x0BC CpuIOOutCpuIOUserModeMask and CpuIOSuperModeMask filtered 0x0C0 CpuIOInCpuIOUserModeMask and CpuIOSuperModeMask filtered 0x0C4CpuDeGlitchUserModeMask Supervisor data mode only 0x0C8 CpuIOInDeglitchCpuDeGlitchUserModeMask filtered. Unrestricted Supervisor data modeaccess Deglitch control 0x0D0-0x0D4 DeGlitchCount[1:0] Supervisor datamode only 0x0D8-0x0DC DeGlitchClkSrc[1:0] Supervisor data mode only0x0E0 DeGlitchSelect Supervisor data mode only Motor Control 0x0E4MotorCtrlUserModeEnable Supervisor data mode only 0x0E8-0x0ECMotorMasterClkPeriod[1:0] MotorCtrlUserModeEnable enabled. 0x0F0MotorMasterClkSrc MotorCtrlUserModeEnable enabled. 0x0F4-0x100MotorCtrlConfig[3:0] MotorCtrlUserModeEnable enabled 0x104MotorMasterClkSelect MotorCtrlUserModeEnable enabled 0x108MotorMasterClockEnable MotorCtrlUserModeEnable enabled BLDC MotorControllers 0x10C BLDCMode MotorCtrlUserModeEnable Enabled 0x110BLDCDirection MotorCtrlUserModeEnable Enabled LED control 0x114LEDCtrlUserModeEnable Supervisor data mode only 0x118-0x124LEDDutySelect[3:0] LEDCtrlUserModeEnable[3:0] enabled Frequency Analyser0x130 FreqAnaUserModeEnable Supervisor data mode only 0x134FreqAnaPinSelect FreqAnaUserModeEnable enabled 0x138FreqAnaPinFormSelect FreqAnaUserModeEnable enabled 0x13CFreqAnaLastPeriod FreqAnaUserModeEnable enabled 0x140 FreqAnaAverageFreqAnaUserModeEnable enabled 0x144 FreqAnaCountIncFreqAnaUserModeEnable enabled 0x148 FreqAnaCount FreqAnaUserModeEnableenabled Miscellaneous 0x150 InterruptSrcSelect Supervisor data mode only0x154 DebugSelect[8:2] Supervisor data mode only 0x158-0x15CMotorMasterCount[1:0] Supervisor data mode only 0x160 WakeUpInputMaskSupervisor data mode only 0x164 WakeUpLevel Supervisor data mode only0x168 USBOverCurrentPinSelect Supervisor data mode only13.11.3 GPIO Partition13.11.4 IO Control

The IO control block connects the IO pin drivers to internal signallingbased on configured setup registers and debug control signals. // OutputControl for (i=0; i<32 ; i++) { if (debug_cntrl[i] == 1) then  // debugmode  gpio_e[i] = 1;gpio_o[i] =debug_data_out[i] else // normal mode case io_mode_select[i] is   0 : gpio_e[i] =1 ;gpio_o[i] =led_ctrl[0]   // LED output 1   1 : gpio_e[i] =1 ;gpio_o[i] =led_ctrl[1]    // LEDoutput 2   2 : gpio_e[i] =1 ;gpio_o[i] =led_ctrl[2]    // LED output 3  3 : gpio_e[i] =1 ;gpio_o[i] =led_ctrl[3]    // LED output 4   4 :gpio_e[i] =1 ;gpio_o[i] =motor_ctrl[0]   // Stepper Motor Control 1   5: gpio_e[i] =1 ;gpio_o[i] =motor_ctrl[1]   // Stepper Motor Control 2  6 : gpio_e[i] =1 ;gpio_o[i] =motor_ctrl[2]   // Stepper Motor Control3   7 : gpio_e[i] =1 ;gpio_o[i] =motor_ctrl[3]   // Stepper MotorControl 4   8 : gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][0]   // BLDC MotorControl 1,output 1   9 : gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][1]   //BLDC Motor Control 1,output 2   10: gpio_e[i] =1 ;gpio_o[i]=bldc_ctrl[0][2]   // BLDC Motor Control 1,output 3   11: gpio_e[i] =1;gpio_o[i] =bldc_ctrl[0][3]   // BLDC Motor Control 1,output 4   12:gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][4]   // BLDC Motor Control1,output 5   13: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[0][5]   // BLDCMotor Control 1,output 6   14: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][0]  // BLDC Motor Control 2,output 1   15: gpio_e[i] =1 ;gpio_o[i]=bldc_ctrl[1][1]   // BLDC Motor Control 2,output 2   16: gpio_e[i] =1;gpio_o[i] =bldc_ctrl[1][2]   // BLDC Motor Control 2,output 3   17:gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][3]   // BLDC Motor Control2,output 4   18: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][4]   // BLDCMotor Control 2,output 5   19: gpio_e[i] =1 ;gpio_o[i] =bldc_ctrl[1][5]  // BLDC Motor Control 2,output 6   20: gpio_e[i] =1 ;gpio_o[i]=lss_gpio_clk[0]  // LSS Clk 0   21: gpio_e[i] =1 ;gpio_o[i]=lss_gpio_clk[1]  // LSS Clk 1   22:   gpio_e[i]   =lss_gpio_e[0]  ;gpio_o[i] =lss_gpio_dout[0]; // LSS Data 0    gpio_lss_din[0] =gpio_i[i]   23:   gpio_e[i]   =lss_gpio_e[1]   ;gpio_o[i]=lss_gpio_dout[1]; // LSS Data 1    gpio_lss_din[1] = gpio_i[i]   24:  gpio_e[i]   =isi_gpio_e[0]   ;gpio_o[i] =isi_gpio_dout[0]; // ISIControl 1    gpio_isi_din[0] = gpio_i[i]   25:   gpio_e[i]  =isi_gpio_e[1]   ;gpio_o[i] =isi_gpio_dout[1]; // ISI Control 2   gpio_isi_din[1] = gpio_i[i]   26:   gpio_e[i]   =isi_gpio_e[2]  ;gpio_o[i] =isi_gpio_dout[2]; // ISI Control 3    gpio_isi_din[2] =gpio_i[i]   27:   gpio_e[i]   =isi_gpio_e[3]   ;gpio_o[i]=isi_gpio_dout[3]; // ISI Control 4    gpio_isi_din[3] = gpio_i[i]   28:gpio_e[i] =cpu_io_dir[i]   ;gpio_o[i] =cpu_io_out[i]; // CPU Direct  29:  gpio e[i]  =1  ;gpio o[i]  =usbh gpio power en // USB host powerenable   30:   gpio e[i]   =0   ;gpio o[i]   =0 // Input only mode  endcase  // all gpio are always readable by the CPU  cpu_io_in[i] =gpio_i[i];  }

The input selection pseudocode, for determining which pin connects towhich de-glitch circuit. for( i=0 ;i < 10 ; i++) {  pin_num =input_pin_select[i]  deglitch_input[i] = gpio_i[pin_num]  }

The gpio_usbh_over_current output to the USB core is driven by aselected deglitched input (configured by the USBOverCurrentPinSelectregister).

-   -   index=USBOverCurrentPinSelect    -   gpio_usbh_over_current=cpu_io_in_deglitch[index]        13.11.5 Wakeup Generator

The wakeup generator compares the deglitched inputs with the configuredmask (WakeUpInputMask) and level (WakeUpLevel), and determines whetherto generate a wakeup to the CPR block. for (i =0;i<10; i++) {  if(wakeup_level = 0) then // level 0 active   wakeup  =  wakeup  OR wakeup_input_mask[i]  AND NOT cpu_io_in_deglitch[i]  else // level 1active   wakeup  =  wakeup  OR  wakeup_input_mask[i] ANDcpu_io_in_deglitch[i]  } // assign the output gpio_cpr_wakeup = wakeup13.11.6 LED Pulse Generator

The pulse generator logic consists of a 7-bit counter that isincremented on a 1 μs pulse from the timers block (tim_pulse[0]). TheLED control signal is generated by comparing the count value with theconfigured duty cycle for the LED (led_duty_sel).

The logic is given by: for (i=0 i<4 ;i++) { // for each LED pin  //period divided into 8 segments  period_div8 = cnt[6:4];  if (period_div8< led_duty_sel[i]) then   led_ctrl[i] = 1  else   led_ctrl[i] = 0  } //update the counter every 1us pulse if (tim_pulse[0] == 1) then  cnt ++13.11.7 Stepper Motor Control

The motor controller consists of 2 counters, and 4 phase generator logicblocks, one per motor control pin. The counters decrement each time atiming pulse (cnt_en) is received. The counters start at the configuredclock period value (motor_mas_clk_period) and decrement to zero. If thecounters are enabled (via motor_mas_clk_enable), the counters willautomatically restart at the configured clock period value, otherwisethey will wait until the counters are re-enabled.

The timing pulse period is one of pclk, 1 μs, 100 μs, 1 ms depending onthe motor_mas_clk_sel signal. The counters are used to derive the phaseand duty cycle of each motor control pin. // decrement logic if (cnt_en== 1) then  if ((mas_cnt == 0) AND (motor_mas_clk_enable == 1)) then  mas_cnt = motor_mas_clk_period[15:0]  elsif ((mas_cnt == 0) AND(motor_mas_clk_enable == 0)) then   mas_cnt = 0  else   mas_cnt −− else // hold the value  mas_cnt = mas_cnt

The phase generator block generates the motor control logic based on theselected clock generator (motor_mas_clk_sel) the motor control hightransition point (curr_motor_ctrl_high) and the motor control lowtransition point (curr_motor_ctrl_low).

The phase generator maintains current copies of the motor_ctrl_configconfiguration value (motor_ctrl_config[31:16] becomescurr_motor_ctrl_high and motor_ctrl_config[15:0] becomescurr_motor_ctrl_low). It updates these values to the current registervalues when it is safe to do so without causing a glitch on the outputmotor pin.

Note that when reprogramming the motor_ctrl_config register to reorderthe sequence of the transition points (e.g changing from low point lessthan high point to low point greater than high point and vice versa)care must taken to avoid introducing glitching on the output pin.

There are 4 instances one per motor control pin.

The logic is given by: // select the input counter to use if(motor_mas_clk_sel == 1) then  count = mas_cnt[1] else  count =mas_cnt[0] // Generate the phase and duty cycle if (count ==curr_motor_ctrl_low) then  motor_ctrl = 0 elsif (count ==curr_motor_ctrl_high) then  motor_ctrl = 1 else  motor_ctrl = motor_ctrl// remain the same // update the current registers at period boundary if(count == 0) then  curr_motor_ctrl_high = motor_ctrl_config[31:16] //update to new high value  curr_motor_ctrl_low = motor_ctrl_config[15:0]// update to new high value13.11.8 Input Deglitch

The input deglitch logic rejects input states of duration less than theconfigured number of time units (deglitch_cnt), input states of greaterduration are reflected on the output cpu_io_in_deglitch. The time unitsused (either pclk, 1 μs, 100 μs, 1 ms) by the deglitch circuit isselected by the deglitch_clk_src bus.

There are 2 possible sets of deglitch_cnt and deglitch_clk_src that canbe used to deglitch the input pins. The values used are selected by thedeglitch_sel signal.

There are 10 deglitch circuits in the GPIO. Any GPIO pin can beconnected to a deglitch circuit. Pins are selected for deglitching bythe InputPinSelect registers.

Each selected input can be used to generate an interrupt. The interruptcan be generated from the raw input signal (deglitch_input) or adeglitched version of the input (cpu_io_in_deglitch). The interruptsource is selected by the interrupt_src_select signal.

The counter logic is given by if (deglitch_input !=deglitch_input_delay) then  cnt    = deglitch_cnt  output_en = 0 elsif(cnt == 0 ) then  cnt    = cnt  output_en = 1 elsif (cnt_en == 1) then cnt −−  output_en = 013.11.9 Frequency Analyser

The frequency analyser block monitors a selected deglitched input(cpu_io_in_deglitch) or a direct selected input (deglitch_input) anddetects positive edges. The selected input is configured byFreqAnaPinSelect and FreqAnaPinFormSel registers. Between successivepositive edges detected on the input it increments a counter(FreqAnaCount) by a programmed amount (FreqAnaCountInc) on each clockcycle. When a positive edge is detected the FreqAnaLastPeriod registeris updated with the top 16 bits of the counter and the counter is reset.The frequency analyser also maintains a running average of theFreqAnaLastPeriod register. Each time a positive edge is detected on theinput the FreqAnaAverage register is updated with the new calculatedFreqAnaLastPeriod. The average is calculated as ⅞ the current value plus⅛ of the new value. The FreqAnaLastPeriod, FreqAnaCount andFreqAnaAverage registers can be written to by the CPU.

The pseudocode is given by if ((pin == 1) AND pin_delay ==0 ))then  //positive edge detected  freq_ana_lastperiod[15:0] =freq_ana_count[31:16]  freq_ana_average[15:0]    =freq_ana_average[15:0]  − freq_ana_average[15:3]               +freq_ana_lastperiod[15:3]  freq_ana_count[15:0]   = 0 else freq_ana_count[31:0]    =  freq_ana_count[31:0]  +freq_ana_count_inc[19:0] // implement the configuration register writeif (wr_last_en == 1) then  freq_ana_lastperiod = wr_data elsif(wr_average_en == 1 ) then  freq_ana_average = wr_data elsif(wr_freq_count_en == 1) then  freq_ana_count = wr_data13.11.10 BLDC Motor Controller

The BLDC controller logic is identical for both instances, only theinput connections are different. The logic implements the truth tableshown in Table. The six q outputs are combinationally based on thedirection, ha, hb, hc and pwm inputs. The direction input has 2 possiblesources selected by the mode, the pseudocode is as follows // determineif in internal or external direction mode if (mode == 1) then //internal mode  direction = int_direction else // external mode direction = ext_direction14 Interrupt Controller Unit (ICU)

The interrupt controller accepts up to N input interrupt sources,determines their priority, arbitrates based on the highest priority andgenerates an interrupt request to the CPU. The ICU complies with theinterrupt acknowledge protocol of the CPU. Once the CPU accepts aninterrupt (i.e. processing of its service routine begins) the interruptcontroller will assert the next arbitrated interrupt if one is pending.

Each interrupt source has a fixed vector number N, and an associatedconfiguration register, IntReg[N]. The format of the IntReg[N] registeris shown in Table 87 below. TABLE 87 IntReg[N] register format Fieldbit(s) Description Priority 3:0 Interrupt priority Type 5:4 Determinesthe triggering conditions for the interrupt 00 - Positive edge 10 -Negative edge 01 - Positive level 11 - Negative level Mask 6 Mask bit.1 - Interrupts from this source are enabled, 0 - Interrupts from thissource are disabled. Note that there may be additional masks inoperation at the source of the interrupt. Reserved 31:7  Reserved. Writeas 0.

Once an interrupt is received the interrupt controller determines thepriority and maps the programmed priority to the appropriate CPUpriority levels, and then issues an interrupt to the CPU. The programmedinterrupt priority maps directly to the LEON CPU interrupt levels. Level0 is no interrupt. Level 15 is the highest interrupt level.

14.1 Interrupt Preemption

With standard LEON pre-emption an interrupt can only be pre-empted by aninterrupt with a higher priority level. If an interrupt with the samepriority level (1 to 14) as the interrupt being serviced becomes pendingthen it is not acknowledged until the current service routine hascompleted. Note that the level 15 interrupt is a special case, in thatthe LEON processor will continue to take level 15 interrupts (i.ere-enter the ISR) as long as level 15 is asserted on the icu_cpu_ilevel.Level 0 is also a special case, in that LEON consider level 0 interruptsas no interrupt, and will not issue an acknowledge when level 0 ispresented on the icu_cpu_ilevel bus.

Thus when pre-emption is required, interrupts should be programmed todifferent levels as interrupt priorities of the same level have noguaranteed servicing order. Should several interrupt sources beprogrammed with the same priority level, the lowest value interruptsource will be serviced first and so on in increasing order.

The interrupt is directly acknowledged by the CPU and the ICUautomatically clears the pending bit of the lowest value pendinginterrupt source mapped to the acknowledged interrupt level.

All interrupt controller registers are only accessible in supervisordata mode. If the user code wishes to mask an interrupt it must requestthis from the supervisor and the supervisor software will resolve useraccess levels.

14.2 Interrupt Sources

The mapping of interrupt sources to interrupt vectors (and thereforeIntReg[N] registers) is shown in Table 88 below. Please refer to theappropriate section of this specification for more details of theinterrupt sources. TABLE 88 Interrupt sources vector table Vector SourceDescription  0 Timers WatchDog Timer Update request  1 Timers GenericTimer 1 interrupt  2 Timers Generic Timer 2 interrupt  3 PCU PEPSub-system Interrupt- TE finished band  4 PCU PEP Sub-system Interrupt-LBD finished band  5 PCU PEP Sub-system Interrupt- CDU finished band  6PCU PEP Sub-system Interrupt- CDU error  7 PCU PEP Sub-system Interrupt-PCU finished band  8 PCU PEP Sub-system Interrupt- PCU Invalid addressinterrupt  9 PHI PEP Sub-system Interrupt- PHI Line Sync Interrupt 10PHI PEP Sub-system Interrupt- PHI Buffer underrun 11 PHI PEP Sub-systemInterrupt- PHI Page finished 12 PHI PEP Sub-system Interrupt- PHI Printready 13 SCB USB Host interrupt 14 SCB USB Device interrupt 15 SCB ISIinterrupt 16 SCB DMA interrupt 17 LSS LSS interrupt, LSS interface 0interrupt request 18 LSS LSS interrupt, LSS interface 1 interruptrequest 19-28 GPIO GPIO general purpose interrupts 29 Timers GenericTimer 3 interrupt14.3 Implentation

14.3.1 Definitions of I/O TABLE 89 Interrupt Controller Unit I/Odefinition Port name Pins I/O Description Clocks and Resets Pclk 1 InSystem Clock prst_n 1 In System reset, synchronous active low CPUinterface cpu_adr[7:2] 6 In CPU address bus. Only 6 bits are required todecode the address space for the ICU block cpu_dataout[31:0] 32 InShared write data bus from the CPU icu_cpu_data[31:0] 32 Out Read databus to the CPU cpu_rwn 1 In Common read/not-write signal from the CPUcpu_icu_sel 1 In Block select from the CPU. When cpu_icu_sel is highboth cpu_adr and cpu_dataout are valid icu_cpu_rdy 1 Out Ready signal tothe CPU. When icu_cpu_rdy is high it indicates the last cycle of theaccess. For a write cycle this means cpu_dataout has been registered bythe ICU block and for a read cycle this means the data on icu_cpu_datais valid. icu_cpu_ilevel[3:0] 4 Out Indicates the priority level of thecurrent active interrupt. cpu_iack 1 In Interrupt request acknowledgefrom the LEON core. cpu_icu_ilevel[3:0] 4 In Interrupt acknowledgedlevel from the LEON core icu_cpu_berr 1 Out Bus error signal to the CPUindicating an invalid access. cpu_acode[1:0] 2 In CPU Access Codesignals. These decode as follows: 00 - User program access 01 - Userdata access 10 - Supervisor program access 11 - Supervisor data accessicu_cpu_debug_valid 1 Out Debug Data valid on icu_cpu_data bus. Activehigh Interrupts tim_icu_wd_irq 1 In Watchdog timer interrupt signal fromthe Timers block tim_icu_irq[2:0] 3 In Generic timer interrupt signalsfrom the Timers block gpio_icu_irq[9:0] 10 In GPIO pin interruptsusb_icu_irq[1:0] 2 In USB host and device interrupts from the SCB Bit0 - USB Host interrupt Bit 1 - USB Device interrupt isi_icu_irq 1 In ISIinterrupt from the SCB dma_icu_irq 1 In DMA interrupt from the SCBlss_icu_irq[1:0] 2 In LSS interface interrupt request cdu_finishedband 1In Finished band interrupt request from the CDU cdu_icu_jpegerror 1 InJPEG error interrupt from the CDU lbd_finishedband 1 In Finished bandinterrupt request from the LBD te_finishedband 1 In Finished bandinterrupt request from the TE pcu_finishedband 1 In Finished bandinterrupt request from the PCU pcu_icu_address_invalid 1 In Invalidaddress interrupt request from the PCU phi_icu_underrun 1 In Bufferunderrun interrupt request from the PHI phi_icu_page_finish 1 In Pagefinished interrupt request from the PHI phi_icu_print_rdy 1 In Printready interrupt request from the PHI phi_icu_linesync_int 1 In Line syncinterrupt request from the PHI14.3.2 Configuration Registers

The configuration registers in the ICU are programmed via the CPUinterface. Refer to section 11.4 on page 69 for a description of theprotocol and timing diagrams for reading and writing registers in theICU. Note that since addresses in SoPEC are byte aligned and the CPUonly supports 32-bit register reads and writes, the lower 2 bits of theCPU address bus are not required to decode the address space for theICU. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of icu_pcu_data. Table 90 liststhe configuration registers in the ICU block.

The ICU block will only allow supervisor data mode accesses (i.e.cpu_acode[1:0]=SUPERVISOR_DATA). All other accesses will result inicu_cpu_berr being asserted. TABLE 90 ICU Register Map Address ICU_base+Register #bits Reset Description 0x00-0x74 IntReg[29:0] 30x7 0x00Interrupt vector configuration register 0x88 IntClear 30 0x0000_0000Interrupt pending clear register. If written with a one it clearscorresponding interrupt Bits[30:0] - Interrupts sources 30 to 0 (Readsas zero) 0x90 IntPending 30 0x0000_0000 Interrupt pending register.(Read Only) Bits[30:0]- Interrupts sources 30 to 0 0xA0 IntSource  50x1F Indicates the interrupt source of the last acknowledged interrupt.The NoInterrupt value is defined as all bits set to one. (Read Only)0xC0 DebugSelect[7:2]  6 0x00 Debug address select. Indicates theaddress of the register to report on the icu_cpu_data bus when it is nototherwise being used.14.3.3 ICU Partition114.3.4 Interrupt Detect

The ICU contains multiple instances of the interrupt detect block, oneper interrupt source. The interrupt detect block examines the interruptsource signal, and determines whether it should generate request pending(int_pend) based on the configured interrupt type and the interruptsource conditions. If the interrupt is not masked the interrupt will bereflected to the interrupt arbiter via the int_active signal. Once aninterrupt is pending it remains pending until the interrupt is acceptedby the CPU or it is level sensitive and gets removed. Masking a pendinginterrupt has the effect of removing the interrupt from arbitration butthe interrupt will still remain pending.

When the CPU accepts the interrupt (using the normal ISR mechanism), theinterrupt controller automatically generates an interrupt clear for thatinterrupt source (cpu_int_clear). Alternatively if the interrupt ismasked, the CPU can determine pending interrupts by polling theIntPending registers. Any active pending interrupts can be cleared bythe CPU without using an ISR via the IntClear registers.

Should an interrupt clear signal (either from the interrupt clear unitor the CPU) and a new interrupt condition happen at the same time, theinterrupt will remain pending. In the particular case of a levelsensitive interrupt, if the level remains the interrupt will stay activeregardless of the clear signal.

The logic is shown below: mask    = int_config[6] type    =int_config[5:4] int_pend   = last_int_pend     // the last pendinginterrupt // update the pending FF // test for interrupt condition if(type == NEG_LEVEL) then  int_pend = NOT(int_src) elsif (type ==POS_LEVEL)  int_pend = int_srcelsif ((type == POS_EDGE ) AND (int_src == 1) AND (last_int_src == 0)) int_pend = 1 elsif ((type == NEG_EDGE ) AND (int_src == 0) AND(last_int_src == 1))  int_pend = 1 elsif ((int_clear == 1 )OR(cpu_int_clear==1)) then  int_pend = 0 else  int_pend = last_int_pend //stay the same as before // mask the pending bit if (mask == 1) then int_active = int_pend else  int_active = 0 // assign the registerslast_int_src = int_src last_int_pend = int_pend14.3.5 Interrupt Arbiter

The interrupt arbiter logic arbitrates a winning interrupt request frommultiple pending requests based on configured priority. It generates theinterrupt to the CPU by setting icu_cpu_ilevel to a non-zero value. Thepriority of the interrupt is reflected in the value assigned toicu_cpu_ilevel, the higher the value the higher the priority, 15 beingthe highest, and 0 considered no interrupt. // arbitrate with thecurrent winner int_ilevel   = 0 for (i=0;i<30;i++) {  if ( int_active[i]== 1) then {   if (int_config[i][3:0] > win_int_ilevel[3:0] ) then   win_int_ilevel[3:0] = int_config[i][3:0]    }   }  } // assign theCPU interrupt level int_ilevel = win_int_ilevel[3:0]14.3.6 Interrupt Clear Unit

The interrupt clear unit is responsible for accepting an interruptacknowledge from the CPU, determining which interrupt source generatedthe interrupt, clearing the pending bit for that source and updating theIntSource register.

When an interrupt acknowledge is received from the CPU, the interruptclear unit searches through each interrupt source looking for interruptsources that match the acknowledged interrupt level (cpu_icu_ilevel) anddetermines the winning interrupt (lower interrupt source numbers havehigher priority). When found the interrupt source pending bit is clearedand the IntSource register is updated with the interrupt source number.

The LEON interrupt acknowledge mechanism automatically disables allother interrupts temporarily until it has correctly saved state andjumped to the ISR routine. It is the responsibility of the ISR tore-enable the interrupts. To prevent the IntSource register indicatingthe incorrect source for an interrupt level, the ISR must read and storethe IntSource value before re-enabling the interrupts via the EnableTraps (ET) field in the Processor State Register (PSR) of the LEON.

See section 11.9 on page 104 for a complete description of the interrupthandling procedure. After reset the state machine remains in Idle stateuntil an interrupt acknowledge is received from the CPU (indicated bycpu_iack). When the acknowledge is received the state machinetransitions to the Compare state, resetting the source counter (cnt) tothe number of interrupt sources.

While in the Compare state the state machine cycles through eachpossible interrupt source in decrementing order. For each activeinterrupt source the programmed priority (int_priority[cnt][3:0]) iscompared with the acknowledged interrupt level from the CPU(cpu_icu_ilevel), if they match then the interrupt is considered the newwinner. This implies the last interrupt source checked has the highestpriority, e.g interrupt source zero has the highest priority and thefirst source checked has the lowest priority. After all interruptsources are checked the state machine transitions to the IntClear state,and updates the int_source register on the transition.

Should there be no active interrupts for the acknowledged level (e.g. alevel sensitive interrupt was removed), the IntSource register will beset to NoInterrupt. NoInterrupt is defined as the highest possible valuethat IntSource can be set to (in this case 0x1F), and the state machinewill return to Idle.

The exact number of compares performed per clock cycle is dependent thenumber of interrupts, and logic area to logic speed trade-off, and isleft to the implementer to determine. A comparison of all interruptsources must complete within 8 clock cycles (determined by the CPUacknowledge hardware).

When in the IntClear state the state machine has determined theinterrupt source to clear (indicated by the int_source register). Itresets the pending bit for that interrupt source, transitions back tothe Idle state and waits for the next acknowledge from the CPU.

The minimum time between successive interrupt acknowledges from the CPUis 8 cycles.

15 Timers Block (TIM)

The Timers block contains general purpose timers, a watchdog timer andtiming pulse generator for use in other sections of SoPEC.

15.1 Watchdog Timer

The watchdog timer is a 32 bit counter value which counts down each timea timing pulse is received. The period of the timing pulse is selectedby the WatchDogUnitSel register. The value at any time can be read fromthe WatchDogTimer register and the counter can be reset by writing anon-zero value to the register. When the counter transitions from 1 to0, a system wide reset will be triggered as if the reset came from ahardware pin.

The watchdog timer can be polled by the CPU and reset each time it getsclose to 1, or alternatively a threshold (WatchDogIntThres) can be setto trigger an interrupt for the watchdog timer to be serviced by theCPU. If the WatchDogIntThres is set to N, then the interrupt will betriggered on the N to N−1 transition of the WatchDogTimer. Thisinterrupt can be effectively masked by setting the threshold to zero.The watchdog timer can be disabled, without causing a reset, by writingzero to the WatchDogTimer register.

15.2 Timing Pulse Generator

The timing block contains a timing pulse generator clocked by the systemclock, used to generate timing pulses of programmable periods. Theperiod is programmed by accessing the TimerStartValue registers. Eachpulse is of one system clock duration and is active high, with the pulseperiod accurate to the system clock frequency. The periods after resetare set to 1 us, 100 us and 100 ms.

The timing pulse generator also contains a 64-bit free running counterthat can be read or reset by accessing the FreeRunCount registers. Thefree running counter can be used to determine elapsed time betweenevents at system clock accuracy or could be used as an input source inlow-security random number generator.

15.3 Generic Timers

SoPEC contains 3 programmable generic timing counters, for use by theCPU to time the system. The timers are programmed to a particular valueand count down each time a timing pulse is received. When a particulartimer decrements from 1 to 0, an interrupt is generated. The counter canbe programmed to automatically restart the count, or wait untilre-programmed by the CPU. At any time the status of the counter can beread from GenCntValue, or can be reset by writing to GenCntValueregister. The auto-restart is activated by setting the GenCntAutoregister, when activated the counter restarts at GenCntStartValue. Acounter can be stopped or started at any time, without affecting thecontents of the GenCntValue register, by writing a 1 or 0 to therelevent GenCntEnable register.

15.4 Implementation

15.4.1 Definitions of I/O TABLE 91 Timers block I/O definition Port namePins I/O Description Clocks and Resets Pclk 1 In System Clock prst_n 1In System reset, synchronous active low tim_pulse[2:0] 3 Out Timersblock generated timing pulses, each one pclk wide 0 - Nominal 1 μs pulse1 - Nominal 100 μs pulse 2 - Nominal 10 ms pulse CPU interfacecpu_adr[6:2] 5 In CPU address bus. Only 5 bits are required to decodethe address space for the ICU block cpu_dataout[31:0] 32 In Shared writedata bus from the CPU tim_cpu_data[31:0] 32 Out Read data bus to the CPUcpu_rwn 1 In Common read/not-write signal from the CPU cpu_tim_sel 1 InBlock select from the CPU. When cpu_tim_sel is high both cpu_adr andcpu_dataout are valid tim_cpu_rdy 1 Out Ready signal to the CPU. Whentim_cpu_rdy is high it indicates the last cycle of the access. For awrite cycle this means cpu_dataout has been registered by the TIM blockand for a read cycle this means the data on tim_cpu_data is valid.tim_cpu_berr 1 Out Bus error signal to the CPU indicating an invalidaccess. cpu_acode[1:0] 2 In CPU Access Code signals. These decode asfollows: 00 - User program access 01 - User data access 10 - Supervisorprogram access 11 - Supervisor data access tim_cpu_debug_valid 1 OutDebug Data valid on tim_cpu_data bus. Active high Miscellaneoustim_icu_wd_irq 1 Out Watchdog timer interrupt signal to the ICU blocktim_icu_irq[2:0] 3 Out Generic timer interrupt signals to the ICU blocktim_cpr_reset_n 1 Out Watch dog timer system reset.15.4.2 Timers Sub-Block Partition15.4.3 Watchdog Timer

The watchdog timer counts down from pre-programmed value, and generatesa system wide reset when equal to one. When the counter passes apre-programmed threshold (wdog_tim_thres) value an interrupt isgenerated (tim_icu_wd_irq) requesting the CPU to update the counter.Setting the counter to zero disables the watchdog reset. In supervisormode the watchdog counter can be written to or read from at any time, inuser mode access is denied. Any accesses in user mode will generate abus error.

The counter logic is given by if (wdog_wen == 1) then  wdog_tim_cnt =write_data // load new data elsif ( wdog_tim_cnt == 0) then wdog_tim_cnt = wdog_tim_cnt // count disabled elsif( cnt_en == 1 ) then  wdog_tim_cnt−− else  wdog_tim_cnt = wdog_tim_cnt

if (( wdog_tim_cnt == wdog_tim_thres) AND (wdog_tim_cnt != 0 )AND(cnt_en == 1)) then  tim_icu_wd_irq = 1 else  tim_icu_wd_irq = 0 //reset generator logic if (wdog_tim_cnt == 1) AND (cnt_en == 1) then tim_cpr_reset_n = 0 else  tim_cpr_reset_n = 115.4.4 Generic Timers

The generic timers block consists of 3 identical counters. A timer isset to a pre-configured value (GenCntStartValue) and counts down onceper selected timing pulse (gen_unit_sel). The timer can be enabled ordisabled at any time (gen_tim_en), when disabled the counter is stoppedbut not cleared. The timer can be set to automatically restart(gen_tim_auto) after it generates an interrupt. In supervisor mode atimer can be written to or read from at any time, in user mode access isdetermined by the GenCntUserModeEnable register settings.

The counter logic is given by if (gen_wen == 1) then  gen_tim_cnt =write_data elsif (( cnt_en == 1 )AND (gen_tim_en == 1 )) then if ( gen_tim_cnt == 1) OR  ( gen_tim_cnt == 0)  then  // counter mayneed re-starting   if (gen_tim_auto == 1) then    gen_tim_cnt =gen_tim_cnt_st_value   else    gen_tim_cnt = 0          // hold count atzero  else   gen_tim_cnt−− else  gen_tim_cnt = gen_tim_cnt

if (gen_tim_cnt == 1)AND ( cnt_en == 1 )AND (gen_tim_en == 1 ) then tim_icu_irq = 1 else  tim_icu_irq = 015.4.5 Timing Pulse Generator

The timing pulse generator contains a general free running 64-bit timerand 3 timing pulse generators producing timing pulses of one cycleduration with a programmable period. The period is programmed by changedthe TimerStartValue registers, but have a nominal starting period of 1μs, 100 μs and 1 ms. In supervisor mode the free running timer registercan be written to or read from at any time, in user mode access isdenied. The status of each of the timers can be read by accessing thePulseTimerStatus registers in supervisor mode. Any accesses in user modewill result in a bus error.

15.4.5.1 Free Run Timer

The increment logic block increments the timer count on each clockcycle. The counter wraps around to zero and continues incrementing ifoverflow occurs. When the timing register (FreeRunCount) is written to,the configuration registers block will set the free_run_wen high for aclock cycle and the value on write_data will become the new count value.If free_run_wen[1] is 1 the higher 32 bits of the counter will bewritten to, otherwise if free_run_wen[0] the lower 32 bits are writtento. It is the responsibility of software to handle these writes in asensible manner.

The increment logic is given by if (free_run_wen[1] == 1) then free_run_cnt[63:32] = write_data elsif (free_run_wen[0] == 1) then free_run_cnt[31:0] = write_data else  free_run_cnt ++15.4.5.2 Pulse Timers

The pulse timer logic generates timing pulses of 1 clock cycle lengthand programmable period. Nominally they generate pulse periods of 1 μs,100 μs and 1 ms. The logic for timer 0 is given by: // Nominal 1usgenerator if (pulse_0_cnt == 0 ) then pulse_0_cnt = timer_start_value[0]  tim_pulse[0]= 1 else pulse_0_cnt −−  tim_pulse[0]= 0

The logic for timer 1 is given by: // 100us generatorif ((pulse_1_cnt == 0) AND (tim_pulse[0] == 1)) then pulse_1_cnt = timer_start_value[1]  tim_pulse[1]= 1 elsif(tim_pulse[0] == 1) then  pulse_1_cnt −−  tim_pulse[1]= 0 else pulse_1_cnt = pulse_1_cnt  tim_pulse[1]= 0

The logic for the timer 2 is given by: // 10ms generatorif ((pulse_2_cnt == 0 ) AND (tim_pulse[1] == 1)) then pulse_2_cnt = timer_start_value[2]  tim_pulse[2]= 1elsif (tim_pulse[1] == 1) then  pulse_2_cnt −−  tim_pulse[2]= 0 else pulse_2_cnt = pulse_2_cnt  tim_pulse[2]= 015.4.6 Configuration Registers

The configuration registers in the TIM are programmed via the CPUinterface. Refer to section 11.4.3 on page 69 for a description of theprotocol and timing diagrams for reading and writing registers in theTIM. Note that since addresses in SoPEC are byte aligned and the CPUonly supports 32-bit register reads and writes, the lower 2 bits of theCPU address bus are not required to decode the address space for theTIM. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of tim_pcu_data. Table 92 liststhe configuration registers in the TIM block. TABLE 92 Timers RegisterMap Address TIM_base+ Register #bits Reset Description 0x00WatchDogUnitSel  2 0x0 Specifies the units used for the watchdog timer:0 - Nominal 1 μs pulse 1 - Nominal 100 μs pulse 2 - Nominal 10 ms pulse3 - pclk 0x04 WatchDogTimer 32 0xFFFF_FFFF Specifies the number of unitsto count before watchdog timer triggers. 0x08 WatchDogIntThres 320x0000_0000 Specifies the threshold value below which the watchdog timerissues an interrupt 0x0C-0x10 FreeRunCount[1:0] 2x32 0x0000_0000 Directaccess to the free running counter register. Bus 0 - Access to bits 31-0Bus 1 - Access to bits 63-32 0x14 to 0x1C GenCntStartValue[2:0] 3x320x0000_0000 Generic timer counter start value, number of units to countbefore event 0x20 to 0x28 GenCntValue[2:0] 3x32 0x0000_0000 Directaccess to generic timer counter registers 0x2C to 0x34GenCntUnitSel[2:0] 3x2 0x0 Generic counter unit select. Selects thetiming units used with corresponding counter: 0 - Nominal 1 μs pulse 1 -Nominal 100 μs pulse 2 - Nominal 10 ms pulse 3 - pclk 0x38 to 0x40GenCntAuto[2:0] 3x1 0x0 Generic counter auto re-start select. When hightimer automatically restarts, otherwise timer stops. 0x44 to 0x4CGenCntEnable[2:0] 3x1 0x0 Generic counter enable. 0 - Counter disabled1 - Counter enabled 0x50 GenCntUserMode  3 0x0 User Mode Access enableto generic Enable timer configuration register. When 1 user access isenabled. Bit 0 - Generic timer 0 Bit 1 - Generic timer 1 Bit 2 - Generictimer 2 0x54 to 0x5C TimerStartValue[2:0] 3x8 0x7F, Timing pulsegenerator start value. 0x63, Indicates the start value for each 0x63timing pulse timers. For timer 0 the start value specifies the timerperiod in pclk cycles −1. For timer 1 the start value specifies thetimer period in timer 0 intervals −1. For timer 2 the start valuespecifies the timer period in timer 1 intervals −1. Nominally the timersgenerate pulses at 1 us, 100 us and 10 ms intervals respecitively. 0x60DebugSelect[6:2]  5 0x00 Debug address select. Indicates the address ofthe register to report on the tim_cpu_data bus when it is not otherwisebeing used. Read Only Registers 0x64 PulseTimerStatus 24 0x00 Currentpulse timer values, and pulses 7:0 - Timer 0 count 15:8 - Timer 1 count23:16 - Timer 2 count 24 - Timer 0 pulse 25 - Timer 1 pulse 26 - Timer 2pulse15.4.6.1 Supervisor and User Mode Access

The configuration registers block examines the CPU access type(cpu_acode signal) and determines if the access is allowed to thatparticular register, based on configured user access registers. If anaccess is not allowed the block will issue a bus error by asserting thetim_cpu_berr signal.

The timers block is fully accessible in supervisor data mode, allregisters can written to and read from. In user mode access is denied toall registers in the block except for the generic timer configurationregisters that are granted user data access. User data access for ageneric timer is granted by setting corresponding bit in theGenCntUserModeEnable register. This can only be changed in supervisordata mode. If a particular timer is granted user data access then allregisters for configuring that timer will be accessible. For example iftimer 0 is granted user data access the GenCntStartValue[0],GenCntUnitSel[0], GenCntAuto[0], GenCntEnable[0] and GenCntValue[0]registers can all be written to and read from without any restriction.

Attempts to access a user data mode disabled timer configurationregister will result in a bus error. Table 93 details the access modesallowed for registers in the TIM block. In supervisor data mode allregisters are accessable. All forbidden accesses will result in a buserror (tim_cpu_berr asserted). TABLE 93 TIM supervisor and user accessmodes Register Address Registers Access Permission 0x00 WatchDogUnitSelSupervisor data mode only 0x04 WatchDogTimer Supervisor data mode only0x08 WatchDogIntThres Supervisor data mode only 0x0C-0x10 FreeRunCountSupervisor data mode only 0x14 GenCntStartValue[0]GenCntUserModeEnable[0] 0x18 GenCntStartValue[1] GenCntUserModeEnable[1]0x1C GenCntStartValue[2] GenCntUserModeEnable[2] 0x20 GenCntValue[0]GenCntUserModeEnable[0] 0x24 GenCntValue[1] GenCntUserModeEnable[1] 0x28GenCntValue[2] GenCntUserModeEnable[2] 0x2C GenCntUnitSel[0]GenCntUserModeEnable[0] 0x30 GenCntUnitSel[1] GenCntUserModeEnable[1]0x34 GenCntUnitSel[2] GenCntUserModeEnable[2] 0x38 GenCntAuto[0]GenCntUserModeEnable[0] 0x3C GenCntAuto[1] GenCntUserModeEnable[1] 0x40GenCntAuto[2] GenCntUserModeEnable[2] 0x44 GenCntEnable[0]GenCntUserModeEnable[0] 0x48 GenCntEnable[1] GenCntUserModeEnable[1]0x4C GenCntEnable[2] GenCntUserModeEnable[2] 0x50 GenCntUserModeEnableSupervisor data mode only 0x54-0x5C TimerStartValue[2:0] Supervisor datamode only 0x60 DebugSelect Supervisor data mode only 0x64PulseTimerStatus Supervisor data mode only16 Clocking, Power and Reset (CPR)

The CPR block provides all of the clock, power enable and reset signalsto the SoPEC device.

16.1 Powerdown Modes

The CPR block is capable of powering down certain sections of the SoPECdevice. When a section is powered down (i.e. put in sleep mode) no stateis retained (except the PSS storage), the CPU must re-initialize thesection before it can be used again.

For the purpose of powerdown the SoPEC device is divided into sections:TABLE 94 Powerdown sectioning Section Block Print Engine Pipeline PCUSubSystem (Section 0) CDU CFU LBD SFU TE TFU HCU DNC DWU LLU PHICPU-DRAM (Section 1) DRAM CPU/MMU DIU TIM ROM LSS PSS ICU ISI Subsystem(Section 2) ISI (SCB) DMA Ctrl (SCB) GPIO USB Subsystem (Section 3) USB(SCB)Note that the CPR block is not located in any section. All configurationregisters in the CPR block are clocked by an ungateable clock and havespecial reset conditions.

Note that the CPR block is not located in any section. All configurationregisters in the CPR block are clocked by an ungateable clock and havespecial reset conditions.

16.1.1 Sleep Mode

Each section can be put into sleep mode by setting the corresponding bitin the SleepModeEnable register. To re-enable the section the sleep modebit needs to be cleared and then the section should be reset by writingto the relevant bit in the ResetSection register. Each block within thesection should then be re-configured by the CPU.

If the CPU system (section 1) is put into sleep mode, the SoPEC devicewill remain in sleep mode until a system level reset is initiated fromthe reset pin, or a wakeup reset by the SCB block as a result ofactivity on either the USB or ISI bus. The watchdog timer cannot resetthe device as it is in section 1 also, and will be in sleep mode.

If the CPU and ISI subsystem are in sleep mode only a reset from the USBor a hardware reset will re-activate the SoPEC device.

If all sections are put into sleep mode, then only a system level resetinitiated by the reset pin will re-activate the SoPEC device.

Like all software resets in SoPEC the ResetSection register isactive-low i e. a 0 should be written to each bit position requiring areset. The ResetSection register is self-reseting.

16.1.2 Sleep Mode Powerdown Procedure

When powering down a section, the section may retain it's current state(although not gauranteed to). It is possible when powering back up asection that inconsistencies between interface state machines couldcause incorrect operation. In order to prevent such condition fromhappening, all blocks in a section must be disabled before poweringdown. This will ensure that blocks are restored in a benign state whenpowered back up.

In the case of PEP section units setting the Go bit to zero will disablethe block. The DRAM subsystem can be effectively disabled by setting theRotationSync bit to zero, and the SCB system disabled by setting theDMAAccessEn bits to zero turning off the DMA access to DRAM. Other CPUsubsystem blocks without any DRAM access do not need to be disabled.

16.2 Reset Source

The SoPEC device can be reset by a number of sources. When a reset froman internal source is initiated the reset source register (ResetSrc)stores the reset source value. This register can then be used by the CPUto determine the type of boot sequence required.

16.3 Clock Relationship

The crystal oscillator excites a 32 MHz crystal through the xtalin andxtalout pins. The 32 MHz output is used by the PLL to derive the masterVCO frequency of 960 MHz. The master clock is then divided to produce320 MHz clock (clk320), 160 MHz clock (clk160) and 48 MHz (clk48) clocksources.

The phase relationship of each clock from the PLL will be defined. Therelationship of internal clocks clk320, clk48 and clk160 to xtalin willbe undefined.

At the output of the clock block, the skew between each pclk domain(pclk_section[2:0] and jclk) should be within skew tolerances of theirrespective domains (defined as less than the hold time of a D-type flipflop).

The skew between doclk and pclk should also be less than the skewtolerances of their respective domains.

The usbclk is derived from the PLL output and has no relationship withthe other clocks in the system and is considered asynchronous.

16.4 PLL Control

The PLL in SoPEC can be adjusted by programming the PLLRangeA,PLLRangeB, PLLTunebits and PLLMult registers. If these registers arechanged by the CPU the values are not updated until the PLLUpdateregister is written to. Writing to the PLLUpdate register triggers thePLL control state machine to update the PLL configuration in a safe way.When an update is active (as indicated by PLLUpdate register) the CPUmust not change any of the configuration registers, doing so could causethe PLL to lose lock indefintely, requiring a hardware reset to recover.Configuring the PLL registers in an inconsistent way can also cause thePLL to lose lock, care must taken to keep the PLL configuration withinspecified parameters.

The VCO frequency of the PLL is calculated by the number of divider inthe feedback path. PLL output A is used as the feedback source.VCOfreq=REFCLK×PLLMult×PLLRangeA×External dividerVCOfreq=32×3×10×1=960 Mhz.

In the default PLL setup, PLLMult is set to 3, PLLRangeA is set to 3which corresponds to a divide by 10, PLLRangeB is set to 5 whichcorresponds to a divide by 3.PLLouta=VCOfreq/PLLRangeA=960 Mhz/10=96 MhzPLLoutb=VCOfreq/PLLRangeB=960 Mhz/3=320 Mhz

See [16] for complete PLL setup parameters.

16.5 Implementation

16.5.1 Definitions of I/O TABLE 95 CPR I/O definition Port name Pins I/ODescription Clocks and Resets Xtalin 1 In Crystal input, direct from IOpin. Xtalout 1 Inout Crystal output, direct to IO pin. pclk_section[3:0]4 Out System clocks for each section Doclk 1 Out Data out clock (2xpclk) for the PHI block Jclk 1 Out Gated version of system clock used toclock the JPEG decoder core in the CDU Usbclk 1 Out USB clock, nominallyat 48 Mhz jclk_enable 1 In Gating signal for jclk. When 1 jclk isenabled reset_n 1 In Reset signal from the reset_n pin usb_cpr_reset_n 1In Reset signal from the USB block isi_cpr_reset_n 1 In Reset signalfrom the ISI block tim_cpr_reset_n 1 In Reset signal from watch dogtimer. gpio_cpr_wakeup 1 In SoPEC wake up from the GPIO, active high.prst_n_section[3:0] 4 Out System resets for each section, synchronousactive low dorst_n 1 Out Reset for PHI block, synchronous to doclkjrst_n 1 Out Reset for JPEG decoder core in CDU block, synchronous tojclk usbrst_n 1 Out Reset for the USB block, synchronous to usbclk CPUinterface cpu_adr[5:2] 3 In CPU address bus. Only 4 bits are required todecode the address space for the CPR block cpu_dataout[31:0] 32 InShared write data bus from the CPU cpr_cpu_data[31:0] 32 Out Read databus to the CPU cpu_rwn 1 In Common read/not-write signal from the CPUcpu_cpr_sel 1 In Block select from the CPU. When cpu_cpr_sel is highboth cpu_adr and cpu_dataout are valid cpr_cpu_rdy 1 Out Ready signal tothe CPU. When cpr_cpu_rdy is high it indicates the last cycle of theaccess. For a write cycle this means cpu_dataout has been registered bythe block and for a read cycle this means the data on cpr_cpu_data isvalid. cpr_cpu_berr 1 Out Bus error signal to the CPU indicating aninvalid access. cpu_acode[1:0] 2 In CPU Access Code signals. Thesedecode as follows: 00 - User program access 01 - User data access 10 -Supervisor program access 11 - Supervisor data accesscpr_cpu_debug_valid 1 Out Debug Data valid on cpr_cpu_data bus. Activehigh16.5.2 Configuration Registers

The configuration registers in the CPR are programmed via the CPUinterface. Refer to section 11.4 on page 69 for a description of theprotocol and timing diagrams for reading and writing registers in theCPR. Note that since addresses in SoPEC are byte aligned and the CPUonly supports 32-bit register reads and writes, the lower 2 bits of theCPU address bus are not required to decode the address space for theCPR. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of cpr_pcu_data. Table 96 liststhe configuration registers in the CPR block.

The CPR block will only allow supervisor data mode accesses (i.e.cpu_acode[1:0]=SUPERVISOR_DATA). All other accesses will result incpr_cpu_berr being asserted. TABLE 96 CPR Register Map Address CPR_base+Register #bits Reset Description 0x00 SleepModeEnable 4 0x0^(a) SleepMode enable, when high a section of logic is put into powerdown. Bit 0 -Controls section 0 Bit 1 - Controls section 1 Bit 2 - Controls section 2Bit 3 - Controls section 3 Note that the SleepModeEnable register hasspecial reset conditions. See Section 16.5.6 for details 0x04 ResetSrc 50x1^(a) Reset Source register, indicating the source of the last reset(or wake-up) Bit 0 - External Reset Bit 1 - USB wakeup reset Bit 2 - ISIwakeup reset Bit 3 - Watchdog timer reset Bit 4 - GPIO wake-up (ReadOnly Register) 0x08 ResetSection 4 0xF Active-low synchronous reset foreach section, self-resetting. Bit 0 - Controls section 0 Bit 1 -Controls section 1 Bit 2 - Controls section 2 Bit 3 - Controls section 30x0C DebugSelect[5:2] 4 0x0 Debug address select. Indicates the addressof the register to report on the cpr_cpu_data bus when it is nototherwise being used. PLL Control 0x10 PLLTuneBits 10 0x3BC PLL tuningbits 0x14 PLLRangeA 4 0x3 PLLOUT A frequency selector (defaults to 60Mhz to 125 Mhz) 0x18 PLLRangeB 3 0x5 PLLOUT B frequency selector(defaults to 200 Mhz to 400 Mhz) 0x1C PLLMultiplier 5 0x03 PLLmultiplier selector, defaults to refclk × 3 0x20 PLLUpdate 1 0x0 PLLupdate control. A write (of any value) to this register will cause thePLL to lose lock for ˜100 us. Reading the register indicates the statusof the update. 0 - PLL update complete 1 - PLL update active No writesto PLLTuneBits, PLLRangeA, PLL- RangeB, PLLMultiplier or PLLUpdate areallowed while the PLL update is active.^(a)Reset value depends on reset source. External reset shown.

-   -   a. Reset value depends on reset source. External reset shown.        16.5.3 CPR Sub-Block Partition        16.5.4 Reset_n deglitch

The external reset_n signal is deglitched for about 1 μs. reset_n mustmaintain a state for 1 us second before the state is passed into therest of the device. All deglitch logic is clocked on bufrefclk.

16.5.5 Sync Reset

The reset synchronizer retimes an asynchronous reset signal to the clockdomain that it resets. The circuit prevents the inactive edge of resetoccurring when the clock is rising

16.5.6 Reset Generator Logic

The reset generator logic is used to determine which clock domainsshould be reset, based on configured reset values (reset_section_n), theexternal reset (reset_n), watchdog timer reset (tim_cpr_reset_n), theUSB reset (usb_cpr_reset_n), the GPIO wakeup control (gpio_cpr_wakeup)and the ISI reset (isi_cpr_reset_n). The reset direct from the IO pin(reset_n) is synchronized and de-glitched before feeding the resetlogic.

All resets are lengthened to at least 16 pclk cycles, regardless of theduration of the input reset. The clock for a particular section must berunning for the reset to have an effect. The clocks to each section canbe enabled/disabled using the SleepModeEnable register.

Resets from the ISI or USB block reset everything except its own section(section 2 or 3). TABLE 97 Reset domains Reset signal Domainreset_dom[0] Section 0 pclk domain (PEP) reset_dom[1] Section 1 pclkdomain (CPU) reset_dom[2] Section 2 pclk domain (ISI) reset_dom[3]Section 3 usbclk/pclk domain (USB) reset_dom[4] doclk domainreset_dom[5] jclk domain

The logic is given by if (reset_dg_n == 0) then  reset_dom[5:0] = 0x00// reset everything  reset_src[4:0] = 0x01  cfg_reset_n = 0 sleep_mode_en[3:0] = 0x0 // re-awaken all sectionselsif (tim_cpr_reset_n == 0) then  reset_dom[5:0]     = 0x00 // reseteverything except CPR config  reset_src[4:0] = 0x08  cfg_reset_n = 1 //CPR config stays the same  sleep_mode_en[1]   = 0 // re-awaken section 1only (awake already) elsif (usb_cpr_reset_n == 0) then reset_dom[5:0]     = 0x08 // all except USB domain + CPR config reset_src[4:0] = 0x02  cfg_reset_n = 1 // CPR config stays the same sleep_mode_en[1] = 0 // re-awaken section 1 only, section 3 is awakeelsif (isi_cpr_reset_n == 0) then  reset_dom[5:0]     = 0x04 // allexcept ISI domain + CPR config  reset_src[4:0] = 0x04  cfg_reset_n = 1// CPR config stays the same  sleep_mode_en[1] = 0 // re-awaken section1 only, section 2 is awake elsif (gpio_cpr_wakeup = 1) then reset_dom[5:0] = 0x3C // PEP and CPU sections only  reset_src[4:0] =0x10  cfg_reset_n = 1 // CPR config stays the same  sleep_mode_en[1] = 0// re-awaken section 1 only, section 2 is awake else  // propagateresets from reset section register  reset_dom[5:0] = 0x3F        //default to on  cfg_reset_n       = 1          // CPR cfg registers arenot in any section  sleep_mode_en[3:0]  = sleep_mode_en[3:0] // stay the same by default  if (reset_section_n[0] == 0) then   reset_dom[5] =0 // jclk domain   reset_dom[4] = 0 // doclk domain   reset_dom[0] = 0// pclk section 0 domain  if (reset_section_n[1] == 0) then  reset_dom[1] = 0 // pclk section 1 domain  if (reset_section_n[2] ==0) then   reset_dom[2] = 0 // pclk section 2 domain (ISI)  if(reset_section_n[3] == 0) then   reset_dom[3] = 0 // USB domain16.5.7 Sleep Logic

The sleep logic is used to generate gating signals for each of SoPECsclock domains. The gate enable (gate_dom) is generated based on theconfigured sleep_mode_en and the internally generated jclk_enablesignal.

The logic is given by  // clock gating for sleep modes  gate_dom[5:0] =0x0  // default to all clocks on  if (sleep_mode_en[0] == 1) then //section 0 sleep   gate_dom[0] = 1 // pclk section 0   gate_dom[4] = 1 //doclk domain   gate_dom[5] = 1 // jclk domain  if (sleep_mode_en[1]== 1) then  // section 1 sleep   gate_dom[1] = 1 // pclk section 1  if(sleep_mode_en[2] == 1) then  // section 2 sleep   gate_dom[2] = 1 //pclk section 2  if (sleep_mode_en[3] == 1) then  // section 3 sleep  gate_dom[3] = 1 // usb section 3  // the jclk can be turned off by CDUsignal  if (jclk_enable == 0) then   gate_dom[5] = 1

The clock gating and sleep logic is clocked with the master_pclk clockwhich is not gated by this logic, but is synchronous to otherpclk_section and jclk domains.

Once a section is in sleep mode it cannot generate a reset to restartthe device. For example if section 1 is in sleep mode then the watchdogtimer is effectively disabled and cannot trigger a reset.

16.5.8 Clock Gate Logic

The clock gate logic is used to safely gate clocks without generatingany glitches on the gated clock. When the enable is high the clock isactive otherwise the clock is gated

16.5.9 Clock Generator Logic

The clock generator block contains the PLL, crystal oscillator, clockdividers and associated control logic. The PLL VCO frequency is at 960MHz locked to a 32 MHz refclk generated by the crystal oscillator. Intest mode the xtalin signal can be driven directly by the test clockgenerator, the test clock will be reflected on the refclk signal to thePLL.

16.5.9.1 Clock Divider A

The clock divider A block generates the 48 MHz clock from the input 96MHz clock (pllouta) generated by the PLL. The divider is enabled onlywhen the PLL has acquired lock.

16.5.9.2 Clock Divider B

The clock divider B block generates the 160 MHz clocks from the input320 MHz clock (plloutb) generated by the PLL. The divider is enabledonly when the PLL has acquired lock.

16.5.9.3 PLL Control State Machine

The PLL will go out of lock whenever pll_reset goes high (the PLL resetis the only active high reset in the device) or if the configurationbits pll_rangea, pll_rangeb, pll_mult, pll_tune are changed. The PLLcontrol state machine ensures that the rest of the device is protectedfrom glitching clocks while the PLL is being reset or it's configurationis being changed.

In the case of a hardware reset (the reset is deglitched), the statemachine first disables the output clocks (via the clk_gate signal), itthen holds the PLL in reset while its configuration bits are reset todefault values. The state machine then releases the PLL reset and waitsapprox. 100 us to allow the PLL to regain lock. Once the lock time haselapsed the state machine re-enables the output clocks and resets theremainder of the device via the reset_dg_n signal.

When the CPU changes any of the configuration registers it must write tothe PLLupdate register to allow the state machine to update the PLL tothe new configuration setup. If a PLLUpdate is detected the statemachine first gates the output clocks. It then holds the PLL in resetwhile the PLL configuration registers are updated. Once updated the PLLreset is released and the state machine waits approx 100 us for the PLLto regain lock before re-enabling the output clocks. Any write to thePLLUpdate register will cause the state machine to perform the updateoperation regardless of whether the configuration values changed or not.

All logic in the clock generator is clocked on bufrefclk which is alwaysan active clock regardless of the state of the PLL.

17 ROM Block

17.1 Overview

The ROM block interfaces to the CPU bus and contains the SoPEC bootcode. The ROM block consists of the CPU bus interface, the ROM macro andthe ChipID macro. The current ROM size is 16 KBytes implemented as a4096×32 macro. Access to the ROM is not cached because the CPU enjoysfast (no more than one cycle slower than a cache access), unarbitratedaccess to the ROM. Each SoPEC device is required to have a unique ChipIDwhich is set by blowing fuses at manufacture. IBM's 300 mm ECID macroand a custom 112-bit ECID macro are used to implement the ChipIDoffering 224-bits of laser fuses. The exact number of fuse bits to beused for the ChipID will be determined later but all bits are madeavailable to the CPU. The ECID macros allows all 224 bits to be read outin parallel and the ROM block will make all 224 bits available in theFuseChipID[N] registers which are readable by the CPU in supervisor modeonly.

17.2 Boot Operation

The are two boot scenarIOs for the SoPEC device namely after power-onand after being awoken from sleep mode. When the device is in sleep modeit is hoped that power will actually be removed from the DRAM, CPU andmost other peripherals and so the program code will need to be freshlydownloaded each time the device wakes up from sleep mode. In order toreduce the wakeup boot time (and hence the perceived print latency)certain data items are stored in the PSS block (see section 18). Thesedata items include the SHA-1 hash digest expected for the program(s) tobe downloaded, the master/slave SoPEC id and some configurationparameters. All of these data items are stored in the PSS by the CPUprior to entering sleep mode. The SHA-1 value stored in the PSS iscalculated by the CPU by decrypting the signature of the downloadedprogram using the appropriate public key stored in ROM. This computeintensive decryption only needs to take place once as part of thepower-on boot sequence—subsequent wakeup boot sequences will simply usethe resulting SHA-1 digest stored in the PSS. Note that the digest onlyneeds to be stored in the PSS before entering sleep mode and the PSS canbe used for temporary storage of any data at all other times.

The CPU is expected to be in supervisor mode for the entire bootsequence described by the pseudocode below. Note that the boot sequencehas not been finalised but is expected to be close to the following:  if(ResetSrc == 1) then // Reset was a power-on reset  configure_sopec // need to configure peris (USB, ISI, DMA, ICU etc.) // Otherwise reset was a wakeup reset so peris etc. were alreadyconfigured  PAUSE: wait until IrqSemaphore != 0 // i.e. wait until aninterrupt has been serviced  if (IrqSemaphore == DMAChan0Msg) then  parse_msg(DMAChan0MsgPtr) // this routine will parse the message andtake any          // necessary action e.g. programming the DMAChannel1registers  elsif (IrqSemaphore == DMAChan1Msg) then // program has beendownloaded   CalculatedHash = gen_sha1(ProgramLocn, ProgramSize)   if(ResetSrc == 1) then    ExpectedHash =sig_decrypt(ProgramSig,public_key)   else    ExpectedHash = PSSHash   if(ExpectedHash == CalculatedHash) then    jmp(PrgramLocn) // transfercontrol to the downloaded program   else    send_host_msg(“ProgramAuthentication Failed”)    goto PAUSE:   elsif (IrqSemaphore ==timeout) then // nothing has happened    if (ResetSrc == 1) then   sleep_mode( ) // put SoPEC into sleep mode to be woken up by USB/ISIactivity    else // we were woken up but nothing happened    reset_sopec(PowerOnReset)   else    goto PAUSE

The boot code places no restrictions on the activity of any programsdownloaded and authenticated by it other than those imposed by theconfiguration of the MMU i.e. the principal function of the boot code isto authenticate that any programs downloaded by it are from a trustedsource. It is the responsibility of the downloaded program to ensurethat any code it downloads is also authenticated and that the systemremains secure. The downloaded program code is also responsible forsetting the SoPEC ISIId (see section 12.5 for a description of theISIID) in a multi-SoPEC system. See the “SoPEC Security Overview”document [9] for more details of the SoPEC security features.

17.3 Implementation

17.3.1 Definitions of I/O TABLE 98 ROM Block I/O Port name Pins I/ODescription Clocks and Resets prst_n 1 In Global reset. Synchronous topclk, active low. Pclk 1 In Global clock CPU Interface cpu_adr[14:2] 13In CPU address bus. Only 13 bits are required to decode the addressspace for this block. rom_cpu_data[31:0] 32 Out Read data bus to the CPUcpu_rwn 1 In Common read/not-write signal from the CPU cpu_acode[1:0] 2In CPU Access Code signals. These decode as follows: 00 - User programaccess 01 - User data access 10 - Supervisor program access 11 -Supervisor data access cpu_rom_sel 1 In Block select from the CPU. Whencpu_rom_sel is high cpu_adr is valid rom_cpu_rdy 1 Out Ready signal tothe CPU. When rom_cpu_rdy is high it indicates the last cycle of theaccess. For a read cycle this means the data on rom_cpu_data is valid.rom_cpu_berr 1 Out ROM bus error signal to the CPU indicating an invalidaccess.17.3.2 Configuration Registers

The ROM block will only allow read accesses to the FuseChipID registersand the ROM with supervisor data space permissions (i.e.cpu_acode[1:0]=11). Write accesses with supervisor data spacepermissions

will have no effect. All other accesses with will result in rom_cpu_berrbeing asserted. The CPU subsystem bus slave interface is described inmore detail in section 9.4.3. TABLE 99 ROM Block Register Map AddressROM_base+ Register #bits Reset Description 0x4000 FuseChipID0 32 n/aValue of corresponding fuse bits 31 to 0 of the IBM 112-bit ECID macro.(Read only) 0x4004 FuseChipID1 32 n/a Value of corresponding fuse bits63 to 32 of the IBM 112-bit ECID macro. (Read only) 0x4008 FuseChipID232 n/a Value of corresponding fuse bits 95 to 64 of the IBM 112-bit ECIDmacro. (Read only) 0x400C FuseChipID3 16 n/a Value of corresponding fusebits 111 to 96 of the IBM 112-bit ECID macro. (Read only) 0x4010FuseChipID4 32 n/a Value of corresponding fuse bits 31 to 0 of theCustom 112-bit ECID macro. (Read only) 0x4014 FuseChipID5 32 n/a Valueof corresponding fuse bits 63 to 32 of the Custom 112-bit ECID macro.(Read only) 0x4018 FuseChipID6 32 n/a Value of corresponding fuse bits95 to 64 of the Custom 112-bit ECID macro. (Read only) 0x401CFuseChipID7 16 n/a Value of corresponding fuse bits 111 to 96 of theCustom 112-bit ECID macro. (Read only)17.3.3 Sub-Block Partition

IBM offer two variants of their ROM macros; A high performance version(ROMHD) and a low power version (ROMLD). It is likely that the low powerversion will be used unless some implementation issue requires the highperformance version. Both versions offer the same bit density. Thesub-block partition diagram below does not include the clocking and testsignals for the ROM or ECID macros. The CPU subsystem bus interface isdescribed in more detail in section 11.4.3.

17.3.4 TABLE 100 ROM Block internal signals Port name Width DescriptionClocks and Resets prst_n 1 Global reset. Synchronous to pclk, activelow. Pclk 1 Global clock Internal Signals rom_adr[11:0] 12 ROM addressbus rom_sel 1 Select signal to the ROM macro instructing it to accessthe location at rom_adr rom_oe 1 Output enable signal to the ROM blockrom_data[31:0] 32 Data bus from the ROM macro to the CPU bus interfacerom_dvalid 1 Signal from the ROM macro indicating that the data onrom_data is valid for the address on rom_adr fuse_data[31:0] 32 Datafrom the FuseChipID[N] register addressed by fuse_reg_adrfuse_reg_adr[2:0] 3 Indicates which of the FuseChipID registers is beingaddressedSub-Block Signal Definition18 Power Safe Storage (PSS) Block18.1 Overview

The PSS block provides 128 bytes of storage space that will maintain itsstate when the rest of the SoPEC device is in sleep mode. The PSS isexpected to be used primarily for the storage of decrypted signaturesassociated with downloaded programmed code but it can also be used tostore any information that needs to survive sleep mode (e.g.configuration details). Note that the signature digest only needs to bestored in the PSS before entering sleep mode and the PSS can be used fortemporary storage of any data at all other times.

Prior to entering sleep mode the CPU should store all of the informationit will need on exiting sleep mode in the PSS. On emerging from sleepmode the boot code in ROM will read the ResetSrc register in the CPRblock to determine which reset source caused the wakeup. The resetsource information indicates whether or not the PSS contains validstored data, and the PSS data determines the type of boot sequence toexecute. If for any reason a full power-on boot sequence should beperformed (e.g. the printer driver has been updated) then this is simplyachieved by initiating a full software reset.

Note that a reset or a powerdown (powerdown is implemented by clockgating) of the PSS block will not clear the contents of the 128 bytes ofstorage. If clearing of the PSS storage is required, then the CPU mustwrite to each location individually.

18.2 Implementation

The storage area of the PSS block will be implemented as a 128-byteregister array. The array is located from PSS_base through toPSS_base+0x7F in the address map. The PSS block will only allow read orwrite accesses with supervisor data space permissions (i.e.cpu_acode[1:0]=11). All other accesses will result in pss_cpu_berr beingasserted. The CPU subsystem bus slave interface is described in moredetail in section 11.4.3.

18.2.1 Definitions of I/O TABLE 101 PSS Block I/O Port name Pins I/ODescription Clocks and Resets prst_n 1 In Global reset. Synchronous topclk, active low. Pclk 1 In Global clock CPU Interface cpu_adr[6:2] 5 InCPU address bus. Only 5 bits are required to decode the address spacefor this block. cpu_dataout[31:0] 32 In Shared write data bus from theCPU pss_cpu_data[31:0] 32 Out Read data bus to the CPU cpus_rwn 1 InCommon read/not-write signal from the CPU cpu_acode[1:0] 2 In CPU AccessCode signals. These decode as follows: 00 - User program access 01 -User data access 10 - Supervisor program access 11 - Supervisor dataaccess cpu_pss_sel 1 In Block select from the CPU. When cpu_pss_sel ishigh both cpu_adr and cpu_dataout are valid pss_cpu_rdy 1 Out Readysignal to the CPU. When pss_cpu_rdy is high it indicates the last cycleof the access. For a read cycle this means the data on pss_cpu_data isvalid. pss_cpu_berr 1 Out PSS bus error signal to the CPU indicating aninvalid access.19 Low Speed Serial Interface (LSS)19.1 Overview

The Low Speed Serial Interface (LSS) provides a mechanism for theinternal SoPEC CPU to communicate with external QA chips via twoindependent LSS buses. The LSS communicates through the GPIO block tothe QA chips. This allows the QA chip pins to be reused in multi-SoPECenvironments. The LSS Master system-level interface is illustrated inFIG. 75. Note that multiple QA chips are allowed on each LSS bus.

19.2 QA Communication

The SoPEC data interface to the QA Chips is a low speed, 2 pin,synchronous serial bus. Data is transferred to the QA chips via thelss_data pin synchronously with the lss_clk pin. When the lss_clk ishigh the data on lss_data is deemed to be valid. Only the LSS master inSoPEC can drive the lss_clk pin, this pin is an input only to the QAchips. The LSS block must be able to interface with an open-collectorpull-up bus. This means that when the LSS block should transmit alogical zero it will drive 0 on the bus, but when it should transmit alogical 1 it will leave high-impedance on the bus (i.e. it doesn't drivethe bus). If all the agents on the LSS bus adhere to this protocol thenthere will be no issues with bus contention.

The LSS block controls all communication to and from the QA chips. TheLSS block is the bus master in all cases. The LSS block interprets acommand register set by the SoPEC CPU, initiates transactions to the QAchip in question and optionally accepts return data. Any returninformation is presented through the configuration registers to theSoPEC CPU. The LSS block indicates to the CPU the completion of acommand or the occurrence of an error via an interrupt. The LSS protocolcan be used to communicate with other LSS slave devices (other than QAchips). However should a LSS slave device hold the clock low (forwhatever reason), it will be in violation of the LSS protocol and is notsupported. The LSS clock is only ever driven by the LSS master.

19.2.1 Start and Stop Conditions

All transmissions on the LSS bus are initiated by the LSS master issuinga STAR_(T) condition and terminated by the LSS master issuing a STOPcondition. STAR_(T) and STOP conditions are always generated by the LSSmaster. As illustrated in FIG. 76, a STAR_(T) condition corresponds to ahigh to low transition on lss_data while lss_clk is high. A STOPcondition corresponds to a low to high transition on lss_data whilelss_clk is high.

19.2.2 Data Transfer

Data is transferred on the LSS bus via a byte orientated protocol. Bytesare transmitted serially. Each byte is sent most significant bit (MSB)first through to least significant bit (LSB) last. One clock pulse isgenerated for each data bit transferred. Each byte must be followed byan acknowledge bit.

The data on the lss_data must be stable during the HIGH period of thelss_clk clock. Data may only change when lss_clk is low. A transmitteroutputs data after the falling edge of lss_clk and a receiver inputs thedata at the rising edge of lss_clk. This data is only considered as avalid data bit at the next lss_clk falling edge provided a STAR_(T) orSTOP is not detected in the period before the next lss_clk falling edge.All clock pulses are generated by the LSS block. The transmitterreleases the lss_data line (high) during the acknowledge clock pulse(ninth clock pulse). The receiver must pull down the lss_data lineduring the acknowledge clock pulse so that it remains stable low duringthe HIGH period of this clock pulse.

Data transfers follow the format shown in FIG. 77. The first byte sentby the LSS master after a STAR_(T) condition is a primary id byte, wherebits 7-2 form a 6-bit primary id (0 is a global id and will address allQA Chips on a particular LSS bus), bit 1 is an even parity bit for theprimary ID, and bit 0 forms the read/write sense. Bit 0 is high if thefollowing command is a read to the primary id given or low for a writecommand to that id. An acknowledge is generated by the QA chip(s)corresponding to the given id (if such a chip exists) by driving thelss_data line low synchronous with the LSS master generated ninthlss_clk.

19.2.3 Write Procedure

The protocol for a write access to a QA Chip over the LSS bus isillustrated in FIG. 79 below. The LSS master in SoPEC initiates thetransaction by generating a STAR_(T) condition on the LSS bus. It thentransmits the primary id byte with a 0 in bit 0 to indicate that thefollowing command is a write to the primary id. An acknowledge isgenerated by the QA chip corresponding to the given primary id. The LSSmaster will clock out M data bytes with the slave QA Chip acknowledgingeach successful byte written. Once the slave QA chip has acknowledgedthe M^(th) data byte the LSS master issues a STOP condition to completethe transfer. The QA chip gathers the M data bytes together andinterprets them as a command. See QA Chip Interface Specification formore details on the format of the commands used to communicate with theQA chip[8]. Note that the QA chip is free to not acknowledge any bytetransmitted. The LSS master should respond by issuing an interrupt tothe CPU to indicate this error. The CPU should then generate a STOPcondition on the LSS bus to gracefully complete the transaction on theLSS bus.

19.2.4 Read Procedure

The LSS master in SoPEC initiates the transaction by generating aSTAR_(T) condition on the LSS bus. It then transmits the primary id bytewith a 1 in bit 0 to indicate that the following command is a read tothe primary id. An acknowledge is generated by the QA chip correspondingto the given primary id. The LSS master releases the lss_data bus andproceeds to clock the expected number of bytes from the QA chip with theLSS master acknowledging each successful byte read. The last expectedbyte is not acknowledged by the LSS master. It then completes thetransaction by generating a STOP condition on the LSS bus. See QA ChipInterface Specification for more details on the format of the commandsused to communicate with the QA chip[8].

19.3 Implementation

A block diagram of the LSS master is given in FIG. 80. It consists of ablock of configuration registers that are programmed by the CPU and twoidentical LSS master units that generate the signalling protocols on thetwo LSS buses as well as interrupts to the CPU. The CPU initiates andterminates transactions on the LSS buses by writing an appropriatecommand to the command register, writes bytes to be transmitted to abuffer and reads bytes received from a buffer, and checks the sources ofinterrupts by reading status registers.

19.3.1 Definitions of IO TABLE 102 LSS IO pins definitions Port namePins I/O Description Clocks and Resets Pclk 1 In System Clock prst_n 1In System reset, synchronous active low CPU Interface cpu_rwn 1 InCommon read/not-write signal from the CPU cpu_adr[6:2] 5 In CPU addressbus. Only 5 bits are required to decode the address space for this blockcpu_dataout[31:0] 32 In Shared write data bus from the CPUcpu_acode[1:0] 2 In CPU access code signals. cpu_acode[0] - Program(0)/Data (1) access cpu_acode[1] - User (0)/Supervisor (1) accesscpu_lss_sel 1 In Block select from the CPU. When cpu_lss_sel is highboth cpu_adr and cpu_dataout are valid lss_cpu_rdy 1 Out Ready signal tothe CPU. When lss_cpu_rdy is high it indicates the last cycle of theaccess. For a write cycle this means cpu_dataout has been registered bythe LSS block and for a read cycle this means the data on lss_cpu_datais valid. lss_cpu_berr 1 Out LSS bus error signal to the CPU.lss_cpu_data[31:0] 32 Out Read data bus to the CPU lss_cpu_debug_valid 1Out Active high. Indicates the presence of valid debug data onlss_cpu_data. GPIO for LSS buses lss_gpio_dout[1:0] 2 Out LSS bus dataoutput Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 gpio_lss_din[1:0] 2 In LSSbus data input Bit 0 - LSS bus 0 Bit 1 - LSS bus 1 lss_gpio_e[1:0] 2 OutLSS bus data output enable, active high Bit 0 - LSS bus 0 Bit 1 - LSSbus 1 lss_gpio_clk[1:0] 2 Out LSS bus clock output Bit 0 - LSS bus 0 Bit1 - LSS bus 1 ICU interface lss_icu_irq[1:0] 2 Out LSS interruptrequests Bit 0 - interrupt associated with LSS bus 0 Bit 1 - interruptassociated with LSS bus 119.3.2 Configuration Registers

The configuration registers in the LSS block are programmed via the CPUinterface. Refer to section 11.4 on page 69 for the description of theprotocol and timing diagrams for reading and writing registers in theLSS block. Note that since addresses in SoPEC are byte aligned and theCPU only supports 32-bit register reads and writes, the lower 2 bits ofthe CPU address bus are not required to decode the address space for theLSS block. Table 103 lists the configuration registers in the LSS block.When reading a register that is less than 32 bits wide zeros should bereturned on the upper unused bit(s) of lss_cpu_data.

The input cpu_acode signal indicates whether the current CPU access issupervisor, user, program or data. The configuration registers in theLSS block can only be read or written by a supervisor data access, i.e.when cpu_acode equals b11. If the current access is a supervisor dataaccess then the LSS responds by asserting lss_cpu_rdy for a single clockcycle.

If the current access is anything other than a supervisor data access,then the LSS generates a bus error by asserting lss_cpu_berr for asingle clock cycle instead of lss_cpu_rdy as shown in section 11.4 onpage 69. A write access will be ignored, and a read access will returnzero. TABLE 103 LSS Control Registers Address (LSS_base+) Register #bitsReset Description Control registers 0x00 Reset 1 0x1 A write to thisregister causes a reset of the LSS. 0x04 LssClockHighLow- 16 0x00C8Lss_clk has a 50:50 duty cycle, this register Duration defines theperiod of lss_clk by means of specifying the duration (in pclk cycles)that lss_clk is low (or high). The reset value specifies transmissionover the LSS bus at a nominal rate of 400 kHz, corresponding to a low(or high) duration of 200 pclk (160 Mhz) cycles. Register should not beset to values less than 8. 0x08 LssClocktoDataHold 6 0x3 Specifies thenumber of pclk cycles that Data must remain valid for after the fallingedge of lss_clk. Minimum value is 3 cycles, and must to programmed to beless than LssClockHighLowDuration. LSS bus 0 registers 0x10Lss0IntStatus 3 0x0 LSS bus 0 interrupt status registers Bit 0 - commandcompleted successfully Bit 1 - error during processing of command,not-acknowledge received after transmission of primary id byte on LSSbus 0 Bit 2 - error during processing of command, not-acknowledgereceived after transmission of data byte on LSS bus 0 All the bits inLss0IntStatus are cleared when the Lss0Cmd register gets written to.(Read only register) 0x14 Lss0CurrentState 4 0x0 Gives the current stateof the LSS bus 0 state machine. (Read only register). (Encoding will bespecified upon state machine implementation) 0x18 Lss0Cmd 21 0x00_0000Command register defining sequence of events to perform on LSS bus 0before interrupting CPU. A write to this register causes all the bits inthe Lss0IntStatus register to be cleared as well as generating alss0_new_cmd pulse. 0x1C-0x2C Lss0Buffer[4:0] 5x32 0x0000_0000 LSS Databuffer. Should be filled with transmit data before transmit command, orread data bytes received after a valid read command. LSS bus 1 registers0x30 Lss1IntStatus 3 0x0 LSS bus 1 interrupt status registers Bit 0 -command completed successfully Bit 1 - error during processing ofcommand, not-acknowledge received after transmission of primary id byteon LSS bus 1 Bit 2 - error during processing of command, not-acknowledgereceived after transmission of data byte on LSS bus 1 All the bits inLss1IntStatus are cleared when the Lss1Cmd register gets written to.(Read only register) 0x34 Lss1CurrentState 4 0x0 Gives the current stateof the LSS bus 1 state machine. (Read only register) (Encoding will bespecified upon state machine implementation) 0x38 Lss1Cmd 21 0x00_0000Command register defining sequence of events to perform on LSS bus 1before interrupting CPU. A write to this register causes all the bits inthe Lss1IntStatus register to be cleared as well as generating alss1_new_cmd pulse. 0x3C-0x4C Lss1Buffer[4:0] 5x32 0x0000_0000 LSS Databuffer. Should be filled with transmit data before transmit command, orread data bytes received after a valid read command. Debug registers0x50 LssDebugSel[6:2] 5 0x00 Selects register for debug output. Thisvalue is used as the input to the register decode logic instead ofcpu_adr[6:2] when the LSS block is not being accessed by the CPU, i.e.when cpu_lss_sel is 0. The output lss_cpu_debug_valid is asserted toindicate that the data on lss_cpu_data is valid debug data. This datacan be mutliplexed onto chip pins during debug mode.19.3.2.1 LSS Command Registers

The LSS command registers define a sequence of events to perform on therespective LSS bus before issuing an interrupt to the CPU. There is aseparate command register and interrupt for each LSS bus. The format ofthe command is given in Table 104. The CPU writes to the commandregister to initiate a sequence of events on an LSS bus. Once thesequence of events has completed or an error has occurred, an interruptis sent back to the CPU.

Some example commands are:

-   -   a single STAR_(T) condition (Start=1, IdByteEnable=0,        RdWrEnable=0, Stop=0)    -   a single STOP condition (Start=0, IdByteEnable=0, RdWrEnable=0,        Stop=1)    -   a STAR_(T) condition followed by transmission of the id byte        (Start=1, IdByteEnable=1, RdWrEnable=0, Stop=0, IdByte contains        primary id byte)    -   a write transfer of 20 bytes from the data buffer (Start=0,        IdByteEnable=0, RdWrEnable=1, RdWrSense=0, Stop=0,        TxRxByteCount=20)    -   a read transfer of 8 bytes into the data buffer (Start=0,        IdByteEnable=0, RdWrEnable=1, RdWrSense=1, ReadNack=0, Stop=0,        TxRxByteCount=8)    -   a complete read transaction of 16 bytes (Start=1,        IdByteEnable=1, RdWrEnable=1, RdWrSense=1, ReadNack=1, Stop=1,        IdByte contains primary id byte, TxRxByteCount=16), etc.

The CPU can thus program the number of bytes to be transmitted orreceived (up to a maximum of 20) on the LSS bus before it getsinterrupted. This allows it to insert arbitrary delays in a transfer ata byte boundary. For example the CPU may want to transmit 30 bytes to aQA chip but insert a delay between the 20^(th) and 21^(st) bytes sent.It does this by first writing 20 bytes to the data buffer. It thenwrites a command to generate a STAR_(T) condition, send the primary idbyte and then transmit the 20 bytes from the data buffer. Wheninterrupted by the LSS block to indicate successful completion of thecommand the CPU can then write the remaining 10 bytes to the databuffer. It can then wait for a defined period of time before writing acommand to transmit the 10 bytes from the data buffer and generate aSTOP condition to terminate the transaction over the LSS bus.

An interrupt to the CPU is generated for one cycle when any bit inLssNIntStatus is set. The CPU can read LssNIntStatus to discover thesource of the interrupt. The LssNIntStatus registers are cleared whenthe CPU writes to the LssNCmd register. A null command write to theLssNCmd register will cause the LssNIntStatus registers to clear and nonew command to start. A null command is defined as Start, IdbyteEnable,RdWrEnable and Stop all set to zero. TABLE 104 LSS command registerdescription bit(s) name Description 0 Start When 1, issue a STARTcondition on the LSS bus. 1 IdByteEnable ID byte transmit enable: 1 -transmit byte in IdByte field 0 - ignore byte in IdByte field 2RdWrEnable Read/write transfer enable: 0 - ignore settings of RdWrSense,ReadNack and TxRxByteCount 1 - if RdWrSense is 0, then perform a writetransfer of TxRxByteCount bytes from the data buffer. if RdWrSense is 1,then perform a read transfer of TxRxByteCount bytes into the databuffer. Each byte should be acknowledged and the last byte received isacknowledged/not-acknowledged according to the setting of ReadNack. 3RdWrSense Read/write sense indicator: 0 - write 1 - read 4 ReadNackIndicates, for a read transfer, whether to issue an acknowledge or anot-acknowledge after the last byte received (indicated byTxRxByteCount). 0 - issue acknowledge after last byte received 1 - issuenot-acknowledge after last byte received. 5 Stop When 1, issue a STOPcondition on the LSS bus. 7:6 reserved Must be 0 15:8  IdByte Byte to betransmitted if IdByteEnable is 1. Bit 8 corresponds to the LSB. 20:16TxRxByteCount Number of bytes to be transmitted from the data buffer orthe number of bytes to be received into the data buffer. The maximumvalue that should be programmed is 20, as the size of the data buffer is20 bytes. Valid values are 1 to 20, 0 is valid when RdWrEnable = 0,other cases are invalid andundefined.

The data buffer is implemented in the LSS master block. When the CPUwrites to the LssNBuffer registers the data written is presented to theLSS master block via the lssN_buffer_wrdata bus and configurationregisters block pulses the lssN_buffer_wen bit corresponding to theregister written. For example if LssNBuffer[2] is written tolssN_buffer_wen[2] will be pulsed. When the CPU reads the LssNBufferregisters the configuration registers block reflect thelssN_buffer_rdata bus back to the CPU.

19.3.3 LSS Master Unit

The LSS master unit is instantiated for both LSS bus 0 and LSS bus 1. Itcontrols transactions on the LSS bus by means of the state machine shownin FIG. 83, which interprets the commands that are written by the CPU.It also contains a single 20 byte data buffer used for transmitting andreceiving data.

The CPU can write data to be transmitted on the LSS bus by writing tothe LssNBuffer registers. It can also read data that the LSS master unitreceives on the LSS bus by reading the same registers. The LSS masteralways transmits or receives bytes to or from the data buffer in thesame order.

For a transmit command, LssNBuffer[0][7:0] gets transmitted first, thenLssNBuffer[0][15:8], LssNBuffer[0][23:16], LssNBuffer[0][31:24],LssNBuffer[1][7:0] and so on until TxRxByteCount number of bytes aretransmitted. A receive command fills data to the buffer in the sameorder. Each new command the buffer start point is reset.

All state machine outputs, flags and counters are cleared on reset.After a reset the state machine goes to the Reset state and initialisesthe LSS pins (lss_clk is set to 1, lss_data is tristated and allowed tobe pulled up to 1). When the reset condition is removed the statemachine transitions to the Wait state.

It remains in the Wait state until lss_new_cmd equals 1. If the Startbit of the command is 0 the state machine proceeds directly to theCheckIdByteEnable state. If the Start bit is 1 it proceeds to theGenerateStart state and issues a STAR_(T) condition on the LSS bus.

In the CheckIdByteEnable state, if the IdByteEnable bit of the commandis 0 the state machine proceeds directly to the CheckRdWrEnable state.If the IdByteEnable bit is 1 the state machine enters the SendIdBytestate and the byte in the IdByte field of the command is transmitted onthe LSS. The WaitForIdAck state is then entered. If the byte isacknowledged, the state machine proceeds to the CheckRdWrEnable state.If the byte is not-acknowledged, the state machine proceeds to theGenerateInterrupt state and issues an interrupt to indicate anot-acknowledge was received after transmission of the primary id byte.

In the CheckRdWrEnable state, if the RdWrEnable bit of the command is 0the state machine proceeds directly to the CheckStop state. If theRdWrEnable bit is 1, count is loaded with the value of the TxRxByteCountfield of the command and the state machine enters either the ReceiveBytestate if the RdWrSense bit of the command is 1 or the TransmitByte stateif the RdWrSense bit is 0.

For a write transaction, the state machine keeps transmitting bytes fromthe data buffer, decrementing count after each byte transmitted, untilcount is 1. If all the bytes are successfully transmitted the statemachine proceeds to the CheckStop state. If the slave QA chipnot-acknowledges a transmitted byte, the state machine indicates thiserror by issuing an interrupt to the CPU and then entering theGenerateInterrupt state.

For a read transaction, the state machine keeps receiving bytes into thedata buffer, decrementing count after each byte transmitted, until countis 1. After each byte received the LSS master must issue an acknowledge.After the last expected byte (i.e. when count is 1) the state machinechecks the ReadNack bit of the command to see whether it must issue anacknowledge or not-acknowledge for that byte. The CheckStop state isthen entered.

In the CheckStop state, if the Stop bit of the command is 0 the statemachine proceeds directly to the GenerateInterrupt state. If the Stopbit is 1 it proceeds to the GenerateStop state and issues a STOPcondition on the LSS bus before proceeding to the GenerateInterruptstate. In both cases an interrupt is issued to indicate successfulcompletion of the command.

The state machine then enters the Wait state to await the next command.When the state machine reenters the Wait state the output pins (lss_andlss_clk) are not changed, they retain the state of the last command.This allows the possibility of multi-command transactions. The CPU mayabort the current transfer at any time by performing a write to theReset register of the LSS block.

19.3.3.1 STAR_(T) and STOP Generation

STAR_(T) and STOP conditions, which signal the beginning and end of datatransmission, occur when the LSS master generates a falling and risingedge respectively on the data while the clock is high.

In the GenerateStart state, lss_gpio_clk is held high with lss_gpio_eremaining deasserted (so the data line is pulled high externally) forLssClockHighLowDuration pclk cycles. Then lss_gpio_e is asserted andlss_gpio_dout is pulled low (to drive a 0 on the data line, creating afalling edge) with lss_gpio_clk remaining high for anotherLssClockHighLowDuration pclk cycles. In the GenerateStop state, bothlss_gpio_clk and lss_gpio_dout are pulled low followed by the assertionof lss_gpio_e to drive a 0 while the clock is low. AfterLssClockHighLowDuration pclk cycles, lss_gpio_clk is set high. After afurther LssClockHighLowDuration pclk cycles, lss_gpio_e is deasserted torelease the data bus and create a rising edge on the data bus during thehigh period of the clock.

If the bus is not in the required state for start and stop generation(lss_clk=1, lss_data=1 for start, and lss_clk=1, lss_data=0), the statemachine moves the bus to the correct state and proceeds as describedabove. FIG. 82 shows the transition timing from any bus state to startand stop generation

19.3.3.2 Clock Pulse Generation

The LSS master holds lss_gpio_clk high while the LSS bus is inactive. Aclock pulse is generated for each bit transmitted or received over theLSS bus. It is generated by first holding lss_gpio_clk low forLssClockHighLowDuration pclk cycles, and then high forLssClockHighLowDuration pclk cycles.

19.3.3.3 Data De-Glitching

When data is received in the LSS block it is passed to a de-glitchingcircuit. The de-glitch circuit samples the data 3 times on pclk andcompares the samples. If all 3 samples are the same then the data ispassed, otherwise the data is ignored.

Note that the LSS data input on SoPEC is double registered in the GPIOblock before being passed to the LSS.

19.3.3.4 Data Reception

The input data, gpio_lss_di, is first synchronised to the pclk domain bymeans of two flip-flops clocked by pclk (the double register resides inthe GPIO block). The LSS master generates a clock pulse for each bitreceived. The output lss_gpio_e is deasserted LssClockToDataHold pclkcycles after the falling edge of lss_gpio_clk to release the data bus.The value on the synchronised gpio_lss_di is sampled Tstrobe number ofclock cycles after the rising edge of lss_gpio_clk (the data isde-glitched over a further 3 stage register to avoid possible glitchdetection). See FIG. 84 for further timing information.

In the ReceiveByte state, the state machine generates 8 clock pulses. Ateach Tstrobe time after the rising edge of lss_gpio_clk the synchronisedgpio_lss_di is sampled. The first bit sampled is LssNBuffer[0][7], thesecond LssNBuffer[0][6], etc to LssNBuffer[0][0]. For each byte receivedthe state machine either sends an NAK or an ACK depending on the commandconfiguration and the number of bytes received.

In the SendNack state the state machine generates a single clock pulse.lss_gpio_e is deasserted and the LSS data line is pulled high externallyto issue a not-acknowledge.

In the SendAck state the state machine generates a single clock pulse.lss_gpio_e is asserted and a 0 driven on lss_gpio_dout afterlss_gpio_clk falling edge to issue an acknowledge.

19.3.3.5 Data Transmission

The LSS master generates a clock pulse for each bit transmitted. Data isoutput on the LSS bus on the falling edge of lss_gpio_clk.

When the LSS master drives a logical zero on the bus it will assertlss_gpio_e and drive a 0 on lss_gpio_dout after lss_gpio_clk fallingedge. lss_gpio_e will remain asserted and lss_gpio_dout will remain lowuntil the next lss_clk falling edge.

When the LSS master drives a logical one lss_gpio_e should be deassertedat lss_gpio_clk falling edge and remain deasserted at least until thenext lss_gpio_clk falling edge. This is because the LSS bus will beexternally pulled up to logical one via a pull-up resistor.

In the SendId byte state, the state machine generates 8 clock pulses totransmit the byte in the IdByte field of the current valid command. Oneach falling edge of lss_gpio_clk a bit is driven on the data bus asoutlined above. On the first falling edge IdByte[7] is driven on thedata bus, on the second falling edge IdByte[6] is driven out, etc.

In the TransmitByte state, the state machine generates 8 clock pulses totransmit the byte at the output of the transmit FIFO. On each fallingedge of lss_gpio_clk a bit is driven on the data bus as outlined above.On the first falling edge LssNBuffer[0][7] is driven on the data bus, onthe second falling edge LssNBuffer[0][6] is driven out, etc on toLssNBuffer[0][7] bits.

In the WaitForAck state, the state machine generates a single clockpulse. At Tstrobe time after the rising edge of lss_gpio_clk thesynchronized gpio_lss_di is sampled. A 0 indicates an acknowledge andack_detect is pulsed, a 1 indicates a not-acknowledge and nack_detect ispulsed.

19.3.3.6 Data Rate Control

The CPU can control the data rate by setting the clock period of the LSSbus clock by programming appropriate value in LssClockHighLowDuration.The default setting for the register is 200 (pclk cycles) whichcorresponds to transmission rate of 400 kHz on the LSS bus (the lss_clkis high for LssClockHighLowDuration cycles then low forLssClockHighLowDuration cycles). The lss_clk will always have a 50:50duty cycle. The LssClockHighLowDuration register should not be set tovalues less than 8.

The hold time of lss_data after the falling edge of lss_clk isprogrammable by the LssClocktoDataHold register. This register shouldnot be programmed to less than 2 or greater than theLssClockHighLowDuration value.

19.3.3.7 LSS Master Timing Parameters

The LSS master timing parameters are shown in FIG. 84 and the associatedvalues are shown in Table 105. TABLE 105 LSS master timing parametersParameter Description min nom max unit LSS Master Driving Tp LSS clockperiod divided by 2 8 200 FFFF pclk cycles Tstart_delay Time to startdata edge from rising Tp + LssClocktoDataHold pclk cycles clock edgeTstop_delay Time to stop data edge from rising Tp + LssClocktoDataHoldpclk cycles clock edge Tdata_setup Time from data setup to rising clockTp − 2 − LssClocktoDataHold pclk cycles edge Tdata_hold Time fromfalling clock edge to data LssClocktoDataHold pclk cycles holdTack_setup Time that outgoing (N)Ack is setup Tp − 2 −LssClocktoDataHold pclk cycles before lss_clk rising edge Tack_hold Timethat outgoing (N)Ack is held LssClocktoDataHold pclk cycles afterlss_clk falling edge LSS Master Sampling Tstrobe LSS master strobe pointfor Tp −2 Tp −2 pclk cycles incoming data and (N)Ack values

DRAM Subsystem

20 DRAM Interface Unit (DIU)

20.1 Overview

FIG. 85 shows how the DIU provides the interface between the on-chip 20Mbit embedded DRAM and the rest of SoPEC. In addition to outlining thefunctionality of the DIU, this chapter provides a top-level overview ofthe memory storage and access patterns of SoPEC and the bufferingrequired in the various SoPEC blocks to support those accessrequirements.

The main functionality of the DIU is to arbitrate between requests foraccess to the embedded DRAM and provide read or write accesses to therequesters. The DIU must also implement the initialisation sequence andrefresh logic for the embedded DRAM.

The arbitration scheme uses a fully programmable timeslot mechanism fornon-CPU requesters to meet the bandwidth and latency requirements foreach unit, with unused slots re-allocated to provide best effortaccesses. The CPU is allowed high priority access, giving it minimumlatency, but allowing bounds to be placed on its bandwidth consumption.

The interface between the DIU and the SoPEC requesters is similar to theinterface on PEC1 i.e. separate control, read data and write databusses.

The embedded DRAM is used principally to store:

-   -   CPU program code and data.    -   PEP (re)programming commands.    -   Compressed pages containing contone, bi-level and raw tag data        and header information.    -   Decompressed contone and bi-level data.    -   Dotline store during a print.    -   Print setup information such as tag format structures, dither        matrices and dead nozzle information.        20.2 IBM Cu-11 Embedded DRAM        20.2.1 Single Bank

SoPEC will use the 1.5 V core voltage option in IBM's 0.13 μm classCu-11 process.

The random read/write cycle time and the refresh cycle time is 3 cyclesat 160 MHz [16]. An open page access will complete in 1 cycle if thepage mode select signal is clocked at 320 MHz or 2 cycles if the pagemode select signal is clocked every 160 MHz cycle. The page mode selectsignal will be clocked at 160 MHz in SoPEC in order to simplify timingclosure. The DRAM word size is 256 bits.

Most SoPEC requesters will make single 256 bit DRAM accesses (seeSection 20.4). These accesses will take 3 cycles as they are randomaccesses i.e. they will most likely be to a different memory row thanthe previous access.

The entire 20 Mbit DRAM will be implemented as a single memory bank. InCu-11, the maximum single instance size is 16 Mbit. The first 1 Mbittile of each instance contains an area overhead so the cheapest solutionin terms of area is to have only 2 instances. 16 Mbit and 4 Mbitinstances would together consume an area of 14.63 mm² as would 2 times10 Mbit instances. 4 times 5 Mbit instances would require 17.2 mm².

The instance size will determine the frequency of refresh. Each refreshrequires 3 clock cycles. In Cu-11 each row consists of 8 columns of256-bit words. This means that 10 Mbit requires 5120 rows. A completeDRAM refresh is required every 3.2 ms. Two times 10 Mbit instances wouldrequire a refresh every 100 clock cycles, if the instances are refreshedin parallel.

The SoPEC DRAM will be constructed as two 10 Mbit instances implementedas a single memory bank.

20.3 SoPEC Memory Usage Requirements

The memory usage requirements for the embedded DRAM are shown in Table106. TABLE 106 Memory Usage Requirements Block Size DescriptionCompressed page 2048 Kbytes Compressed data page store for Bi- storelevel and contone data Decompressed 108 Kbyte 13824 lines with scalefactor 6 = 2304 Contone Store pixels, store 12 lines, 4 colors = 108 kB13824 lines with scale factor 5 = 2765 pixels, store 12 lines, 4 colors= 130 kB Spot line store 5.1 Kbyte 13824 dots/line so 3 lines is 5.1 kBTag Format Structure Typically 12 Kbyte (2.5 mm 55 kB in for 384 dotline tags tags @ 800 dpi) 2.5 mm tags (1/10th inch) @ 1600 dpi require160 dot lines = 160/384 ×55 or 23 kB 2.5 mm tags (1/10th inch) @ 800 dpirequire 80/384 ×55 = 12 kB Dither Matrix store 4 Kbytes 64×64 dithermatrix is 4 kB 128×128 dither matrix is 16 kB 256×256 dither matrix is64 kB DNC Dead Nozzle 1.4 Kbytes Delta encoded, (10 bit delta position +6 Table dead nozzle mask) x % Dnozzle 5% dead nozzles requires (10 +6)×692 Dnozzles = 1.4 Kbytes Dot-line store 369.6 Kbytes Assume eachcolor row is separated by 5 dot lines on the print head The dot linestore will be 0+5+10...50+55 = 330 half dot lines + 48 extra half dotlines (4 per dot row) + 60 extra half dot lines estimated to account forprinthead misalignment = 438 half dot lines. 438 half dot lines of 6912dots = 369.6 Kbytes PCU Program code 8 Kbytes 1024 commands of 64 bits =8 kB CPU 64 Kbytes Program code and data TOTAL 2620 Kbytes (12 Kbyte TFSstorage)Note:Total storage is fixed to 2560 Kbytes to align to 20 Mbit DRAM. Thiswill mean that less space than noted in Table may be available for thecompressed band store.20.4 SoPEC Memory Access Patterns

Table 107 shows a summary of the blocks on SoPEC requiring access to theembedded DRAM and their individual memory access patterns. Most blockswill access the DRAM in single 256-bit accesses. All accesses must bepadded to 256-bits except for 64-bit CDU write accesses and CPU writeaccesses. Bits which should not be written are masked using theindividual DRAM bit write inputs or byte write inputs, depending on thefoundry. Using single 256-bit accesses means that the buffering requiredin the SoPEC DRAM requesters will be minimized. TABLE 107 Memory accesspatterns of SoPEC DRAM Requesters DRAM requester Direction Memory accesspattern CPU R Single 256-bit reads. W Single 32-bit, 16-bit or 8-bitwrites. SCB R Single 256-bit reads. W Single 256-bit writes, with byteenables. CDU R Single 256-bit reads of the compressed contone data. WEach CDU access is a write to 4 consecutive DRAM words in the same rowbut only 64 bits of each word are written with the remaining bits writemasked. The access time for this 4 word page mode burst is 3 + 2 + 2 + 2= 9 cycles if the page mode select signal is clocked at 160 MHz. CFU RSingle 256 bit reads. LBD R Single 256 bit reads. SFU R Separate single256 bit reads for previous and current line but sharing the same DIUinterface W Single 256 bit writes. TE(TD) R Single 256 bit reads. Eachread returns 2 times 128 bit tags. TE(TFS) R Single 256 bit reads. TFSis 136 bytes. This means there is unused data in the fifth 256 bit read.A total of 5 reads is required. HCU R Single 256 bit reads. 128 × 128dither matrix requires 4 reads per line with double buffering. 256 × 256dither matrix requires 8 reads at the end of the line with singlebuffering. DNC R Single 256 bit dead nozzle table reads. Each deadnozzle table read contains 16 dead-nozzle tables entries each of 10delta bits plus 6 dead nozzle mask bits. DWU W Single 256 bit writessince enable/disable DRAM access per color plane. LLU R Single 256 bitreads since enable/disable DRAM access per color plane. PCU R Single 256bit reads. Each PCU command is 64 bits so each 256 bit word can contain4 PCU commands. PCU reads from DRAM used for reprogramming PEP should beexecuted with minimum latency. If this occurs between pages then therewill be free bandwidth as most of the other SoPEC Units will not berequesting from DRAM. If this occurs between bands then the LDB, CDU andTE bandwidth will be free. So the PCU should have a high priority toaccess to any spare bandwidth. Refresh Single refresh.20.5 Buffering Required in SoPEC DRAM Requesters

If each DIU access is a single 256-bit access then we need to provide a256-bit double buffer in the DRAM requester. If the DRAM requester has a64-bit interface then this can be implemented as an 8×64-bit FIFO. TABLE108 Buffer sizes in SoPEC DRAM requesters Buffering required in DRAMRequester Direction Access patterns block CPU R Single 256-bit reads.Cache. W Single 32-bit writes but allowing 16-bit or None. byteaddressable writes. SCB R Single 256-bit reads. Double 256-bit buffer. WSingle 256-bit writes, with byte enables. Double 256-bit buffer. CDU RSingle 256-bit reads of the compressed Double 256-bit buffer. contonedata. W Each CDU access is a write to 4 Double half JPEG blockconsecutive DRAM words in the same buffer. row but only 64 bits of eachword are written with the remaining bits write masked. CFU R Single 256bit reads. Triple 256-bit buffer. LBD R Single 256 bit reads. Double256-bit buffer. SFU R Separate single 256 bit reads for Double 256-bitbuffer for previous and current line but sharing each read channel. thesame DIU interface W Single 256 bit writes. Double 256-bit buffer.TE(TD) R Single 256 bit reads. Double 256-bit buffer. TE(TFS) R Single256 bit reads. TFS is 136 bytes. Double line-buffer for This means thereis unused data in the 136 bytes implemented fifth 256 bit read. A totalof 5 reads is in TE. required. HCU R Single 256 bit reads. 128 × 128dither Configurable between matrix requires 4 reads per line with double128 byte buffer double buffering. 256 × 256 dither matrix and requires 8reads at the end of the line single 256 byte buffer. with singlebuffering. DNC R Single 256 bit reads Double 256-bit buffer. Deeperbuffering could be specified to cope with local clusters of deadnozzles. DWU W Single 256 bit writes per enabled Double 256-bit bufferper odd/even color plane. color plane. LLU R Single 256 bit reads perenabled Double 256-bit buffer per odd/even color plane. color plane. PCUR Single 256 bit reads. Each PCU Single 256-bit buffer. command is 64bits so each 256 bit DRAM read can contain 4 PCU commands. Requestedcommand is read from DRAM together with the next 3 contiguous 64-bitswhich are cached to avoid unnecessary DRAM reads. Refresh Singlerefresh. None.

20.6 SoPEC DIU Bandwidth Requirements TABLE 109 SoPEC DIU BandwidthRequirements Number of cycles between Peak each Bandwidth Example256-bit DRAM which must be Average number of access to meet suppliedBandwidth allocated Block Name Direction peak bandwidth (bits/cycle)(bits/cycle) timeslots¹ CPU R W SCB R W 3482 0.734 0.3933 1 CDU R 128(SF = 4), 288 64/n2 (SF = n), 32/10 * n2 (SF = n), 1 (SF = 6) (SF = 6),1:1 1.8 (SF = 6), 0.09 (SF = 6), 2 (SF = 4) compression4 4 (SF = 4) 0.2(SF = 4) (1:1 (10:1 compression) compression)5 W For individual 64/n2(SF = n), 32/n2 (SF = n)7, 2 (SF = 6)8 accesses: 16 1.8 (SF = 6), 0.9(SF = 6), 4 (SF = 4) cycles (SF = 4), 36 4 (SF = 4) 2 (SF = 4) cycles(SF = 6), n2 cycles (SF = n). Will be implemented as a page mode burstof 4 accesses every 64 cycles (SF = 4), 144 (SF = 6), 4 * n2 (SF = n)cycles6 CFU R 32 (SF = 4), 48 (SF = 6)9 32/n (SF = n), 32/n (SF = n), 6(SF = 6) 5.4 (SF = 6), 5.4 (SF = 6), 8 (SF = 4) 8 (SF = 4) 8 (SF = 4)LBD R 256 (1:1 1 (1:1 0.1 (10:1 1 compression)10 compression)compression)11 SFU R 12812 2 2 2 W 25613 1 1 1 TE(TD) R 25214 1.02 1.021 TE(TFS) R 5 reads per line15 0.093 0.093 0 HCU R 4 reads per line for0.074 0.074 0 128 × 128 dither matrix16 DNC R 106 (5% dead- 2.4 (clumpof 0.8 (equally 3 nozzles 10-bit delta dead nozzles) spaced deadencoded)17 nozzles) DWU W 6 writes every 6 6 6 25618 LLU R 8 reads every8 6 8 25619 PCU R 25620 1 1 1 Refresh 10021 2.56 2.56 3 (effective)TOTAL SF = 6: 34.9 SF = 6: 27.5 SF = 6: 36 SF = 4: 41.9 SF = 4: 31.2excluding CPU. excluding CPU excluding CPU SF = 4: 41 excluding CPUNotes:¹The number of allocated timeslots is based on 64 timeslots each of 1bit/cycle but broken down to a granularity of 0.25 bit/cycle. Bandwidthis allocated based on peak bandwidth.2: Wire-speed bandwidth for a 4 wire SCB configuration is 32 Mbits/s foreach wire plus 12 Mbit/s for USB. This is a maximum of 138 Mbit/s. Themaximum effective data rate is 26 Mbits/s for each wire plus 8 Mbit/sfor USB. This is 112 Mbit/s. 112 Mbit/s is 0.734 bits/cycle or 256 bitsevery 348 cycles.3: Wire-speed bandwidth for a 2 wire SCB configuration is 32 Mbits/s foreach wire plus 12 Mbit/s for USB. This is a maximum of 74 Mbit/s. Themaximum effective data rate is 26 Mbits/s for each wire plus 8 Mbit/sfor USB. This is 60 Mbit/s. 60 Mbit/s is 0.393 bits/cycle or 256 bitsevery 650 cycles.4: At 1:1 compression CDU must read a 4 color pixel (32 bits) every SF²cycles.5: At 10:1 average compression CDU must read a 4 color pixel (32 bits)every 10 * SF² cycles.6: 4 color pixel (32 bits) is required, on average, by the CFU every SF²(scale factor) cycles. The time available to write the data is afunction of the size of the buffer in DRAM. 1.5 buffering means 4 colorpixel (32 bits) must be written every SF²/2 (scale factor) cycles.Therefore, at a scale factor of SF, 64 bits are required every SF²cycles. Since 64 valid bits are written per 256-bit write (Figure onpage379 on page Error! Bookmark# not defined.) then the DRAM is accessed every SF² cycles i.e. at SF4an access every 16 cycles, at SF6 an access every 36 cycles. If a pagemode burst of 4 accesses is used then each access takes (3 + 2 + 2 + 2)equals 9 cycles. This means at SF, a set of 4 back-to-back accesses mustoccur every 4 * SF² cycles. This assumes the page mode select signal isclocked at 160 MHz. CDU timeslots therefore take 9 cycles. # For scalefactors lower than 4 double buffering will be used.7: The peak bandwidth is twice the average bandwidth in the case of 1.5buffering.8: Each CDU(W) burst takes 9 cycles instead of 4 cycles for otheraccesses so CDU timeslots are longer.9: 4 color pixel (32 bits) read by CFU every SF cycles. At SF4, 32 bitsis required every 4 cycles or 256 bits every 32 cycles. At SF6, 32bitsevery 6 cycles or 256 bits every 48 cycles.10: At 1:1 compression require 1 bit/cycle or 256 bits every 256 cycles.11: The average bandwidth required at 10:1 compression is 0.1bits/cycle.12: Two separate reads of 1 bit/cycle.13: Write at 1 bit/cycle.14: Each tag can be consumed in at most 126 dot cycles and requires 128bits. This is a maximum rate of 256 bits every 252 cycles.15: 17 × 64 bit reads per line in PEC1 is 5 × 256 bit reads per line inSoPEC. Double-line buffered storage.16: 128 bytes read per line is 4 × 256 bit reads per line. Double-linebuffered storage.17: 5% dead nozzles 10-bit delta encoded stored with 6-bit dead nozzlemask requires 0.8 bits/cycle read access or a 256-bit access every 320cycles. This assumes the dead nozzles are evenly spaced out. In practicedead nozzles are likely to be clumped. Peak bandwidth is estimated as 3times average bandwidth.18: 6 bits/cycle requires 6 × 256 bit writes every 256 cycles.19: 6 bits/160 MHz SoPEC cycle average but will peak at 2 × 6 bits per106 MHz print head cycle or 8 bits/SoPEC cycle. The PHI can equalise theDRAM access rate over the line so that the peak rate equals the averagerate of 6 bits/cycle. The print head is clocked at an effective speed of106 MHz.20: Assume one 256 read per 256 cycles is sufficient i.e. maximumlatency of 256 cycles per access is allowable.21: Refresh must occur every 3.2 ms. Refresh occurs row at a time over5120 rows of 2 parallel 10 Mbit instances. Refresh must occur every 100cycles. Each refresh takes 3 cycles.20.7 DIU BUS Topology

20.7.1 Basic Topology TABLE 110 SoPEC DIU Requesters Read Write OtherCPU CPU Refresh SCB SCB CDU CDU CFU SFU LBD DWU SFU TE(TD) TE(TFS) HCUDNC LLU PCU

Table 110 shows the DIU requesters in SoPEC. There are 12 readrequesters and 5 write requesters in SoPEC as compared with 8 readrequesters and 4 write requesters in PEC1. Refresh is an additionalrequester.

In PEC1, the interface between the DIU and the DIU requesters had thefollowing main features:

-   -   separate control and address signals per DIU requester        multiplexed in the DIU according to the arbitration scheme,    -   separate 64-bit write data bus for each DRAM write requester        multiplexed in the DIU,    -   common 64-bit read bus from the DIU with separate enables to        each DIU read requester.

Timing closure for this bussing scheme was straight-forward in PEC1.This suggests that a similar scheme will also achieve timing closure inSoPEC. SoPEC has 5 more DRAM requesters but it will be in a 0.13 umprocess with more metal layers and SoPEC will run at approximately thesame speed as PEC1.

Using 256-bit busses would match the data width of the embedded DRAM butsuch large busses may result in an increase in size of the DIU and theentire SoPEC chIP. The SoPEC requestors would require double 256-bitwide buffers to match the 256-bit busses. These buffers, which must beimplemented in flip-flops, are less area efficient than 8-deep 64-bitwide register arrays which can be used with 64-bit busses. SoPEC willtherefore use 64-bit data busses. Use of 256-bit busses would howeversimplify the DIU implementation as local buffering of 256-bit DRAM datawould not be required within the DIU.

20.7.1.1 CPU DRAM Access

The CPU is the only DIU requestor for which access latency is critical.All DIU write requesters transfer write data to the DIU using separatepoint-to-point busses. The CPU will use the cpu_dataout[31:0] bus. CPUreads will not be over the shared 64-bit read bus. Instead, CPU readswill use a separate 256-bit read bus.

20.7.2 Making More Efficient Use of DRAM Bandwidth

The embedded DRAM is 256-bits wide. The 4 cycles it takes to transferthe 256-bits over the 64-bit data busses of SoPEC means that effectivelyeach access will be at least 4 cycles long. It takes only 3 cycles toactually do a 256-bit random DRAM access in the case of IBM DRAM.

20.7.2.1 Common Read Bus

If we have a common read data bus, as in PEC1, then if we are doing backto back read accesses the next DRAM read cannot start until the readdata bus is free. So each DRAM read access can occur only every 4cycles. This is shown in FIG. 86 with the actual DRAM access taking 3cycles leaving 1 unused cycle per access.

20.7.2.2 Interleaving CPU and Non-CPU Read Accesses

The CPU has a separate 256-bit read bus. All other read accesses are256-bit accesses are over a shared 64-bit read bus. Interleaving CPU andnon-CPU read accesses means the effective duration of an interleavedaccess timeslot is the DRAM access time (3 cycles) rather than 4 cycles.

FIG. 87 shows interleaved CPU and non-CPU read accesses.

20.7.2.3 Interleaving Read and Write Accesses

Having separate write data busses means write accesses can beinterleaved with each other and with read accesses. So now the effectiveduration of an interleaved access timeslot is the DRAM access time (3cycles) rather than 4 cycles. Interleaving is achieved by ordering theDIU arbitration slot allocation appropriately.

FIG. 88 shows interleaved read and write accesses. FIG. 89 showsinterleaved write accesses.

256-bit write data takes 4 cycles to transmit over 64-bit busses so a256-bit buffer is required in the DIU to gather the write data from thewrite requester. The exception is CPU write data which is transferred ina single cycle.

FIG. 89 shows multiple write accesses being interleaved to obtain 3cycle DRAM access. Since two write accesses can overlap two sets of256-bit write buffers and multiplexors to connect two write requestorssimultaneously to the DIU are required.

Write requestors only require approximately one third of the totalnon-CPU bandwidth. This means that a rule can be introduced such thatnon-CPU write requestors are not allocated adjacent timeslots. Thismeans that a single 256-bit write buffer and multiplexor to connect theone write requestor at a time to the DIU is all that is required.

Note that if the rule prohibiting back-to-back non-CPU writes is notadhered to, then the second write slot of any attempted such pair willbe disregarded and re-allocated under the unused read round-robinscheme.

20.7.3 Bus Widths Summary TABLE 111 SoPEC DIU Requesters Data Bus WidthRead Bus access width Write Bus access width CPU 256 (separate) CPU 32SCB  64 (shared) SCB 64 CDU  64 (shared) CDU 64 CFU  64 (shared) SFU 64LBD  64 (shared) DWU 64 SFU  64 (shared) TE(TD)  64 (shared) TE(TFS)  64(shared) HCU  64 (shared) DNC  64 (shared) LLU  64 (shared) PCU  64(shared)20.7.4 Conclusions

Timeslots should be programmed to maximise interleaving of shared readbus accesses with other accesses for 3 cycle DRAM access. Theinterleaving is achieved by ordering the DIU arbitration slot allocationappropriately. CPU arbitration has been designed to maximiseinterleaving with non-CPU requesters

20.8 SoPEC DRAM Addressing Scheme

The embedded DRAM is composed of 256-bit words. However theCPU-subsystem may need to write individual bytes of DRAM. Therefore itwas decided to make the DIU byte addressable. 22 bits are required tobyte address 20 Mbit of DRAM.

Most blocks read or write 256 bit words of DRAM. Therefore only the top17 bits i.e. bits 21 to 5 are required to address 256-bit word alignedlocations.

The exceptions are

-   -   CDU which can write 64-bits so only the top 19 address bits i.e.        bits 21-3 are required.    -   CPU writes can be 8, 16 or 32-bits. The cpu_diu_wmask[1:0] pins        indicate whether to write 8, 16 or 32 bits.

All DIU accesses must be within the same 256-bit aligned DRAM word. Theexception is the CDU write access which is a write of 64-bits to each of4 contiguous 256-bit DRAM words.

20.8.1 Write Address Constaints Specific to the CDU

Note the following conditions which apply to the CDU write address, dueto the four masked page-mode writes which occur whenever a CDU writeslot is arbitrated.

-   -   The CDU address presented to the DIU is cdu_diu_wadr[21:3].    -   Bits [4:3] indicate which 64-bit segment out of 256 bits should        be written in 4 successive masked page-mode writes.    -   Each 10-Mbit DRAM macro has an input address port of width        [15:0]. Of these bits, [2:0] are the “page address”. Page-mode        writes, where you just vary these LSBs (i.e. the “page” or        column address), but keep the rest of the address constant, are        faster than random writes. This is taken advantage of for CDU        writes.    -   To guarantee against trying to span a page boundary, the DIU        treats “cdu_diu_wadr[6:5]” as being fixed at “00”.    -   From cdu_diu_wadr[21:3], a initial address of        cdu_diu_wadr[21:7], concatenated with “00”, is used as the        starting location for the first CDU write. This address is then        auto-incremented a further three times.        20.9 DIU Protocols

The DIU protocols are

-   -   Pipelined i.e. the following transaction is initiated while the        previous transfer is in progress.    -   Split transaction i.e. the transaction is split into independent        address and data transfers.        20.9.1 Read Protocol Except CPU

The SoPEC read requestors, except for the CPU, perform single 256-bitread accesses with the read data being transferred from the DIU in 4consecutive cycles over a shared 64-bit read bus, diu_data[63:0]. Theread address <unit>_diu_radr[21:5] is 256-bit aligned.

The read protocol is:

-   -   <unit>_diu_rreq is asserted along with a valid        <unit>_diu_radr[21:5].    -   The DIU acknowledges the request with diu_<unit>_rack. The        request should be deasserted. The minimum number of cycles        between <unit>_diu_rreq being asserted and the DIU generating an        diu_<unit>_rack strobe is 2 cycles (1 cycle to register the        request, 1 cycle to perform the arbitration—see Section        20.14.10).    -   The read data is returned on diu_data[63:0] and its validity is        indicated by diu_<unit>_rvalid. The overall 256 bits of data are        transferred over four cycles in the order:        [63:0]->[127:64]->[191:128]->[255:192].    -   When four diu_<unit>_rvalid pulses have been received then if        there is a further request <unit>_diu_rreq should be asserted        again. diu_<unit>_rvalid will be always be asserted by the DIU        for four consecutive cycles. There is a fixed gap of 2 cycles        between diu_<unit>_rack and the first diu_<unit>_rvalid pulse.        For more detail on the timing of such reads and the implications        for back-to-back sequences, see Section 20.14.10.        20.9.2 Read Protocol for CPU

The CPU performs single 256-bit read accesses with the read data beingtransferred from the DIU over a dedicated 256-bit read bus for DRAMdata, dram_cpu_data[255.0]. The read address cpu_adr[21:5] is 256-bitaligned.

The CPU DIU read protocol is:

-   -   cpu_diu_rreq is asserted along with a valid cpu_adr[21:5].    -   The DIU acknowledges the request with diu_cpu_rack. The request        should be deasserted. The minimum number of cycles between        cpu_diu_rreq being asserted and the DIU generating a        cpu_diu_rack strobe is 1 cycle (1 cycle to perform the        arbitration—see Section 20.14.10).    -   The read data is returned on dram_cpu_data[255:0] and its        validity is indicated by diu_cpu_rvalid.    -   When the diu_cpu_rvalid pulse has been received then if there is        a further request cpu_diu_rreq should be asserted again. The        diu_cpu_rvalid pulse with a gap of 1 cycle after rack (1 cycle        for the read data to be returned from the DRAM—see Section        20.14.10).        20.9.3 Write Protocol Except CPU and CDU

The SoPEC write requestors, except for the CPU and CDU, perform single256-bit write accesses with the write data being transferred to the DIUin 4 consecutive cycles over dedicated point-to-point 64-bit write databusses. The write address <unit>_diu_wadr[21:5] is 256-bit aligned.

The write protocol is:

-   -   <unit>_diu_wreq is asserted along with a valid        <unit>_diu_wadr[21:5].    -   The DIU acknowledges the request with diu_<unit>_wack. The        request should be deasserted. The minimum number of cycles        between <unit>_diu_wreq being asserted and the DIU generating an        diu_<unit>_wack strobe is 2 cycles (1 cycle to register the        request, 1 cycle to perform the arbitration—see Section        20.14.10).    -   In the clock cycles following diu_<unit>_wack the SoPEC Unit        outputs the 15<unit>_diu_data[63:0], asserting        <unit>_diu_wvalid. The first <unit>_diu_wvalid pulse can occur        the clock cycle after diu_<unit>_wack. <unit>_diu_wvalid remains        asserted for the following 3 clock cycles. This allows for        reading from an SRAM where new data is available in the clock        cycle after the address has changed e.g. the address for the        second 64-bits of write data is available the cycle after        diu_<unit>_wack meaning the second 64-bits of write data is a        further cycle later. The overall 256 bits of data is transferred        over four cycles in the order:        [63:0]->[127:64]->[191:128]->[255:192].    -   Note that for SCB writes, each 64-bit quarter-word has an 8-bit        byte enable mask associated with it. A different mask is used        with each quarter-word. The 4 mask values are transferred along        with their associated data, as shown in FIG. 92.    -   If four consecutive <unit>_diu_wvalid pulses are not provided by        the requester, then the arbitration logic will disregard the        write and re-allocate the slot under the unused read round-robin        scheme.

Once all the write data has been output then if there is a furtherrequest <unit>_diu_wreq should be asserted again.

20.9.4 CPU Write Protocol

The CPU performs single 128-bit writes to the DIU on a dedicated writebus, cpu_diu_wdata[127:0]. There is an accompanying write mask,cpu_diu_wmask[15:0], consisting of 16 byte enables and the CPU alsosupplies a 128-bit aligned write address on cpu_diu_wadr[21:4]. Notethat writes are posted by the CPU to the DIU and stored in a 1-deepbuffer. When the DAU subsequently arbitrates in favour of the CPU, thecontents of the buffer are written to DRAM.

The CPU write protocol, illustrated in FIG. 93, is as follows:—

-   -   The DIU signals to the CPU via diu_cpu_write_rdy that its write        buffer is empty and that the CPU may post a write whenever it        wishes.    -   The CPU asserts cpu_diu_wdatavalid to enable a write into the        buffer and to confirm the validity of the write address, data        and mask.    -   The DIU de-asserts diu_cpu_write_rdy in the following cycle to        indicate that its buffer is full and that the posted write is        pending execution.    -   When the CPU is next awarded a DRAM access by the DAU, the        buffer's contents are written to memory. The DIU re-asserts        diu_cpu_write_rdy once the write data has been captured by DRAM,        namely in the “MSN1” DCU state.    -   The CPU can then, if it wishes, asynchronously use the new value        of .diu_cpu_write_rdy to enable a new posted write in the same        “MSN1” cycle.        20.9.5 CDU Write Protocol

The CDU performs four 64-bit word writes to 4 contiguous 256-bit DRAMaddresses with the first address specified by cdu_diu_wadr[21:3]. Thewrite address cdu_diu_wadr[21:5] is 256-bit aligned with bitscdu_diu_wadr[4:3] allowing the 64-bit word to be selected.

The write protocol is:

-   -   cdu_diu_wdata is asserted along with a valid cdu_diu_wadr[21:3].    -   The DIU acknowledges the request with diu_cdu_wack. The request        should be deasserted. The minimum number of cycles between        cdu_diu_wreq being asserted and the DIU generating an        diu_cdu_wack strobe is 2 cycles (1 cycle to register the        request, 1 cycle to perform the arbitration—see Section        20.14.10).    -   In the clock cycles following diu_cdu_wack the CDU outputs the        cdu_diu_data[63:0], together with asserted cdu_diu_wvalid. The        first cdu_diu_wvalid pulse can occur the clock cycle after        diu_cdu_wack. cdu_diu_wvalid remains asserted for the following        3 clock cycles. This allows for reading from an SRAM where new        data is available in the clock cycle after the address has        changed e.g. the address for the second 64-bits of write data is        available the cycle after diu_cdu_wack meaning the second        64-bits of write data is a further cycle later. Data is        transferred over the 4-cycle window in an order, such that each        successive 64 bits will be written to a monotonically increasing        (by 1 location) 256-bit DRAM word.    -   If four consecutive cdu_diu_wvalid pulses are not provided with        the data, then the arbitration logic will disregard the write        and re-allocate the slot under the unused read round-robin        scheme.    -   Once all the write data has been output then if there is a        further request cdu_diu_wreq should be asserted again.        20.10 DIU Arbitration Mechanism

The DIU will arbitrate access to the embedded DRAM. The arbitrationscheme is outlined in the next sections.

20.10.1 Timeslot Based Arbitration Scheme

Table summarised the bandwidth requirements of the SoPEC requestors toDRAM. If we allocate the DIU requestors in terms of peak bandwidth thenwe require 35.25 bits/cycle (at SF=6) and 40.75 bits/cycle (at SF=4) forall the requestors except the CPU.

A timeslot scheme is defined with 64 main timeslots. The number of usedmain timeslots is programmable between 1 and 64.

Since DRAM read requesters, except for the CPU, are connected to the DIUvia a 64-bit data bus each 256-bit DRAM access requires 4 pclk cycles totransfer the read data over the shared read bus. The timeslot rotationperiod for 64 timeslots each of 4 pclk cycles is 256 pclk cycles or 1.6μs, assuming pclk is 160 MHz. Each timeslot represents a 256-bit accessevery 256 pclk cycles or 1 bit/cycle. This is the granularity of themajority of DIU requesters bandwidth requirements in Table.

The SoPEC DIU requesters can be represented using 4 bits (Table n page288 on page 268). Using 64 timeslots means that to allocate eachtimeslot to a requester, a total of 64×5-bit configuration registers arerequired for the 64 main timeslots.

Timeslot based arbitration works by having a pointer point to thecurrent timeslot. When re-arbitration is signaled the arbitration winneris the current timeslot and the pointer advances to the next timeslot.Each timeslot denotes a single access. The duration of the timeslotdepends on the access.

Note that advancement through the timeslot rotation is dependent on anenable bit, RotationSync, being set. The consequences of clearing andsetting this bit are described in section 20.14.12.2.1 on page 295.

If the SoPEC Unit assigned to the current timeslot is not requestingthen the unused timeslot arbitration mechanism outlined in Section20.10.6 is used to select the arbitration winner.

Note that there is always an arbitration winner for every slot. This isbecause the unused read re-allocation scheme includes refresh in itsround-robin protocol. If all other blocks are not requesting, an earlyrefresh will act as fall-back for the slot.

20.10.2 Separate Read and Write Arbitration Windows

For write accesses, except the CPU, 256-bits of write data aretransferred from the SoPEC DIU write requestors over 64-bit write bussesin 4 clock cycles. This write data transfer latency means that writesaccesses, except for CPU writes and also the CDU, must be arbitrated 4cycles in advance. (The CDU is an exception because CDU writes can startonce the first 64-bits of write data have been transferred since each64-bits is associated with a write to a different 256-bit word).

Since write arbitration must occur 4 cycles in advance, and the minimumduration of a timeslot duration is 3 cycles, the arbitration rules mustbe modified to initiate write accesses in advance. Accordingly, there isa write timeslot lookahead pointer shown in FIG. 96 two timeslots inadvance of the current timeslot pointer.

The following examples illustrate separate read and write timeslotarbitration with no adjacent write timeslots. (Recall rule on adjacentwrite timeslots introduced in Section 20.7.2.3 on page 238.)

In FIG. 97 writes are arbitrated two timeslots in advance. Reads arearbitrated in the same timeslot as they are issued. Writes can bearbitrated in the same timeslot as a read. During arbitration thecommand address of the arbitrated SoPEC Unit is captured.

Other examples are shown in FIG. 98 and FIG. 99. The actual timeslotorder is always the same as the programmed timeslot order i.e. out oforder accesses do not occur and data coherency is never an issue.

Each write must always incur a latency of two timeslots.

Startup latency may vary depending on the position of the first writetimeslot. This startup latency is not important.

Table 112 shows the 4 scenarIOs depending on whether the currenttimeslot and write timeslot lookahead pointers point to read or writeaccesses. TABLE 112 Arbitration with separate windows for read and writeaccesses write timeslot lookahead current timeslot pointer pointeractions Read write Initiate DRAM read, Initiate write arbitration Read1read2 Initiate DRAM read1. Write1 write2 Initiate write2 arbitration.Execute DRAM write1. Write read Execute DRAM write.

If the current timeslot pointer points to a read access then this willbe initiated immediately. If the write timeslot lookahead pointer pointsto a write access then this access is arbitrated immediately, orimmediately after the read access associated with the current timeslotpointer is initiated.

When a write access is arbitrated the DIU will capture the writeaddress. When the current timeslot pointer advances to the writetimeslot then the actual DRAM access will be initiated. Writes willtherefore be arbitrated 2 timeslots in advance of the DRAM writeoccurring.

At initialisation, the write lookahead pointer points to the firsttimeslot. The current timeslot pointer is invalid until the writelookahead pointer advances to the third timeslot when the currenttimeslot pointer will point to the first timeslot. Then both pointersadvance in tandem.

CPU write accesses are excepted from the lookahead mechanism.

If the selected SoPEC Unit is not requesting then there will be separateread and write selection for unused timeslots. This is described inSection 20.10.6.

20.10.3 Arbitration of CPU Accesses

What distinguishes the CPU from other SoPEC requesters, is that the CPUrequires minimum latency DRAM access i.e. preferably the CPU should getthe next available timeslot whenever it requests.

The minimum CPU read access latency is estimated in Table 113. This isthe time between the CPU making a request to the DIU and receiving theread data back from the DIU. TABLE 113 Estimated CPU read access latencyignoring caching CPU read access latency Duration CPU cache miss 1 cycleCPU MMU logic issues request and 1 cycle DIU arbitration completesTransfer the read address to the DRAM 1 cycle DRAM read latency 1 cycleRegister the read data in CPU bridge 1 cycle Register the read data inCPU 1 cycle CPU cache miss 1 cycle CPU MMU logic issues request and 1cycle DIU arbitration completes TOTAL gap between requests 6 cycles

If the CPU, as is likely, requests DRAM access again immediately afterreceiving data from the DIU then the CPU could access every secondtimeslot if the access latency is 6 cycles. This assumes thatinterleaving is employed so that timeslots last 3 cycles. If the CPUaccess latency were 7 cycles, then the CPU would only be able to accessevery third timeslot.

If a cache hit occurs the CPU does not require DRAM access. For its nextDIU access it will have to wait for its next assigned DIU slot. Cachehits therefore will reduce the number of DRAM accesses but not speed upany of those accesses.

To avoid the CPU having to wait for its next timeslot it is desirable tohave a mechanism for ensuring that the CPU always gets the nextavailable timeslot without incurring any latency on the non-CPUtimeslots.

This can be done by defining each timeslot as consisting of a CPU accesspreceding a non-CPU access. Each timeslot will last 6 cycles i.e. a CPUaccess of 3 cycles and a non-CPU access of 3 cycles. This is exactly theinterleaving behaviour outlined in Section 20.7.2.2. If the CPU does notrequire an access, the timeslot will take 3 or 4 and the timeslotrotation will go faster. A summary is given in Table 114. TABLE 114Timeslot access times. Access Duration Explanation CPU access + 3 + 3 =6 cycles Interleaved access non-CPU access non-CPU access 4 cyclesAccess and preceding access both to shared read bus non-CPU access 3cycles Access and preceding access not both to shared read bus CDU writeaccess 3+2+2+2 = 9 cycles Page mode select signal is clocked at 160 MHz

CDU write accesses require 9 cycles. CDU write accesses preceded by aCPU access require 12 cycles. CDU timeslots therefore take longer thanall other DIU requestors timeslots.

With a 256 cycle rotation there can be 42 accesses of 6 cycles.

For low scale factor applications, it is desirable to have moretimeslots available in the same 256 5 cycle rotation. So two counters of4-bits each are defined allowing the CPU to get a maximum of(CPUPreAccessTimeslots+1) pre-accesses for every (CPUTotalTimeslots+1)main slots. A timeslot counter starts at CPUTotalTimeslots anddecrements every timeslot, while another counter starts atCPUPreAccessTimeslots and decrements every timeslot in which the CPUuses its access. When the CPU pre-access counter goes to zero beforeCPUTotalTimeslots, no further CPU accesses are allowed. When theCPUTotalTimeslots counter reaches zero both counters are reset to theirrespective initial values.

The CPU is not included in the list of SoPEC DIU requesters, Table, forthe main timeslot allocations. The CPU cannot therefore be allocatedmain timeslots. It relies on pre-accesses in advance of such slots asthe sole method for DRAM transfers.

CPU access to DRAM can never be fully disabled, since to do so wouldrender SoPEC inoperable. Therefore the CPUPreAccessTimeslots andCPUTotalTimeslots register values are interpreted as follows: In eachsucceeding window of (CPUTotalTimeslots+1) slots, the maximum quota ofCPU pre-accesses allowed is (CPUPreAccessTimeslots+1). The “+1”implementations mean that the CPU quota cannot be made zero.

The various modes of operation are summarised in Table 115 with anominal rotation period of 256 cycles. TABLE 115 CPU timeslot allocationmodes with nominal rotation period of 256 cycles Nominal Timeslot Numberof Access Type duration timeslots Notes CPU Pre-access 6 cycles   42timeslots Each access is CPU + non-CPU. i.e. If CPU does not use atimeslot then CPUPreAccessTimeslots = CPUTotalTimeslots rotation isfaster. Fractional CPU Pre- 4 or 6 42-64 timeslots Each CPU + non-CPUaccess access cycles requires a 6 cycle i.e. timeslot.CPUPreAccessTimeslots < CPUTotalTimeslots Individual non-CPU timeslotstake 4 cycles if current access and preceding access are both to sharedread bus. Individual non-CPU timeslots take 3 cycles if current accessand preceding access are not both to shared read bus.20.10.4 CDU Accesses

As indicated in Section 20.10.3, CDU write accesses require 9 cycles.CDU write accesses preceded by a CPU access require 12 cycles. CDUtimeslots therefore take longer than all other DIU requestors timeslots.This means that when a write timeslot is unused it cannot bere-allocated to a CDU write as CDU accesses take 9 cycles. The writeaccesses which the CDU write could otherwise replace require only 3 or 4cycles.

Unused CDU write accesses can be replaced by any other write accessaccording to 20.10.6.1 Unused write timeslots allocation on page 247.

20.10.5 Refresh Controller

Refresh is not included in the list of SoPEC DIU requesters, Table, forthe main timeslot allocations. Timeslots cannot therefore be allocatedto refresh.

The DRAM must be refreshed every 3.2 ms. Refresh occurs row at a timeover 5120 rows of 2 parallel 10 Mbit instances. A refresh operation musttherefore occur every 100 cycles. The refresh_period register has adefault value of 99. Each refresh takes 3 cycles.

A refresh counter will count down the number of cycles between eachrefresh. When the down-counter reaches 0, the refresh controller willissue a refresh request and the down-counter is reloaded with the valuein refresh_period and the count-down resumes immediately. Allocation ofmain slots must take into account that a refresh is required at leastonce every 100 cycles. Refresh is included in the unused read and writetimeslot allocation. If unused timeslot allocation results in refreshoccurring early by N cycles, then the refresh counter will have counteddown to N. In this case, the refresh counter is reset to refresh_periodand the count-down recommences. Refresh can be preceded by a CPU accessin the same way as any other access. This is controlled by theCPUPreAccessTimeslots and CPUTotalTimeslots configuration registers.Refresh will therefore not affect CPU performance. A sequence ofaccesses including refresh might therefore be CPU, refresh, CPU, actualtimeslot.

20.10.6 Allocating Unused Timeslots

Unused slots are re-allocated separately depending on whether the unusedaccess was a read access or a write access. This is best-effort traffic.Only unused non-CPU accesses are re-allocated.

20.10.6.1 Unused Write Timeslots Allocation

Unused write timeslots are re-allocated according to a fixed priorityorder shown in Table 116. TABLE 116 Unused write timeslot priority orderPriority Name Order SCB(W) 1 SFU(W) 2 DWU 3 Unused read timeslotallocation 4

CDU write accesses cannot be included in the unused timeslot allocationfor write as CDU accesses take 9 cycles. The write accesses which theCDU write could otherwise replace require only 3 or 4 cycles.

Unused write timeslot allocation occurs two timeslots in advance asnoted in Section 20.10.2. If the units at priorities 1-3 are notrequesting then the timeslot is re-allocated according to the unusedread timeslot allocation scheme described in Section 20.10.6.2. However,the unused read timeslot allocation will occur when the current timeslotpointer of FIG. 96 reaches the timeslot i.e. it will not occur inadvance.

20.10.6.2 Unused Read Timeslots Allocation

Unused read timeslots are re-allocated according to a two levelround-robin scheme. The SoPEC Units included in read timeslotre-allocation is shown in Table 117. TABLE 117 Unused read timeslotallocation Name SCB(R) CDU(R) CFU LBD SFU(R) TE(TD) TE(TFS) HCU DNC LLUPCU CPU Refresh

Each SoPEC requestor has an associated bit, ReadRoundRobinLevel, whichindicates whether it is in level 1 or level 2 round-robin. TABLE 118Read round-robin level selection Level Action ReadRoundRobinLevel = 0Level 1 ReadRoundRobinLevel = 1 Level 2

A pointer points to the most recent winner on each of the round-robinlevels. Re-allocation is carried out by traversing level 1 requesters,starting with the one immediately succeeding the last level 1 winner. Ifa requesting unit is found, then it wins arbitration and the level 1pointer is shifted to its position. If no level 1 unit wants the slot,then level 2 is similarly examined and its pointer adjusted.

Since refresh occupies a (shared) position on one of the two levels andcontinually requests access, there will always be some round-robinwinner for any unused slot.

20.10.6.2.1 Shared CPU/Refresh Round-Robin Position

Note that the CPU can conditionally be allowed to take part in theunused read round-robin scheme. Its participation is controlled via theconfiguration bit EnableCPURoundRobin. When this bit is set, the CPU andrefresh share a joint position in the round-robin order, shown in Table.When cleared, the position is occupied by refresh alone.

If the shared position is next in line to be awarded an unused non-CPUread/write slot, then the CPU will have first option on the slot. Onlyif the CPU doesn't want the access, will it be granted to refresh. Ifthe CPU is excluded from the round robin, then any awards to theposition benefit refresh.

20.11 Guidelines for Programming the DIU

Some guidelines for programming the DIU arbitration scheme are given inthis section together with an example.

20.11.1 Circuit Latency

Circuit latency is a fixed service delay which is incurred, as and fromthe acceptance by the DIU arbitration logic of a block's pendingread/write request. It is due to the processing time of the request,readying the data, plus the DRAM access time. Latencies differ for readand write requests. See Tables 79 and 80 for respective breakdowns.

If a requesting block is currently stalled, then the longest time itwill have to wait between issuing a new request for data and actuallyreceiving it would be its timeslot period, plus the circuit latencyoverhead, along with any intervening non-standard slot durations, suchas refresh and CDU(W). In any case, a stalled block will always incurthis latency as an additional overhead, when coming out of a stall.

In the case where a block starts up or unstalls, it will startprocessing newly-received data at a time beyond its serviced timeslotequivalent to the circuit latency. If the block's timeslots are evenlyspaced apart in time to match its processing rate, (in the hope ofminimising stalls,) then the earliest that the block could restall, ifnot re-serviced by the DIU, would be the same latency delay beyond itsnext timeslot occurrence. Put another way, the latency incurred atstart-up pushes the potential DIU-induced stall point out by the samefixed delta beyond each successive timeslot allocated to the block. Thisassumes that a block re-requests access well in advance of its upcomingtimeslots. Thus, for a given stall-free run of operation, the circuitlatency overhead is only incurred inititially when unstalling.

While a block can be stalled as a result of how quickly the DIU servicesits DRAM requests, it is also prone to stalls caused by its upstream ordownstream neighbours being able to supply or consume data which istransferred between the blocks directly, (as opposed to via the DIU).Such neighbour-induced stalls, often occurring at events like end ofline, will have the effect that a block's DIU read buffer will tend tofill, as the block stops processing read data. Its DIU write buffer willalso tend to fill, unable to despatch to DRAM until the downstream blockfrees up shared-access DRAM locations. This scenario is beneficial, inthat when a block unstalls as a result of its neighbour releasing it,then that block's read/write DIU buffers will have a fill state lesslikely to stall it a second time, as a result of DIU service delays.

A block's slots should be scheduled with a service guarantee in mind.This is dictated by the block's processing rate and hence, requiredaccess to the DRAM. The rate is expressed in terms of bits per cycleacross a processing window, which is typically (though not always) 256cycles. Slots should be evenly interspersed in this window (or“rotation”) so that the DIU can fulfill the block's service needs.

The following ground rules apply in calculating the distribution ofslots for a given non-CPU block:—

-   -   The block can, at maximum, suffer a stall once in the rotation,        (i.e. unstall and restall) and hence incur the circuit latency        described above.

This rule is, by definition, always fulfilled by those blocks which havea service requirement of only

-   -   1 bit/cycle (equivalent to 1 slot/rotation) or fewer. It can be        shown that the rule is also satisfied by those blocks requiring        more than 1 bit/cycle. See Section 20.12.1 Slot Distributions        and Stall Calculations for Individual Blocks, on page 255.    -   Within the rotation, certain slots will be unavailable, due to        their being used for refresh. (See Section 20.11.2 Refresh        latencies)    -   In programming the rotation, account must be taken of the fact        that any CDU(W) accesses will consume an extra 6 cycles/access,        over and above the norm, in CPU pre-access mode, or 5        cycles/access without pre-access.    -   The total delay overhead due to latency, refreshes and CDU(W)        can be factored into the service guarantee for all blocks in the        rotation by deleting once, (i.e. reducing the rotation window,)        that number of slots which equates to the cumulative duration of        these various anomalies.    -   The use of lower scale factors will imply a more frequent demand        for slots by non-CPU blocks. The percentage of slots in the        overall rotation which can therefore be designated as CPU        pre-access ones should be calculated last, based on what can be        accommodated in the light of the non-CPU slot need.

Read latency is summarised below in Table 119. TABLE 119 Read latencyNon-CPU read access latency Duration non-CPU read requestor internally 1cycle generates DIU request register the non-CPU read request 1 cyclecomplete the arbitration of the request 1 cycle transfer the readaddress to the DRAM 1 cycle DRAM read latency 1 cycle register the DRAMread data in DIU 1 cycle register the 1st 64-bits of read data in 1cycle requester register the 2nd 64-bits of read data in 1 cyclerequester register the 3rd 64-bits of read data in 1 cycle requesterregister the 4th 64-bits of read data in 1 cycle requester TOTAL 10cycles

Write latency is summarised in Table 120. TABLE 120 Write latencyNon-CPU write access latency Duration non-CPU write requestor internallygenerates DIU request 1 cycle register the non-CPU write request 1 cyclecomplete the arbitration of the request 1 cycle transfer the acknowledgeto the write requester 1 cycle transfer the 1st 64 bits of write data tothe DIU 1 cycle transfer the 2nd 64 bits of write data to the DIU 1cycle transfer the 3rd 64 bits of write data to the DIU 1 cycle transferthe 4th 64 bits of write data to the DIU 1 cycle Write to DRAM withlocally registered write data 1 cycle TOTAL 9 cycles

Timeslots removed to allow for read latency will also cover writelatency, since the former is the larger of the two.

20.11.2 Refresh Latencies

The number of allocated timeslots for each requester needs to take intoaccount that a refresh must occur every 100 cycles. This can be achievedby deleting timeslots from the rotation since the number of timeslots ismade programmable.

Refresh is preceded by a CPU access in the same way as any other access.This is controlled by the CPUPreAccessTimeslots and CPUTotalTimeslotsconfiguration registers. Refresh will therefore not affect CPUperformance.

As an example, in CPU pre-access mode each timeslot will last 6 cycles.If the timeslot rotation has 50 timeslots then the rotation will last300 cycles. The refresh controller will trigger a refresh every 100cycles. Up to 47 timeslots can be allocated to the rotation ignoringrefresh. Three timeslots deleted from the 50 timeslot rotation willallow for the latency of a refresh every 100 cycles.

20.11.3 Ensuring Sufficient DNC and PCU Access

PCU command reads from DRAM are exceptional events and should completein as short a time as possible. Similarly, we must ensure there issufficient free bandwidth for DNC accesses e.g. when clusters of deadnozzles occur. In Table DNC is allocated 3 times average bandwidth. PCUand DNC can also be allocated to the level 1 round-robin allocation forunused timeslots so that unused timeslot bandwidth is preferentiallyavailable to them.

20.11.4 Basing Timeslot Allocation on Peak Bandwidths

Since the embedded DRAM provides sufficient bandwidth to use 1:1compression rates for the CDU and LBD, it is possible to simplify themain timeslot allocation by basing the allocation on peak bandwidths. Ascombined bi-level and tag bandwidth at 1:1 scaling is only 5 bits/cycle,we will usually only consider the contone scale factor as the variablein determining timeslot allocations.

If slot allocation is based on peak bandwidth requirements then DRAMaccess will be guaranteed to all SoPEC requesters. If we do not allocateslots for peak bandwidth requirements then we can also allow for thepeaks deterministically by adding some cycles to the print line time.

20.11.5 Adjacent Timeslot Restrictions

20.11.5.1 Non-CPU Write Adjacent Timeslot Restrictions

Non-CPU write requesters should not be assigned adjacent timeslots asdescribed in Section 20.7.2.3. This is because adjacent timeslotsassigned to non-CPU requestors would require two sets of 256-bit writebuffers and multiplexors to connect two write requestors simultaneouslyto the DIU. Only one 256-bit write buffer and multiplexor isimplemented. Recall from section 20.7.2.3 on page 238 that if adjacentnon-CPU writes are attempted, that the second write of any such pairwill be disregarded and re-allocated under the unused read scheme.

20.11.5.2 Same DIU Requestor Adjacent Timeslot Restrictions

All DIU requesters have state-machines which request and transfer theread or write data before requesting again. From FIG. 90 read requestshave a minimum separation of 9 cycles. From FIG. 92 write requests havea minimum separation of 7 cycles. Therefore adjacent timeslots shouldnot be assigned to a particular DIU requester because the requester willnot be able to make use of all these slots.

In the case that a CPU access precedes a non-CPU access timeslots last 6cycles so write and read requesters can only make use of every secondtimeslot. In the case that timeslots are not preceded by CPU accessestimeslots last 4 cycles so the same write requester can use every secondtimeslot but the same read requestor can use only every third timeslot.Some DIU requestors may introduce additional pipeline delays before theycan request again. Therefore timeslots should be separated by more thanthe minimum to allow a margin.

20.11.6 Line Margin

The SFU must output 1 bit/cycle to the HCU. Since HCUNumDots may not bea multiple of 256 bits the last 256-bit DRAM word on the line cancontain extra zeros. In this case, the SFU may not be able to provide 1bit/cycle to the HCU. This could lead to a stall by the SFU. This stallcould then propagate if the margins being used by the HCU are notsufficient to hide it. The maximum stall can be estimated by thecalculation: DRAM service period—X scale factor * dots used from lastDRAM read for HCU line.

Similarly, if the line length is not a multiple of 256-bits then e.g.the LLU could read data from DRAM which contains padded zeros. Thiscould lead to a stall. This stall could then propagate if the pagemargins cannot hide it.

A single addition of 256 cycles to the line time will suffice for allDIU requesters to mask these stalls.

20.12 Example Outline DIU Programming TABLE 121 Timeslot allocationbased on peak bandwidth Peak Bandwidth which must be Block suppliedMainTimeslots Name Direction (bits/cycle) allocated SCB R W 0.734⁷ 1 CDUR 0.9 (SF = 6), 1 (SF = 6) 2 (SF = 4) 2 (SF = 4) W 1.8 (SF = 6),⁸ 2 (SF= 6) 4 (SF = 4) 4 (SF = 4) CFU R 5.4 (SF = 6), 6 (SF = 6) 8 (SF = 4) 8(SF = 4) LBD R 1 1 SFU R 2 2 W 1 1 TE(TD) R 1.02 1 TE(TFS) R 0.093 0 HCUR 0.074 0 DNC R 2.4 3 DWU W 6 6 LLU R 8 8 PCU R 1 1 TOTAL 33 (SF = 6) 38 (SF = 4) ⁷The SCB figure of 0.734 bits/cycle applies to multi-SoPEC systems. Forsingle-SoPEC systems, the figure is 0.050 bits/cycle.⁸Bandwidth for CDU(W) is peak value. Because of 1.5 buffering in DRAM,peak CDU(W) b/w equals 2 × average CDU(W) b/w. For CDU(R), peak b/w =average CDU(R) b/w.

Table 121 shows an allocation of main timeslots based on the peakbandwidths of Table The bandwidth required for each unit is calculatedallowing extra cycles for read and write circuit latency for each accessrequiring a bandwidth of more than 1 bit/cycle. Fractional bandwidth issupplied via unused read slots.

The timeslot rotation is 256 cycles. Timeslots are deleted from therotation to allow for circuit latencies for accesses of up to 1 bit percycle i.e. 1 timeslot per rotation.

EXAMPLE 1 Scale-Factor=6

Program the MainTimeslot configuration register (Table) for peakrequired bandwidths of SoPEC Units according to the scale factor.

Program the read round-robin allocation to share unused read slots.Allocate PCU, DNC, HCU and TFS to level 1 read round-robin.

-   -   Assume scale-factor of 6 and peak bandwidths from Table        -   Assign all DIU requestors except TE(TFS) and HCU to            multiples of 1 timeslot, as indicated in Table, where each            timeslot is 1 bit/cycle. This requires 33 timeslots.        -   No timeslots are explicitly allocated for the fractional            bandwidth requirements of TE(TFS) and HCU accesses. Instead,            these units are serviced via unused read slots.        -   Allow 3 timeslots to allow for 3 refreshes in the rotation.        -   Therefore, 36 scheduled slots are used in the rotation for            main timeslots and refreshes, some or all of which may be            able to have a CPU pre-access, provided they fit in the            rotation window.        -   Each of the 2 CDU(W) accesses requires 9 cycles. Per access,            this implies an overhead of 1 slot (12 cycles instead of 6)            in pre-access mode, or 1.25 slots (9 cycles instead of 4)            for no pre-access. The cumulative overhead of the two            accesses is either 2 slots (pre-access) or 3 slots (no            pre-access).        -   Assuming all blocks require a service guarantee of no more            than a single stall across 256 bits, allow 10 cycles for            read latency, which also takes care of 9-cycle write            latency. This can be accounted for by reserving 2 six-cycle            slots (CPU pre-access) or 3 four-cycle slots (no            pre-access).    -   Assume a 256 cycle timeslot rotation.    -   CDU(W) and read latency reduce the number of available cycles in        a rotation to: 256−2×6−2×6=232 cycles (CPU pre-access) or        256−3×4−3×4=232 cycles (no pre-access).    -   As a result, 232 cycles available for 36 accesses implies each        access can take 232/36=6.44 cycles maximum. So, all accesses can        have a pre-access.    -   Therefore the CPU achieves a pre-access ratio of 36/36=100% of        slots in the rotation.

EXAMPLE 2 Scale-Factor=4

Program the MainTimeslot configuration register (Table) for peakrequired bandwidths of SoPEC Units according to the scale factor.Program the read round-robin allocation to share unused read slots.Allocate PCU, DNC, HCU and TFS to level 1 read round-robin.

-   -   Assume scale-factor of 4 and peak bandwidths from Table    -   Assign all DIU requestors except TE(TFS) and HCU multiples of 1        timeslot, as indicated in Table, where each timeslot is 1        bit/cycle. This requires 38 timeslots.    -   No timeslots are explicitly allocated for the fractional        bandwidth requirements of TE(TFS) and HCU accesses. Instead,        these units are serviced via unused read slots.    -   Allow 3 timeslots to allow for 3 refreshes in the rotation.    -   Therefore, 41 scheduled slots are used in the rotation for main        timeslots and refreshes, some or all of which can have a CPU        pre-access, provided they fit in the rotation window.    -   Each of the 4 CDU(W) accesses requires 9 cycles. Per access,        this implies an overhead of 1 slot (12 cycles instead of 6) for        pre-access mode, or 1.25 slots (9 cycles instead of 4) for no        pre-access. The cumulative overhead of the four accesses is        either 4 slots (pre-access) or 5 slots (no pre-access).    -   Assuming all blocks require a service guarantee of no more than        a single stall across 256 bits, allow 10 cycles for read        latency, which also takes care of 9-cycle write latency. This        can be accounted for by reserving 2 six-cycle slots (CPU        pre-access) or 3 four-cycle slots (no pre-access).    -   Assume a 256 cycle timeslot rotation.    -   CDU(W) and read latency reduce the number of available cycles in        a rotation to: 256−4×6−2×6=220 cycles (CPU pre-access) or        256−5×4−3×4=224 cycles (no pre-access).    -   As a result, between 220 and 224 cycles are available for 41        accesses, which implies each access can take between 220/41=5.36        cycles and 224/41=5.46 cycles.    -   Work out how many slots can have a pre-access: For the lower        number of 220 cycles, this implies (41−n)*6+n*4<=220, where        n=number of slots with no pre-access cycle. Solving the equation        gives n>=13. Check answer: 28*6+0.13*4=220.    -   So 28 slots out of the 41 in the rotation can have CPU        pre-accesses.    -   The CPU thus achieves a pre-access ratio of 28/41=68.3% of slots        in the rotation.        20.12.1 Slot Distributions and Stall Calculations for Individual        Blocks

The following sections show how the slots for blocks with a servicerequirement greater than 1 bit/cycle should be distributed. Calculationsare included to check that such blocks will not suffer more than onestall per rotation.

20.12.1.1 SFU

This has 2 bits/cycle on read but this is two separate channels of 1bit/cycle sharing the same DIU interface so it is effectively 2 channelseach of 1 bit/cycle so allowing the same margins as the LBD will work.

20.12.1.2 DWU

The DWU has 12 double buffers in each of the 6 colour planes, odd andeven. These buffers are filled by the DNC and will request DIU accesswhen double buffers fill. The DNC supplies 6 bits to the DWU every cycle(6 odd in one cycle, 6 even in the next cycle). So the service deadlineis 512 cycles, given 6 accesses per 256-cycle rotation.

20.12.1.3 CFU

Here the requirement is that the DIU stall should be less than the timetaken for the CFU to consume one third of its triple buffer. The totalDIU stall=refresh latency+extra CDU(W) latency+read circuit latency=3+5(for 4 cycle timeslots)+10=18 cycles. The CFU can consume its data at 8bits/cycle at SF=4. Therefore 256 bits of data will last 32 cycles sothe triple buffer is safe. In fact we only need an extra 144 bits ofbuffering or 3×64 bits. But it is safer to have the full extra 256 bitsor 4×64 bits of buffering.

20.12.1.4 LLU

The LLU has 2 channels, each of which could request at 6 bits/106 MHzchannel or 4 bits/160 MHz cycle, giving a total of 8 bits/160 MHz cycle.The service deadline for each channel is 256×106 MHz cycles, i.e. all 6colours must be transferred in 256 cycles to feed the printhead. Thisequates to 384×160 MHz cycles.

Over a span of 384 cycles, there will be 6 CDU(W) accesses, 4 refreshesand one read latency encountered at most. Assuming CPU pre-accesses forthese occurrences, this means the number of available cycles is given by384−6×6−4×6−10=314 cycles.

For a CPU pre-access slot rate of 50%, 314 cycles implies 31 CPU and 63non-CPU accesses (31×6+32×4=314). For 12 LLU accesses interspersedamongst these 63 non-CPU slots, implies an LLU allocation rate ofapproximately one slot in 5.

If the CPU pre-access is 100% across all slots, then 314 cycles gives 52slots each to CPU and non-CPU accesses, (52×6=312 cycles). Twelveaccesses spread over 52 slots, implies a 1-in-4 slot allocation to theLLU.

The same LLU slot allocation rate (1 slot in 5, or 1 in 4) can beapplied to programming slots across a 256-cycle rotation window. Thewindow size does not affect the occurrence of LLU slots, so the384-cycle service requirement will be fulfilled.

20.12.1.5 DNC

This has a 2.4 bits/cycle bandwidth requirement. Each access will seethe DIU stall of 18 cycles. 2.4 bits/cycle corresponds to an accessevery 106 cycles within a 256 cycle rotation. So to allow for DIUlatency we need an access every 106-18 or 88 cycles. This is a bandwidthof 2.9 bits/cycle, requiring 3 timeslots in the rotation.

20.12.1.6 CDU

The JPEG decoder produces 8 bits/cycle. Peak CDUR[ead] bandwidth is 4bits/cycle (SF=4), peak CDUW[rite] bandwidth is 4 bits/cycle (SF=4).both with 1.5 DRAM buffering.

The CDU(R) does a DIU read every 64 cycles at scale factor 4 with 1.5DRAM buffering. The delay in being serviced by the DIU could be readcircuit latency (10)+refresh (3)+extra CDU(W) cycles (6)=19 cycles. TheJPEG decoder can consume each 256 bits of DIU-supplied data at 8bits/cycle, i.e. in 32 cycles. If the DIU is 19 cycles late (due tolatency) in supplying the read data then the JPEG decoder will havefinished processing the read data 32+19=49 cycles after the DIU access.This is 64-49=15 cycles in advance of the next read. This 15 cycles isthe upper limit on how much the DIU read service can further be delayed,without causing a stall. Given this margin, a stall on the read sidewill not occur.

On the write side, for scale factor 4, the access pattern is a DIUwrites every 64 cycles with 1.5 DRAM buffereing. The JPEG decoder runsat 8 bits cycle and consumes 256 bits in 32 cycles. The CDU will notstall if the JPEG decode time (32)+DIU stall (19)<64, which is true.

20.13 CPU DRAM Access Performance

The CPU's share of the timeslots can be specified in terms of guaranteedbandwidth and average bandwidth allocations.

-   -   The CPU's access rate to memory depends on the CPU read access        latency i.e. the time between the CPU making a request to the        DIU and receiving the read data back from the DIU.    -   how often it can get access to DIU timeslots.

Table estimated the CPU read latency as 6 cycles.

How often the CPU can get access to DIU timeslots depends on the accesstype. This is summarised in Table 122. TABLE 122 CPU DRAM accessperformance Nominal Access Timeslot CPU DRAM Type Duration access rateNotes CPU Pre- 6 cycles Lower bound CPU can access every timeslot.access (guaranteed bandwidth) is 160 MHz/6 = 26.27 MHz Fractional 4 or 6cycles Lower bound CPU accesses precede a fraction CPU (guaranteedbandwidth) N of timeslots Pre-access is (160 MHz * N/P) where N = C/T. C= CPUPreAccessTimeslots T = CPUTotalTimeslots P = (6 * C + 4 * (T −C))/T

In both CPU Pre-access and Fractional CPU Pre-access modes, if the CPUis not requesting the timeslots will have a duration of 3 or 4 cyclesdepending on whether the current access and preceding access are both tothe shared read bus. This will mean that the timeslot rotation will runfaster and more bandwidth is available.

If the CPU runs out of its instruction cache then instruction fetchperformance is only limited by the on-chip bus protocol. If data residesin the data cache then 160 MHz performance is achieved. Accessing memorymapped registers, PSS or ROM with a 3 cycle bus protocol (addresscycle+data cycle) gives 53 MHz performance.

Due to the action of CPU caching, some bandwidth limiting of the CPU inFractional CPU Pre-access mode is expected to have little or no impacton the overall CPU performance.

20.14 Implementation

The DRAM Interface Unit (DIU) is partitioned into 2 logical blocks tofacilitate design and verification.

a. The DRAM Arbitration Unit (DAU) which interfaces with the SoPEC DIUrequesters.

b. The DRAM Controller Unit (DCU) which accesses the embedded DRAM.

The basic principle in design of the DIU is to ensure that the eDRAM isaccessed at its maximum rate while keeping the CPU read access latencyas low as possible.

The DCU is designed to interface with single bank 20 Mbit IBM Cu-11embedded DRAM performing random accesses every 3 cycles. Page mode burstof 4 write accesses, associated with the CDU, are also supported.

The DAU is designed to support interleaved accesses allowing the DRAM tobe accessed every 3 cycles where back-to-back accesses do not occur overthe shared 64-bit read data bus.

20.14.1 DIU Partition

20.14.2 Definition of DCU IO TABLE 123 DCU interface Port Name Pins I/ODescription Clocks and Resets pclk 1 In SoPEC Functional clockdau_dcu_reset_n 1 In Active-low, synchronous reset in pclk domain.Incorporates DAU hard and soft resets. Inputs from DAU dau_dcu_msn2stall1 In Signal indicating from DAU Arbitration Logic which when assertedstalls DCU in MSN2 state. dau_dcu_adr[21:5] 17 In Signal indicating theaddress for the DRAM access. This is a 256-bit aligned DRAM address.dau_dcu_rwn 1 In Signal indicating the direction for the DRAM access(1=read, 0=write). dau_dcu_cduwpage 1 In Signal indicating if access isa CDU write page mode access (1=CDU page mode, 0=not CDU page mode).dau_dcu_refresh 1 In Signal indicating that a refresh command is to beissued. If asserted day_dcu_adr, dau_dcu_rwn and dau_dcu_cduwpage areignored. dau_dcu_wdata 256 In 256-bit write data to DCU dau_dcu_wmask 32In Byte encoded write data mask for 256-bit dau_dcu_wdata to DCUPolarity: A “1” in a bit field of dau_dcu_wmask means that thecorresponding byte in the 256-bit dau_dcu_wdata is written to DRAM.Outputs to DAU dcu_dau_adv 1 Out Signal indicating to DAU to supply nextcommand to DCU dcu_dau_wadv 1 Out Signal indicating to DAU to initiatenext non- CPU write dcu_dau_refreshcomplete 1 Out Signal indicating thatthe DCU has completed a refresh. dcu_dau_rdata 256 Out 256-bit read datafrom DCU. dcu_dau_rvalid 1 Out Signal indicating valid read data ondcu_dau_rdata.20.14.3 DRAM Access Types

The DRAM access types used in SoPEC are summarised in Table 124. For arefresh operation the DRAM generates the address internally. TABLE 124SoPEC DRAM access types Type Access Read Random 256-bit read WriteRandom 256-bit write with byte write masking Page mode write for burstof 4 256-bit words with byte write masking Refresh Single refresh20.14.4 Constructing the 20 Mbit DRAM From Two 10 Mbit Instances

The 20 Mbit DRAM is constructed from two 10 Mbit instances. The addressranges of the two instances are shown in Table 125. TABLE 125 Addressranges of the two 10 Mbit instances in the 20 Mbit DRAM Hex 256-bitBinary 256-bit Instance Address word address word address Instance0First word in 00000 0 0000 0000 0000 0000 lower 10 Mbit Instance0 Lastword in 09FFF 0 1001 1111 1111 1111 lower 10 Mbit Instance1 First wordin 0A000 0 1010 0000 0000 0000 upper 10 Mbit Instance1 Last word in13FFF 1 0011 1111 1111 1111 upper 10 Mbit

There are separate macro select signals, inst0_MSN and inst1_MSN, foreach instance and separate dataout busses inst0_DO and inst1_DO, whichare multiplexed in the DCU. Apart from these signals both instancesshare the DRAM output pins of the DCU.

The DRAM Arbitration Unit (DAU) generates a 17 bit address,dau_dcu_adr[21:5], sufficient to address all 256-bit words in the 20Mbit DRAM. The upper 5 bits are used to select between the two memoryinstances by gating their MSN pins. If instance1 is selected then thelower 16-bits are translated to map into the 10 Mbit range of thatinstance. The multiplexing and address translation rules are shown inTable 126.

In the case that the DAU issues a refresh, indicated by dau_dcu_refresh,then both macros are selected. The other control signals TABLE 126Instance selection and address translation DAU Address bits Instancedau_dcu_refresh dau_dcu_adr[21:17] selected inst0_MSN inst1_MSN Addresstranslation 0   <01010 Instance0 MSN 1 A[15:0] =dau_dcu_adr[20:5] >=01010 Instance1 1 MSN A[15:0] = dau_dcu_adr[21:5] −hA000 1 — Instance0 MSN MSN — and Instance1dau_dcu_adr[21:5], dau_dcu_rwn and dau_dcu_cduwpage are ignored.

The instance selection and address translation logic is shown in FIG.102.

The address translation and instance decode logic also increments theaddress presented to the DRAM in the case of a page mode write. Pseudocode is given below. if rising_edge(dau_dcu_valid) then  //capture theaddress from the DAU  next_cmdadr[21:5] = dau_dcu_adr[21:5] elsifpagemode_adr_inc == 1 then  //increment the address  next_cmdadr[21:5] =cmdadr[21:5] + 1 else  next_cmdadr[21:5] = cmdadr[21:5] ifrising_edge(dau_dcu_valid) then  //capture the address from the DAU adr_var[21:5] := dau_dcu_adr[21:5] else  adr_var[21:5] := cmdadr[21:5]if adr_var[21:17] < 01010 then  //choose instance0  instance_sel = 0 A[15:0] = adr_var[20:5] else  //choose instance1  instance_sel = 1  A[15:0] = adr_var[21:5] − hA000

Pseudo code for the select logic, SEL0, for DRAM Instance0 is givenbelow. //instance0 selected or refresh if instance_sel == 0 ORdau_dcu_refresh == 1 then  inst0_MSN = MSN else  inst0_MSN = 1

Pseudo code for the select logic, SEL1, for DRAM instance1 is givenbelow. //instance1 selected or refresh if instance_sel == 1 ORdau_dcu_refresh == 1 then  inst1_MSN = MSN else  inst1_MSN = 1

During a random read, the read data is returned, on dcu_dau_rdata, aftertime T_(acc), the random access time, which varies between 3 and 8 ns(see Table). To avoid any metastability issues the read data must becaptured by a flip-flop which is enabled 2 pclk cycles or 12.5 ns afterthe DRAM access has been started. The DCU generates the enable signaldcu_dau_rvalid to capture dcu_dau_rdata.

The byte write mask dau_dcu_wmask[31:0] must be expanded to the bitwrite mask bitwritemask[255:0 needed by the DRAM.

20.14.5 DAU-DCU Interface Description

The DCU asserts dcu_dau_adv in the MSN2 state to indicate to the DAU tosupply the next command. dcu_dau_adv causes the DAU to performarbitration in the MSN2 cycle. The resulting command is available to theDCU in the following cycle, the RST state. The timing is shown in FIG.103. The command to the DRAM must be valid in the RST and MSN1 states,or at least meet the hold time requirement to the MSN falling edge atthe start of the MSN1 state.

Note that the DAU issues a valid arbitration result following everydcu_dau_adv pulse. If no unit is requesting DRAM access, then afall-back refresh request will be issued. When dau_dcu_refresh isasserted the operation is a refresh and dau_dcu_adr, dau_dcu_rwn anddau_dcu_cduwpage are ignored.

The DCU generates a second signal, dcu_dau_wadv, which is asserted inthe RST state. This indicates to the DAU that it can perform arbitrationin advance for non-CPU writes. The reason for performing arbitration inadvance for non-CPU writes is explained in “Command MultiplexorSub-block TABLE 136 Command Multiplexor Sub-block IO Definition Portname Pins I/O Description Clocks and Resets pclk 1 In System Clockprst_n 1 In System reset, synchronous active low DIU Read Interface toSoPEC Units <unit>_diu_radr[21:5] 17 In Read address to DIU 17 bits wide(256-bit aligned word). diu_<unit>_rack 1 Out Acknowledge from DIU thatread request has been accepted and new read address can be placed on<unit>_diu_radr DIU Write Interface to SoPEC Units <unit>_diu_wadr[21:5]17 In Write address to DIU except CPU, SCB, CDU 17 bits wide (256-bitaligned word) cpu_diu_wadr[21:4]] 22 In CPU Write address to DIU(128-bit aligned address.) cpu_diu_wmask 16 In Byte enables for CPUwrite. cdu_diu_wadr[21:3] 19 In CDU Write address to DIU 19 bits wide(64-bit aligned word) Addresses cannot cross a 256-bit word DRAMboundary. diu_<unit>_wack 1 Out Acknowledge from DIU that write requesthas been accepted and new write address can be placed on <unit>_diu_wadrOutputs to CPU Interface and Arbitration Logic sub-block re_arbitrate 1Out Signalling telling the arbitration logic to choose the nextarbitration winner. re_arbitrate_wadv 1 Out Signal telling thearbitration logic to choose the next arbitration winner for non-CPUwrites 2 timeslots in advance Debug Outputs to CPU Configuration andArbitration Logic Sub-block write_sel 5 Out Signal indicating the SoPECUnit for which the current write transaction is occurring. Encoding isdescribed in Table . write_complete 1 Out Signal indicating that writetransaction to SoPEC Unit indicated by write_sel is complete. Inputsfrom CPU Interface and Arbitration Logic sub-block arb_gnt 1 In Signallasting 1 cycle which indicates arbitration has occurred and arb_sel isvalid. arb_sel 5 In Signal indicating which requesting SoPEC Unit haswon arbitration. Encoding is described in Table . dir_sel 2 In Signalindicating which sense of access associated with arb_sel 00: issuenon-CPU write 01: read winner 10: write winner 11: refresh winner Inputsfrom Read Write Multiplexor Sub-block write_data_valid 2 In Signalindicating that valid write data is available for the current command.00=not valid 01=CPU write data valid 10=non-CPU write data valid 11=bothCPU and non-CPU write data Valid wdata 256 In 256-bit non-CPU write datacpu_wdata 32 In 32-bit CPU write data Outputs to Read Write MultiplexorSub-block write_data_accept 2 Out Signal indicating the CommandMultiplexor has accepted the write data from the write multiplexor00=not valid 01=accepts CPU write data 10=accepts non-CPU write data11=not valid Inputs from DCU dcu_dau_adv 1 In Signal indicating to DAUto supply next command to DCU dcu_dau_wadv 1 In Signal indicating to DAUto initiate next non-CPU write Outputs to DCU dau_dcu_adr[21:5] 17 OutSignal indicating the address for the DRAM access. This is a 256-bitaligned DRAM address. dau_dcu_rwn 1 Out Signal indicating the directionfor the DRAM access (1=read, 0=write). dau_dcu_cduwpage 1 Out Signalindicating if access is a CDU write page mode access (1=CDU page mode, 0= not CDU page mode). dau_dcu_refresh 1 Out Signal indicating that arefresh command is to be issued. If asserted dau_dcu_adr, dau_dcu_rwnand dau_dcu_cduwpage are ignored. dau_dcu_wdata 256 Out 256-bit writedata to DCU dau_dcu_wmask 32 Out Byte encoded write data mask for256-bit dau_dcu_wdata to DCU

The DCU state-machine can stall in the MSN2 state when the signaldau_dcu_msn2stall is asserted by the DAU Arbitration Logic,

The states of the DCU state-machine are summarised in Table 127. TABLE127 States of the DCU state-machine State Description RST Restore stateMSN1 Macro select state 1 MSN2 Macro select state 220.14.6 DCU State Machines

The IBM DRAM has a simple SRAM like interface. The DRAM is accessed as asingle bank. The state machine to access the DRAM is shown in FIG. 104.

The signal pagemode_adr_inc is exported from the DCU asdcu_dau_cduwaccept. dcu_dau_cduwaccept tells the DAU to supply the nextwrite data to the DRAM

20.14.7 CU-11DRAM Timing Diagrams

The IBM Cu-11 embedded DRAM datasheet is referenced as [16].

Table 128 shows the timing parameters which must be obeyed for the IBMembedded DRAM. TABLE 128 1.5 V Cu-11 DRAM a.c. parameters SymbolParameter Min Max Units T_(set) Input setup to MSN/PGN 1 — ns T_(hld)Input hold to MSN/PGN 2 — ns T_(acc) Random access time 3 8   ns T_(act)MSN active time 8 100k ns T_(res) MSN restore time 4 — ns T_(cyc) RandomR/W cycle time 12 — ns T_(rfc) Refresh cycle time 12 — ns T_(accp) Pagemode access time 1 3.9 ns T_(pa) PGN active time 1.6 — ns T_(pr) PGNrestore time 1.6 — ns T_(pcyc) PGN cycle time 4 — ns T_(mprd) MSN to PGNrestore delay 6 — ns T_(actp) MSN active for page mode 12 — ns T_(ref)Refresh period — 3.2 ms T_(pamr) Page active to MSN restore 4 — ns

The IBM DRAM is asynchronous. In SoPEC it interfaces to signals clockedon pclk. The following timing diagrams show how the timing parameters inTable 129 are satisfied in SoPEC.

20.14.8 Definition of DAU IO TABLE 129 DAU interface Port Name Pins I/ODescription Clocks and Resets pclk 1 In SoPEC Functional clock prst_n 1In Active-low, synchronous reset in pclk domain dau_dcu_reset_n 1 OutActive-low, synchronous reset in pclk domain. This reset signal,exported to the DCU, incorporates the locally captured DAU version ofhard reset (prst_n) and the soft reset configuration register bit“Reset”. CPU Interface cpu_adr 22 In CPU address bus for both DRAM andconfiguration register access. 9 bits (bits 10:2) are required to decodethe configuration register address space. 22 bits can address the DRAMat byte level. DRAM addresses cannot cross a 256-bit word DRAM boundary.cpu_dataout 32 In Shared write data bus from the CPU for DRAM andconfiguration data diu_cpu_data 32 Out Configuration, status and debugread data bus to the CPU diu_cpu_debug_valid 1 Out Signal indicating thedata on the diu_cpu_data bus is valid debug data. cpu_rwn 1 In Commonread/not-write signal from the CPU cpu_acode 2 In CPU access codesignals. cpu_acode[0] - Program (0)/Data (1) access cpu_acode[1] - User(0)/Supervisor (1) access The DAU will only allow supervisor modeaccesses to data space. cpu_diu_sel 1 In Block select from the CPU. Whencpu_diu_sel is high both cpu_adr and cpu_dataout are valid diu_cpu_rdy 1Out Ready signal to the CPU. When diu_cpu_rdy is high it indicates thelast cycle of the access. For a write cycle this means cpu_dataout hasbeen registered by the block and for a read cycle this means the data ondiu_cpu_data is valid. diu_cpu_berr 1 Out Bus error signal to the CPUindicating an invalid access. DIU Read Interface to SoPEC Units<unit>_diu_rreq 1 In SoPEC unit requests DRAM read. A read request mustbe accompanied by a valid read address. <unit>_diu_radr[21:5] 17 In Readaddress to DIU 17 bits wide (256-bit aligned word). Note: “<unit>”refers to non-CPU requesters only. CPU addresses are provided via“cpu_adr”. diu_<unit>_rack 1 Out Acknowledge from DIU that read requesthas been accepted and new read address can be placed on <unit>_diu_radrdiu_data 64 Out Data from DIU to SoPEC Units except CPU. First 64-bitsis bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bitword Third 64-bits is bits 191:128 of 256 bit word Fourth 64-bits isbits 255:192 of 256 bit word dram_cpu_data 256 Out 256-bit data fromDRAM to CPU. diu_<unit>_rvalid 1 Out Signal from DIU telling SoPEC Unitthat valid read data is on the diu_data bus DIU Write Interface to SoPECUnits <unit>_diu_wreq 1 In SoPEC unit requests DRAM write. A writerequest must be accompanied by a valid write address. Note: “<unit>”refers to non-CPU requesters only. <unit>_diu_wadr[21:5] 17 In Writeaddress to DIU except CPU, CDU 17 bits wide (256-bit aligned word) Note:“<unit>” refers to non-CPU requesters, excluding the CDU.scb_diu_wmask[7:0] 8 In Byte write enables applicable to a given 64-bitquarter- word transferred from the SCB. Note that different mask valuesare used with each quarter-word. Requirement for the USB host core.diu_cpu_write_rdy 1 Out Flag indicating that the CPU posted write bufferis empty. cpu_diu_wdatavalid 1 In Write enable for the CPU posted writebuffer. Also confirms that the CPU write data, address and mask arevalid. cpu_diu_wdata 128 In CPU write data which is loaded into theposted write buffer. cpu_diu_wadr[21:4] 18 In 128-bit aligned CPU writeaddress. cpu_diu_wmask[15:0] 16 In Byte enables for 128-bit CPU postedwrite. cdu_diu_wadr[21:3] 19 In CDU Write address to DIU 19 bits wide(64-bit aligned word) Addresses cannot cross a 256-bit word DRAMboundary. diu_<unit>_wack 1 Out Acknowledge from DIU that write requesthas been accepted and new write address can be placed on <unit>_diu_wadr<unit>_diu_data[63:0] 64 In Data from SoPEC Unit to DIU except CPU.First 64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64of 256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth64-bits is bits 255:192 of 256 bit word Note: “<unit>” refers to non-CPUrequesters only. <unit>_diu_wvalid 1 In Signal from SoPEC Unitindicating that data on <unit>_diu_data is valid. Note: “<unit>” refersto non-CPU requesters only. Outputs to DCU dau_dcu_msn2stall 1 OutSignal indicating from DAU Arbitration Logic which when de-assertedstalls DCU in MSN2 state. dau_dcu_adr[21:5] 17 Out Signal indicating theaddress for the DRAM access. This is a 256-bit aligned DRAM address.dau_dcu_rwn 1 Out Signal indicating the direction for the DRAM access(1=read, 0=write). dau_dcu_cduwpage 1 Out Signal indicating if access isa CDU write page mode access (1=CDU page mode, 0=not CDU page mode).dau_dcu_refresh 1 Out Signal indicating that a refresh command is to beissued. If asserted dau_dcu_cmd_adr, dau_dcu_rwn and dau_dcu_cduwpageare ignored. dau_dcu_wdata 256 Out 256-bit write data to DCUdau_dcu_wmask 32 Out Byte-encoded write data mask for 256-bitdau_dcu_wdata to DCU Polarity: A “1” in a bit field of dau_dcu_wmaskmeans that the corresponding byte in the 256-bit dau_dcu_wdata iswritten to DRAM. Inputs from DCU dcu_dau_adv 1 In Signal indicating toDAU to supply next command to DCU dcu_dau_wadv 1 In Signal indicating toDAU to initiate next non-CPU write dcu_dau_refreshcomplete 1 In Signalindicating that the DCU has completed a refresh. dcu_dau_rdata 256 In256-bit read data from DCU. dcu_dau_rvalid 1 In Signal indicating validread data on dcu_dau_rdata.

The CPU subsystem bus interface is described in more detail in Section11.4.3. The DAU block will only allow supervisor-mode accesses to updateits configuration registers (i.e. cpu_acode[1:0]=b11). All otheraccesses will result in diu_cpu_berr being asserted.

20.14.9 DAU Configuration Registers TABLE 130 DAU configurationregisters Address (DIU_base+) Register #bits Reset Description Reset0x00 Reset 1 0x1 A write to this register causes a reset of the DIU.This register can be read to indicate the reset state: 0 - reset inprogress 1 - reset not in progress Refresh 0x04 RefreshPeriod 9 0x063Refresh controller. When set to 0 refresh is off, otherwise the valueindicates the number of cycles, less one, between each refresh. [Notethat for a system clock frequency of 160 MHz, a value exceeding 0x63(indicating a 100-cycle refresh period) should not be programmed, or theDRAM will malfunction.] Timeslot allocation and control 0x08NumMainTimeslots 6 0x01 Number of main timeslots (1-64) less one 0x0CCPUPreAccessTimes 4 0x0 (CPUPreAccessTimeslots + 1) main lots slots outof a total of (CPUTotalTimeslots + 1) are preceded by a CPU access. 0x10CPUTotalTimeslots 4 0x0 (CPUPreAccessTimeslots + 1) main slots out of atotal of (CPUTotalTimeslots + 1) are preceded by a CPU access.0x100-0x1FC MainTimeslot[63:0] 64x4 [63:1][3:0] = 0x0 Programmable maintimeslots (up to [0][3:0] = 0xE 64 main timeslots). 0x200ReadRoundRobinLevel 12 0x000 For each read requester plus refresh 0 =level1 of round-robin 1 = level2 of round-robin The bit order is definedin Table . 0x204 EnableCPURound 1 0x1 Allows the CPU to particpate inthe Robin unused read round-robin scheme. If disabled, the sharedCPU/refresh round-robin position is dedicated solely to refresh. 0x208RotationSync 1 0x1 Writing 0, followed by 1 to this bit allows thetimeslot rotation to advance on a cycle basis which can be determined bythe CPU. 0x20C minNonCPUReadAdr 12 0x800 12 MSBs of lowest DRAM addresswhich may be read by non-CPU requesters. 0x210 minDWUWriteAdr 12 0x80012 MSBs of lowest DRAM address which may be written to by the DWU. 0x214minNonCPUWriteAdr 12 0x800 12 MSBs of lowest DRAM address which may bewritten to by non-CPU requesters other than the DWU. Debug 0x300DebugSelect[11:2] 10 0x304 Debug address select. Indicates the addressof the register to report on the diu_cpu_data bus when it is nototherwise being used. When this signal carries debug information thesignal diu_cpu_debug_valid will be asserted. Debug: arbitration andperformance 0x304 ArbitrationHistory 22 — Bit 0 = arb_gnt Bit 1 =arb_executed Bit 6:2 = arb_sel[4:0] Bit 12:7 = timeslot_number[5:0] Bit15:13 = access_type[2:0] Bit 16 = back2back_non_cpu_write Bit 17 =sticky_back2back_non_cpu_write (Sticky version of same, cleared onreset.) Bit 18 = rotation_sync Bit 20:19 = rotation_state Bit 21 =sticky_invalid_non_cpu_adr See Section 20.14.9.2 DIU Debug for adescription of the fields. Read only register. 0x308 DIUPerformance 31 —Bit 0 = cpu_diu_rreq Bit 1 = scb_diu_rreq Bit 2 = cdu_diu_rreq Bit 3 =cfu_diu_rreq Bit 4 = lbd_diu_rreq Bit 5 = sfu_diu_rreq Bit 6 =td_diu_rreq Bit 7 = tfs_diu_rreq Bit 8 = hcu_diu_rreq Bit 9 =dnc_diu_rreq Bit 10 = llu_diu_rreq Bit 11 = pcu_diu_rreq Bit 12 =cpu_diu_wreq Bit 13 = scb_diu_wreq Bit 14 = cdu_diu_wreq Bit 15 =sfu_diu_wreq Bit 16 = dwu_diu_wreq Bit 17 = refresh_req Bit 22:18 =read_sel[4:0] Bit 23 = read_complete Bit 28:24 = write_sel[4:0] Bit 29 =write_complete Bit 30 = dcu_dau_refreshcomplete See Section 20.14.9.2DIU Debug for a description of the fields. Read only register. Debug DIUread requesters interface signals 0x30C CPUReadInterface 25 — Bit 0 =cpu_diu_rreq Bit 22:1 = cpu_adr[21:0] Bit 23 = diu_cpu_rack Bit 24 =diu_cpu_rvalid Read only register. 0x310 SCBReadInterface 20 Bit 0 =scb_diu_rreq Bit 17:1 = scb_diu_radr[21:5] Bit 18 = diu_scb_rack Bit 19= diu_scb_rvalid Read only register. 0x314 CDUReadInterface 20 — Bit 0 =cdu_diu_rreq Bit 17:1 = cdu_diu_radr[21:5] Bit 18 = diu_cdu_rack Bit 19= diu_cdu_rvalid Read only register. 0x318 CFUReadInterface 20 — Bit 0 =cfu_diu_rreq Bit 17:1 = cfu_diu_radr[21:5] Bit 18 = diu_cfu_rack Bit 19= diu_cfu_rvalid Read only register. 0x31C LBDReadInterface 20 — Bit 0 =lbd_diu_rreq Bit 17:1 = lbd_diu_radr[21:5] Bit 18 = diu_lbd_rack Bit 19= diu_lbd_rvalid Read only register. 0x320 SFUReadInterface 20 — Bit 0 =sfu_diu_rreq Bit 17:1 = sfu_diu_radr[21:5] Bit 18 = diu_sfu_rack Bit 19= diu_sfu_rvalid Read only register. 0x324 TDReadInterface 20 — Bit 0 =td_diu_rreq Bit 17:1 = td_diu_radr[21:5] Bit 18 = diu_td_rack Bit 19 =diu_td_rvalid Read only register. 0x328 TFSReadInterface 20 — Bit 0 =tfs_diu_rreq Bit 17:1 = tfs_diu_radr[21:5] Bit 18 = diu_tfs_rack Bit 19= diu_tfs_rvalid Read only register. 0x32C HCUReadInterface 20 — Bit 0 =hcu_diu_rreq Bit 17:1 = hcu_diu_radr[21:5] Bit 18 = diu_hcu_rack Bit 19= diu_hcu_rvalid Read only register. 0x330 DNCReadInterface 20 — Bit 0 =dnc_diu_rreq Bit 17:1 = dnc_diu_radr[21:5] Bit 18 = diu_dnc_rack Bit 19= diu_dnc_rvalid Read only register. 0x334 LLUReadInterface 20 — Bit 0 =llu_diu_rreq Bit 17:1 = lluu_diu_radr[21:5] Bit 18 = diu_llu_rack Bit 19= diu_llu_rvalid Read only register. 0x338 PCUReadInterface 20 — Bit 0 =pcu_diu_rreq Bit 17:1 = pcu_diu_radr[21:5] Bit 18 = diu_pcu_rack Bit 19= diu_pcu_rvalid Read only register. Debug DIU write requestersinterface signals 0x33C CPUWriteInterface 27 — Bit 0 = cpu_diu_wreq Bit22:1 = cpu_adr[21:0] Bit 24:23 = cpu_diu_wmask[1:0] Bit 25 =diu_cpu_wack Bit 26 = cpu_diu_wvalid Read only register. 0x340SCBWriteInterface 20 — Bit 0 = scb_diu_wreq Bit 17:1 =scb_diu_wadr[21:5] Bit 18 = diu_scb_wack Bit 19 = scb_diu_wvalid Readonly register. 0x344 CDUWriteInterface 22 — Bit 0 = cdu_diu_wreq Bit19:1 = cdu_diu_wadr[21:3] Bit 20 = diu_cdu_wack Bit 21 = cdu_diu_wvalidRead only register. 0x348 SFUWriteInterface 20 — Bit 0 = sfu_diu_wreqBit 17:1 = sfu_diu_wadr[21:5] Bit 18 = diu_sfu_wack Bit 19 =sfu_diu_wvalid Read only register. 0x34C DWUWriteInterface 20 — Bit 0 =dwu_diu_wreq Bit 17:1 = dwu_diu_wadr[21:5] Bit 18 = diu_dwu_wack Bit 19= dwu_diu_wvalid Read only register. Debug DAU-DCU interface signals0x350 DAU-DCUInterface 25 — Bit 16:0 = dau_dcu_adr[21:5] Bit 17 =dau_dcu_rwn Bit 18 = dau_dcu_cduwpage Bit 19 = dau_dcu_refresh Bit 20 =dau_dcu_msn2stall Bit 21 = dcu_dau_adv Bit 22 = dcu_dau_wadv Bit 23 =dcu_dau_refreshcomplete Bit 24 = dcu_dau_rvalid Read only register.

Each main timeslot can be assigned a SoPEC DIU requestor according toTable 131. TABLE 131 SoPEC DIU requester encoding for main timeslots.Name Index (binary) Index (HEX) Write SCB(W) b0_0000 0x00 CDU(W) b00010x1 SFU(W) b0010 0x2 DWU b0011 0x3 Read SCB(R) b0100 0x4 CDU(R) b01010x5 CFU b0110 0x6 LBD b0111 0x7 SFU(R) b1000 0x8 TE(TD) b1001 0x9TE(TFS) b1010 0xA HCU b1011 0xB DNC b1100 0xC LLU b1101 0xD PCU b11100xE

ReadRoundRobinLevel and ReadRoundRobinEnable registers are encoded inthe bit order defined in Table 132. TABLE 132 Read round-robin registersbit order Name Bit index SCB(R) 0 CDU(R) 1 CFU 2 LBD 3 SFU(R) 4 TE(TD) 5TE(TFS) 6 HCU 7 DNC 8 LLU 9 PCU 10 CPU/ 11 Refresh20.14.9.1 Configuration Register Reset State

The RefreshPeriod configuration register has a reset value of 0x063which ensures that a refresh will occur every 100 cycles and thecontents of the DRAM will remain valid.

The CPUPreAccessTimeslots and CPUTotalTimeslots configuration registersboth have a reset value of 0x0. Matching values in these two registersmeans that every slot has a CPU pre-acess. NumMainTimeslots is reset to0x1, so there are just 2 main timeslots in the rotation initially. Theseslots alternate between SCB writes and PCU reads, as defined by thereset value of MainTimeslot[63:0], thus respecting at reset time thegeneral rule that adjacent non-CPU writes are not permitted.

The first access issued by the DIU after reset will be a refresh.

20.14.9.2 DIU Debug

External visibility of the DIU must be provided for debug purposes. Tofacilitate this debug registers are added to the DIU address space.

The DIU CPU system data bus diu_cpu_data[31:0] returns configuration andstatus register information to the CPU. When a configuration or statusregister is not being read by the CPU debug data is returned ondiu_cpu_data[31:0] instead. An accompanying active highdiu_cpu_debug_valid signal is used to indicate when the data buscontains valid debug data. The DIU features a DebugSelect register thatcontrols a local multiplexor to determine which register is output ondiu_cpu_data[31:0].

Three kinds of debug information are gathered:

a. The order and access type of DIU requesters winning arbitration.

This information can be obtained by observing the signals in theArbitrationHistory debug register at DIU_Base+0x304 described in Table133. TABLE 133 ArbitrationHistory debug register description,DIU_base+0x304 Field name Bits Description arb_gnt 1 Signal lasting 1cycle which is asserted in the cycle following a main arbitration orpre-arbitration. arb_executed 1 Signal lasting 1 cycle which indicatesthat an arbitration result has actually been executed. Is used todifferentiate between *pre*-arbitration and *main* arbitration, both ofwhich cause arb_gnt to be asserted. If arb_executed and arb_gnt are bothhigh, then a main (executed) arbitration is indicated. arb_sel 5 Signalindicating which requesting SoPEC Unit has won arbitration. Encoding isdescribed in Table . Refresh winning arbitration is indicated byaccess_type. timeslot_number 6 Signal indicating which main timeslot iseither currently being serviced, or about to be serviced. The lattercase applies where a main slot is pre- empted by a CPU pre-access or ascheduled refresh. access_type 3 Signal indicating the origin of thewinning arbitration 000 = Standard CPU pre-access. 001 = Scheduledrefresh. 010 = Standard non-CPU timeslot. 011 = CPU access via unusedread/write slot, re-allocated by round robin. 100 = Non-CPU write viaunused write slot, re-allocated at pre- arbitration. 101 = Non-CPU readvia unused read/write slot, re-allocated by round robin. 110 = Refreshvia unused read/write slot, re-allocated by round robin. 111 =CPU/Refresh access due to RotationSync = 0. back2back_non_cpu_write 1Instantaneous indicator of attempted illegal back-to-back non-CPU write.(Recall from section 20.7.2.3 on page 212 that the second write of anysuch pair is disregarded and re-allocated via the unused readround-robin scheme.) sticky_back2back_non_cpu_write 1 Sticky version ofsame, cleared on reset. rotation_sync 1 Current value of theRotationSync configuration bit. rotation_state 2 These bits indicate thecurrent status of pre-arbitation and main timeslot rotation, as a resultof the RotationSync setting. 00 = Pre-arb enabled, rotation enabled. 01= Pre-arb disabled, rotation enabled. 10 = Pre-arb disabled, rotationdisabled. 11 = Pre-arb enabled, rotation disabled. 00 is the normalfunctional setting when RotationSync is 1. 01 indicates thatpre-arbitration has halted at the end of its rotation because ofRotationSync having been cleared. However the main arbitration has yetto finish its current rotation. 10 indicates that both pre-arb and themain rotation have halted, due to RotationSync being 0 and that only CPUaccesses and refreshes are allowed. 11 indicates that RotationSync hasjust been changed from 0 to 1 and that pre-arbitration is being given ahead start to look ahead for non- CPU writes, in advance of the mainrotation starting up again. sticky_invalid_non_cpu_adr 1 Sticky bit toindicate an attempted non-CPU access with an invalid address. Cleared byreset or by an explicit write by the CPU.

TABLE 134 arb_sel, read_sel and write_sel encoding Name Index (binary)Index (HEX) Write SCB(W) b0_0000 0x00 CDU(W) b0_0001 0x01 SFU(W) b0_00100x02 DWU b0_0011 0x03 Read SCB(R) b0_0100 0x04 CDU(R) b0_0101 0x05 CFUb0_0110 0x06 LBD b0_0111 0x07 SFU(R) b0_1000 0x08 TE(TD) b0_1001 0x09TE(TFS) b0_1010 0x0A HCU b0_1011 0x0B DNC b0_1100 0x0C LLU b0_1101 0x0DPCU b0_1110 0x0E Refresh Refresh b0_1111 0x0F CPU CPU(R) b1_0000 0x10CPU(W) b1_0001 0x11

The encoding for arb_sel is described in Table 134.

b. The time between a DIU requester requesting an access and completingthe access. This information can be obtained by observing the signals inthe DIUPerformance debug register at DIU_Base+0x308 described in Table135. The encoding for read_sel and write_sel is described in Table. Thedata collected from DIUPerformance can be post-processed to count thenumber of cycles between a unit requesting DIU access and the accessbeing completed. TABLE 135 DIUPerformance debug register description,DIU_base+0x308 Field name Bits Description <unit>_diu_rreq 12 Signalindicating that SoPEC unit requests DRAM read. <unit>_diu_wreq 5 Signalindicating that SoPEC unit requests DRAM write. refresh_req 1 Signalindicating that refresh has requested a DIU access. read_sel[4:0] 5Signal indicating the SoPEC Unit for which the current read transactionis occurring. Encoding is described in Table read_complete 1 Signalindicating that read transaction to SoPEC Unit indicated by read_sel iscomplete i.e. that the last read data has been output by the DIU.write_sel[4:0] 5 Signal indicating the SoPEC Unit for which the currentwrite transaction is occurring. Encoding is described in Tablewrite_complete 1 Signal indicating that write transaction to SoPEC Unitindicated by write_sel is complete i.e. that the last write data hasbeen transferred to the DIU. dcu_refresh_complete 1 Signal indicatingthat refresh has completed.

c. Interface signals to DIU requestors and DAU-dCU interface.

All interface signals with the exception of data busses at theinterfaces between the DAU and DCU and DIU write and read requestors canbe monitored in debug mode by observing debug registers DIU_Base+0x314to DIU_Base+0x354.

20.14.10 DRAM Arbitration Unit (DAU)

The DAU is shown in FIG. 101.

The DAU is composed of the following sub-blocks

a. CPU Configuration and Arbitration Logic sub-block.

b. Command Multiplexor sub-block.

c. Read and Write Data Multiplexor sub-block.

The function of the DAU is to supply DRAM commands to the DCU.

-   -   The DCU requests a command from the DAU by asserting        dcu_dau_adv.    -   The DAU Command Multiplexor requests the Arbitration Logic        sub-block to arbitrate the next DRAM access. The Command        Multiplexor passes dcu_dau_adv as the re_arbitrate signal to the        Arbitration Logic sub-block.    -   If the RotationSync bit has been cleared, then the arbitration        logic grants exclusive access to the CPU and scheduled        refreshes. If the bit has been set, regular arbitration occurs.        A detailed description of RotationSync is given in section        20.14.12.2.1 on page 295.    -   Until the Arbitration Logic has a valid result it stalls the DCU        by asserting dau_dcu_msn2stall. The Arbitration Logic then        returns the selected arbitration winner to the Command        Multiplexor which issues the command to the DRAM. The        Arbitration Logic could stall for example if it selected a        shared read bus access but the Read Multiplexor indicated it was        busy by de-asserting read_cmd_rdy[1].    -   In the case of a read command the read data from the DRAM is        multiplexed back to the read requestor by the Read Multiplexor.        In the case of a write operation the Write Multiplexor        multiplexes the write data from the selected DIU write requester        to the DCU before the write command can occur. If the write data        is not available then the Command Multiplexor will keep        dau_dcu_valid de-asserted. This will stall the DCU until the        write command is ready to be issued.    -   Arbitration for non-CPU writes occurs in advance. The DCU        provides a signal dcu_dau_wadv which the Command Multiplexor        issues to the Arbitrate Logic as re_arbitrate_wadv. If        arbitration is blocked by the Write Multiplexor being busy, as        indicated by write_cmd_rdy[1] being de-asserted, then the        Arbitration Logic will stall the DCU by asserting        dau_dcu_msn2stall until the Write Multiplexor is ready.        20.14.10.1 Read Accesses

The timing of a non-CPU DIU read access are shown in FIG. 109. Notere_arbitrate is asserted in the MSN2 state of the previous access.

Note the fixed timing relationship between the read acknowledgment andthe first rvalid for all non-CPU reads. This means that the second andany later reads in a back-to-back non-CPU sequence have theiracknowledgments asserted one cycle later, i.e. in the “MSN1” DCU state.The timing of a CPU DIU read access is shown in FIG. 110. Notere_arbitrate is asserted in the MSN2 state of the previous access.

Some points can be noted from FIG. 109 and FIG. 110.

DIU requests:

-   -   For non-CPU accesses the <unit>_diu_rreq signals are registered        before the arbitration can occur.    -   For CPU accesses the cpu_diu_rreq signal is not registered to        reduce CPU DIU access latency.

Arbitration occurs when the dcu_dau_adv signal from the DCU is asserted.The DRAM address for the arbitration winner is available in the nextcycle, the RST state of the DCU.

The DRAM access starts in the MSN1 state of the DCU and completes in theRST state of the DCU.

Read data is available:

-   -   In the MSN2 cycle where it is output unregistered to the CPU    -   In the MSN2 cycle and registered in the DAU before being output        in the next cycle to all other read requesters in order to ease        timing.

The DIU protocol is in fact:

-   -   Pipelined i.e. the following transaction is initiated while the        previous transfer is in progress.    -   Split transaction i.e. the transaction is split into independent        address and data transfers.

Some general points should be noted in the case of CPU accesses:

-   -   Since the CPU request is not registered in the DIU before        arbitration, then the CPU must generate the request, route it to        the DAU and complete arbitration all in 1 cycle. To facilitate        this CPU access is arbitrated late in the arbitration cycle (see        Section 20.14.12.2).    -   Since the CPU read data is not registered in the DAU and CPU        read data is available 8 ns after the start of the access then        4.5 ns are available for routing and any shallow logic before        the CPU read data is captured by the CPU (see Section 20.14.4).

The phases of CPU DIU read access are shown in FIG. 111. This matchesthe timing shown in Table 135.

20.14.10.2 Write Accesses

CPU writes are posted into a 1-deep write buffer in the DIU and writtento DRAM as shown below in FIG. 112.

The sequence of events is as follows:—

-   -   [1] The DIU signals that its buffer for CPU posted writes is        empty (and has been for some time in the case shown).    -   [2] The CPU asserts “cpu_diu_wdatavalid” to enable a write to        the DIU buffer and presents valid address, data and write mask.        The CPU considers the write posted and thus complete in the        cycle following [2] in the diagram below.    -   [3] The DIU stores the address/data/mask in its buffer and        indicates to the arbitration logic that a posted write wishes to        participate in any upcoming arbitration.    -   [4] Provided the CPU still has a pre-access entitlement left, or        is next in line for a round-robin award, a slot is arbitrated in        favour of the posted write. Note that posted CPU writes have        higher arbitration priority than simultaneous CPU reads.    -   [5] The DRAM write occurs.    -   [6] The earliest that “diu_cpu_write_rdy” can be re-asserted in        the “MSN1” state of the DRAM write. In the same cycle, having        seen the re-assertion, the CPU can asynchronously turn around        “cpu_diu_wdatavalid” and enable a subsequent posted write,        should it wish to do so. The timing of a non-CPU/non-CDU DIU        write access is shown below in FIG. 113.

Compared to a read access, write data is only available from therequester 4 cycles after the address. An extra cycle is used to ensurethat data is first registered in the DAU, before being despatched toDRAM. As a result, writes are pre-arbitrated 5 cycles in advance of themain arbitration decision to actually write the data to memory.

The diagram above shows the following sequence of events:—

-   -   [1] A non-CPU block signals a write request.    -   [2] A registered version of this is available to the DAU        arbitration logic.    -   [3] Write pre-arbitration occurs in favour of the requester.    -   [4] A write acknowledgment is returned by the DIU.    -   [5] The pre-arbitration will only be upheld if the requester        supplies 4 consecutive write data quarter-words, qualified by an        asserted wvalid flag.    -   [6] Provided this has happened, the main arbitration logic is in        a position at [6] to reconfirm the pre-arbitration decision.        Note however that such reconfirmation may have to wait a further        one or two DRAM accesses, if the write is pre-empted by a CPU        pre-access and/or a scheduled refresh.    -   [7] This is the earliest that the write to DRAM can occur.    -   Note that neither the arbitration at [8] nor the pre-arbitration        at [9] can award its respective slot to a non-CPU write, due to        the ban on back-to-back accesses.

The timing of a CDU DIU write access is shown overleaf in FIG. 114.

This is simular to a regular non-CPU write access, but uses page mode tocarry out 4 consecutive DRAM writes to contiguous addresses. As aconsequence, subsequent accesses are delayed by 6 cycles, as shown inthe diagram. Note that a new write can be pre-arbitrated at [10] in FIG.114.

20.14.11 Command Multiplexor Sub-Block TABLE 136 Command MultiplexorSub-block IO Definition Port name Pins I/O Description Clocks and Resetspclk 1 In System Colck prst_n 1 In System reset, synchronous active lowDIU Read Interface to SoPEC Units <unit>_diu_radr[21:5] 17 In Readaddress to DIU 17 bits wide (256-bit aligned word). diu_<unit>_rack 1Out Acknowledge from DIU that read request has been accepted and newread address can be placed on <unit>_diu_radr DIU Write Interface toSoPEC Units <unit>_diu_wadr[21:5] 17 In Write address to DIU except CPU,SCB, CDU 17 bits wide (256-bit aligned word) cpu_diu_wadr[21:4]] 22 InCPU Write address to DIU (128-bit aligned address.) cpu_diu_wmask 16 InByte enables for CPU write. cdu_diu_wadr[21:3] 19 In CDU Write addressto DIU 19 bits wide (64-bit aligned word) Addresses cannot cross a256-bit word DRAM boundary. diu_<unit>_wack 1 Out Acknowledge from DIUthat write request has been accepted and new write address can be placedon <unit>_diu_wadr Outputs to CPU Interface and Arbitration Logicsub-block re_arbitrate 1 Out Signalling telling the arbitration logic tochoose the next arbitration winner. re_arbitrate_wadv 1 Out Signaltelling the arbitration logic to choose the next arbitration winner fornon-CPU writes 2 timeslots in advance Debug Outputs to CPU Configurationand Arbitration Logic Sub-block write_sel 5 Out Signal indicating theSoPEC Unit for which the current write transaction is occurring.Encoding is described in Table . write_complete 1 Out Signal indicatingthat write transaction to SoPEC Unit indicated by write_sel is complete.Inputs from CPU Interface and Arbitration Logic sub-block arb_gnt 1 InSignal lasting 1 cycle which indicates arbitration has occurred andarb_sel is valid. arb_sel 5 In Signal indicating which requesting SoPECUnit has won arbitration. Encoding is described in Table . dir_sel 2 InSignal indicating which sense of access associated with arb_sel 00:issue non-CPU write 01: read winner 10: write winner 11: refresh winnerInputs from Read Write Multiplexor Sub-block write_data_valid 2 InSignal indicating that valid write data is available for the currentcommand. 00=not valid 01=CPU write data valid 10=non-CPU write datavalid 11=both CPU and non-CPU write data valid wdata 256 In 256-bitnon-CPU write data cpu_wdata 32 In 32-bit CPU write data Outputs to ReadWrite Multiplexor Sub-block write_data_accept 2 Out Signal indicatingthe Command Multiplexor has accepted the write data from the writemultiplexor 00=not valid 01=accepts CPU write data 10=accepts non-CPUwrite data 11=not valid Inputs from DCU dcu_dau_adv 1 In Signalindicating to DAU to supply next command to DCU dcu_dau_wadv 1 In Signalindicating to DAU to initiate next non-CPU write Outputs to DCUdau_dcu_adr[21:5] 17 Out Signal indicating the address for the DRAMaccess. This is a 256-bit aligned DRAM address. dau_dcu_rwn 1 Out Signalindicating the direction for the DRAM access (1=read, 0=write).dau_dcu_cduwpage 1 Out Signal indicating if access is a CDU write pagemode access (1=CDU page mode, 0=not CDU page mode). dau_dcu_refresh 1Out Signal indicating that a refresh command is to be issued. Ifasserted dau_dcu_adr, dau_dcu_rwn and dau_dcu_cduwpage are ignored.dau_dcu_wdata 256 Out 256-bit write data to DCU dau_dcu_wmask 32 OutByte encoded write data mask for 256-bit dau_dcu_wdata to DCU20.14.11.1 Command Multiplexor Sub-Block Description

The Command Multiplexor sub-block issues read, write or refresh commandsto the DCU, according to the SoPEC Unit selected for DRAM access by theArbitration Logic. The Command Multiplexor signals the Arbitration Logicto perform arbitration to select the next SoPEC Unit for DRAM access. Itdoes this by asserting the re_arbitrate signal. re_arbitrate is assertedwhen the DCU indicates on dcu_dau_adv that it needs the next command.

The Command Multiplexor is shown in FIG. 115.

Initially, the issuing of commands is described. Then the additionalcomplexity of handling non-CPU write commands arbitrated in advance isintroduced.

DAU-DCU Interface

See Section 20.14.5 for a description of the DAU-DCU interface.

Generating re_arbitrate

The condition for asserting re_arbitrate is that the DCU is looking foranother command from the DAU. This is indicated by dcu_dau_adv beingasserted.re _(—) arbitrate=dcu _(—) dau _(—) advInterface to SoPEC DIU Requestors

When the Command Multiplexor initiates arbitration by assertingre_arbitrate to the Arbitration Logic sub-block, the arbitration winneris indicated by the arb_sel[4:0] and dir_sel[1:0] signals returned fromthe Arbitration Logic. The validity of these signals is indicated byarb_gnt. The encoding of arb_sel[4:0] is shown in Table.

The value of arb_sel[4:0] is used to control the steering multiplexor toselect the DIU address of the winning arbitration requestor. The arb_gntsignal is decoded as an acknowledge, diu_<unit>_*ack back to the winningDIU requestor. The timing of these operations is shown in FIG. 116.adr[21:0] is the output of the steering multiplexor controlled byarb_sel[4:0]. The steering multiplexor can acknowledge DIU requestors insuccessive cycles.

Command Issuing Logic

The address presented by the winning SoPEC requestor from the steeringmultiplexor is presented to the command issuing logic together witharb_sel[4:0] and dir_sel[1:0].

The command issuing logic translates the winning command into thesignals required by the DCU. adr_(—)[21:0], arb_sel[4:0] anddir_sel[1:0] comes from the steering multiplexor. dau_dcu_adr[21:5] =adr[21:5] dau_dcu_rwn = (dir_sel[1:0] == read) dau_dcu_cduwpage =(arb_sel[4:0] == CDU write)  dau_dcu_refresh = (dir_sel[1:0]== refresh)dau_dcu_valid indicates that a valid command is available to the DCU.

For a write command, dau_dcu_valid will not be asserted until there isalso valid write data present. This is indicated by the signalwrite_data_valid[1:0] from the Read Write Data Multiplexor sub-block.

For a write command, the data issued to the DCU on dau_dcu_wdata[255:0]is multiplexed from cpu_wdata[31:0] and wdata[255:0] depending onwhether the write is a CPU or non-CPU write. The write data from theWrite Multiplexor for the CDU is available on wdata[63:0]. This datamust be issued to the DCU on dau_dcu_wdata[255:0]. wdata[63:0] is copiedto each 64-bit word of dau_dcu_wdata[255:0]. dau_dcu_wdata[255:0] =0x00000000 if (arb_sel[4:0]==CPU write) then   dau_dcu_wdata[31:0] =cpu_wdata[31:0] elsif (arb_sel[4:0]==CDU write)) then  dau_dcu_wdata[63:0] = wdata[63:0]   dau_dcu_wdata[127:64] =wdata[63:0]   dau_dcu_wdata[191:128] = wdata[63:0]  dau_dcu_wdata[255:192] = wdata[63:0] else   dau_dcu_wdata[255:0] =wdata[255:0]CPU Write Masking

The CPU write data bus is only 128 bits wide. cpu_diu_wmask[15:0]indicates how many bytes of that 128 bits should be written. Theassociated address cpu_diu_wadr[21:4] is a 128-bit aligned address. Theactual DRAM write must be a 256-bit access. The command multiplexorissues the 256-bit DRAM address to the DCU on dau_dcu_adr[21:5].cpu_diu_wadr[4] and cpu_diu_wmask[15:0] are used jointly to construct abyte write mask dau_dcu_wmask[31:0] for this 256-bit write access.

CDU Write Masking

The CPU performs four 64-bit word writes to 4 contiguous 256-bit DRAMaddresses with the first address specified by cdu_diu_wadr[21:3]. Thewrite address cdu_diu_wadr[21:5] is 256-bit aligned with bitscdu_diu_wadr[44:3] allowing the 64-bit word to be selected. If these 4DRAM words lie in the same DRAM row then an efficient access will beobtained.

The command multiplexor logic must issue 4 successive accesses to256-bit DRAM addresses cdu_diu_wadr[21:5],+1,+2,+3.

dau_dcu_wmask[31:0] indicates which 8 bytes (64-bits) of the 256-bitword are to be written.

dau_dcu_wmask[31:0] is calculated using cdu_diu_wadr[4:3] i.e. bits8*cdu_diu_wadr[4:3] to 8*(cdu_diu_wadr[4:3]+1)−1 ofdau_dcu_wmask[31:0]are asserted.

Arbitrating Non-CPU Writes in Advance

In the case of a non-CPU write commands, the write data must betransferred from the SoPEC requester before the write can occur.Arbitration should occur early to allow for any delay for the write datato be transferred to the DRAM.

FIG. 113 indicates that write data transfer over 64-bit busses will takea further 4 cycles after the address is transferred. The arbitrationmust therefore occur 4 cycles in advance of arbitration for readaccesses, FIG. 109 and FIG. 110, or for CPU writes FIG. 112. Arbitrationof CDU write accesses, FIG. 114, should take place 1 cycle in advance ofarbitration for read and CPU write accesses. To simplify implementationCDU write accesses are arbitrated 4 cycles in advance, similar to othernon-CPU writes.

The Command Multiplexor generates another version of re_arbitrate calledre_arbitrate_wadv based on the signal dcu_dau_wadv from the DCU. In the3 cycle DRAM access dcu_dau_adv and therefore re_arbitrate are assertedin the MSN2 state of the DCU state-machine. dcu_dau_wadv and thereforere_arbitrate_wadv will therefore be asserted in the following RST state,see FIG. 117. This matches the timing required for non-CPU writes shownin FIG. 113 and FIG. 114.

re_arbitrate_wadv causes the Arbitration Logic to perform an arbitrationfor non-CPU in advance. re_arbitrate = dcu_dau_adv re_arbitrate_wadv =dcu_dau_wadv

If the winner of this arbitration is a non-CPU write then arb_gnt isasserted and the arbitration winner is output on arb_sel[4:0] anddir_sel[1:0]. Otherwise arb_gnt is not asserted.

Since non-CPU write commands are arbitrated early, the non-CPU commandis not issued to the DCU immediately but instead written into an advancecommand register. if (arb_sel(4:0 == non-CPU write) then advance_cmd_register[3:0] = arb_sel[4:0]  advance_cmd_register[5:4] =dir_sel[1:0]  advance_cmd_register[27:6] = adr[21:0]

If a DCU command is in progress then the arbitration in advance of anon-CPU write command will overwrite the steering multiplexor input tothe command issuing logic. The arbitration in advance happens in the DCUMSN1 state. The new command is available at the steering multiplexor inthe MSN2 state. The command in progress will have been latched in theDRAM by MSN falling at the start of the MSN1 state.

Issuing Non-CPU Write Commands

The arb_sel[4:0] and dir_(—)[1:0] values generated by the ArbitrationLogic reflect the out of order arbitration sequence.

This out of order arbitration sequence is exported to the Read WriteData Multiplexor sub-block. This is so that write data in available intime for the actual write operation to DRAM. Otherwise a latency wouldbe introduced every time a write command is selected.

However, the Command Multiplexor must execute the command streamin-order. In-order command execution is achieved by waiting untilre_arbitrate has advanced to the non-CPU write timeslot from whichre_arbitrate_wadv has previously issued a non-CPU write written to theadvance command register.

If re_arbitrate_wadv arbitrates a non-CPU write in advance then withinthe Arbitration Logic the timeslot is marked to indicate whether a writewas issued.

When re_arbitrate advances to a write timeslot in the Arbitration Logicthen one of two actions can occur depending on whether the slot wasmarked by re_arbitrate_wadv to indicate whether a write was issued ornot.

-   -   Non-CPU write arbitrated by re_arbitrate_wadv

If the timeslot has been marked as having issued a write then thearbitration logic responds to re_arbitrate by issuing arb_sel[4:0],dir_sel[1:0] and asserting arb_gnt as for a normal arbitration butselecting a non-CPU write access. Normally, re_arbitrate does not issuenon-CPU write accesses. Non-CPU writes are arbitrated byre_arbitrate_wadv. dir_sel[1:0]==00 indicates a non-CPU write issued byre_arbitrate.

The command multiplexor does not write the command into the advancecommand register as it has already been placed there earlier byre_arbitrate_wadv. Instead, the already present write command in theadvance command register is issued when write_data_valid[1]=1. Note,that the value of arb_sel[4:0] issued by re_arbitrate could specify adifferent write than that in the advance command register since time hasadvanced. It is always the command in the advance command register thatis issued. The steering multiplexor in this case must not issue anacknowledge back to SoPEC requester indicated by the value ofarb_sel[4:0].   if (dir_sel[1:0] == 00) then   command_issuing_logic[27:0]        == advance_cmd_register[27:0]  else    command_issuing_logic[27:0]        ==steering_multiplexor[27:0]   ack = arb_gnt AND NOT (dir_sel[1:0] == 00)

-   -   Non-CPU write not arbitrated by re_arbitrate_wadv

If the timeslot has been marked as not having issued a write, there_arbitrate will use the un-used read timeslot selection to replace theun-used write timeslot with a read timeslot according to Section20.10.6.2 Unused read timeslots allocation.

The mechanism for write timeslot arbitration selects non-CPU writes inadvance. But the selected non-CPU write is stored in the CommandMultiplexor and issued when the write data is available. This means thateven if this timeslot is overwritten by the CPU reprogramming thetimeslot before the write command is actually issued to the DRAM, theoriginally arbitrated non-CPU write will always be correctly issued.

Accepting Write Commands

When a write command is issued then write_data_accept[1:0] is asserted.This tells the Write Multiplexor that the current write data has beenaccepted by the DRAM and the write multiplexor can receive write datafrom the next arbitration winner if it is a write.write_data_accept[1:0] differentiates between CPU and non-CPU writes. Awrite command is known to have been issued when re_arbitrate_wadv todecide on the next command is detected.

In the case of CDU writes the DCU will generate a signaldcu_dau_cduwaccept which tells the Command Multiplexor to issue awrite_data_accept[1]. This will result in the Write Multiplexorsupplying the next CDU write data to the DRAM.   write_data_accept[0] =RISING EDGE(re_arbitrate_wadv) AND command_issuing_logic(dir_sel[1]==1) AND command_issuing_logic(arb_sel[4:0]==CPU)   write_data_accept[1] =(RISING EDGE(re_arbitrate_wadv)  ANDcommand_issuing_logic(dir_sel[1]==1)  ANDcommand_issuing_logic(arb_sel[4:0]==non_CPU)) OR dcu_dau_cduwaccept==1

Debug logic output to CPU Configuration and Arbitration Logic sub-blockwrite_sel[4:0] reflects the value of arb_sel[4:0] at the command issuinglogic. The signal write complete is asserted when every any bit ofwrite_data_accept[1:0] is asserted.  write_complete  =  write_data_accept[0]  OR write_data_accept[0]write_sel[4:0] and write_complete are CPU readable from theDIUPerformance nad WritePerformance status registers. Whenwrite_complete is asserted write_sel[4:0] will indicate which writeaccess the DAU has issued.

20.14.12 CPU Configuration and Arbitration Logic Sub-Block TABLE 137 CPUConfiguration and Arbitration Logic Sub-block IO Definition Port namePins I/O Description Clocks and Resets Pclk 1 In System Clock prst_n 1In System reset, synchronous active low CPU Interface data and controlsignals cpu_adr[10:2] 9 In 9 bits (bits 10:2) are required to decode theconfiguration register address space. cpu_dataout 32 In Shared writedata bus from the CPU for DRAM and configuration data diu_cpu_data 32Out Configuration, status and debug read data bus to the CPUdiu_cpu_debug_valid 1 Out Signal indicating the data on the diu_cpu_databus is valid debug data. cpu_rwn 1 In Common read/not-write signal fromthe CPU cpu_acode 2 In CPU access code signals. cpu_acode[0] - Program(0)/Data (1) access cpu_acode[1] - User (0)/Supervisor (1) access TheDAU will only allow supervisor mode accesses to data space. cpu_diu_sel1 In Block select from the CPU. When cpu_diu_sel is high both cpu_adrand cpu_dataout are valid diu_cpu_rdy 1 Out Ready signal to the CPU.When diu_cpu_rdy is high it indicates the last cycle of the access. Fora write cycle this means cpu_dataout has been registered by the blockand for a read cycle this means the data on diu_cpu_data is valid.diu_cpu_berr 1 Out Bus error signal to the CPU indicating an invalidaccess. DIU Read Interface to SoPEC Units <unit>_diu_rreq 11 In SoPECunit requests DRAM read. DIU Write Interface to SoPEC Unitsdiu_cpu_write_rdy 1 In Indicator that CPU posted write buffer is empty.<unit>_diu_wreq 4 In Non-CPU SoPEC unit requests DRAM write. Inputs fromCommand Multiplexor sub-block re_arbitrate 1 In Signal telling thearbitration logic to choose the next arbitration winner.re_arbitrate_wadv 1 In Signal telling the arbitration logic to choosethe next arbitration winner for non-CPU writes 2 timeslots in advanceOutputs to DCU dau_dcu_msn2stall 1 Out Signal indicating from DAUArbitration Logic which when asserted stalls DCU in MSN2 state. Inputsfrom Read and Write Multiplexor sub-block read_cmd_rdy 2 In Signalindicating that read multiplexor is ready for next read read command.00=not ready 01=ready for CPU read 10=ready for non-CPU read 11=readyfor both CPU and non-CPU reads write_cmd_rdy 2 In Signal indicating thatwrite multiplexor is ready for next write command. 00=not ready 01=readyfor CPU write 10=ready for non-CPU write 11=ready for both CPU andnon-CPU write Outputs to other DAU sub-block s arb_gnt 1 In Signallasting 1 cycle which indicates arbitration has occurred and arb_sel isvalid. arb_sel 5 In Signal indicating which requesting SoPEC Unit haswon arbitration. Encoding is described in Table . dir_sel 2 In Signalindicating which sense of access associated with arb_sel 00: issuenon-CPU write 01: read winner 10: write winner 11: refresh winner DebugInputs from Read-Write Multiplexor sub-block read_sel 5 In Signalindicating the SoPEC Unit for which the current read transaction isoccurring. Encoding is described in Table . read_complete 1 In Signalindicating that read transaction to SoPEC Unit indicated by read_sel iscomplete. Debug Inputs from Command Multiplexor sub-block write_sel 5 InSignal indicating the SoPEC Unit for which the current write transactionis occurring. Encoding is described in Table . write_complete 1 InSignal indicating that write transaction to SoPEC Unit indicated bywrite_sel is complete. Debug Inputs from DCU dcu_dau_refreshcomplete 1In Signal indicating that the DCU has completed a refresh. Debug Inputsfrom DAU IO various n In Various DAU IO signals which can be monitoredin debug mode

The CPU Interface and Arbitration Logic sub-block is shown in FIG. 118.

20.14.12.1 CPU Interface and Configuration Registers Description

The CPU Interface and Configuration Registers sub-block provides for theCPU to access DAU specific registers by reading or writing to the DAUaddress space.

The CPU subsystem bus interface is described in more detail in Section11.4.3. The DAU block will only allow supervisor mode accesses to dataspace (i.e. cpu_acode[1:0]=b11). All other accesses will result indiu_cpu_berr being asserted.

The configuration registers described in Section 20.14.9 TABLE 130 DAUconfiguration registers Address (DIU_base+) Register #bits ResetDescription Reset 0x00 Reset 1 0x1 A write to this register causes areset of the DIU. This register can be read to indicate the reset state:0 - reset in progress 1 - reset not in progress Refresh 0x04RefreshPeriod 9 0x063 Refresh controller. When set to 0 refresh is off,otherwise the value indicates the number of cycles, less one, betweeneach refresh. [Note that for a system clock frequency of 160 MHz, avalue exceeding 0x63 (indicating a 100-cycle refresh period) should notbe programmed, or the DRAM will malfunction.] Timeslot allocation andcontrol 0x08 NumMainTimeslots 6 0x01 Number of main timeslots (1-64)less one 0x0C CPUPreAccessTimes 4 0x0 (CPUPreAccessTimeslots + 1) mainlots slots out of a total of (CPUTotalTimeslots + 1) are preceded by aCPU access. 0x10 CPUTotalTimeslots 4 0x0 (CPUPreAccessTimeslots + 1)main slots out of a total of (CPUTotalTimeslots + 1) are preceded by aCPU access. 0x100-0x1FC MainTimeslot[63:0] 64x4 [63:1][3:0] = 0x0Programmable main timeslots (up to [0][3:0] = 0xE 64 main timeslots).0x200 ReadRoundRobinLevel 12 0x000 For each read requester plus refresh0 = level1 of round-robin 1 = level2 of round-robin The bit order isdefined in Table . 0x204 EnableCPURound 1 0x1 Allows the CPU toparticpate in the Robin unused read round-robin scheme. If disabled, theshared CPU/refresh round-robin position is dedicated solely to refresh.0x208 RotationSync 1 0x1 Writing 0, followed by 1 to this bit allows thetimeslot rotation to advance on a cycle basis which can be determined bythe CPU. 0x20C minNonCPUReadAdr 12 0x800 12 MSBs of lowest DRAM addresswhich may be read by non-CPU requesters. 0x210 minDWUWriteAdr 12 0x80012 MSBs of lowest DRAM address which may be written to by the DWU. 0x214minNonCPUWriteAdr 12 0x800 12 MSBs of lowest DRAM address which may bewritten to by non-CPU requesters other than the DWU. Debug 0x300DebugSelect[11:2] 10 0x304 Debug address select. Indicates the addressof the register to report on the diu_cpu_data bus when it is nototherwise being used. when this signal carries debug information thesignal diu_cpu_debug_valid will be asserted. Debug: arbitration andperformance 0x304 ArbitrationHistory 22 — Bit 0 = arb_gnt Bit 1 =arb_executed Bit 6:2 = arb_sel[4:0] Bit 12:7 = timeslot_number[5:0] Bit15:13 = access_type[2:0] Bit 16 = back2back_non_cpu_write Bit 17 =sticky_back2back_non_cpu_write (Sticky version of same, cleared onreset.) Bit 18 = rotation_sync Bit 20:19 = rotation_state Bit 21 =sticky_invalid_non_cpu_adr See Section 20.14.9.2 DIU Debug for adescription of the fields. Read only register. 0x308 DIUPerformance 31 —Bit 0 = cpu_diu_rreq Bit 1 = scb_diu_rreq Bit 2 = cdu_diu_rreq Bit 3 =cfu_diu_rreq Bit 4 = lbd_diu_rreq Bit 5 = sfu_diu_rreq Bit 6 =td_diu_rreq Bit 7 = tfs_diu_rreq Bit 8 = hcu_diu_rreq Bit 9 =dnc_diu_rreq Bit 10 = llu_diu_rreq Bit 11 = pcu_diu_rreq Bit 12 =cpu_diu_wreq Bit 13 = scb_diu_wreq Bit 14 = cdu_diu_wreq Bit 15 =sfu_diu_wreq Bit 16 = dwu_diu_wreq Bit 17 = refresh_req Bit 22:18 =read_sel[4:0] Bit 23 = read_complete Bit 28:24 = write_sel[4:0] Bit 29 =write_complete Bit 30 = dcu_dau_refreshcomplete See Section 20.14.9.2DIU Debug for a description of the fields. Read only register. Debug DIUread requesters interface signals 0x30C CPUReadInterface 25 — Bit 0 =cpu_diu_rreq Bit 22:1 = cpu_adr[21:0] Bit 23 = diu_cpu_rack Bit 24 =diu_cpu_rvalid Read only register. 0x310 SCBReadInterface 20 Bit 0 =scb_diu_rreq Bit 17:1 = scb_diu_radr[21:5] Bit 18 = diu_scb_rack Bit 19= diu_scb_rvalid Read only register. 0x314 CDUReadInterface 20 — Bit 0 =cdu_diu_rreq Bit 17:1 = cdu_diu_radr[21:5] Bit 18 = diu_cdu_rack Bit 19= diu_cdu_rvalid Read only register. 0x318 CFUReadInterface 20 — Bit 0 =cfu_diu_rreq Bit 17:1 = cfu_diu_radr[21:5] Bit 18 = diu_cfu_rack Bit 19= diu_cfu_rvalid Read only register. 0x31C LBDReadInterface 20 — Bit 0 =lbd_diu_rreq Bit 17:1 = lbd_diu_radr[21:5] Bit 18 = diu_lbd_rack Bit 19= diu_lbd_rvalid Read only register. 0x320 SFUReadInterface 20 — Bit 0 =sfu_diu_rreq Bit 17:1 = sfu_diu_radr[21:5] Bit 18 = diu_sfu_rack Bit 19= diu_sfu_rvalid Read only register. 0x324 TDReadInterface 20 — Bit 0 =td_diu_rreq Bit 17:1 = td_diu_radr[21:5] Bit 18 = diu_td_rack Bit 19 =diu_td_rvalid Read only register. 0x328 TFSReadInterface 20 — Bit 0 =tfs_diu_rreq Bit 17:1 = tfs_diu_radr[21:5] Bit 18 = diu_tfs_rack Bit 19= diu_tfs_rvalid Read only register. 0x32C HCUReadInterface 20 — Bit 0 =hcu_diu_rreq Bit 17:1 = hcu_diu_radr[21:5] Bit 18 = diu_hcu_rack Bit 19= diu_hcu_rvalid Read only register. 0x330 DNCReadInterface 20 — Bit 0 =dnc_diu_rreq Bit 17:1 = dnc_diu_radr[21:5] Bit 18 = diu_dnc_rack Bit 19= diu_dnc_rvalid Read only register. 0x334 LLUReadInterface 20 — Bit 0 =llu_diu_rreq Bit 17:1 = lluu_diu_radr[21:5] Bit 18 = diu_llu_rack Bit 19= diu_llu_rvalid Read only register. 0x338 PCUReadInterface 20 — Bit 0 =pcu_diu_rreq Bit 17:1 = pcu_diu_radr[21:5] Bit 18 = diu_pcu_rack Bit 19= diu_pcu_rvalid Read only register. Debug DIU write requestersinterface signals 0x33C CPUWriteInterface 27 — Bit 0 = cpu_diu_wreq Bit22:1 = cpu_adr[21:0] Bit 24:23 = cpu_diu_wmask[1:0] Bit 25 =diu_cpu_wack Bit 26 = cpu_diu_wvalid Read only register. 0x340SCBWriteInterface 20 — Bit 0 = scb_diu_wreq Bit 17:1 =scb_diu_wadr[21:5] Bit 18 = diu_scb_wack Bit 19 = scb_diu_wvalid Readonly register. 0x344 CDUWriteInterface 22 — Bit 0 = cdu_diu_wreq Bit19:1 = cdu_diu_wadr[21:3] Bit 20 = diu_cdu_wack Bit 21 = cdu_diu_wvalidRead only register. 0x348 SFUWriteInterface 20 — Bit 0 = sfu_diu_wreqBit 17:1 = sfu_diu_wadr[21:5] Bit 18 = diu_sfu_wack Bit 19 =sfu_diu_wvalid Read only register. 0x34C DWUWriteInterface 20 — Bit 0 =dwu_diu_wreq Bit 17:1 = dwu_diu_wadr[21:5] Bit 18 = diu_dwu_wack Bit 19= dwu_diu_wvalid Read only register. Debug DAU-DCU interface signals0x350 DAU-DCUInterface 25 — Bit 16:0 = dau_dcu_adr[21:5] Bit 17 =dau_dcu_rwn Bit 18 = dau_dcu_cduwpage Bit 19 = dau_dcu_refresh Bit 20 =dau_dcu_msn2stall Bit 21 = dcu_dau_adv Bit 22 = dcu_dau_wadv Bit 23 =dcu_dau_refreshcomplete Bit 24 = dcu_dau_rvalid Read only register.are implemented here.20.14.12.2 Arbitration Logic Description

Arbitration is triggered by the signal re_arbitrate from the CommandMultiplexor sub-block with the signal arb_gnt indicating thatarbitration has occurred and the arbitration winner is indicated byarb_sel[4:0]. The encoding of arb_sel[4:0] is shown in Table. The signaldir_sel[1:0] indicates if the arbitration winner is a read, write orrefresh. Arbitration should complete within one clock cycle so arb_gntis normally asserted the clock cycle after re_arbitrate and stays highfor 1 clock cycle. arb_sel[4:0] and dir_sel[1:0] remain persistent untilarbitration occurs again. The arbitration timing is shown in FIG. 119.

20.14.12.2.1 Rotation Synchronisation

A configuration bit, RotationSync, is used to initialise advancementthrough the timeslot rotation, in order that the CPU will know, on acycle basis, which timeslot is being arbitrated. This is essential fordebug purposes, so that exact arbitration sequences can be reproduced.

In general, if RotationSync is set, slots continue to be arbitrated inthe regular order specified by the timeslot rotation. When the bit iscleared, the current rotation continues until the slot pointers for pre-and main arbitration reach zero. The arbitration logic then grants DRAMaccess exclusively to the CPU and refreshes.

When the CPU again writes to RotationSync to cause a 0-to-1 transitionof the bit, the rdy acknowledgment back to the CPU for this write willbe exactly coincident with the RST cycle of the initial refresh whichheralds the enabling of a new rotation. This refresh, along with thesecond access which can be either a CPU pre-access or a refresh,(depending on the CPU's request inputs), form a 2-access “preamble”before the first non-CPU requester in the new rotation can be serviced.This preamble is necessary to give the write pre-arbitration thenecessary head start on the main arbitration, so that write data can beloaded in time. See FIG. 105 below. The same preamble procedure isfollowed when emerging from reset.

The alignment of rdy with the commencement of the rotation ensures thatthe CPU is always able to calculate at any point how far a rotation hasprogressed. RotationSync has a reset value of 1 to ensure that thedefault power-up rotation can take place.

Note that any CPU writes to the DIU's other configuration registersshould only be made when RotationSync is cleared. This ensures thataccesses by non-CPU requesters to DRAM are not affected by partialconfiguration updates which have yet to be completed.

20.14.12.2.2 Motivation for Rotation Synchronisation

The motivation for this feature is that communications with SoPEC fromexternal sources are synchronised to the internal clock of our positionwithin a DIU full timeslot rotation. This means that if an externalsource told SoPEC to start a print 3 separate times, it would likely beat three different points within a full DIU rotation. This differencemeans that the DIU arbitration for each of the runs would be different,which would manifest itself externally as anomalous or inconsistentprint performance. The lack of reproducibility is the problem here.

However, if in response to the external source saying to start theprint, we caused the internal to pass through a known state at a fixedtime offset to other internal actions, this would result in reproducibleprints. So, the plan is that the software would do a rotationsynchronise action, then writes “Go” into various PEP units to cause theprints. This means the DIU state will be the identical with respect tothe PEP units state between separate runs.

20.14.12.2.3 Wind-Down Protocol When Rotation Synchronisation isInitiated

When a zero is written to “RotationSync”, this initiates a “wind-downprotocol” in the DIU, in which any rotation already begun must be fullycompleted. The protocol implements the following sequence:—

-   -   The pre-arbitration logic must reach the end of whatever        rotation it is on and stop pre-arbitrating.    -   Only when this has happened, does the main arbitration consider        doing likewise with its current rotation. Note that the main        arbitration lags the pre-arbitration by at least 2 DRAM        accesses, subject to variation by CPU pre-accesses and/or        scheduled refreshes, so that the two arbitration processes are        sometimes on different rotations.    -   Once the main arbitration has reached the end of its rotation,        rotation synchronisation is considered to be fully activated.        Arbitration then proceeds as outlined in the next section.        20.14.12.2.4 Arbitration During Rotation Synchronisation

Note that when RotationSync is ‘0’ and, assuming the terminatingrotation has completely drained out, then DRAM arbitration is grantedaccording to the following fixed priority order:—ScheduledRefresh->CPU(W)->CPU(R)->Default Refresh.

CPU pre-access counters play no part in arbitration during this period.It is only subsequently, when emerging from rotation sync, that they arereloaded with the values of CPUPreAccessTimeslots and CPUTotalTimeslotsand normal service resumes.

20.14.12.2.5 Timeslot-Based Arbitration

Timeslot-based arbitration works by having a pointer point to thecurrent timeslot. This is shown in FIG. 95 repeated here as FIG. 121.When re-arbitration is signaled the arbitration winner is the currenttimeslot and the pointer advances to the next timeslot. Each timeslotdenotes a single access. The duration of the timeslot depends on theaccess.

If the SoPEC Unit assigned to the current timeslot is not requestingthen the unused timeslot arbitration mechanism outlined in Section20.10.6 is used to select the arbitration winner. Note that this unusedslot re-allocation is guaranteed to produce a result, because of theinclusion of refresh in the round-robin scheme.

Pseudo-code to represent arbitration is given below:     if re_arbitrate== 1 then        arb_gnt = 1      if current timeslot requesting then        choose(arb_sel,  dir_sel)  at  current timeslot      else //un-used timeslot scheme          choose winner  according  to  un-usedtimeslot allocation of Section 20.10.6        arb_gnt = 020.14.12.3 Arbitrating Non-CPU Writes in Advance

In the case of a non-CPU write commands, the write data must betransferred from the SoPEC requester before the write can occur.Arbitration should occur early to allow for any delay for the write datato be transferred to the DRAM.

FIG. 113 indicates that write data transfer over 64-bit busses will takea further 4 cycles after the address is transferred. The arbitrationmust therefore occur 4 cycles in advance of arbitration for readaccesses, FIG. 109 and FIG. 110, or for CPU writes FIG. 112. Arbitrationof CDU write accesses, FIG. 114, should take place 1 cycle in advance ofarbitration for read and CPU write accesses. To simplify implementationCDU write accesses are arbitrated 4 cycles in advance, similar to othernon-CPU writes.

The Command Multiplexor generates a second arbitration signalre_arbitrate_wadv which initiates the arbitration in advance of non-CPUwrite accesses.

The timeslot scheme is then modified to have 2 separate pointers:

-   -   re_arbitrate can arbitrate read, refresh and CPU read and write        accesses according to the position of the current timeslot        pointer.    -   re_arbitrate_wadv can arbitrate only non-CPU write accesses        according to the position of the write lookahead pointer.

Pseudo-code to represent arbitration is given below: //re_arbitrate if(re_arbitrate == 1) AND (current timeslot pointer!= non- CPU write) then arb_gnt = 1  if current timeslot requesting then    choose(arb_sel,dir_sel) at current timeslot  else // un-used read timeslot scheme  choose winner according to un-used read timeslot allocation of Section20.10.6.2

If the SoPEC Unit assigned to the current timeslot is not requestingthen the unused read timeslot arbitration mechanism outlined in Section20.10.6.2 is used to select the arbitration winner. //re_arbitrate_wadvif (re_arbitrate_wadv == 1) AND (write lookahead timeslot pointer ==non-CPU write) then  if write lookahead timeslot requesting then   choose(arb_sel, dir_sel) at write lookahead timeslot   arb_gnt = 1 elsif un-used write timeslot scheme has a requestor   choose winneraccording to un-used write timeslot allocation of Section 20.10.6.1  arb_gnt = 1  else   //no arbitration winner   arb_gnt = 0

-   -   re_arbitrate is generated in the MSN2 state of the DCU        state-machine, whereas    -   re_arbitrate_wadv is generated in the RST state. See FIG. 103.

The write lookahead pointer points two timeslots in advance of thecurrent timeslot pointer. Therefore re_arbitrate_wadv causes theArbitration Logic to perform an arbitration for non-CPU two timeslots inadvance. As noted in Table, each timeslot lasts at least 3 cycles.Therefor re_arbitrate_wadv arbitrates at least 4 cycles in advance.

At initialisation, the write lookahead pointer points to the firsttimeslot. The current timeslot pointer is invalid until the writelookahead pointer advances to the third timeslot when the currenttimeslot pointer will point to the first timeslot. Then both pointersadvance in tandem.

Some accesses can be preceded by a CPU access as in Table. These CPUaccesses are not allocated timeslots. If this is the case the timeslotwill last 3 (CPU access)+3 (non-CPU access)=6 cycles. In that case, asecond write lookahead pointer, the CPU pre-access write lookaheadpointer, is selected which points only one timeslot in advance.re_arbitrate_wadv will still arbitrate 4 cycles in advance.

20.14.12.3.1 Issuing Non-CPU Write Commands

Although the Arbitration Logic will arbitrate non-CPU writes in advance,the Command Multiplexor must issue all accesses in the timeslot order.This is achieved as follows:

If re_arbitrate_wadv arbitrates a non-CPU write in advance then withinthe Arbitration Logic the timeslot is marked to indicate whether a writewas issued. //re_arbitrate_wadv if (re_arbitrate_wadv == 1) AND (writelookahead timeslot pointer == non-CPU write) then  if write lookaheadtimeslot requesting then    choose(arb_sel, dir_sel) at write lookaheadtimeslot   arb_gnt = 1   MARK_timeslot = 1  elsif un-used write timeslotscheme has a requestor   choose winner according to un-used writetimeslot allocation of Section 20.10.6.1   arb_gnt = 1   MARK_timeslot =1  else   //no pre-arbitration winner   arb_gnt = 0   MARK_timeslot = 0

When re_arbitrate advances to a write timeslot in the Arbitration Logicthen one of two actions can occur depending on whether the slot wasmarked by re_arbitrate_wadv to indicate whether a write was issued ornot.

-   -   Non-CPU write arbitrated by re_arbitrate_wadv

If the timeslot has been marked as having issued a write then thearbitration logic responds to re_arbitrate by issuing arb_sel[4:0],dir_sel[1:0] and asserting arb gnt as for a normal arbitration butselecting a non-CPU write access. Normally, re_arbitrate does not issuenon-CPU write accesses. Non-CPU writes are arbitrated byre_arbitrate_wadv. dir_sel[1:0]==00 indicates a non-CPU write issued byre_arbitrate.

-   -   Non-CPU write not arbitrated by re_arbitrate_wadv

If the timeslot has been marked as not having issued a write, there_arbitrate will use the un-used read timeslot selection to replace theun-used write timeslot with a read timeslot according to Section20.10.6.2 Unused read timeslots allocation. //re_arbitrate except fornon-CPU writes if (re_arbitrate == 1) AND (current timeslot pointer!=non- CPU write) then  arb_gnt = 1  if current timeslot requesting then   choose(arb_sel, dir_sel) at current timeslot  else // un-used readtimeslot scheme   choose winner according to un-used read timeslotallocation of Section 20.10.6.2   arb_gnt = 1 //non-CPU write MARKED asissued elsif (re_arbitrate == 1) AND (current timeslot pointer ==non-CPU write) AND    (MARK_timeslot == 1) then    //indicate to CommandMultiplexor that non-CPU write has been arbitrated in    //advance   arb_gnt = 1    dir_sel[1:0] == 00 //non-CPU write not MARKED asissued elsif (re_arbitrate == 1) AND (current timeslot pointer ==non-CPU write) AND    (MARK_timeslot == 0) then   choose winneraccording to un-used read timeslot allocation of Section 20.10.6.2  arb_gnt = 120.14.12.4 Flow Control

If read commands are to win arbitration, the Read Multiplexor must beready to accept the read data from the DRAM. This is indicated by theread_cmd_rdy[1:0] signal. read_cmd_rdy[1:0] supplies flow control fromthe Read Multiplexor.  read_cmd_rdy[0]==1 //Read multiplexor ready forCPU read  read_cmd_rdy[1]==1 //Read multiplexor ready for non-CPU read

The Read Multiplexor will normally always accept CPU reads, see Section20.14.13.1, so read_cmd_rdy[0]==1 should always apply.

Similarly, if write commands are to win arbitration, the WriteMultiplexor must be ready to accept the write data from the winningSoPEC requestor. This is indicated by the write_cmd_rdy[1:0] signal.write_cmd_rdy[1:0] supplies flow control from the Write Multiplexor. write_cmd_rdy[0]==1 //Write multiplexor ready for CPU write write_cmd_rdy[1]==1 //Write multiplexor ready for non- CPU write

The Write Multiplexor will normally always accept CPU writes, seeSection 20.14.13.2, so write_cmd_rdy[0]==1 should always apply.

Non-CPU Read Flow Control

If re_arbitrate selects an access then the signal dau_dcu_msn2stall isasserted until the Read Write Multiplexor is ready.

arb_gnt is not asserted until the Read Write Multiplexor is ready.

This mechanism will stall the DCU access to the DRAM until the ReadWrite Multiplexor is ready to accept the next data from the DRAM in thecase of a read. //other access flow control dau_dcu_msn2stall =(((re_arbitrate selects CPU read) AND  read_cmd_rdy[0]==0) OR       (re_arbitrate  selects  non-CPU read) AND  read_cmd_rdy[1]==0))arb_gnt not asserted until dau_dcu_msn2stall de-asserts20.14.12.5 Arbitration Hierarchy

CPU and refresh are not included in the timeslot allocations defined inthe DAU configuration registers of Table.

The hierarchy of arbitration under normal operation is

-   a. CPU access-   b. Refresh access-   c. Timeslot access.

This is shown in FIG. 124. The first DRAM access issued after reset mustbe a refresh.

As shown in FIG. 118, the DIU request signals <unit>_diu_rreq,<unit>_diu_wreq are registered at the input of the arbitration block toease timing. The exceptions are the refresh_req signal, which isgenerated locally in the sub-block and cpu_diu_rreq. The CPU readrequest signal is not registered so as to keep CPU DIU read accesslatency to a minimum. Since CPU writes are posted, cpu_diu_wreq isregistered so that the DAU can process the write at a later juncture.The arbitration logic is coded to perform arbitration of non-CPUrequests first and then to gate the result with the CPU requests. Inthis way the CPU can make the requests available late in the arbitrationcycle.

Note that when RotationSync is set to ‘0’, a modified hierarchy ofarbitration is used. This is outlined in section 20.14.12.2.3 on page280.

20.14.12.6 Timeslot Access

The basic timeslot arbitration is based on the MainTimeslotconfiguration registers. Arbitration works by the timeslot pointed to byeither the current or write lookahead pointer winning arbitration. Thepointers then advance to the next timeslot. This was shown in FIG. 90.

Each main timeslot pointer gets advanced each time it is accessedregardless of whether the slot is used.

20.14.12.7 Unused Timeslot Allocation

If an assigned slot is not used (because its corresponding SoPEC Unit isnot requesting) then it is reassigned according to the scheme describedin Section 20.10.6.

Only used non-CPU accesses are reallocated. CDU write accesses cannot beincluded in the unused timeslot allocation for write as CDU accessestake 6 cycles. The write accesses which the CDU write could otherwisereplace require only 3 or 4 cycles.

Unused write accesses are re-allocated according to the fixed priorityscheme of Table. Unused read timeslots are re-allocated according to thetwo-level round-robin scheme described in Section 20.10.6.2.

A pointer points to the most recently re-allocated unit in each of theround-robin levels. If the unit immediately succedling the pointer isrequesting, then this unit wins the arbitration and the pointer isadvanced to reflect the new winner. If this is not the case, then thesubsequent units (wrapping back eventually to the pointed unit) in thelevel 1 round-robin are examined. When a requesting unit is found thisunit wins the arbitration and the pointer is adjusted. If no unit isrequesting then the pointer does not advance and the second level ofround-robin is examined in a similar fashion. In the followingpseudo-code the bit indices are for the ReadRoundRobinLevelconfiguration register described in Table.   //choose the winningarbitration level   level1 = 0   level2 = 0   for i = 0 to 11    ifunit(i) requesting AND ReadRoundRobinLevel(i) = 0 then    level1 = 1   if unit(i) requesting AND ReadRoundRobinLevel(i) = 1 then    level2 =1

Round-robin arbitration is effectively a priority assignment with theunits assigned a priority according to the round-robin order of Tablebut starting at the unit currently pointed to. //levelptr is pointer ofselected round robin level  priority is array 0 to 11 // index 0 isSCBR(0) etc. from Table  //assign decreasing priorities from the currentpointer; maximum priority is 11  for i = 1 to 12    priority(levelptr +i) = 12 − i   i++

The arbitration winner is the one with the highest priority provided itis requesting and its ReadRoundRobinLevel bit points to the chosenlevel. The levelptr is advanced to the arbitration winner.

The priority comparison can be done in the hierarchical manner shown inFIG. 125.

20.14.12.8 How Non-CPU Address Restrictions Affect Arbitration

Recall from Table “DAU configuration registers,” on page 288, “DAUconfiguration registers,” on page 268 that there are minimum valid DRAMaddresses for non-CPU accesses, defined by minNonCPUReadAdr,minDWUWriteAdr and minNonCPUWriteAdr. Similarly, a non-CPU requester maynot try to access a location above the high memory mark.

To ensure compliance with these address restrictions, the following DIUresponse occurs for any incorrectly addressed non-CPU writes:—

-   -   Issue a write acknowledgment at pre-arbitration time, to prevent        the write requester from hanging.    -   Disregard the incoming write data and write valids and void the        pre-arbitration.    -   Subsequently re-allocate the write slot at main arbitration time        via the round robin.

For any incorrectly addressed non-CPU reads, the response is:—

-   -   Arbitrate the slot in favour of the scheduled, misbehaving        requester.    -   Issue the read acknowledgement and rvalids to keep the requester        from hanging.    -   Intercept the read data coming from the DCU and send back all        zeros instead.

If an invalidly addressed non-CPU access is attempted, then a stickybit, sticky_invalid_non_cpu_adr, is set in the ArbitrationHistoryconfiguration register. See Table n page 293 on page 275 for details.

20.14.12.9 Refresh Controller Description

The refresh controller implements the functionality described in detailin Section 20.10.5. Refresh is not included in the timeslot allocations.

CPU and refresh have priority over other accesses. If the refreshcontroller is requesting i.e. refresh_req is asserted, then the refreshrequest will win any arbitration initiated by re_arbitrate. When therefresh has won the arbitration refresh_req is de-asserted.

The refresh counter is reset to RefreshPeriod[8:0] i.e. the number ofcycles between each refresh. Every time this counter decrements to 0, arefresh is issued by asserting refresh_req. The counter immediatelyreloads with the value in RefreshPeriod[8:0] and continues itscountdown. It does not wait for an acknowledgment, since the priority ofa refresh request supersedes that of any pending non-CPU access and itwill be serviced immediately. In this way, a refresh request isguaranteed to occur every (RefreshPeriod[8:0]+1) cycles. A given refreshrequest may incur some incidental delay in being serviced, due toalignment with DRAM accesses and the possibility of a higher-priorityCPU pre-access.

Refresh is also included in the unused read and write timeslotallocation, having second option on awards to a round-robin positionshared with the CPU. A refresh issued as a result of an unused timeslotallocation also causes the refresh counter to reload with the value inRefreshPeriod[8:0]. The first access issued by the DAU after reset mustbe a refresh. This assures that refreshes for all DRAM words fall withinthe required 3.2 ms window.  //issue a refresh request if counterreaches 0 or at reset or for re-allocated slot  if RefreshPeriod != 0AND (refresh_cnt == 0 OR    diu_soft_reset_n == 0 OR          prst_n      ==0 OR unused_timeslot_allocation == 1) then   refresh_req = 1 //de-assert refresh request when refresh acked  else if refresh_ack ==1 then   refresh_req = 0  //refresh counter if refresh_cnt == 0 ORdiu_soft_reset_n == 0 OR prst_n ==0           ORunused_timeslot_allocation ==           1 then   refresh_cnt =RefreshPeriod  else   refresh_cnt = refresh_cnt − 1

Refresh can preceded by a CPU access in the same way as any otheraccess. This is controlled by the CPUPreAccessTimeslots andCPUTotalTimeslots configuration registers. Refresh will therefore notaffect CPU performance. A sequence of accesses including refresh mighttherefore be CPU, refresh, CPU, actual timeslot.

20.14.12.10 CPU Timeslot Controller Description

CPU accesses have priority over all other accesses. CPU access is notincluded in the timeslot allocations. CPU access is controlled by theCPUPreAccessTimeslots and CPUTotalTimeslots configuration registers.

To avoid the CPU having to wait for its next timeslot it is desirable tohave a mechanism for ensuring that the CPU always gets the nextavailable timeslot without incurring any latency on the non-CPUtimeslots.

This is be done by defining each timeslot as consisting of a CPU accesspreceding a non-CPU access. Two counters of 4-bits each are definedallowing the CPU to get a maximum of (CPUPreAccessTimeslots+1)pre-accesses out of a total of (CPUTotalTimeslots+1) main slots. Atimeslot counter starts at CPUTotalTimeslots and decrements everytimeslot, while another counter starts at CPUPreAccessTimeslots anddecrements every timeslot in which the CPU uses its access. If thepre-access entitlement is used up before (CPUTotalTimeslots+1) slots, nofurther CPU accesses are allowed. When the CPUTotalTimeslots counterreaches zero both counters are reset to their respective initial values.

When CPUPreAccessTimeslots is set to zero then only one pre-access willoccur during every (CPUTotalTimeslots+1) slots.

20.14.12.10.1 Conserving CPU Pre-Accesses

In section 20.10.6.2.1 on page 249, it is described how the CPU can beallowed participate in the unused read round-robin scheme. When enabledby the configuration bit EnableCPURoundRobin, the CPU shares a jointposition in the round robin with refresh. In this case, the CPU haspriority, ahead of refresh, in availing of any unused slot awarded tothis position.

Such CPU round-robin accesses do not count towards depleting the CPU'squota of pre-accesses, specified by CPUPreAccessTimeslots. Note that inorder to conserve these pre-accesses, the arbitration logic, when facedwith the choice of servicing a CPU request either by a pre-access or byan immediately following unused read slot which the CPU is poised towin, will opt for the latter.

20.14.13 Read and Write Data Multiplexor Sub-Block TABLE 138 Read andWrite Multiplexor Sub-block IO Definition Port name Pins I/O DescriptionClocks and Resets Pclk 1 In System Clock prst_n 1 In System reset,synchronous active low DIU Read Interface to SoPEC Units diu_data 64 OutData from DIU to SoPEC Units except CPU. First 64-bits is bits 63:0 of256 bit word Second 64-bits is bits 127:64 of 256 bit word Third 64-bitsis bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256bit word dram_cpu_data 256 Out 256-bit data from DRAM to CPU.diu_<unit>_rvalid 1 Out Signal from DIU telling SoPEC Unit that validread data is on the diu_data bus DIU Write Interface to SoPEC Units<unit>_diu_data 64 In Data from SoPEC Unit to DIU except CPU. First64-bits is bits 63:0 of 256 bit word Second 64-bits is bits 127:64 of256 bit word Third 64-bits is bits 191:128 of 256 bit word Fourth64-bits is bits 255:192 of 256 bit word cpu_diu_wdatat 128 In Write datafrom CPU to DIU. <unit>_diu_wvalid 1 In Signal from SoPEC Unitindicating that data on <unit>_diu_data is valid. Note that “unit”refers to non-CPU requesters only. cpu_diu_wdatavalid 1 In Write enablefor the CPU posted write buffer. Also confirms the validity ofcpu_diu_wdata. diu_cpu_write_rdy 1 Out Indicator that the CPU postedwrite buffer is empty. Inputs from CPU Configuration and ArbitrationLogic Sub-block arb_gnt 1 In Signal lasting 1 cycle which indicatesarbitration has occurred and arb_sel is valid. arb_sel 5 In Signalindicating which requesting SoPEC Unit has won arbitration. Encoding isdescribed in Table . dir_sel 2 In Signal indicating which sense ofaccess associated with arb_sel 00: issue non-CPU write 01: read winner10: write winner 11: refresh winner Outputs to Command MultiplexorSub-block write_data_valid 2 Out Signal indicating that valid write datais available for the current command. 00=not valid 01=CPU write datavalid 10=non-CPU write data valid 11=both CPU and non-CPU write datavalid wdata 256 Out 256-bit non-CPU write data cpu_wdata 32 Out 32-bitCPU write data Inputs from Command Multiplexor Sub-blockwrite_data_accept 2 In Signal indicating the Command Multiplexor hasaccepted the write data from the write multiplexor 00=not valid01=accepts CPU write data 10=accepts non-CPU write data 11=not validInputs from DCU dcu_dau_rdata 256 In 256-bit read data from DCU.dcu_dau_rvalid 1 In Signal indicating valid read data on dcu_dau_rdata.Outputs to CPU Configuration and Arbitration Logic Sub-blockread_cmd_rdy 2 Out Signal indicating that read multiplexor is ready fornext read read command. 00=not ready 01=ready for CPU read 10=ready fornon-CPU read 11=ready for both CPU and non-CPU reads write_cmd_rdy 2 OutSignal indicating that write multiplexor is ready for next writecommand. 00=not ready 01=ready for CPU write 10=ready for non-CPU write11=ready for both CPU and non-CPU writes Debug Outputs to CPUConfiguration and Arbitration Logic Sub-block read_sel 5 Out Signalindicating the SoPEC Unit for which the current read transaction isoccurring. Encoding is described in Table . read_complete 1 Out Signalindicating that read transaction to SoPEC Unit indicated by read_sel iscomplete.20.14.13.1 Read Multiplexor Logic Description

The Read Multiplexor has 2 read channels

-   -   a separate read bus for the CPU, dram_cpu_data[255:0].    -   and a shared read bus for the rest of SoPEC, diu_data[63:0].

The validity of data on the data busses is indicated by signalsdiu_<unit>_rvalid.

Timing waveforms for non-CPU and CPU DIU read accesses are shown in FIG.90 and FIG. 91, respectively.

The Read Multiplexor timing is shown in FIG. 127. FIG. 127 shows bothCPU and non-CPU reads. Both CPU and non-CPU channels are independenti.e. data can be output on the CPU read bus while non-CPU data is beingtransmitted in 4 cycles over the shared 64-bit read bus. CPU read data,dram_cpu_data[255.0], is available in the same cycle as output from theDCU. CPU read data needs to be registered immediately on entering theCPU by a flip-flop enabled by the diu_cpu_rvalid signal.

To ease timing, non-CPU read data from the DCU is first registered inthe Read Multiplexor by capturing it in the shared read data buffer ofFIG. 126 enabled by the dcu_dau_rvalid signal.

The data is then partitioned in 64-bit words on diu_data[63:0].

20.14.13.1.1 Non-CPU Read Data Coherency

Note that for data coherency reasons, a non-CPU read will always resultin read data being returned to the requester which includes theafter-effects of any pending (i.e. pre-arbitrated, but not yet executed)non-CPU write to the same address, which is currently cached in thenon-CPU write buffer. This is shown graphically in Figure n page 319 onpage Err r! B kmark not defined.

Should the pending write be partially masked, then the read datareturned must take account of that mask. Pending, masked writes by theCDU and SCB, as well as all unmasked non-CPU writes are fully supported.

Since CPU writes are dealt with on a dedicated write channel, no attemptis made to implement coherency between posted, unexecuted CPU writes andnon-CPU reads to the same address.

20.14.13.1.2 Read Multiplexor Command Queue

When the Arbitration Logic sub-block issues a read command theassociated value of arb_sel[4:0], which indicates which SoPEC Unit haswon arbitration, is written into a buffer, the read command queue.write_en = arb_gnt AND dir_sel[1:0]==“01” if write_en==1 then   WRITEarb_sel into read command queue

The encoding of arb_sel[4:0] is given in Table. dir_sel[1:0]==“01”indicates that the operation is a read. The read command queue is shownin FIG. 128.

The command queue could contain values of arb_sel[4:0] for 3 reads at atime.

-   -   In the scenario of FIG. 127 the command queue can contain 2        values of arb_sel[4:0] i.e. for the simultaneous CDU and CPU        accesses.    -   In the scenario of FIG. 130, the command queue can contain 3        values of arb_sel[4:0] i.e. at the time of the second        dcu_dau_rvalid pulse the command queue will contain an        arb_sel[4:0] for the arbitration performed in that cycle, and        the two previous arb_sel[4:0] values associated with the data        for the first two dcu_dau_rvalid pulses, the data associated        with the first dcu_dau_rvalid pulse not having been fully        transfered over the shared read data bus.

The read command queue is specified as 4 deep so it is never expected tofill.

The top of the command queue is a signal read_type[4:0] which indicatesthe destination of the current read data. The encoding of read_type[4:0]is given in Table.

20.14.13.1.3 CPU Reads

Read data for the CPU goes straight out on dram_cpu_data[255:0] anddcu_dau_rvalid is output on diu_cpu_rvalid.

cpu_read_complete(0) is asserted when a CPU read at the top of the readcommand queue occurs. cpu_read_complete(0) causes the read command queueto be popped.  cpu_read_complete(0) = (read_type[4:0] == CPU read) AND(dcu_dau_rvalid == 1)

If the current read command queue location points to a non-CPU accessand the second read command queue location points to a CPU access thenthe next dcu_dau_rvalid pulse received is associated with a CPU access.This is the scenario illustrated in FIG. 127. The dcu_dau_rvalid pulsefrom the DCU must be output to the CPU as diu_cpu_rvalid. This isachieved by using cpu_read_complete(1) to multiplex dcu_dau_rvalid todiu_cpu_rvalid. cpu_read_complete(1) is also used to pop the second fromtop read command queue location from the read command queue. cpu_read_complete(1) = (read_type == non-CPU read)         AND SECOND(read_type == CPU read) AND (dcu_dau_rvalid == 1)20.14.13.1.4 Multiplexing dcu_dau_rvalid

read_type[4:0] and cpu_read_complete(1) multiplexes the data validsignal, dcu_dau_rvalID, from the DCU, between the CPU and the sharedread bus logic. diu_cpu_rvalid is the read valid signal going to theCPU. noncpu_rvalid is the read valid signal used by the Read Multiplexorcontrol logic to generate read valid signals for non-CPU reads.  ifread_type[4:0] == CPU-read then  //select CPU   diu_cpu_rvalid:= 1  noncpu_rvalid:= 0  if  (read_type[4:0]==    non-CPU-read)    ANDSECOND(read_type[4:0]== CPU-read)   AND dcu_dau_rvalid == 1 then //select CPU   diu_cpu_rvalid:= 1   noncpu_rvalid:= 0  else   //selectshared read bus logic   diu_cpu_rvalid:= 0   noncpu_rvalid:= 120.14.13.1.5 Non-CPU Reads

Read data for the shared read bus is registered in the shared read databuffer using noncpu_rvalid. The shared read buffer has 5 locations of 64bits with separate read pointer, read_ptr[2:0], and write pointer,write_ptr[2:0].  if noncpu_rvalid == 1 and (4 spaces in shared readbuffer) then   shared_read_data_buffer[write_ptr] = dcu_dau_data[63:0]  shared_read_data_buffer[write_ptr+1] = dcu_dau_data[127:64]  shared_read_data_buffer[write_ptr+2] = dcu_dau_data[191:128]  shared_read_data_buffer[write_ptr+3] = dcu_dau_data[255:192]

The data written into the shared read buffer must be output to thecorrect SoPEC DIU read requestor according to the value ofread_type[4:0] at the top of the command queue. The data is output 64bits at a time on diu_data[63:0] according to a multiplexor controlledby read_ptr[2:0].

-   -   diu_data[63:0=shared_read_data_buffer[read_ptr]

FIG. 126 shows how read_type[4:0] also selects which shared read busrequesters diu_<unit>_rvalid signal is connected to shared_rvalid. Sincethe data from the DCU is registered in the Read Multiplexor thenshared_rvalid is a delayed version of noncpu_rvalid.

When the read valID, diu_<unit>_rvalID, for the command associated withread_type[4:0] has been asserted for 4 cycles then a signalshared_read_complete is asserted. This indicates that the read hascompleted. shared_read_complete causes the value of read_type[4:0] inthe read command queue to be popped.

A state machine for shared read bus access is shown in FIG. 129. Thisshow the generation of shared_rvalID, shared_read_complete and theshared read data buffer read pointer, read_ptr[2:0], being incremented.

Some points to note from FIG. 129 are:

-   -   shared_rvalid is asserted the cycle after dcu_dau_rvalid        associated with a shared read bus access. This matches the cycle        delay in capturing dau_dcu_data[255:0] in the shared read data        buffer. shared_rvalid remains asserted in the case of back to        back shared read bus accesses.    -   shared_read_complete is asserted in the last shared_rvalid cycle        of a non-CPU access. shared_read_complete causes the shared read        data queue to be popped.        20.14.13.1.6 Read Command Queue Read Pointer Logic

The read command queue read pointer logic works as follows.  ifshared_read_complete == 1 OR cpu_read_complete(0) == 1 then   POP top ofread command queue  if cpu_read_complete(1) == 1 then   POP second readcommand queue location20.14.13.1.7 Debug Signals

shared_read_complete and cpu_read_complete together define read_whichindicates to the debug logic that a read has completed. The source ofthe read is indicated on read_sel[4:0].   read_complete   =  shared_read_complete   OR cpu_read_complete(0)       ORcpu_read_complete(1)   if cpu_read_complete(1) == 1 then    read_sel:=SECOND(read_type)   else    read_sel:= read_type20.14.13.1.8 Flow Control

There are separate indications that the Read Multiplexor is able toaccept CPU and shared read bus commands from the Arbitration Logic.These are indicated by read_cmd_rdy[1:0].

The Arbitration Logic can always issue CPU reads except if the readcommand queue fills. The read command queue should be large enough thatthis should never occur.   //Read Multiplexor ready for ArbitrationLogic to issue CPU reads    read_cmd_rdy[0] == read command queue notfull

For the shared read data, the Read Multiplexor deasserts the shared readbus read_cmd_rdy[1] indication until a space is available in the readcommand queue. The read command queue should be large enough that thisshould never occur.

read_cmd_rdy[1] is also deasserted to provide flow control back to theArbitration Logic to keep the shared read data bus just full.  //ReadMultiplexor not ready for Arbitration Logic to issue non-CPU reads read_cmd_rdy[1] = (read command queue not full) AND (flow_control = 0)

The flow control condition is that DCU read data from the second of twoback-to-back shared read bus accesses becomes available. This causesread_cmd rdy[1] to de-assert for 1 cycle, resulting in a repeated MSN2DCU state. The timing is shown in FIG. 130.  flow_control =(read_type[4:0] == non-CPU read)        AND SECOND(read_type[4:0] ==non- CPU read)        AND (current DCU state == MSN2)       AND(previous DCU state == MSN1).

FIG. 130 shows a series of back to back transfers over the shared readdata bus. The exact timing of the implementation must not introduce anyadditional latency on shared read bus read transfers i.e. arbitrationmust be re-enabled just in time to keep back to back shared read busdata full.

The following sequence of events is illustrated in FIG. 130:

-   -   Data from the first DRAM access is written into the shared read        data buffer.    -   Data from the second access is available 3 cycles later, but its        transfer into the shared read buffer is delayed by a cycle, due        to the MSN2 stall condition. (During this delay, read data for        access 2 is maintained at the output of the DRAM.) A similar        1-cycle delay is introduced for every subsequent read access        until the back-to-back sequence comes to an end.    -   Note that arbitration always occurs during the last MSN2 state        of any access. So, for the second and later of any back-to-back        non-CPU reads, arbitration is delayed by one cycle, i.e. it        occurs every fourth cycle instead of the standard every third.

This mechanism provides flow control back to the Arbitration Logicsub-block. Using this mechanism means that the access rate will belimited to which ever takes longer—DRAM access or transfer of read dataover the shared read data bus. CPU reads are always be accepted by theRead Multiplexor.

20.14.13.2 Write Multiplexor Logic Description

The Write Multiplexor supplies write data to the DCU.

There are two separate write channels, one for CPU data oncpu_diu_(—)[127:0], one for non-CPU data on non_cpu_wdata[255:0]. Asignal write_data valid[1:0] indicates to the Command Multiplexor thatthe data is valid. The Command Multiplexor then asserts a signalwrite_data_accept[1:0] indicating that the data has been captured by theDRAM and the appropriate channel in the Write Multiplexor can accept thenext write data.

Timing waveforms for write accesses are shown in FIG. 92 to FIG. 94,respectively.

There are 3 types of write accesses:

-   -   CPU accesses

CPU write data on cpu_diu_wdata[127:0] is output on cpu_wdata[127:0].Since CPU writes are posted, a local buffer is used to store the writedata, address and mask until the CPU wins arbitration. This buffer isone position deep. write_data_valid[0], which is synonymous with!diu_cpu_w_write_rdy, remains asserted until the Command Multiplexorindicates it has been written to the DRAM by assertingwrite_data_accept[0]. The CPU write buffer can then accept new postedwrites.

For non-CPU writes, the Write Multiplexor multiplexes the write datafrom the DIU write requester to the write data buffer and the<unit>_diu_wvalid signal to the write multiplexor control logic.

-   -   CDU accesses

64-bits of write data each for a masked write to a separate 256-bit wordare transferred to the Write Multiplexor over 4 cycles.

When a CDU write is selected the first 64-bits of write data oncdu_diu_wdata[63:0] are multiplexed to non_cpu_wdata[63:0].write_data_valid[1] is asserted to indicate a non-CPU access whencdu_diu_wvalid is asserted. The data is also written into the firstlocation in the write data buffer. This is so that the data can continueto be output on non_cpu_wdata[63:0] and write_data_valid[1] remainsasserted until the Command Multiplexor indicates it has been written tothe DRAM by asserting write_data_accept[1]. Data continues to beaccepted from the CDU and is written into the other locations in thewrite data buffer. Successive write_data_accept[1] pulses cause thesuccessive 64-bit data words to be output on wdata[63:0] together withwrite_data_valid[1]. The last write_data_accept[1] means the writebuffer is empty and new write data can be accepted.

-   -   Other write accesses.

256-bits of write data are transferred to the Write Multiplexor over 4successive cycles.

When a write is selected the first 64-bits of write data on<unit>_diu_wdata[63:0] are written into the write data buffer. The next64-bits of data are written to the buffer in successive cycles. Once thelast 64-bit word is available on <unit>_diu_wdata[63:0] the entire wordis output on non_cpu_wdata[255:0], write_data_valid [1] is asserted toindicate a non-CPU access, and the last 64-bit word is written into thelast location in the write data buffer. Data continues to be output onnon_cpu_wdata[255:0] and write_data_valid[1] remains asserted until theCommand Multiplexor indicates it has been written to the DRAM byasserting write_data_accept[1]. New write data can then be written intothe write buffer.

CPU write multiplexor control logic

When the Command Multiplexor has issued the CPU write it assertswrite_data_accept[0]. write_data_accept[0] causes the write multiplexorto assert write_cmd_rdy[0].

The signal write_cmd_rdy[0] tells the Arbitration Logic sub-block thatit can issue another CPU write command i.e. the CPU write data buffer isempty.

Non-CPU Write Multiplexor Control Logic

The signal write_cmd_rdy[1] tells the Arbitration Logic sub-block thatthe Write Multiplexor is ready to accept another non-CPU write command.When write_cmd_rdy[1] is asserted the Arbitration Logic can issue awrite command to the Write Multiplexor. It does this by writing thevalue of arb_sel[4:0] which indicates which SoPEC Unit has wonarbitration into a write command register, write_cmd[3:0].  write_en =arb_gnt AND dir_sel[1]==1 AND arb_sel = non- CPU  if write_en==1 then  write_cmd = arb_sel

The encoding of arb_sel[4:0] is given in Table. dir_sel[1]==1 indicatesthat the operation is a write. arb_sel[4:0] is only written to the writecommand register if the write is a non-CPU write.

A rule was introduced in Section 20.7.2.3 Interleaving read and writeaccesses to the effect that non-CPU write accesses would not beallocated adjacent timeslots. This means that a single write commandregister is required.

The write command register, write_cmd[3:0], indicates the source of thewrite data. write_cmd[3:0] multiplexes the write data <unit>_diu_wdata,and the data valid signal, <unit>_diu_wvalID, from the selected writerequestor to the write data buffer. Note, that CPU write data is notincluded in the multiplex as the CPU has its own write channel. The<unit>_diu_wvalid are counted to generate the signal word_sel[1:0] whichdecides which 64-bit word of the write data buffer to store the datafrom <unit>_diu_wdata. //when the Command Multiplexor accepts the writedata if write_data_accept[1] = 1 then  //reset the word select signal word_sel[1:0]=00 //when wvalid is asserted if wvalid = 1 then //increment the word select signal  if word_sel[1:0] == 11 then  word_sel[1:0] == 00  else   word_sel[1:0] == word_sel[1:0] + 1wvalid is the <unit>_diu_wvalid signal multiplexed by write_cmd[3:0].word_sel[1:0] is reset when the Command Multiplexor accepts the writedata. This is to ensure that word_sel[1:0] is always starts at 00 forthe first wvalid pulse of a 4 cycle write data transfer.

The write command register is able to accept the next write when theCommand Multiplexor accepts the write data by assertingwrite_data_accept[1]. Only the last write_data_accept[1] pulseassociated with a CDU access (there are 4) will cause the write commandregister to be ready to accept the next write data.

Flow control back to the Command Multiplexor

-   write_cmd rdy[0] is asserted when the CPU data buffer is empty.-   write_cmd_rdy[1] is asserted when both the write command register    and the write data buffer is empty.    PEP Subsystem    21 PEP Controller Unit (PCU)    21.1 Overview

The PCU has three functions:

-   -   The first is to act as a bus bridge between the CPU-bus and the        PCU-bus for reading and writing PEP configuration registers.

The second is to support page banding by allowing the PEP blocks to bereprogrammed between bands by retrieving commands from DRAM instead ofbeing programmed directly by the CPU.

The third is to send register debug information to the RDU, within theCPU subsystem, when the PCU is in Debug Mode.

21.2 Interfaces Between PCU and Other Units

21.3 Bus Bridge

The PCU is a bus-bridge between the CPU-bus and the PCU-bus. The PCU isa slave on the CPU-bus but is the only master on the PCU-bus. See Figurepage 39 on page Error! Bookmark not defined.

21.3.1 CPU Accessing PEP

All the blocks in the PEP can be addressed by the CPU via the PCU. TheMMU in the CPU-subsystem will decode a PCU select signal, cpu_pcu_sel,for all the PCU mapped addresses (see section 11.4.3 on page 69). Usingcpu_adr bits 15-12 the PCU will decode individual block selects for eachof the blocks within the PEP. The PEP blocks then decode the remainingaddress bits needed to address their PCU-bus mapped registers. Note: theCPU is only permitted to perform supervisor-mode data-type accesses ofthe PEP, i.e. cpu_acode=11. If the PCU is selected by the CPU and anyother code is present on the cpu_acode bus the access is ignored by thePCU and the pcu_cpu_berr signal is strobed,

CPU commands have priority over DRAM commands. When the PCU is executingeach set of four commands retrieved from DRAM the CPU can access PCU-busregisters. In the case that DRAM commands are being executed and the CPUresets the CmdSource to zero, the contents of the DRAM CmdFifo isinvalidated and no further commands from the fifo are executed. TheCmdPending and NextBandCmdEnable work registers are also cleared.

When a DRAM command writes to the CmdAdr register it means the next DRAMaccess will occur at the address written to CmdAdr. Therefore if theJUMP instruction is the first command in a group of four, the otherthree commands get executed and then the PCU will issue a read requestto DRAM at the address specified by the JUMP instruction. If the JUMPinstruction is the second command then the following two commands willbe executed before the PCU requests from the new DRAM address specifiedby the JUMP instruction etc. Therefore the PCU will always execute theremaining commands in each four command group before carrying out theJUMP instruction.

21.4 Page Banding

The PCU can be programmed to associate microcode in DRAM with eachfinishedband signal. When a finishedband signal is asserted the PCU willread commands from DRAM and execute these commands. These commands areeach 64-bits (see Section 21.8.5) and consist of 32-bit address bits and32 data bits and allow PCU mapped registers to be programmed directly bythe PCU.

If more than one finishedband signal is received at the same time, orothers are received while microcode is already executing, the PCU willhold the commands as pending, and will execute them at the firstopportunity.

Each microcode program associated with cdu_finishedband,lbd_finishedband and te_finishedband would simply restart theappropriate unit with new addresses—a total of about 4 or 5 microcodeinstructions. As well, or alternatively, pcu_finishedband can be used toset up all of the units and therefore involves many more instructions.This minimizes the time that a unit is idle in between bands. Thepcu_finishedband control signal is issued once the specified combinationof CDU, LBD and TE (programmed in BandSelectMask) have finished theirprocessing for a band.

21.5 Interrupts, Address Legality and Security

Interrupts are generated when the various page expansion units havefinished a particular band of data from DRAM. The cdu_finishedband,lbd_finishedband and te_finishedband signals are combined in the PCUinto a single interrupt pcu_finishedband which is exported by the PCU tothe interrupt controller.

The PCU mapped registers should only be accessible from Supervisor DataMode. The area of DRAM where PCU commands are stored should be aSupervisor Mode only DRAM area, although this is not enforced by thePCU.

When the PCU is executing commands from DRAM, any block-address decodedfrom a command which is not part of the PEP block-address map will causethe PCU to ignore the command and strobe the pcu_icu_address_invalidinterrupt signal. The CPU can then interrogate the PCU to find thesource of the illegal command. The MMU will ensure that the CPU cannotaddress an invalid PEP subsystem block.

When the PCU is executing commands from DRAM, any address decoded from acommand which is not part of the PEP address map will cause the PCU to:

-   -   Cease execution of current command and flush all remaining        commands already retrieved from DRAM.    -   Clear CmdPending work-register.    -   Clear NextBandCmdEnable registers.    -   Set CmdSource to zero.

In addition to cancelling all current and pending DRAM accesses the PCUstrobes the pcu_icu_address_invalid interrupt signal. The CPU can theninterrogate the PCU to find the source of the illegal command.

21.6 Debug Mode

When the need to monitor the (possibly changing) value in any PEPconfiguration register the PCU may be placed in Debug Mode. This is donevia the CPU setting certain Debug Address register within the PCU. Oncein Debug Mode the PCU continually reads the target PEP configurationregister and sends the read value to the RDU. Debug Mode has the lowestpriority of all PCU functions: if the CPU wishes to perform an access orthere are DRAM commands to be executed they will interrupt the Debugaccess, and the PCU will resume Debug access once a CPU or DRAM commandhas completed.

21.7 Implementation

21.7.1 Definitions of I/O TABLE 139 PCU Port List Port Name Pins I/ODescription Clocks and Resets Pclk 1 In SoPEC functional clock prst_n 1In Active-low, synchronous reset in pclk domain End of BandFunctionality cdu_finishedband 1 In Finished band signal from CDUlbd_finishedband 1 In Finished band signal from LBD te_finishedband 1 InFinished band signal from TE pcu_finishedband 1 Out Asserted once thespecified combination of CDU, LBD, and TE have finished their processingfor a band. PCU address error pcu_icu_address_invalid 1 Out Strobed ifPCU decodes a non PEP address from commands retrieved from DRAM or CPU.CPU Subsystem Interface Signals cpu_adr[15:2] 14 In CPU address bus. 14bits are required to decode the address space for the PEP.cpu_dataout[31:0] 32 In Shared write data bus from the CPUpcu_cpu_data[31:0] 32 Out Read data bus to the CPU cpu_rwn 1 In Commonread/not-write signal from the CPU cpu_acode[1:0] 2 In CPU Access Codesignals. These decode as follows: 00 - User program access 01 - Userdata access 10 - Supervisor program access 11 - Supervisor data accesscpu_pcu_sel 1 In Block select from the CPU. When cpu_pcu_sel is highboth cpu_adr and cpu_dataout are valid pcu_cpu_rdy 1 Out Ready signal tothe CPU. When pcu_cpu_rdy is high it indicates the last cycle of theaccess. For a write cycle this means cpu_dataout has been registered bythe block and for a read cycle this means the data on pcu_cpu_data isvalid. pcu_cpu_berr 1 Out Bus error signal to the CPU indicating aninvalid access. pcu_cpu_debug_valid 1 Out Debug Data valid onpcu_cpu_data bus. Active high. PCU Interface to PEP blocks pcu_adr[11:2]10 Out PCU address bus. The 10 least significant bits of cpu_adr [15:2]allow 1024 32-bit word addressable locations per PEP block. Only thenumber of bits required to decode the address space are exported to eachblock. pcu_dataout[31:0] 32 Out Shared write data bus from the PCU<unit>_pcu_datain[31:0] 32 In Read data bus from each PEP subblock tothe PCU pcu_rwn 1 Out Common read/not-write signal from the PCUpcu_<unit>_sel 1 Out Block select for each PEP block from the PCU.Decoded from the 4 most significant bits of cpu_adr[15:2]. Whenpcu_<unit>_sel is high both pcu_adr and pcu_dataout are valid<unit>_pcu_rdy 1 In Ready from each PEP block signal to the PCU. when<unit>_pcu_rdy is high it indicates the last cycle of the access. For awrite cycle this means pcu_dataout has been registered by the block andfor a read cycle this means the data on <unit>_pcu_datain is valid. DIURead Interface signals pcu_diu_rreq 1 Out PCU requests DRAM read. A readrequest must be accompanied by a valid read address. pcu_diu_radr[21:5]17 Out Read address to DIU 17 bits wide (256-bit aligned word).diu_pcu_rack 1 In Acknowledge from DIU that read request has beenaccepted and new read address can be placed on pcu_diu_radrdiu_data[63:0] 64 In Data from DIU to PCU. First 64-bits is bits 63:0 of256 bit word Second 64-bits is bits 127:64 of 256 bit word third 64-bitsis bits 191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256bit word diu_pcu_rvalid 1 In Signal from DIU telling PCU that valid readdata is on the diu_data bus

21.7.2 Configuration Registers TABLE 140 PCU Configuration RegistersAddress PCU_base+ register #bits reset description Control registers0x00 Reset 1 0x1 A write to this register causes a reset of the PCU.This register can be read to indicate the reset state: 0 - reset inprogress 1 - reset not in progress 0x04 CmdAdr[21:5] 17 0x00 000 Theaddress of the next set of commands to (256-bit retrieve from DRAM.aligned When this register is written to, either by the DRAM CPU or DRAMcommand, 1 is also written to address) CmdSource to cause the executionof the commands at the specified address. 0x08 BandSelect 3 0x0 Selectswhich input finishedBand flags are to Mask[2:0] be watched to generatethe combined pcu_finishedband signal. Bit0 - lbd_finishedband Bit1 -cdu_finishedband Bit2 - te_finishedband 0x0C, 0x10, NextBandCmd 4x170x00 000 The address to transfer to CmdAdr as soon 0x14, 0x18 Adr[3:0]as possible after the next finishedBand[n] [21:5] signal has beenreceived as long as (256-bit NextBandCmdEnable[n] is set. aligned Awrite from the PCU to NextBandCmdAdr[n] DRAM with a non-zero value alsosets address) NextBandCmdEnable[n]. A write from the PCU toNextBandCmdAdr[n] with a 0 value clears NextBandCmdEnable[n]. 0x1CNextCmdAdr 17 0x00 000 The address to transfer to CmdAdr when the [21:5]CPU pending bit (CmdPending[4]) get serviced. A write from the PCU toNextCmdAdr[n] with a non-zero value also sets CmdPending[4]. A writefrom the PCU to NextCmdAdr[n] with a 0 value clears CmdPending[4] 0x20CmdSource 1 0x0 0 - commands are taken from the CPU 1 - commands aretaken from the CPU as well as DRAM at CmdAdr. 0x24 DebugSelect 14 0x0000 Debug address select. Indicates the address [15:2] of the register toreport on the pcu_cpu_data bus when it is not otherwise being used, andthe PEP bus is not being used Bits [15:12] select the unit (see Table)Bits [11:2] select the register within the unit Work registers (readonly) 0x28 InvalidAddress 19 0 DRAM Address of current 64-bit command[21:3] attempting to execute. (64-bit Read only register. aligned DRAM)0x2C CmdPending 5 0x00 For each bit n, where n is 0 to 3 0 -no commandspending for NextBandCmdAdr[n] 1 -commands pending for NextBandCmdAdr[n]For bit 4 0 -no commands pending for NextCmdAdr[n] 1 -commands pendingfor NextCmdAdr[n] Read only register. 0x34 FinishedSo 3 0x0 Theappropriate bit is set whenever the corresponding Far input finishedBandflag is set and the corresponding bit in the BandSelectMask bit is alsoset. If all FinishedSoFar bits are set wherever BandSelect bits are alsoset, all FinishedSoFar bits are cleared and the output pcu_finishedbandsignal is given. Read only register. 0x38 NextBandCmd 4 0x0 Thisregister can be written to indirectly (i.e. Enable the bits are set orcleared via writes to NextBandCmdAdr[n]) For each bit: 0 - do nothing atthe next finishedBand[n] signal. 1 - Execute instructions atNextBandCmdAdr[n] as soon as possible after receipt of the nextfinishedBand[n] signal. Bit0 - lbd_finishedband Bit1 - cdu_finishedbandBit2 - te_finishedband Bit3 - pcu_finishedband Read only register.21.8 Detailed Description21.8.1 PEP Blocks Register Map

All PEP accesses are 32-bit register accesses.

From Table 140 it can be seen that four bits only are necessary toaddress each of the sub-blocks within the PEP part of SoPEC. Up to 14bits may be used to address any configurable 32-bit register within PEP.This gives scope for 1024 configurable registers per sub-block. Thisaddress will come either from the CPU or from a command stored in DRAM.The bus is assembled as follows:

-   -   adr[15:12]=sub-block address

adr[n:2]=32-bit register address within sub-block, only the number ofbits required to decode the registers within each sub-block are used.TABLE 141 PEP blocks Register Map Block Select Decode = cpu_adr Block[15:12] PCU 0x0 CDU 0x1 CFU 0x2 LBD 0x3 SFU 0x4 TE 0x5 TFU 0x6 HCU 0x7DNC 0x8 DWU 0x9 LLU 0xA PHI 0xB Reserved 0xC to 0xF21.8.2 Internal PCU PEP Protocol

The PCU performs PEP configuration register accesses via a selectsignal, pcu_<block>_sel. The read/write sense of the access iscommunicated via the pcu_rwn signal (1=read, 0=write). Write data isclocked out, and read data clocked in upon receipt of the appropriateselect-read/write-address combination.

FIG. 133 shows a write operation followed by a read operation. The readoperation is shown with wait states while the PEP block returns the readdata.

For access to the PEP blocks a simple bus protocol is used. The PCUfirst determines which particular PEP block is being addressed so thatthe appropriate block select signal can be generated. During a writeaccess PCU write data is driven out with the address and block selectsignals in the first cycle of an access. The addressed PEP blockresponds by asserting its ready signal indicating that it has registeredthe write data and the access can complete. The write data bus is commonto all PEP blocks.

A read access is initiated by driving the address and select signalsduring the first cycle of an access. The addressed PEP block responds byplacing the read data on its bus and asserting its ready signal toindicate to the PCU that the read data is valid. Each block has aseparate point-to-point data bus for read accesses to avoid the need fora tri-stateable bus.

Consecutive accesses to a PEP block must be separated by at least asingle cycle, during which the select signal must be de-asserted.

21.8.3 PCU DRAM Access Requirements

The PCU can execute register programming commands stored in DRAM. Thesecommands can be executed at the start of a print run to initialize allthe registers of PEP. The PCU can also execute instructions at the startof a page, and between bands. In the inter-band time, it is critical tohave the PCU operate as fast as possible. Therefore in the inter-pageand inter-band time the PCU needs to get low latency access to DRAM.

A typical band change requires on the order of 4 commands to restarteach of the CDU, LBD, and TE, followed by a single command to terminatethe DRAM command stream. This is on the order of 5 commands per restartcomponent.

The PCU does single 256 bit reads from DRAM. Each PCU command is 64 bitsso each 256 bit DRAM read can contain 4 PCU commands. The requestedcommand is read from DRAM together with the next 3 contiguous 64-bitswhich are cached to avoid unnecessary DRAM reads. Writing zero toCmdSource causes the PCU to flush commands and terminate program accessfrom DRAM for that command stream. The PCU requires a 256-bit buffer tothe 4 PCU commands read by each 256-bit DRAM access. When the buffer isempty the PCU can request DRAM access again. Adding a 256-bit doublebuffer would allow the next set of 4 commands to be fetched from DRAMwhile the current commands are being executed.

1024 commands of 64 bits requires 8 kB of DRAM storage.

Programs stored in DRAM are referred to as PCU Program Code.

21.8.4 End of Band Unit

The state machine is responsible for watching the various inputxx_finishedband signals, setting the FinishedSoFar flags, and outputtingthe pcu_finishedband flags as specified by the BandSelect register.

Each cycle, the end of band unit performs the following tasks:pcu_finishedband = (FinishedSoFar[0] == BandSelectMask[0]) AND    (FinishedSoFar[1] == BandSelectMask[1]) AND     (FinishedSoFar[2] ==BandSelectMask[2]) AND     (BandSelectMask[0]) OR BandSelectMask[1] ORBandSelectMask[2])  if (pcu_finishedband == 1) then   FinishedSoFar[0] =0   FinishedSoFar[1] = 0   FinishedSoFar[2] = 0  else   FinishedSoFar[0]  =   (FinishedSoFar[0] OR lbd_finishedband) AND BandSelectMask[0]  FinishedSoFar[1]   =   (FinishedSoFar[1] OR cdu_finishedband) ANDBandSelectMask[1]   FinishedSoFar[2]   =   (FinishedSoFar[2] ORte_finishedband) AND BandSelectMask[2]

Note that it is the responsibility of the microcode at the start ofprinting a page to ensure that all 3 FinishedSoFar bits are cleared. Itis not necessary to clear them between bands since this happensautomatically.

If a bit of BandSelectMask is cleared, then the corresponding bit ofFinishedSoFar has no impact on the generation of pcu_finishedband.

21.8.5 Executing Commands From DRAM

Registers in PEP can be programmed by means of simple 64-bit commandsfetched from DRAM. The format of the commands is given in Table 142.Register locations can have a data value of up to 32 bits. Commands arePEP register write commands only. TABLE 142 Register write commands inPEP command bits 63-32 bits 31-16 bits 15-2 bits 1-0 Register write datazero 32-bit word zero address

Due attention must be paid to the endianness of the processor. The LEONprocessor is a big-endian processor (bit 7 is the most significant bit).

21.8.6 General Operation

Upon a Reset condition, CmdSource is cleared (to 0), which means thatall commands are initially sourced only from the CPU bus interface.Registers and can then be written to or read from one location at a timevia the CPU bus interface.

If CmdSource is 1, commands are sourced from the DRAM at CmdAdr and fromthe CPU bus.

Writing an address to CmdAdr automatically sets CmdSource to 1, andcauses a command stream to be retrieved from DRAM. The PCU will executecommands from the CPU or from the DRAM command stream, giving higherpriority to the CPU always.

If CmdSource is 0 the DRAM requester examines the CmdPending bits todetermine if a new DRAM command stream is pending. If any of CmdPendingbits are set, then the appropriate NextBandCmdAdr or NextCmdAdr iscopied to CmdAdr (causing CmdSource to get set to 1) and a new commandDRAM stream is retrieved from DRAM and executed by the PCU. If there aremultiple pending commands the DRAM requestor will service the lowestnumber pending bit first. Note that a new DRAM command stream only getsretrieved when the current command stream is empty.

If there are no DRAM commands pending, and no CPU commands the PCUdefaults to an idle state. When idle the PCU address bus defaults to theDebugSelect register value (bits 11 to 2 in particular) and the defaultunit PCU data bus is reflected to the CPU data bus. The default unit isdetermined by the DebugSelect register bits 15 to 12.

In conjunction with this, upon receipt of a finishedBand[n] signal,NextBandCmdEnable[n] is copied to CmdPending[n] and NextBandCmdEnable[n]is cleared. Note, each of the LBD, CDU, and TE (where present) may bere-programmed individually between bands by appropriately settingNextBandCmdAdr[2-0] respectively. However, execution of inter-bandcommands may be postponed until all blocks specified in theBandSelectMask register have pulsed their finishedband signal. This maybe accomplished by only setting NextBandCmdAdr[3] (indirectly causingNextBandCmdEnable[3] to be set) in which case it is the pcu_finishedbandsignal which causes NextBandCmdEnable[3] to be copied to CmdPending[3].

To conveniently update multiple registers, for example at the start ofprinting a page, a series of Write Register commands can be stored inDRAM. When the start address of the first Write Register command iswritten to the CmdAdr register (via the CPU), the CmdSource register isautomatically set to 1 to actually start the execution at CmdAdr.Alternatively the CPU can write to NextCmdAdr causing the CmdPending[4]bit to get set, which will then get serviced by the DRAM requester inthe pending bit arbitration order.

The final instruction in the command block stored in DRAM must be aregister write of 0 to CmdSource so that no more commands are read fromDRAM. Subsequent commands will come from pending programs or can be sentvia the CPU bus interface.

21.8.6.1 Debug Mode

Debug mode is implemented by reusing the normal CPU and DRAM accessdecode logic. When in the Arbitrate state (see state machine A below),the PEP address bus is defaulted to the value in the DebugSelectregister. The top bits of the DebugSelect register are used to decode aselect to a PEP unit and the remaining bits are reflected on the PEPaddress bus. The selected units read data bus is reflected on thepcu_cpu_data bus to the RDU in the CPU. The pcu_cpu_debug_valid signalindicates to the RDU that the data on the pcu_cpu_data bus is validdebug data.

Normal CPU and DRAM command access will require the PEP bus, and as suchwill cause the debug data to be invalid during the access, this isindicated to the RDU by setting pcu_cpu_debug_valid to zero.

The decode logic is: // Default Debug decode if state == Arbitrate then if  (cpu_pcu_sel  ==  1 AND  cpu_acode     /= SUPERVISOR_DATA_MODE)then   pcu_cpu_debug_valid = 0  // bus error condition   pcu_cpu_data =0  else   <unit> = decode(DebugSelect[15:12])   if (<unit> == PCU ) then   pcu_cpu_data = Internal PCU register   else    pcu_cpu_data =<unit>_pcu_datain[31:0]   pcu_adr[11:2]  = DebugSelect[11:2]  pcu_cpu_debug_valid  = 1 AFTER 4 clock cycles else pcu_cpu_debug_valid  = 021.8.7 State Machines

DRAM command fetching and general command execution is accomplishedusing two state machines. State machine A evaluates whether a CPU orDRAM command is being executed, and proceeds to execute the command(s).Since the CPU has priority over the DRAM it is permitted to interruptthe execution of a stream of DRAM commands.

Machine B decides which address should be used for DRAM access, fetchescommands from DRAM and fills a command fifo which A executes. The reasonfor separating the two functions is to facilitate the execution of CPUor Debug commands while state machine B is performing DRAM reads andfilling the command fifo. In the case where state machine A is ready toexecute commands (in its Arbitrate state) and it sees both a full DRAMcommand fifo and an active cpu_pcu_sel then the DRAM commands areexecuted last.

21.8.7.1 State Machine A: Arbitration and Execution of Commands

The state-machine enters the Reset state when there is an active strobeon either the reset pin, prst_n, or the PCU's soft-reset register. Allregisters in the PCU are zeroed, unless otherwise specified, on the nextrising clock edge. The PCU self-deasserts the soft reset in the pclkcycle after it has been asserted.

The state changes from Reset to Arbitrate when prst_n==1 andPCU_softreset==1.

The state-machine waits in the Arbitrate state until it detects arequest for CPU access to the PEP units (cpu_pcu_sel==1 andcpu_acode==11) or a request to execute DRAM commands CmdSource==1, andDRAM commands are available, CmdFifoFull==1. Note if (cpu_pcu_sel==1 andcpu_acode !=11) the CPU is attempting an illegal access. The PCU ignoresthis command and strobes the cpu_pcu_berr for one cycle.

While in the Arbitrate state the machine assigns the DebugSelectregister to the PCU unit decode logic and the remaining bits to the PEPaddress bus. When in this state the debug data returned from theselected PEP unit is reflected on the CPU bus (pcu_cpu_data bus) and thepcu_cpu_debug valid=1.

If a CPU access request is detected (cpu_pcu_sel==1 and cpu_acode==11)then the machine proceeds to the CpuAccess state. In the CpuAccess statethe cpu address is decoded and used to determine the PEP unit to select.The remaining address bits are passed through to the PEP address bus.The machine remains in the CpuAccess state until a valid ready from theselected PEP unit is received. When received the machine returns to thearbitrate state, and the ready signal to the CPU is pulsed. // decodethe logic pcu_<unit>_sel = decode(cpu_adr[15:12]) pcu_adr[11:2] =cpu_adr[11:2]

The CPU is prevented from generating an invalid PEP unit address(prevented in the MMU) and so CPU accesses cannot generate an invalidaddress error.

If the state machine detects a request to execute DRAM commands(CmdSource==1), it will wait in the Arbitrate state until commands havebeen loaded into the command FIFO from DRAM (all controlled by statemachine B). When the DRAM commands are available (cmd_fifo_full==1) thestate machine will proceed to the DRAMAccess state.

When in the DRAMAccess state the commands are executed from thecmd_(—)_fifo. A command in the cmd_fifo consists of 64-bits (or whichthe FIFO holds 4). The decoding of the 64-bits to commands is given inTable. For each command the decode is // DRAM command decodepcu_<unit>_sel = decode( cmd_fifo[cmd_count][15:12] ) pcu_adr[11:2] =cmd_fifo[cmd_count][11:2] pcu_dataout = cmd_fifo[cmd_count][63:32]

When the selected PEP unit returns a ready signal (<unit>_pcu_rdy==1)indicating the command has completed, the state machine will return tothe Arbitrate state. If more commands exists (cmd_count !=0) thetransition will decrement the command count.

When in the DRAMAccess state, if when decoding the DRAM command addressbus (cmd_fifo[cmd_count][15.12]), the address selects a reservedaddress, the state machine proceeds to the AdrError state, and then backto the Arbitrate state. An address error interrupt will be generated andthe DRAM command FIFOs will be cleared.

A CPU access can pre-empt any pending DRAM commands. After each commandis completed the state machine returns to the Arbitrate state. If a CPUaccess is required and DRAM command stream is executing the CPU accessalways takes priority. If a CPU or DRAM command sets the CmdSource to 0,all subsequent DRAM commands in the command FIFO are cleared. If the CPUsets the CmdSource to 0 the CmdPending and NextBandCmdEnable workregisters are also cleared.

21.8.7.2 State Machine B: Fetching DRAM Commands

A system reset (prst_n==0) or a software reset (pcu_softreset_n==0) willcause the state machine to reset to the Reset state. The state machineremains in the Reset until both reset conditions are removed. Whenremoved the machine proceeds to the Waft state.

The state machine waits in the Wait state until it determines thatcommands are needed from DRAM. Two possible conditions exist thatrequire DRAM access. Either the PCU is processing commands which must befetched from DRAM (cmd_source==1), and the command FIFO is empty(cmd_fifo_full_(—) _(—)=0), or the cmd_source==0 and the command FIFO isempty and there are some commands pending (cmd_pending !=0). In eitherof these conditions the machine proceeds to the Ack state and issues aread request to DRAM (pcu_diu_rreq==1), it calculates the address toread from dependent on the transition condition. In the command pendingtransition condition, the highest priority NextBandCmdAdr (orNextCmdAdr) that is pending is used for the read address (pcu_diu_radr)and is also copied to the CmdAdr register. If multiple pending bits areset the lowest pending bits are serviced first. In the normal PCUprocessing transition the pcu_diu_radr is the CmdAdr register.

When an acknowledge is received from the DRAM the state machine goes tothe FillFifo state. In the FillFifo state the machine waits for the DRAMto respond to the read request and transfer data words. On receipt ofthe first word of data diu_pcu_rvalid==1, the machine stores the 64-bitdata word in the command FIFO (cmd_fifo[3]) and transitions to theData1, Data2, Data3 states each time waiting for a diu_pcu_rvalid==1 andstoring the transferred data word to cmd_fifo[2], cmd_fifo[1] andcmd_fifo[0] respectively.

When the transfer is complete the machine returns to the Wait state,setting the cmd_count to 3, the cmd_fifo_full is set to 1 and the CmdAdris incremented.

If the CPU sets the CmdSource register low while the PCU is in themiddle of a DRAM access, the statemachine returns to the Wait state andthe DRAM access is aborted.

21.8.7.3 PCU_ICU_Address_Invalid Interrupt

When the PCU is executing commands from DRAM, addresses decoded fromcommands which are not PCU mapped addresses (4-bits only) will result inthe current command being ignored and the pcu_icu_address_invalidinterrupt signal is strobed. When an invalid command occurs allremaining commands already retrieved from DRAM are flushed from theCmdFifo, and the CmdPending, NextBandCmdEnable and CmdSource registersare cleared to zero.

The CPU can then interrogate the PCU to find the source of the illegalDRAM command via the InvalidAddress register.

The CPU is prevented by the MMU from generating an invalid addresscommand.

22 Contone Decoder Unit (CDU)

22.1 Overview

The Contone Decoder Unit (CDU) is responsible for performing theoptional decompression of the contone data layer.

The input to the CDU is up to 4 planes of compressed contone data inJPEG interleaved format. This will typically be 3 planes, representing aCMY contone image, or 4 planes representing a CMYK contone image. TheCDU must support a page of A4 length (11.7 inches) and Letter width (8.5inches) at a resolution of 267 ppi in 4 colors and a print speed of 1side per 2 seconds.

The CDU and the other page expansion units support the notion of pagebanding. A compressed page is divided into one or more bands, with anumber of bands stored in memory. As a band of the page is consumed forprinting a new band can be downloaded. The new band may be for thecurrent page or the next page. Band-finish interrupts have been providedto notify the CPU of free buffer space.

The compressed contone data is read from the on-chip DRAM. The output ofthe CDU is the decompressed contone data, separated into planes. Thedecompressed contone image is written to a circular buffer in DRAM withan expected minimum size of 12 lines and a configurable maximum. Thedecompressed contone image is subsequently read a line at a time by theCFU, optionally color converted, scaled up to 1600 ppi and then passedon to the HCU for the next stage in the printing pipeline. The CDU alsooutputs a cdu_finishedband control flag indicating that the CDU hasfinished reading a band of compressed contone data in DRAM and that areaof DRAM is now free. This flag is used by the PCU and is available as aninterrupt to the CPU.

22.2 Storage Requirements for Decompressed Contone Data in DRAM

A single SoPEC must support a page of A4 length (11.7 inches) and Letterwidth (8.5 inches) at a resolution of 267 ppi in 4 colors and a printspeed of 1 side per 2 seconds. The printheads specified in the Bi-lithicPrinthead Specification [2] have 13824 nozzles per color to provide fullbleed printing for A4 and Letter. At 267 ppi, there are 2304 contonepixels⁹ per line represented by 288 JPEG blocks per color. However eachof these blocks actually stores data for 8 lines, since a single JPEGblock is 8×8 pixels. The CDU produces contone data for 8 lines inparallel, while the HCU processes data linearly across a line on a lineby line basis. The contone data is decoded only once and then bufferedin DRAM. This means we require two sets of 8 buffer-lines—one set of 8buffer lines is being consumed by the CFU while the other set of 8buffer lines is being generated by the CDU.⁹Pixels may be 8, 16, 24 or 32 bits depending on the number of colorplanes (8-bits per color)

The buffer requirement can be reduced by using a 1.5 buffering scheme,where the CDU fills 8 lines while the CFU consumes 4 lines. The bufferspace required is a minimum of 12 line stores per color, for a totalspace of 108 KBytes¹⁰. A circular buffer scheme is employed whereby theCDU may only begin to write a line of JPEG blocks (equals 8 lines ofcontone data) when there are 8-lines free in the buffer. Once the full 8lines have been written by the CDU, the CFU may now begin to read themon a line by line basis.¹⁰ 12 lines×4 colors×2304 bytes (assumes 267 ppi, 4 color, full bleedA4/Letter)

This reduction in buffering comes with the cost of an increased peakbandwidth requirement for the CDU write access to DRAM. The CDU must beable to write the decompressed contone at twice the rate at which theCFU reads the data. To allow for trade-offs to be made between peakbandwidth and amount of storage, the size of the circular buffer isconfigurable. For example, if the circular buffer is configured to be 16lines it behaves like a double-buffer scheme where the peak bandwidthrequirements of the CDU and CFU are equal. An increase over 16 linesallows the CDU to write ahead of the CFU and provides it with a marginto cope with very poor local compression ratIOs in the image.

SoPEC should also provide support for A3 printing and printing atresolutions above 267 ppi. This increases the storage requirement forthe decompressed contone data (buffer) in DRAM. Table 143 gives thestorage requirements for the decompressed contone data at some samplecontone resolutions for different page sizes. It assumes 4 color planesof contone data and a 1.5 buffering scheme. TABLE 143 Storagerequirements for decompressed contone data (buffer) Page Contoneresolution Scale Pixels per Storage required size (ppi) factor^(a) line(kBytes) A4/Letter^(b) 267 6 2304  108^(d) 400 4 3456 162 800 2 6912 324A3^(c) 267 6 3248   152.25 400 4 4872   228.37 800 2 9744   456.75^(a)Required for CFU to convert to final output at 1600 dpi^(b)Bi-lithic printhead has 13824 nozzles per color providing full bleedprinting for A4/Letter^(c)Bi-lithic printhead has 19488 nozzles per color providing full bleedprinting for A3^(d)12 lines × 4 colors × 2304 bytes.22.3 Decompression Performance Requirements

The JPEG decoder core can produce a single color pixel every systemclock (pclk) cycle, making it capable of decoding at a peak output rateof 8 bits/cycle. SoPEC processes 1 dot (bi-level in 6 colors) per systemclock cycle to achieve a print speed of 1 side per 2 seconds for full.bleed A4/Letter printing. The CFU replicates pixels a scale factor (SF)number of times in both the horizontal and vertical directions toconvert the final output to 1600 ppi. Thus the CFU consumes a 4 colorpixel (32 bits) every SF x SF cycles. The 1.5 buffering scheme describedin section 22.2 on page 327 means that the CDU must write the data attwice this rate. With support for 4 colors at 267 ppi, the decompressionoutput bandwidth requirement is 1.78 bits/cycle¹¹.

The JPEG decoder is fed directly from the main memory via the DRAMinterface. The amount of compression determines the input bandwidthrequirements for the CDU. As the level of compression increases, thebandwidth decreases, but the quality of the final output image can alsodecrease. Although the average compression ratio for contone data isexpected to be 10:1, the average bandwidth allocated to the CDU allowsfor a local minimum compression ratio of 5:1 over a single line of JPEGblocks. This equates to a peak input bandwidth requirement of 0.36bits/cycle for 4 colors at 267 ppi, full bleed A4/Letter printing at 1side per 2 seconds.

Table 144 gives the decompression output bandwidth requirements fordifferent resolutions of contone data to meet a print speed of 1 sideper 2 seconds. Higher resolution requires higher bandwidth and largerstorage for decompressed contone data in DRAM. A resolution of 400 ppicontone data in 4 colors requires 4 bits/cycle¹², which is practicalusing a 1.5 buffering scheme. However, a resolution of 800 ppi wouldrequire a double buffering scheme (16 lines) so the CDU only has tomatch the CFU consumption rate. In this case the decompression outputbandwidth requirement is 8 bits/cycle¹³, the limiting factor being theoutput rate of the JPEG decoder core.¹¹2×((4 colors×8 bits)/(6×6 cycles))=1.78 bits/cycle¹²2×((4 colors×8 bits)/(4×4 cycles))=4 bits/cycle¹³(4 colors×8 bits)/(2×2 cycles)=8 bits/cycleTABLE 144 CDU performance requirements for full bleed A4/Letter printingat 1 side per 2 seconds. Contone resolution Scale Decompression outputbandwidth (ppi) factor requirement (bits/cycle)^(a) 267 6   1.78 400 4 4800 2  8^(b)^(a)Assumes 4 color pixel contone data and a 12 line buffer.^(b)Scale factor 2 requires at least a 16 line buffer.22.4 Data Flow

FIG. 136 shows the general data flow for contone data—compressed contoneplanes are read from DRAM by the CDU, and the decompressed contone datais written to the 12-line circular buffer in DRAM. The line buffers aresubsequently read by the CFU.

The CDU allows the contone data to be passed directly on, which will bethe case if the color represented by each color plane in the JPEG imageis an available ink. For example, the four colors may be C, M, Y, and K,directly represented by CMYK inks. The four colors may represent gold,metallic green etc. for multi-SoPEC printing with exact colors.

However JPEG produces better compression ratIOs for a given visiblequality when luminance and chrominance channels are separated. WithCMYK, K can be considered to be luminance, but C, M, and Y each containluminance information, and so would need to be compressed withappropriate luminance tables. We therefore provide the means by whichCMY can be passed to SoPEC as YCrCb. K does not need color conversion.When being JPEG compressed, CMY is typically converted to RGB, then toYCrCb and then finally JPEG compressed. At decompression, the YCrCb datais obtained and written to the decompressed contone store by the CDU.This is read by the CFU where the YCrCb can then be optionally colorconverted to RGB, and finally back to CMY.

The external RIP provides conversion from RGB to YCrCb, specifically tomatch the actual hardware implementation of the inverse transform withinSoPEC, as per CCIR 601-2 [24] except that Y, Cr and Cb are normalized tooccupy all 256 levels of an 8-bit binary encoding.

The CFU provides the translation to either RGB or CMY. RGB is includedsince it is a necessary step to produce CMY, and some printers increasetheir color gamut by including RGB inks as well as CMYK.

22.5 Implementation

A block diagram of the CDU is shown in FIG. 137.

All output signals from the CDU (cdu_cfu_wradv8line, cdu_finishedband,cdu_icu_jpegerror, and control signals to the DIU) must always be validafter reset. If the CDU is not currently decoding, cdu_cfu_wradv8line,cdu_finishedband and cdu_icu_jpegerror will always be 0.

The read control unit is responsible for keeping the JPEG decoder'sinput FIFO full by reading compressed contone bytestream from externalDRAM via the DIU, and produces the cdu_finishedband signal. The writecontrol unit accepts the output from the JPEG decoder a half JPEG block(32 bytes) at a time, writes it into a double-buffer, and writes thedouble buffered decompressed half blocks to DRAM via the DIU,interacting with the CFU in order to share DRAM buffers.

22.5.1 Definitions of I/O TABLE 145 CDU port list and description Portname Pins I/O Description Clocks and reset Pclk 1 In System clock. Jclk1 In Gated version of system clock used to clock the JPEG decoder coreand logic at the output of the core. Allows for stalling of the JPEGcore at a pixel sample boundary. jclk_enable 1 Out Gating signal forjclk. prst_n 1 In System reset, synchronous active low. jrst_n 1 InReset for jclk domain, synchronous active low. PCU interface pcu_cdu_sel1 In Block select from the PCU. When pcu_cdu_sel is high both pcu_adrand pcu_dataout are valid. pcu_rwn 1 In Common read/not-write signalfrom the PCU. pcu_adr[7:2] 6 In PCU address bus. Only 6 bits arerequired to decode the address space for this block. pcu_dataout[31:0]32 In Shared write data bus from the PCU. cdu_pcu_rdy 1 Out Ready signalto the PCU. When cdu_pcu_rdy is high it indicates the last cycle of theaccess. For a write cycle this means pcu_dataout has been registered bythe block and for a read cycle this means the data on cdu_pcu_datain isvalid. cdu_pcu_datain[31:0] 32 Out Read data bus to the PCU. DIU readinterface cdu_diu_rreq 1 Out CDU read request, active high. A readrequest must be accompanied by a valid read address. diu_cdu_rack 1 InAcknowledge from DIU, active high. Indicates that a read request hasbeen accepted and the new read address can be placed on the address bus,cdu_diu_radr. cdu_diu_radr[21:5] 17 Out CDU read address. 17 bits wide(256-bit aligned word). diu_cdu_rvalid 1 In Read data valid, activehigh. Indicates that valid read data is now on the read data bus,diu_data. diu_data[63:0] 64 In Read data from DRAM. DIU write interfacecdu_diu_wreq 1 Out CDU write request, active high. A write request mustbe accompanied by a valid write address and valid write data.diu_cdu_wack 1 In Acknowledge from DIU, active high. Indicates that awrite request has been accepted and the new write address can be placedon the address bus, cdu_diu_wadr. cdu_diu_wadr[21:3] 19 Out CDU writeaddress. 19 bits wide (64-bit aligned word). cdu_diu_wvalid 1 Out Writedata valid, active high. Indicates that valid data is now on the writedata bus, cdu_diu_data. cdu_diu_data[63:0] 64 Out Write data bus. CFUinterface cfu_cdu_rdadvline 1 In Read line pulse, active high. Indicatesthat the CFU has finished reading a line of decompressed contone data tothe circular buffer in DRAM and that line of the buffer is now free.cdu_cfu_linestore_rdy 1 Out Indicates if the contone line store has 1 ormore lines available to read by the CFU. TE and LBD interfacecdu_start_of_bandstore[21:5] 17 Out Points to the 256-bit word thatdefines the start of the memory area allocated for page bands.cdu_end_of_bandstore[21:5] 17 Out Points to the 256-bit word thatdefines the last address of the memory area allocated for page bands.ICU interface cdu_finishedband 1 Out CDU's finishedBand flag, activehigh. Interrupt to the CPU to indicate that the CDU has finishedprocessing a band of compressed contone data in DRAM and that area ofDRAM is now free. This signal goes to both the interrupt controller andthe PCU. cdu_icu_jpegerror 1 Out Active high interrupt indicating anerror has occurred in the JPEG decoding process and decompression hasstopped. A reset of the CDU must be performed to clear this interrupt.22.5.2 Configuration Registers

The configuration registers in the CDU are programmed via the PCUinterface. Refer to section 21.8.2 on page 321 for the description ofthe protocol and timing diagrams for reading and writing registers inthe CDU. Note that since addresses in SoPEC are byte aligned and the PCUonly supports 32-bit register reads and writes, the lower 2 bits of thePCU address bus are not required to decode the address space for theCDU. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of cdu_pcu_datain.

Since the CDU, LBD and TE all access the page band store, they share tworegisters that enable sequential memory accesses to the page band storesto be circular in nature. Table 146 lists these two registers. TABLE 146Registers shared between the CDU, LBD, and TE Address Value on(CDU_base+) Register name #bits reset description Setup registers(remain constant during the processing of multiple bands) 0x80StartOfBandStore[21:5] 17 0x0_0000 Points to the 256-bit word thatdefines the start of the memory area allocated for page bands. Circularaddress generation wraps to this start address. 0x84EndOfBandStore[21:5] 17 0x1_3FFF Points to the 256-bit word that definesthe last address of the memory area allocated for page bands. If thecurrent read address is from this address, then instead of adding 1 tothe current address, the current address will be loaded from theStartOfBandStore register.

The software reset logic should include a circuit to ensure that boththe pclk and jclk domains are reset regardless of the state of thejclk_enable when the reset is initiated.

The CDU contains the following additional registers: TABLE 147 CDUregisters Address Value on (CDU_base+) Register name #bits resetDescription Control registers 0x00 Reset 1 0x1 A write to this registercauses a reset of the CDU. This terminates all internal operationswithin the CS6150. All configuration data previously loaded into thecore except for the tables is deleted. 0x04 Go 1 0x0 Writing 1 to thisregister starts the CDU. Writing 0 to this register halts the CDU. WhenGo is deasserted the state- machines go to their idle states but allcounters and configuration registers keep their values. When Go isasserted all counters are reset, but configuration registers keep theirvalues (i.e. they don't get reset). NextBandEnable is cleared when Go isasserted. The CFU must be started before the CDU is started. Go mustremain low for at least 384 jclk cycles after a hardware reset (prst_n =0) to allow the JPEG core to complete its memory itnitialisationsequence. This register can be read to determine if the CDU is running(1 - running, 0 - stopped). Setup registers 0x0C NumLinesAvail 7 0x0 Thenumber of image lines of data that there is space available for in thedecompressed data buffer in DRAM. If this drops <8 the CDU will stall.In normal operation this value will start off atNumBuffLines and will bedecremented by 8 whenever the CDU writes a line of JPEG blocks (8 linesof data) to DRAM and incremented by 1 whenever the CFU reads a line ofdata from DRAM. NumLinesAvail can be overwritten by the CPU to preventthe CDU from stalling. 0x10 MaxPlane 2 0x0 Defines the number of contoneplanes −1. For example, this will be 0 for K (greyscale printing), 2 forCMY, and 3 for CMYK. 0x14 MaxBlock 13 0x000 Number of JPEG MCUs (or JPEGblock equivalents, i.e. 8 × 8 bytes) in a line −1. 0x18BuffStartAdr[21:7] 15 0x0000 Points to the start of the decompressedcontone circular buffer in DRAM, aligned to a half JPEG block boundary.A half JPEG block consists of 4 words of 256-bits, enough to hold 32contone pixels in 4 colors, i.e. half a JPEG block. 0x1CBuffEndAdr[21:7] 15 0x0000 Points to the start of the last half JPEGblock at the end of the decompressed contone circular buffer in DRAM,aligned to a half JPEG block boundary. A half JPEG block consists of 4words of 256-bits, enough to hold 32 contone pixels in 4 colors, i.e.half a JPEG block. 0x20 NumBuffLines[6:2] 5 0x03 Defines size of bufferin DRAM in terms of the number of decompressed contone lines. The sizeof the buffer should be a multiple of 4 lines with a minimum size of 8lines. 0x24 BypassJpg 1 0x0 Determines whether or not the JPEG decoderwill be bypassed (and hence pixels are copied directly from input tooutput) 0 - don't bypass, 1 - bypass Should not be changed betweenbands. 0x30 NextBandCurr- 17 0x0_0000 The 256-bit aligned word addressSourceAdr[21:5] containing the start of the next band of compressedcontone data in DRAM. This value is copied to CurrSourceAdr when bothDoneBand is 1 and NextBandEnable is 1, or when Go transitions from 0to 1. 0x34 NextBandEnd- 19 0x0_0000 The 64-bit aligned word addressSourceAdr[21:3] containing the last bytes of the next band of compressedcontone data in DRAM. This value is copied to EndSourceAdr when whenboth DoneBand is 1 and NextBandEnable is 1, or when Go transitions from0 to 1. 0x38 NextBandValid- 3 0x0 Indicates the number of valid bytes −1BytesLastFetch in the last 64-bit fetch of the next band of compressedcontone data from DRAM. eg 0 implies bits 7:0 are valid, 1 implies bits15:0 are valid, 7 implies all 63:0 bits are valid etc. This value iscopied to ValidBytesLastFetch when both DoneBand is 1 and NextBandEnableis 1, or when Go transitions from 0 to 1. 0x3C NextBandEnable 1 0x0 WhenNextBandEnable is 1 and DoneBand is 1 NextBandCurrSourceAdr is copied toCurrSourceAdr, NextBandEndSourceAdr is copied to EndSourceAdrNextBandValidBytesLastFetch is copied to ValidBytesLastFetch DoneBand iscleared, NextBandEnable is cleared. NextBandEnable is cleared when Go isasserted. Note that DoneBand gets cleared regardless of the state of Go.Read-only registers 0x40 DoneBand 1 0x0 Specifies whether or not thecurrent band has finished loading into the local FIFO. It is cleared to0 when Go transitions from 0 to 1. When the last of the compressedcontone data for the band has been loaded into the local FIFO, thecdu_finishedband signal is given out and the DoneBand flag is set. IfNextBandEnable is 1 at this time then CurrSourceAdr, EndSourceAdr andValidBytesLastFetch are updated with the values for the next band andDoneBand is cleared. Processing of the next band starts immediately. IfNextBandEnable is 0 then the remainder of the CDU will continue to run,decompressing the data already loaded, while the read control unit waitsfor NextBandEnable to be set before it restarts. 0x44CurrSourceAdr[21:5] 17 0x0_0000 The current 256-bit aligned word addresswithin the current band of compressed contone data in DRAM. 0x48EndSourceAdr[21:3] 19 0x0_0000 The 64-bit aligned word addresscontaining the last bytes of the current band of compressed contone datain DRAM. 0x4C ValidBytesLastFetch 3 0x00 Indicates the number of validbytes −1 in the last 64-bit fetch of the current band of compressedcontone data from DRAM. eg 0 implies bits 7:0 are valid, 1 implies bits15:0 are valid, 7 implies all 63:0 bits are valid etc. JPEG decoder coresetup registers 0x50 JpgDecMask 5 0x00 As segments are decoded they canalso be output on the DecJpg (JpgDecHdr) port with the user selectingthe segments for output by setting bits in the jpgDecMask port asfollows: 4 SOF+SOS+DNL 3 COM+APP 2 DRI 1 DQT 0 DHT If any one of thebits of jpgDecMask is asserted then the SOI and EOI markers are alsopassed to the DecJpg port. 0x54 JpgDecTType 1 0x0 Test type selector:0 - DCT coefficients displayed on JpgDecTdata 1 - QDCT coefficientdisplayed on JpgDecTdata 0x58 JpgDecTestEn 1 0x0 Signal which causes thememories to be bypassed for test purposes. 0x5C JpgDecPType 4 0x0 Signalspecifying parameters to be placed on port JpgDecPValue (See Table).JPEG decoder core read-only status registers 0x60 JpgDecHdr 8 0x00Selected header segments from the JPEG stream that is currently beingdecoded. Segments selected using JpgMask. 0x64 JpgDecTData 13 0x000012 - TSOS output of CS1650, indicates the first output byte of the first8 × 8 block of the test data. 11 - TSOB output of CS1650, indicates thefirst output byte of each 8 × 8 block of test data. 10-0 - 11-bit outputtest data port - displays DCT coefficients or quantized coefficientsdepending on value of JpgDecTType. 0x68 JpgDecPValue 16 0x0000 Decodingparameter bus which enables various parameters used by the core to beread. The data available on the PValue port is for information only, anddoes not contain control signals for the decoder core. 0x6C JpgDecStatus24 0x00_0000 Bit 23 - jpg_core_stall (if set, indicates that the JPEGcore is stalled by gating of jclk as the output JPEG halfblockdouble-buffers of the CDU are full) Bit 22 - pix_out_valid (This signalis an output from the JPEG decoder core and is asserted when a pixel isbeing output Bits 21-16 - fifo_contents (Number of bytes in compressedcontone FIFO at the input of CDU which feeds the JPEG decoder core) Bits15-0 are JPEG decoder status outputs from the CS6150 (see Table fordescription of bits).22.5.3 Typical Operation

The CDU should only be started after the CFU has been started.

For the first band of data, users set up NextBandCurrSourceAdr,NextBandEndSourceAdr, NextBandValidBytesLastFetch, and the variousMaxPlane, MaxBlock, BuffStartBlockAdr, BuffEndBlockAdr and NumBuffLines.Users then set the CDU's Go bit to start processing of the band. Whenthe compressed contone data for the band has finished being read in, thecdu_finishedband interrupt will be sent to the PCU and CPU indicatingthat the memory associated with the first band is now free. Processingcan now start on the next band of contone data.

In order to process the next band NextBandCurrSourceAdr,NextBandEndSourceAdr and NextBandValidBytesLastFetch need to be updatedbefore finally writing a 1 to NextBandEnable. There are 4 mechanisms forrestarting the CDU between bands:

-   a. cdu_finishedband causes an interrupt to the CPU. The CDU will    have set its DoneBand bit. The CPU reprograms the    NextBandCurrSourceAdr, NextBandEndSourceAdr and    NextBandValidBytesLastFetch registers, and sets NextBandEnable to    restart the CDU.-   b. The CPU programs the CDU's NextBandCurrSourceAdr,    NextBandCurrEndAdr and NextBandValidBytesLastFetch registers and    sets the NextBandEnable bit before the end of the current band. At    the end of the current band the CDU sets DoneBand. As NextBandEnable    is already 1, the CDU starts processing the next band immediately.-   c. The PCU is programmed so that cdu_finishedband triggers the PCU    to execute commands from DRAM to reprogram the    NextBandCurrSourceAdr, NextBandEndSourceAdr and    NextBandValidBytesLastFetch registers and set the NextBandEnable bit    to start the CDU processing the next band. The advantage of this    scheme is that the CPU could process band headers in advance and    store the band commands in DRAM ready for execution.-   d. This is a combination of b and c above. The PCU (rather than the    CPU in b) programs the CDU's NextBandCurrSourceAdr,    NextBandCurrEndAdr and NextBandValidBytesLastFetch registers and    sets the NextBandEnable bit before the end of the current band. At    the end of the current band the CDU sets DoneBand and pulses    cdu_finishedband. As NextBandEnable is already 1, the CDU starts    processing the next band immediately. Simultaneously,    cdu_finishedband triggers the PCU to fetch commands from DRAM. The    CDU will have restarted by the time the PCU has fetched commands    from DRAM. The PCU commands program the CDU's next band shadow    registers and sets the NextBandEnable bit.

If an error occurs in the JPEG stream, the JPEG decoder will suspend itsoperation, an error bit will be set in the JpgDecStatus register and thecore will ignore any input data and await a reset before startingdecoding again. An interrupt is sent to the CPU by assertingcdu_icu_jpegerror and the CDU should then be reset by means of a writeto its Reset register before a new page can be printed.

22.5.4 Read Control Unit

The read control unit is responsible for reading the compressed contonedata and passing it to the JPEG decoder via the FIFO. The compressedcontone data is read from DRAM in single 256-bit accesses, receiving thedata from the DIU over 4 clock cycles (64-bits per cycle). The protocoland timing for read accesses to DRAM is described in section 20.9.1 onpage 240. Read accesses to DRAM are implemented by means of the statemachine described in FIG. 138. All counters and flags should be clearedafter reset. When Go transitions from 0 to 1 all counters and flagsshould take their initial value. While the Go bit is set, the statemachine relies on the DoneBand bit to tell it whether to attempt to reada band of compressed contone data. When DoneBand is set, the statemachine does nothing. When DoneBand is clear, the state machinecontinues to load data into the JPEG input FIFO up to 256-bits at a timewhile there is space available in the FIFO. Note that the state machinehas no knowledge about numbers of blocks or numbers of color planes—itmerely keeps the JPEG input FIFO full by consecutive reads from DRAM.The DIU is responsible for ensuring that DRAM requests are satisfied atleast at the peak DRAM read bandwidth of 0.36 bits/cycle (see section22.3 on page 329).

A modulo 4 counter, rd_count, is use to count each of the 64-bitsreceived in a 256-bit read access. It is incremented wheneverdiu_cdu_rvalid is asserted. As each 64-bit value is returned, indicatedby diu_cdu_rvalid being asserted, curr_source_adr is compared to bothend_source_adr and end_of_bandstore:

-   -   If {curr_source_adr rd_count} equals end_source_adr, the        end_of_band control signal sent to the FIFO is 1 (to signify the        end of the band), the finishedCDUBand signal is output, and the        DoneBand bit is set. The remaining 64-bit values in the burst        from the DIU are ignored, i.e. they are not written into the        FIFO.    -   If rd_count equals 3 and {curr_source_adr, rd_count} does not        equal end_source_adr, then curr_source_adr is updated to be        either start_of_bandstore or curr_source_adr+1, depending on        whether curr_source_adr also equals end_of_bandstore. The        end_of_band control signal sent to the FIFO is 0.

curr_source_adr is output to the DIU as cdu_diu_radr.

A count is kept of the number of 64-bit values in the FIFO. Whendiu_cdu_rvalid is 1 and ignore_data is 0, data is written to the FIFO byasserting FifoWr, and fifo_contents[3:0] and fifo_wr_adr[2:0] are bothincremented.

When fifo_contents[3:0] is greater than 0, jpg_in_strb is asserted toindicate that there is data available in the FIFO for the JPEG decodercore. The JPEG decoder core asserts jpg_in_rdy when it is ready toreceive data from the FIFO. Note it is also possible to bypass the JPEGdecoder core by setting the BypassJpg register to 1. In this case datais sent directly from the FIFO to the half-block double-buffer. Whilethe JPEG decoder is not stalled (jpg_core_stall equal 0), and jpg_in_rdy(or bypass_jpg) and jpg_in_strb are both 1, a byte of data is consumedby the JPEG decoder core. fifo_rd_adr[5:0] is then incremented to selectthe next byte. The read address is byte aligned, i.e. the upper 3 bitsare input as the read address for the FIFO and the lower 3 bits are usedto select a byte from the 64 bits. If fifo_rd_adr[2:0]=111 then the next64-bit value is read from the FIFO by asserting fifo_rd, andfifo_contents[3:0] is decremented.

22.5.5 Compressed Contone FIFO

The compressed contone FIFO conceptually is a 64-bit input, and 8-bitoutput FIFO to account for the 64-bit data transfers from the DIU, andthe 8-bit requirement of the JPEG decoder.

In reality, the FIFO is actually 8 entries deep and 65-bits wide (toaccommodate two 256-bit accesses), with bits 63-0 carrying data, and bit64 containing a 1-bit end_of_band flag. Whenever 64-bit data is writtento the FIFO from the DIU, an end of band flag is also passed in from theread control unit. The end_of_band bit is 1 if this is the last datatransfer for the current band, and 0 if it is not the last transfer.When end_of_band=1 during an input, the ValidBytesLastFetch register isalso copied to an image version of the same.

On the JPEG decoder side of the FIFO, the read address is byte aligned,i.e. the upper 3 bits are input as the read address for the FIFO and thelower 3 bits are used to select a byte from the 64 bits (1st bytecorresponds to bits 7-0, second byte to bits 15-8 etc.). If bit 64 isset on the read, bits 63-0 contain the end of the bytestream for thatband, and only the bytes specified by the image of ValidBytesLastFetchare valid bytes to be read and presented to the JPEG decoder. Note thatValidBytesLastFetch is copied to an image register as it may be possiblefor the CDU to be reprogrammed for the next band before the previousband's compressed contone data has been read from the FIFO (as anadditional effect of this, the CDU has a non-problematic limitation inthat each band of contone data must be more than 4×64-bits, or 32 bytes,in length).

22.5.6 CS6150 JPEG Decoder

JPEG decoder functionality is implemented by means of a modified versionof the Amphion CS6150 JPEG decoder core. The decoder is run at a nominalclock speed of 160 MHz. (Amphion have stated that the CS6150 JPEGdecoder core can run at 185 MHz in 0.13 um technology). The core isclocked by jclk which a gated version of the system clock pclk. Gatingthe clock provides a mechanism for stalling the JPEG decoder on a singlecolor pixel-by-pixel basis. Control of the flow of output data is alsoprovided by the PixOutEnab input to the JPEG decoder. However, this onlyallows stalling of the output at a JPEG block boundary and isinsufficient for SoPEC. Thus gating of the clock is employed andPixOutEnab is instead tied high.

The CS6150 decoder automatically extracts all relevant parameters fromthe JPEG bytestream and uses them to control the decoding of the image.The JPEG bytestream contains data for the Huffman tables, quantizationtables, restart interval definition and frame and scan headers. Thedecoder parses and checks the JPEG bytestream automatically detectingand processing all the JPEG marker segments. After identifying the JPEGsegments the decoder re-directs the data to the appropriate units to bestored or processed as appropriate. Any errors detected in thebytestream, apart from those in the entropy coded segments, aresignalled and, if an error is found, the decoder stops reading the JPEGstream and waits to be reset.

JPEG images must have their data stored in interleaved format with nosubsampling. Images longer than 65536 lines are allowed: these must havean initial imageHeight of 0. If the image has a Define Number Lines(DNL) marker at the end (normally necessary for standard JPEG, but notnecessary for SoPEC's version of the CS6150), it must be equal to thetotal image height mod 64 k or an error will be generated.

See the CS6150 Databook [21] for more details on how the core is used,and for timing diagrams of the interfaces. Note that [21] does notdescribe the use of the DNL marker in images of more than 64 k lineslength as this is a modification to the core.

The CS6150 decoder can be bypassed by setting the BypassJpg register. Ifthis register is set, then the data read from DRAM must be in the sameformat as if it was produced by the JPEG decoder: 8×8 blocks of pixelsin the correct color order. The data is uncompressed and is thereforelossless.

The following subsections describe the means by which the CS6150internals can be made visible.

22.5.6.1 JPEG Decoder Reset

The JPEG decoder has 2 possible types of reset, an asynchronous resetand a synchronous clear. In SoPEC the asynchronous reset is connected tothe hardware synchronous reset of the CDU and can be activated by anyhardware reset to SoPEC (either from external pin or from any of thewake-up sources, e.g. USB activity, Wake-up register timeout) or byresetting the PEP section (ResetSection register in the CPR block).

The synchronous clear is connected to the software reset of the CDU andcan be activated by the low to high transition of the Go register, or asoftware reset via the Reset register.

The 2 types of reset differ, in that the asynchronous reset, resets theJPEG core and causes the core to enter a memory initialization sequencethat takes 384 clock cycles to complete after the reset is deasserted.The synchronous clear resets the core, but leaves the memory as is. Thishas some implications for programming the CDU.

In general the CDU should not be started (i.e. setting Go to 1) until atleast 384 cycles after a hardware reset. If the CDU is started beforethen, the memory initialization sequence will be terminated leaving theJPEG core memory in an unknown state. This is allowed if the memory isto be initialized from the incoming JPEG stream.

22.5.6.2 JPEG Decoder Parameter Bus

The decoding parameter bus JpgDecPValue is a 16-bit port used to outputvarious parameters extracted from the input data stream and currentlyused by the core. The 4-bit selector input (JpgDecPType) determineswhich internal parameters are displayed on the parameter bus as perTable 148. The data available on the PValue port does not containcontrol signals used by the CS6150. TABLE 148 Parameter bus definitionsPType Output orientation PValue 0x0 FY[15:0] FY: number of lines inframe 0x1 FX[15:0] FX: number of columns in frame 0x2 00_YMCU[13:0]YMCU: number of MCUs in Y direction of the current scan 0x300_XMCU[13:0] XMCU: number of MCUs in X direction of the current scan0x4 Cs0[7:0]_Tq0[1:0]_V0[2:0]_H0[2:0] Cs0: identifier for the first scancomponent Tq0: quantization table identifier for the first scancomponent V0: vertical sampling factor for the first scan component.Values = 1-4 H0: horizontal sampling factor for the first scancomponent. Values = 1-4 0x5 Cs1[7:0]_Tq1[1:0]_V1[2:0]_H1[2:0] Cs1, Tq1,V1 and H1 for the second scan component. V1, H1 undefined if NS<2 0x6Cs2[7:0]_Tq2[1:0]_V2[2:0]_H2[2:0] Cs2, Tq2, V2 and H2 for the secondscan component. V2, H2 undefined if NS<3 0x7Cs3[7:0]_Tq3[1:0]_V3[2:0]_H3[2:0] Cs3, Tq3, V3 and H3 for the secondscan component. V3, H3 undefined if NS<4 0x8 CsH[15:0] CsH: no. of rowsin current scan 0x9 CsV[15:0] CsV: no. of columns in current scan 0xADRI[15:0] DRI: restart interval 0xB000_HMAX[2:0]_VMAX[2:0]_MCUBLK[3:0]_NS[2:0] HMAX: maximal horizontalsampling factor in frame VMAX: maximal vertical sampling factor in frameMCUBLK: number of blocks per MCU of the current scan, from 1 to 10 NS:number of scan components in current scan, 1-422.5.6.3 JPEG Decoder Status Register

The status register flags indicate the current state of the CS6150operation. When an error is detected during the decoding process, thedecompression process in the JPEG decoder is suspended and an interruptis sent to the CPU by asserting cdu_icu_jpegerror (generated fromDecError). The CPU can check the source of the error by reading theJpgDecStatus register. The CS6150 waits until a reset process is invokedby asserting the hard reset prst_n or by a soft reset of the CDU. Theindividual bits of JpgDecStatus are set to zero at reset and active highto indicate an error condition as defined in Table 149.

Note: A DecHfError will not block the input as the core will try torecover and produce the correct amount of pixel data. The DecHfError iscleared automatically at the start of the next image and so nointervention is required from the user. If any of the other errors occurin the decode mode then, following the error cancellation, the core willdiscard all input data until the next Start Of Image (SOI) withouttriggering any more errors.

The progress of the decoding can be monitored by observing the values ofTbIDef, IDctInProg, DecInProg and JpgInProg. TABLE 149 JPEG decoderstatus register definitions Bit Name Description 15-12 TblDef[7:4]Indicates the number of Huffman tables defined, 1bit/table. 11-8 TblDef[3:0] Indicates the number of quantization tables defined,1bit/table. 7 DecHfError Set when an undefined Huffman table symbol isreferenced during decoding. 6 CtlError Set when an invalid SOF parameteror an invalid SOS parameter is detected. Also set when there is amismatch between the DNL segment input to the core and the number oflines in the input image which have already been decoded. Note thatSoPEC's implementation of the CS6150 does not require a final DNL whenthe initial setting for ImageHeight is 0. This is to allow images longerthan 64k lines. 5 HtError Set when an invalid DHT segment is detected. 4QtError Set when an invalid DQT segment is detected. 3 DecError Set whenanything other than a JPEG marker is input. Set when any ofDecFlags[6:4] are set. Set when any data other than the SOI marker isdetected at the start of a stream. Set when any SOF marker is detectedother than SOF0. Set if incomplete Huffman or quantization definition isdetected. 2 IDctInProg Set when IDCT starts processing first data of ascan. Cleared when IDCT has processed the last data of a scan. 1DecInProg For each scan this signal is asserted after the SigSOS (Startof Scan Segment) signal has been output from the core and is de-asserted when the decoding of a scan is complete. It indicates that thecore is in the decoding state. 0 JpgInProg Set when core starts toprocess input data (JpgIn) and de-asserted when decoding has beencompleted i.e. when the last pixel of last block of the image is output.22.5.7 Half-Block Buffer Interface

Since the CDU writes 256 bits (4×64 bits) to memory at a time, itrequires a double-buffer of 2×256 bits at its output. This isimplemented in an 8×64 bit FIFO. It is required to be able to stall theJPEG decoder core at its output on a half JPEG block boundary, i.e.after 32 pixels (8 bits per pixel). We provide a mechanism for stallingthe JPEG decoder core by gating the clock to the core (with jclk_enable)when the FIFO is full. The output FIFO is responsible for providing twobuffered half JPEG blocks to decouple JPEG decoding (read control unit)from writing those JPEG blocks to DRAM (write control unit). Data comingin is in 8-bit quantities but data going out is in 64-bit quantities fora single color plane.

22.5.8 Write Control Unit

A line of JPEG blocks in 4 colors, or 8 lines of decompressed contonedata, is stored in DRAM with the memory arrangement as shown FIG. 139.The arrangement is in order to optimize access for reads by writing thedata so that 4 color components are stored together in each 256-bit DRAMword.

The CDU writes 8 lines of data in parallel but stores the first 4 linesand second 4 lines separately in DRAM. The write sequence for a singleline of JPEG 8×8 blocks in 4 colors, as shown in FIG. 139, is as followsbelow and corresponds to the order in which pixels are output from theJPEG decoder core:  block 0, color 0, line 0 in word p bits 63-0, line 1in word p+1 bits 63-0,    line 2 in word p+2 bits 63-0, line 3 in wordp+3 bits 63-0,  block 0, color 0, line 4 in word q bits 63-0, line 5 inword q+1 bits 63-0,    line 6 in word q+2 bits 63-0, line 7 in word q+3bits 63-0,  block 0, color 1, line 0 in word p bits 127-64, line 1 inword p+1 bits 127-64,    line 2 in word p+2 bits 127-64, line 3 in wordp+3 bits 127-64,  block 0, color 1, line 4 in word q bits 127-64, line 5in word q+1 bits 127-64,    line 6 in word q+2 bits 127-64, line 7 inword q+3 bits 127-64,   repeat for block 0 color 2, block 0 color3........  block 1, color 0, line 0 in word p+4 bits 63-0, line 1 inword p+5 bits 63-0,  etc...................................................  block N, color3, line 4 in word q+4n bits 255-192, line 5 in word q+4n+1 bits 255-192,   line 6 in word q+4n+2 bits 255- 192, line 7 in word q+4n+3 bit255-192

In SoPEC data is written to DRAM 256 bits at a time. The DIU receives a64-bit aligned address from the CDU, i.e. the lower 2 bits indicatewhich 64-bits within a 256-bit location are being written to. With thataddress the DIU also receives half a JPEG block (4 lines) in a singlecolor, 4×64 bits over 4 cycles. All accesses to DRAM must be padded to256 bits or the bits which should not be written are masked using theindividual bit write inputs of the DRAM. When writing decompressedcontone data from the CDU, only 64 bits out of the 256-bit access toDRAM are valID, and the remaining bits of the write are masked by theDIU. This means that the decompressed contone data is written to DRAM in4 back-to-back 64-bit write masked accesses to 4 consecutive 256-bitDRAM locations/words.

Writing of decompressed contone data to DRAM is implemented by the statemachine in FIG. 140. The CDU writes the decompressed contone data toDRAM half a JPEG block at a time, 4×64 bits over 4 cycles. All countersand flags should be cleared after reset. When Go transitions from 0 to 1all counters and flags should take their initial value. While the Go bitis set, the state machine relies on the half_block_ok_to_read andline_store_ok_to_write flags to tell it whether to attempt to write ahalf JPEG block to DRAM. Once the half-block buffer interface contains ahalf JPEG block, the state machine requests a write access to DRAM byasserting cdu_diu_wreq and providing the write address, corresponding tothe first 64-bit value to be written, on cdu_diu_wadr (only the addressthe first 64-bit value in each access of 4×64 bits is issued by the CDU.The DIU can generate the addresses for the second, third and fourth64-bit values). The state machine then waits to receive an acknowledgefrom the DIU before initiating a read of 4×64-bit values from thehalf-block buffer interface by asserting rd_adv for 4 cycles. The outputcdu_diu_wvalid is asserted in the cycle after rd_adv to indicate to theDIU that valid data is present on the cdu_diu_data bus and should bewritten to the specified address in DRAM. A rd_adv_half block pulse isthen sent to the half-block buffer interface to indicate that thecurrent read buffer has been read and should now be available to bewritten to again. The state machine then returns to the request state.

The pseudocode below shows how the write address is calculated on a perclock cycle basis.

Note counters and flags should be cleared after reset. When Gotransitions from 0 to 1 all counters and flags should be cleared andlwr_halfblock_adr gets loaded with buff_start_adr and upr_halfblock_adrgets loaded with buff_start_adr+max_block+1. // assign write addressoutput to DRAM  cdu_diu_wadr[6:5]  = 00     // corresponds tolinenumber, only first address is // issued for each DRAM access. Thusline is always 0. // The DIU generates these bits of the address. cdu_diu_wadr[4:3] = color  if (half == 1) then   cdu_diu_wadr[21:7] =upr_halfblock_adr  // for lines 4-7 of JPEG block  else  cdu_diu_wadr[21:7] = lwr_halfblock_adr  // for lines 0-3 of JPEG block// update half, color, block and addresses after each DRAM write access if (rd_adv_half_block == 1) then   if (half == 1) then    half = 0   if (color == max_plane) then     color = 0     if (block ==max_block) then   // end of writing a line of JPEG blocks      pulsewradv8line      block = 0      // update half block address for start ofnext line of JPEG blocks taking      // account of address wrapping incircular buffer and 4 line offset      if (upr_halfblock_adr ==buff_end_adr) then       upr_halfblock_adr = buff_start_adr +max_block + 1       elsif (upr_halfblock_adr + max_block + 1 ==buff_end_adr) then       upr_halfblock_adr = buff_start_adr      else      upr_halfblock_adr = upr_halfblock_adr + max_block + 2     else     block ++      upr_halfblock_adr ++    // move to address for lines4-7 for next block    else     color ++   else    half = 1    if (color== max_plane) then     if (block == max_block) then // end of writing aline of JPEG blocks      // update half block address for start of nextline of JPEG blocks taking      // account of address wrapping incircular buffer and 4 line offset      if (lwr_halfblock_adr ==buff_end_adr) then       lwr_halfblock_adr = buff_start_adr +max_block + 1      elsif (lwr_halfblock_adr + max_block + 1 ==buff_end_adr) then       lwr_halfblock_adr = buff_start_adr      else      lwr_halfblock_adr = lwr_halfblock_adr + max_block + 2     else     lwr_halfblock_adr ++    // move to address for lines 0-3 for nextblock22.5.9 Contone Line Store Interface

The contone line store interface is responsible for providing thecontrol over the shared resource in DRAM. The CDU writes 8 lines of datain up to 4 color planes, and the CFU reads them line-at-a-time. Thecontone line store interface provides the mechanism for keeping track ofthe number of lines stored in DRAM, and provides signals so that a givenline cannot be read from until the complete line has been written.

The CDU writes 8 lines of data in parallel but writes the first 4 linesand second 4 lines to separate areas in DRAM. Thus, when the CFU hasread 4 lines from DRAM that area now becomes free for the CDU to writeto. Thus the size of the line store in DRAM should be a multiple of 4lines.

The minimum size of the line store interface is 8 lines, providing asingle buffer scheme. Typical sizes are 12 lines for a 1.5 buffer schemewhile 16 lines provides a double-buffer scheme.

The size of the contone line store is defined by num_buff_lines. A countis kept of the number of lines stored in DRAM that are available to bewritten to. When Go transitions from 0 to 1, NumLinesAvail is set to thevalue of num_buff_lines. The CDU may only begin to write to DRAM as longas there is space available for 8 lines, indicated when theline_store_ok_to_write bit is set.

When the CDU has finished writing 8 lines, the write control unit sendsan wradv8line pulse to the contone line store interface, andNumLinesAvail is decremented by 8. The write control unit then waits forline_store_ok_to_write to be set again.

If the contone line store is not empty (has one or more lines availablein it), the CDU will indicate to the CFU via the cdu_cfu_linestore_rdysignal. The cdu_cfu_linestore_rdy signal is generated by comparing theNumLinesAvail with the programmed num_buff_lines. As the CFU reads aline from the contone line store it will pulse the rdadvline to indicatethat it has read a full line from the line store. NumLinesAvail isincremented by 1 on receiving a rdadvline pulse.

To enable running the CDU while the CFU is not running the NumLinesAvailregister can also be updated via the configuration register interface.In this scenario the CPU polls the value of the NumLinesAvail registerand overwrites it to prevent stalling of the CDU (NumLinesAvail<8). TheCPU will always have priority in any updating of the NumLinesAvailregister.

23 Contone FIFO Unit (CFU)

23.1 Overview

The Contone FIFO Unit (CFU) is responsible for reading the decompressedcontone data layer from the circular buffer in DRAM, performing optionalcolor conversion from YCrCb to RGB followed by optional color inversionin up to 4 color planes, and then feeding the data on to the HCU.Scaling of data is performed in the horizontal and vertical directionsby the CFU so that the output to the HCU matches the printer resolution.Non-integer scaling is supported in both the horizontal and verticaldirections. Typically, the scale factor will be the same in bothdirections but may be programmed to be different.

23.2 Bandwidth Requirements

The CFU must read the contone data from DRAM fast enough to match therate at which the contone data is consumed by the HCU.

Pixels of contone data are replicated a X scale factor (SF) number oftimes in the X direction and Y scale factor (SF) number of times in theY direction to convert the final output to 1600 dpi. Replication in theX direction is performed at the output of the CFU on a pixel-by-pixelbasis while replication in the Y direction is performed by the CFUreading each line a number of times, according to the Y-scale factor,from DRAM. The HCU generates 1 dot (bi-level in 6 colors) per systemclock cycle to achieve a print speed of 1 side per 2 seconds for fullbleed A4/Letter printing. The CFU output buffer needs to be suppliedwith a 4 color contone pixel (32 bits) every SF cycles. With support for4 colors at 267 ppi the CFU must read data from DRAM at 5.33bits/cycle¹⁴.¹⁴32 bits/6 cycles=5.33 bits/cycle

23.3 Color Space Conversion

The CFU allows the contone data to be passed directly on, which will bethe case if the color represented by each color plane in the JPEG imageis an available ink. For example, the four colors may be C, M, Y, and K,directly represented by CMYK inks. The four colors may represent gold,metallic green etc. for multi-SoPEC printing with exact colors.

JPEG produces better compression ratIOs for a given visible quality whenluminance and chrominance channels are separated. With CMYK, K can beconsidered to be luminance, but C, M and Y each contain luminanceinformation and so would need to be compressed with appropriateluminance tables. We therefore provide the means by which CMY can bepassed to SoPEC as YCrCb. K does not need color conversion.

When being JPEG compressed, CMY is typically converted to RGB, then toYCrCb and then finally JPEG compressed. At decompression, the YCrCb datais obtained, then color converted to RGB, and finally back to CMY.

The external RIP provides conversion from RGB to YCrCb, specifically tomatch the actual hardware implementation of the inverse transform withinSoPEC, as per CCIR 601-2 [24] except that Y, Cr and Cb are normalized tooccupy all 256 levels of an 8-bit binary encoding.

The CFU provides the translation to either RGB or CMY. RGB is includedsince it is a necessary step to produce CMY, and some printers increasetheir color gamut by including RGB inks as well as CMYK.

Consequently the JPEG stream in the color space convertor is one of:

-   -   1 color plane, no color space conversion    -   2 color planes, no color space conversion    -   3 color planes, no color space conversion    -   3 color planes YCrCb, conversion to RGB    -   4 color planes, no color space conversion    -   4 color planes YCrCbX, conversion of YCrCb to RGB, no color        conversion of X

The YCrCb to RGB conversion is described in [14]. Note that if the datais non-compressed, there is no specific advantage in performing colorconversion (although the CDU and CFU do permit it).

23.4 Color Space Inversion

In addition to performing optional color conversion the CFU alsoprovides for optional bit-wise inversion in up to 4 color planes. Thisprovides the means by which the conversion to CMY may be finalised, orto may be used to provide planar correlation of the dither matrices.

The RGB to CMY conversion is given by the relationship:

-   -   C=255−R    -   M=255−G    -   Y=255−B

These relationships require the page RIP to calculate the RGB from CMYas follows:

-   -   R=255−C    -   G=255−M    -   B=255−Y        23.5 Scaling

Scaling of pixel data is performed in the horizontal and verticaldirections by the CFU so that the output to the HCU matches the printerresolution. The CFU supports non-integer scaling with the scale factorrepresented by a numerator and a denominator. Only scaling up of thepixel data is allowed, i.e. the numerator should be greater than orequal to the denominator. For example, to scale up by a factor of twoand a half, the numerator is programmed as 5 and the denominatorprogrammed as 2.

Scaling is implemented using a counter as described in the pseudocodebelow. An advance pulse is generated to move to the next dot (x-scaling)or line (y-scaling). if (count + denominator − numerator >= 0) then count = count + denominator − numerator  advance = 1 else  count =count + denominator  advance = 023.6 Lead-In and Lead-Out Clipping

The JPEG algorithm encodes data on a block by block basis, each blockconsists of 64 8-bit pixels (representing 8 rows each of 8 pixels). Ifthe image is not a multiple of 8 pixels in X and Y then padding must bepresent. This padding (extra pixels) will be present after decoding ofthe JPEG bytestream.

Extra padded lines in the Y direction (which may get scaled up in theCFU) will be ignored in the HCU through the setting of the BottomMarginregister.

Extra padded pixels in the X direction must also be removed so that thecontone layer is clipped to the target page as necessary.

In the case of a multi-SoPEC system, 2 SoPECs may be responsible forprinting the same side of a page, e.g. SoPEC #1 controls printing of theleft side of the page and SoPEC #2 controls printing of the right sideof the page and shown in FIG. 141. The division of the contone layerbetween the 2 SoPECs may not fall on a 8 pixel (JPEG block) boundary.The JPEG block on the boundary of the 2 SoPECs (JPEG block n below) willbe the last JPEG block in the line printed by SoPEC #1 and the firstJPEG block in the line printed by SoPEC #2. Pixels in this JPEG blocknot destined for SoPEC #1 are ignored by appropriately setting theLeadOutClipNum. Pixels in this JPEG block not destined for SoPEC #2 mustbe ignored at the beginning of each line. The number of pixels to beignored at the start of each line is specified by the LeadInClipNumregister. It may also be the case that the CDU writes out more JPEGblocks than is required to be read by the CFU, as shown for SBPEC #2below. In this case_the value of the MaxBlock register in the CDU is setto correspond to JPEG block m but the value for the MaxBlock register inthe CFU is set to correspond to JPEG block m⁻1. Thus JPEG block m is notread in by the CFU. Additional clipping on contone pixels is requiredwhen they are scaled up to the printer's resolution. The scaling of thefirst valid pixel in the line is controlled by setting the XstartCountregister. The HcuLineLength register defines the size of the target pagefor the contone layer at the printer's resolution and controls thescaling of the last valid pixel in a line sent to the HCU.

23.7 Implementation

FIG. 142 shows a block diagram of the CFU.

23.7.1 Definitions of I/O TABLE 150 CFU port list and description PortName Pins I/O Description Clocks and reset pclk 1 In System clock prst_n1 In System reset, synchronous active low. PCU interface pcu_cfu_sel 1In Block select from the PCU. When pcu_cfu_sel is high both pcu_adr andpcu_dataout are valid. pcu_rwn 1 In Common read/not-write signal fromthe PCU. pcu_adr[6:2] 4 In PCU address bus. Only 5 bits are required todecode the address space for this block. pcu_dataout[31:0] 32 In Sharedwrite data bus from the PCU. cfu_pcu_rdy 1 Out Ready signal to the PCU.When cfu_pcu_rdy is high it indicates the last cycle of the access. Fora write cycle this means pcu_dataout has been registered by the blockand for a read cycle this means the data on cfu_pcu_datain is valid.cfu_pcu_datain[31:0] 32 Out Read data bus to the PCU. DIU interfacecfu_diu_rreq 1 Out CFU read request, active high. A read request must beaccompanied by a valid read address. diu_cfu_rack 1 In Acknowledge fromDIU, active high. Indicates that a read request has been accepted andthe new read address can be placed on the address bus, cfu_diu_radr.cfu_diu_radr[21:5] 17 Out CFU read address. 17 bits wide (256-bitaligned word). diu_cfu_rvalid 1 In Read data valid, active high.Indicates that valid read data is now on the read data bus, diu_data.diu_data[63:0] 64 In Read data from DRAM. CDU interfacecdu_cfu_linestore_rdy 1 In When high indicates that the contone linestore has 1 or more lines available to be read by the CFU.cfu_cdu_rdadvline 1 Out Read line pulse, active high. Indicates that theCFU has finished reading a line of decompressed contone data to thecircular buffer in DRAM and that line of the buffer is now free. HCUinterface hcu_cfu_advdot 1 In Informs the CFU that the HCU has capturedthe pixel data on cfu_hcu_c[0-3]data lines and the CFU can now place thenext pixel on the data lines. cfu_hcu_avail 1 Out Indicates valid datapresent on cfu_hcu_c[0-3]data lines. cfu_hcu_c0data[7:0] 8 Out Pixel ofdata in contone plane 0. cfu_hcu_c1data[7:0] 8 Out Pixel of data incontone plane 1. cfu_hcu_c2data[7:0] 8 Out Pixel of data in contoneplane 2. cfu_hcu_c3data[7:0] 8 Out Pixel of data in contone plane 3.23.7.2 Configuration Registers

The configuration registers in the CFU are programmed via the PCUinterface. Refer to section 21.8.2 on page 321 for the description ofthe protocol and timing diagrams for reading and writing registers inthe CFU. Note that since addresses in SoPEC are byte aligned and the PCUonly supports 32-bit register reads and writes, the lower 2 bits of thePCU address bus are not required to decode the address space for theCFU. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of cfu_pcu_datain. Theconfiguration registers of the CFU are listed in Table 151: TABLE 151CFU registers Value Address on (CFU_base+) Register Name #bits ResetDescription Control registers 0x00 Reset 1 0x1 A write to this registercauses a reset of the CFU. 0x04 Go 1 0x0 Writing 1 to this registerstarts the CFU. Writing 0 to this register halts the CFU. When Go isdeasserted the state- machines go to their idle states but all countersand configuration registers keep their values. When Go is asserted allcounters are reset, but configuration registers keep their values (i.e.they don't get reset). The CFU must be started before the CDU isstarted. This register can be read to determine if the CFU is running(1 - running, 0 - stopped). Setup registers 0x10 MaxBlock 13 0x000Number of JPEG MCUs (or JPEG block equivalents, i.e. 8 × 8 bytes) in aline - 1. 0x14 BuffStartAdr[21:7] 15 0x0000 Points to the start of thedecompressed contone circular buffer in DRAM, aligned to a half JPEGblock boundary. A half JPEG block consists of 4 words of 256-bits,enough to hold 32 contone pixels in 4 colors, i.e. half a JPEG block.0x18 BuffEndAdr[21:7] 15 0x0000 Points to the end of the decompressedcontone circular buffer in DRAM, aligned to a half JPEG block boundary(address is inclusive). A half JPEG block consists of 4 words of256-bits, enough to hold 32 contone pixels in 4 colors, i.e. half a JPEGblock. 0x1C 4LineOffset 13 0x0000 Defines the offset between the startof one 4 line store to the start of the next 4 line store −1. In Figure$$n page394 on page Error! Bookmark not defined., if BufStartAdrcorresponds to line 0 block 0 then BuffStartAdr + 4LineOffsetcorresponds to line 4 block 0. 4LineOffset is specified in units of128bytes, eg 0-128 bytes, 1-256 bytes etc. This register is required inaddition to MaxBlock as the number of JPEG blocks in a line required bythe CFU may be different from the number of JPEG blocks in a linewritten by the CDU. 0x20 YCrCb2RGB 1 0x0 Set this bit to enableconversion from YCrCb to RGB. Should not be changed between bands. 0x24InvertColorPlane 4 0x0 Set these bits to perform bit-wise inversion on aper color plane basis. bit0 - 1 invert color plane 0 0 do not convertbit1 - 1 invert color plane 1 0 do not convert bit2 - 1 invert colorplane 2 0 do not convert bit3 - 1 invert color plane 3 Should not bechanged between bands. 0x28 HcuLineLength 16 0x0000 Number of contonepixels − 1 in a line (after scaling). Equals the number ofhcu_cfu_dotadv pulses − 1 received from the HCU for each line of contonedata. 0x2C LeadInClipNum 3 0x0 Number of contone pixels to be ignored atthe start of a line (from JPEG block 0 in a line). They are not passedto the output buffer to be scaled in the X direction. 0x30LeadOutClipNum 3 0x0 Number of contone pixels to be ignored at the endof a line (from JPEG block MaxBlock in a line). They are not passed tothe output buffer to be scaled in the X direction. 0x34 XstartCount 80x00 Value to be loaded at the start of every line into the counter usedfor scaling in the X direction. Used to control the scaling of the firstpixel in a line to be sent to the HCU. This value will typically bezero, except in the case where a number of dots are clipped on the leadin to a line. 0x38 XscaleNum 8 0x01 Numerator of contone scale factor inX direction. 0x3C XscaleDenom 8 0x01 Denominator of contone scale factorin X direction. 0x40 YscaleNum 8 0x01 Numerator of contone scale factorin Y direction. 0x44 YscaleDenom 8 0x01 Denominator of contone scalefactor in Y direction.23.7.3 Storage of Decompressed Contone Data in DRAM

The CFU reads decompressed contone data from DRAM in single 256-bitaccesses. JPEG blocks of decompressed contone data are stored in DRAMwith the memory arrangement as shown The arrangement is in order tooptimize access for reads by writing the data so that 4 color componentsare stored together in each 256-bit DRAM word. The means that the CFUreads 64-bits in 4 colors from a single line in each 256-bit DRAMaccess.

The CFU reads data line at a time in 4 colors from DRAM. The readsequence, as shown in FIG. 143, is as follows:  line 0, block 0 in wordp of DRAM  line 0, block 1 in word p+4 of DRAM .........................................  line 0, block n in word p+4nof DRAM  (repeat to read line a number of times according to scalefactor)  line 1, block 0 in word p+1 of DRAM  line 1, block 1 in wordp+5 of DRAM  etc......................................

The CFU reads a complete line in up to 4 colors a Y scale factor numberof times from DRAM before it moves on to read the next. When the CFU hasfinished reading 4 lines of contone data that 4 line store becomesavailable for the CDU to write to.

23.7.4 Decompressed Contone Buffer

Since the CFU reads 256 bits (4 colors x 64 bits) from memory at a time,it requires storage of at least 2×256 bits at its input. To allow forall possible DIU stall conditions the input buffer is increased to 3×256bits to meet the CFU target bandwidth requirements. The CFU receives thedata from the DIU over 4 clock cycles (64-bits of a single color percycle). It is implemented as 4 buffers. Each buffer conceptually is a64-bit input and 8-bit output buffer to account for the 64-bit datatransfers from the DIU, and the 8-bit output per color plane to thecolor space converter.

On the DRAM side, wr_buff indicates the current buffer within eachtriple-buffer that writes are to occur to. wr_sel selects whichtriple-buffer to write the 64 bits of data to when wr_en is asserted. Onthe color space converter side, rd_buff indicates the current bufferwithin each triple-buffer that reads are to occur from. When rd_en isasserted a byte is read from each of the triple-buffers in parallel.rd_sel is used to select a byte from the 64 bits (1st byte correspondsto bits 7-0, second byte to bits 15-8 etc.).

Due to the limitations of available register arrays in IBM technology,the decompressed contone buffer is implemented as a quadruple buffer.While this offers some benefits for the CFU it is not necessitated bythe bandwidth requirements of the CFU.

23.7.5 Y-Scaling Control Unit

The Y-scaling control unit is responsible for reading the decompressedcontone data and passing it to the color space converter via thedecompressed contone buffer. The decompressed contone data is read fromDRAM in single 256-bit accesses, receiving the data from the DIU over 4clock cycles (64-bits per cycle). The protocol and timing for readaccesses to DRAM is described in section 20.9.1 on page 240. Readaccesses to DRAM are implemented by means of the state machine describedin FIG. 144.

All counters and flags should be cleared after reset. When Gotransitions from 0 to 1 all counters and flags should take their initialvalue. While the Go bit is set, the state machine relies on theline8_ok_to_read and buff_ok_to_write flags to tell it whether toattempt to read a line of compressed contone data from DRAM. Whenline8_ok_to_read is 0 the state machine does nothing. Whenline8_ok_to_read is 1 the state machine continues to load data into thedecompressed contone buffer up to 256-bits at a time while there isspace available in the buffer. A bit is kept for the status of each64-bit buffer: buff_avail[0] and buff_avail[1]. It also keeps a singlebit (rd_buff) for the current buffer that reads are to occur from, and asingle bit (wr_buff) for the current buffer that writes are to occur to.

-   -   buff ok_to_write equals ˜buff_avail[wr_buff]. When a wr_adv_buff        pulse is received, buff_avail[wr_buff] is set, and wr_buff is        inverted. Whenever diu_cfu_rvalid is asserted, wr_en is asserted        to write the 64-bits of data from DRAM to the buffer selected by        wr_sel and wr_buff.    -   buff ok_to_read equals buff_avail[rd_buff]. If there is data        available in the buffer and the output double-buffer has space        available (outbuff_ok_to_write equals 1) then data is read from        the buffer by asserting rd_en and rd_sel gets incremented to        point to the next value. wr_adv is asserted in the following        cycle to write the data to the output double-buffer of the CFU.        When finished reading the buffer, rd_sel equals b111 and rd_en        is asserted, buff_avail[rd_buff] is set, and rd_buff is        inverted.

Each line is read a number of times from DRAM, according to the Y-scalefactor, before the CFU moves on to start reading the next line ofdecompressed contone data. Scaling to the printhead resolution in the Ydirection is thus performed.

The pseudocode below shows how the read address from DRAM is calculatedon a per clock cycle basis. Note all counters and flags should becleared after reset or when Go is cleared. When a 1 is written to Go,both curr_halfblock and line_start_halfblock get loaded withbuff_start_adr, and y_scale_count gets loaded with y_scale_denom.Scaling in the Y direction is implemented by line replication byre-reading lines from DRAM. The algorithm for non-integer scaling isdescribed in the pseudocode below. // assign read address output to DRAM cdu_diu_wadr[21:7] = curr_halfblock  cdu_diu_wadr[6:5] = line[1:0] //update block, line, y_scale_count and addresses after each DRAM readaccess  if (wr_adv_buff == 1) then   if (block == max_block) then   //end of reading a line of contone in up to 4 colors    block = 0    //check whether to advance to next line of contone data in DRAM    if(y_scale_count + y_scale_denom − y_scale_num >= 0) then    y_scale_count = y_scale_count + y_scale_denom − y_scale_num    pulse RdAdvline     if (line == 3) then   // end of reading 4 linestore of contone data      line = 0      // update half block addressfor start of next line taking account of      // address wrapping incircular buffer and 4 line offset      if (curr_halfblock ==buff_end_adr) then       curr_halfblock = buff_start_adr      line_start_adr = buff_start_adr      elsif ((line_start_adr +4line_offset) == buff_end_adr)) then       curr_halfblock =buff_start_adr       line_start_adr = buff_start_adr      else      curr_halfblock  = line_start_adr + 4line_offset      line_start_adr = line_start_adr + 4line_offset     else      line++      curr_halfblock = line_start_adr    else     // re-read currentline from DRAM     y_scale_count = y_scale_count + y_scale_denom    curr_halfblock = line_start_adr   else    block ++    curr_halfblock++23.7.6 Contone Line Store Interface

The contone line store interface is responsible for providing thecontrol over the shared resource in DRAM. The CDU writes 8 lines of datain up to 4 color planes, and the CFU reads them line-at-a-time. Thecontone line store interface provides the mechanism for keeping track ofthe number of lines stored in DRAM, and provides signals so that a givenline cannot be read from until the complete line has been written.

A count is kept of the number of lines that have been written to DRAM bythe CDU and are available to be read by the CFU. At start-up,buff_lines_avail is set to the 0. The CFU may only begin to read fromDRAM when the CDU has written 8 complete lines of contone data. When theCDU has finished writing 8 lines, it sends an cdu_cfu_wradv8line pulseto the CFU, and buff_lines_avail is incremented by 8. The CFU maycontinue reading from DRAM as long as buff_lines_avail is greater than0. line8_ok_to_read is set while buff_lines_avail is greater than 0.When it has completely finished reading a line of contone data fromDRAM, the Y-scaling control unit sends a RdAdvLine signal to contoneline store interface and to the CDU to free up the line in the buffer inDRAM. buff_lines_avail is decremented by 1 on receiving a RdAdvlinepulse.

23.7.7 Color Space Converter (CSC)

The color space converter consists of 2 stages: optional colorconversion from YCrCb to RGB followed by optional bit-wise inversion inup to 4 color planes.

The convert YCrCb to RGB block takes 3 8-bit inputs defined as Y, Cr,and Cb and outputs either the same data YCrCb or RGB. The YCrCb2RGBparameter is set to enable the conversion step from YCrCb to RGB. IfYCrCb2RGB equals 0, the conversion does not take place, and the inputpixels are passed to the second stage. The 4th color plane, if present,bypasses the convert YCrCb to RGB block. Note that the latency of theconvert YCrCb to RGB block is 1 cycle. This latency should be equalizedfor the 4th color plane as it bypasses the block.

The second stage involves optional bit-wise inversion on a per colorplane basis under the control of invert_color_plane. For example if theinput is YCrCbK, then YCrCb2RGB can be set to 1 to convert YCrCb to RGB,and invert_color_plane can be set to 0111 to then convert the RGB toCMY, leaving K unchanged.

If YCrCb2RGB equals 0 and invert_color_plane equals 0000, no colorconversion or color inversion will take place, so the output pixels willbe the same as the input pixels.

FIG. 145 shows a block diagram of the color space converter.

The convert YCrCb to RGB block is an implementation of [14]. Althoughonly 10 bits of coefficients are used (1 sign bit, 1 integer bit, 8fractional bits), full internal accuracy is maintained with 18 bits. Theconversion is implemented as follows:

-   -   R*=Y+(359/256)(Cr−128)    -   G*=Y−(183/256)(Cr−128)−(88/256)(Cb−128)    -   B*=Y+(454/256)(Cb−128)

R*, G* and B* are rounded to the nearest integer and saturated to therange 0-255 to give R, G and B. Note that, while a Reset results inall-zero output, a zero input gives output RGB=[0¹⁵, 136¹⁶, 0¹⁷].¹⁵-179 is saturated to 0¹⁶135.5, with rounding becomes 136.¹⁷-227 is saturated to 0

23.7.8 X-Scaling Control Unit

The CFU has a 2×32-bit double-buffer at its output between the colorspace converter and the HCU. The X-scaling control unit performs thescaling of the contone data to the printers output resolution, providesthe mechanism for keeping track of the current read and write buffers,and ensures that a buffer cannot be read from until it has been writtento.

A bit is kept for the status of each 32-bit buffer: buff_avail[0] andbuff_avail[1]. It also keeps a single bit (rd_buff) for the currentbuffer that reads are to occur from, and a single bit (wr_buff) for thecurrent buffer that writes are to occur to.

The output value outbuff_ok_to_write equals ˜buff_avail[wr_buff].Contone pixels are counted as they are received from the Y-scalingcontrol unit, i.e. when wr_adv is 1. Pixels in the lead-in and lead-outareas are ignored, i.e. they are not written to the output buffer.Lead-in and lead-out clipping of pixels is implemented by the followingpseudocode that generates the wr_en pulse for the output buffer.  if(wradv == 1) then   if (pixel_count == {max_block,b111}) then   pixel_count = 0   else    pixel_count ++   if ((pixel_count <leadin_clip_num)      OR (pixel_count > ({max_block,b111} −leadout_clip_num))) then    wr_en = 0   else    wr_en = 1

When a wr_en pulse is sent to the output double-buffer,buff_avail[wr_buff] is set, and wr_buff is inverted.

The output cfu_hcu_avail equals buff_avail[rd_buff]. When cfu_hcu_availequals 1, this indicates to the HCU that data is available to be readfrom the CFU. The HCU responds by asserting hcu_cfu_advdot to indicatethat the HCU has captured the pixel data on cfu_hcu_c[0-3]data lines andthe CFU can now place the next pixel on the data lines.

The input pixels from the CSC may be scaled a non-integer number oftimes in the X direction to produce the output pixels for the HCU at theprinthead resolution. Scaling is implemented by pixel replication. Thealgorithm for non-integer scaling is described in the pseudocode below.Note, x_scale_count should be loaded with x_start_count after reset andat the end of each line. This controls the amount by which the firstpixel is scaled by. hcu_line_length and hcu_cfu_dotadv control theamount by which the last pixel in a line that is sent to the HCU isscaled by.  if (hcu_cfu_dotadv == 1) then   if (x_scale_count +x_scale_denom − x_scale_num >= 0) then   x_scale_count = x_scale_count + x_scale_denom − x_scale_num    rd_en= 1   else    x_scale_count = x_scale_count + x_scale_denom    rd_en = 0 else   x_scale_count = x_scale_count   rd_en = 0

When a rd_en pulse is received, buff_avail[rd_buff] is cleared, andrd_buff is inverted.

A 16-bit counter, dot_adv_count, is used to keep a count of the numberof hcu_cfu_dotadv pulses received from the HCU. If the value ofdot_adv_count equals hcu_line_length and a hcu_cfu_dotadv pulse isreceived, then a rd_en pulse is genrated to present the next dot at theoutput of the CFU, dot_adv_count is reset to 0 and x_scale_count isloaded with x_start_count.

24 Lossless Bi-Level Decoder (LBD)

24.1 Overview

The Lossless Bi-level Decoder (LBD) is responsible for decompressing asingle plane of bi-level data. In SoPEC bi-level data is limited to asingle spot color (typically black for text and line graphics).

The input to the LBD is a single plane of bi-level data, read as abitstream from DRAM. The LBD is programmed with the start address of thecompressed data, the length of the output (decompressed) line, and thenumber of lines to decompress. Although the requirement for SoPEC is tobe able to print text at 10:1 compression, the LBD can cope with anycompression ratio if the requested DRAM access is available. Apass-through mode is provided for 1:1 compression. Ten-point plain textcompresses with a ratio of about 50:1. Lossless bi-level compressionacross an average page is about 20:1 with 10:1 possible for pages whichcompress poorly.

The output of the LBD is a single plane of decompressed bi-level data.The decompressed bi-level data is output to the SFU (Spot FIFO Unit),and in turn becomes an input to the HCU (Halftoner/Compositor unit) forthe next stage in the printing pipeline. The LBD also outputs albd_finishedband control flag that is used by the PCU and is availableas an interrupt to the CPU.

24.2 Main Features OF LBD

FIG. 147 shows a schematic outline of the LBD and SFU.

The LBD is required to support compressed images of up to 800 dpi. Ifpossible we would like to support bi-level images of up to 1600 dpi. Theline buffers must therefore be long enough to store a complete line at1600 dpi.

The PEC1 LBD is required to output 2 dots/cycle to the HCU. Thisthroughput capability is retained for SoPEC to minimise changes to theblock, although in SoPEC the HCU will only read 1 dot/cycle. The PEC1LDB outputs 16 bits in parallel to the PEC1 spot buffer. This is alsoretained for SoPEC. Therefore the LBD in SoPEC can run much faster thanis required. This is useful for allowing stalls, e.g. due to bandprocessing latency, to be absorbed.

The LBD has a pass through mode to cope with local negative compression.Pass through mode is activated by a special run-length code. Passthrough mode continues to either end of line or for a pre-programmednumber of bits, whichever is shorter. The special run-length code isalways executed as a run-length code, followed by pass through.

The LBD outputs decompressed bi-level data to the NextLineFiFO in theSpot FIFO Unit (SFU). This stores the decompressed lines in DRAM, with atypical minimum of 2 lines stored in DRAM, nominally 3 lines up to aprogrammable number of lines. The SFU's NextLineFIFO can fill while theSFU waits for write access to DRAM. Therefore the LBD must be able tosupport stalling at its coding process. This is provided by the SFU viait's output during a line.

The LBD uses the previous line in the decoding process. This is providedby the SFU via it's PrevLineFIFO. Decoding can stall in the LBD whilethis FIFO waits to be filled from DRAM. A signal sfu_lbd_rdy indicatesthat both the SFU's NextLineFIFO and PrevLineFIFO are available forwriting and reading, respectively.

A configuration register in the LBD controls whether the first linebeing decoded at the start of a band uses the previous line read fromthe SFU or uses an all 0's line instead.

The line length is stored in DRAM must be programmable to a valuegreater than 128. An A4 line of 13824 dots requires 1.7 Kbytes ofstorage. An A3 line of 19488 dots requires 2.4 Kbytes of storage.

The compressed spot data can be read at a rate of 1 bit/cycle for passthrough mode 1:1 compression.

The LBD finished band signal is exported to the PCU and is additionallyavailable to the CPU as an interrupt.

24.2.1 Bi-Level Decoding in the LBD

The black bi-level layer is losslessly compressed using SilverbrookModified Group 4 (SMG4) compression which is a version of Group 4Facsimile compression [22] without Huffman and with simplified runlength encodings. The encoding are listed in Table 152 and Table 153.TABLE 152 Bi-Level group 4 facsimile style compression encodingsEncoding Description same as Group 4 Facsimile  1000Pass  Command:  a0 ← b2, skip  next  two  edges    1Vertical(0):  a0 ← b1, color = \!color   110Vertical(1):  a0 ← b1 + 1, color = \!color   010Vertical(−1):  a0 ← b1 − 1, color = \!color 110000Vertical(2):  a0 ← b1 + 2, color = \!color 010000Vertical(−2):  a0 ← b1 − 2, color = \!color Unique to thisimplementation 100000 Vertical(3):  a0 ← b1 + 3, color = \!color 000000Vertical(−3):  a0 ← b1 − 3, color = \!color <RL><RL>10    0Horizontal:  a0 ← a0+ < RL > + < RL>

SMG4 has a pass through mode to cope with local negative compression.Pass through mode is activated by a special run-length code. Passthrough mode continues to either end of line or for a pre-programmednumber of bits, whichever is shorter. The special run-length code isalways executed as a run-length code, followed by pass through. The passthrough escape code is a medium length run-length with a run of lessthan or equal to 31. TABLE 153 Run length (RL) encodings EncodingDescription Unique to this RRRRR1 Short Black implementation Runlength(5 bits) RRRRR1 Short White Runlength (5 bits) RRRRRRRRRR10 Medium BlackRunlength (10 bits) RRRRRRRR10 Medium White Runlength (8 bits)RRRRRRRRRR10 Medium Black Runlength with RRRRRRRRRR <=31, Enter passthrough RRRRRRRR10 Medium White Runlength with RRRRRRRR <=31, Enter passthrough RRRRRRRRRRRRRRR00 Long Black Runlength (15 bits)RRRRRRRRRRRRRRR00 Long White Runlength (15 bits)

Since the compression is a bitstream, the encodings are read right(least significant bit) to left (most significant bit). The run lengthsgiven as RRRRR in Table 153 are read in the same way (least significantbit at the right to most significant bit at the left).

There is an additional enhancement to the G4 fax algorithm, it relatesto pass through mode. It is possible for data to compress negativelyusing the G4 fax algorithm. On occasions like this it would be easier topass the data to the LBD as un-compressed data. Pass through mode is anew feature that was not implemented in the PEC1 version of the LBD.When the LBD is in pass through mode the least significant bit of thedata stream is an un-compressed bit. This bit is used to construct thecurrent line.

To enter pass through mode the LBD takes advantage of the way runlengths can be written.

Usually if one of the runlength pair is less than or equal to 31 itshould be encoded as a short runlength. However under the coding schemeof Table it is still legal to write it as a medium or long runlength.The LBD has been designed so that if a short runlength value is detectedin a medium runlength then once the horizontal command containing thisrunlength is decoded completely this will tell the LBD to enter passthrough mode and the bits following the runlength is un-compressed data.The number of bits to pass through is either a programmed number of bitsor the end of the line which ever comes first. Once the pass throughmode is completed the current color is the same as the color of the lastbit of the passed through data.

24.2.2 DRAM Access Requirements

The compressed page store for contone, bi-level and raw tag data is 2Mbytes. The LBD will access the compressed page store in single 256-bitDRAM reads. The LBD will need a 256-bit double buffer in its interfaceto the DIU. The LBD's DIU bandwidth requirements are summarized in Table154 TABLE 154 DRAM bandwidth requirements Maximum number of Averagecycles between each Peak Bandwidth Bandwidth Direction 256-bit DRAMaccess (bits/cycle) (bits/cycle) Read 2561 (1:1 compression) 1 (1:1compression) 0.1 (10:1 compression)

1: At 1:1 compression the LBD requires 1 bit/cycle or 256 bits every 256cycles.

24.3 Implementation

24.3.1 Definitions of IO TABLE 155 LBD Port List Port Name Pins I/ODescription Clocks and Resets Pclk 1 In SoPEC Functional clock. prst_n 1In Global reset signal. Bandstore signals cdu_endofbandstore[21:5] 17 InAddress of the end of the current band of data. 256-bit word alignedDRAM address. cdu_startofbandstore[21:5] 17 In Address of the start ofthe current band of data. 256-bit word aligned DRAM address.lbd_finishedband 1 Out LBD finished band signal to PCU and InterruptController. DIU Interface signals lbd_diu_rreq 1 Out LBD requests DRAMread. A read request must be accompanied by a valid read address.lbd_diu_radr[21:5] 17 Out Read address to DIU 17 bits wide (256-bitaligned word). diu_lbd_rack 1 In Acknowledge from DIU that read requesthas been accepted and new read address can be placed on lbd_diu_radr.diu_data[63:0] 64 In Data from DIU to SoPEC Units. First 64-bits is bits63:0 of 256 bit word. Second 64-bits is bits 127:64 of 256 bit word.Third 64-bits is bits 191:128 of 256 bit word. Fourth 64-bits is bits255:192 of 256 bit word. diu_lbd_rvalid 1 In Signal from DIU tellingSoPEC Unit that valid read data is on the diu_data bus PCU Interfacedata and control signals pcu_addr[5:2] 4 In PCU address bus. Only 4 bitsare required to decode the address space for this block.pcu_dataout[31:0] 32 In Shared write data bus from the PCU.lbd_pcu_datain[31:0] 32 Out Read data bus from the LBD to the PCU.pcu_rwn 1 In Common read/not-write signal from the PCU. pcu_lbd_sel 1 InBlock select from the PCU. When pcu_lbd_sel is high both pcu_addr andpcu_dataout are valid. lbd_pcu_rdy 1 Out Ready signal to the PCU. Whenlbd_pcu_rdy is high it indicates the last cycle of the access. For awrite cycle this means pcu_dataout has been registered by the block andfor a read cycle this means the data on lbd_pcu_datain is valid. SFUInterface data and control signals sfu_lbd_rdy 1 In Ready signalindicating SFU has previous line data available for reading and is alsoready to be written to. lbd_sfu_advline 1 Out Advance line signal toprevious and next line buffers lbd_sfu_pladvword 1 Out Advance wordsignal for previous line buffer. sfu_lbd_pldata[15:0] 16 In Data fromthe previous line buffer. lbd_sfu_wdata[15:0] 16 Out Write data for nextline buffer. lbd_sfu_wdatavalid 1 Out Write data valid signal for nextline buffer data.

24.3.2 Configuration Registers TABLE 156 LBD Configuration RegistersValue Address Register on (LBD_base+) Name #Bits Reset DescriptionControl registers 0x00 Reset 1 0x1 A write to this register causes areset of the LBD. This register can be read to indicate the reset state:0 - reset in progress 1 - reset not in progress 0x04 Go 1 0x0 Writing 1to this register starts the LBD. Writing 0 to this register halts theLBD. The Go register is reset to 0 by the LBD when it finishesprocessing a band. When Go is deasserted the state-machines go to theiridle states but all counters and configuration registers keep theirvalues. When Go is asserted all counters are reset, but configurationregisters keep their values (i.e. they don't get reset). The LBD shouldonly be started after the SFU is started. This register can be read todetermine if the LBD is running (1 - running, 0 - stopped). Setupregisters (constant for during processing the page) 0x08 LineLength 160x0000 Width of expanded bi-level line (in dots) (must be set greaterthan 128 bits). 0x0C PassThrough 1 0x1 Writing 1 to this registerenables passthrough Enable mode. Writing 0 to this register disablespass- through mode thereby making the LBD compatible with PEC1. 0x10PassThrough 16 0x0000 This is the dot length - 1 for which pass-DotLength through mode will last. If the end of the line is reachedfirst then pass-through will be disabled. The value written to thisregister must be a non-zero value. Work registers (need to be set upbefore processing a band) 0x14 NextBandCurrReadAdr[21:5] 17 0x00000Shadow register which is copied to (256-bit CurrReadAdr when(NextBandEnable == 1 & aligned Go == 0). DRAM NextBandCurrReadAdr is theaddress of the address) start of the next band of compressed bi-leveldata in DRAM. 0x18 NextBandLinesRemaining 15 0x0000 Shadow registerwhich is copied to Lines- Remaining when (NextBandEnable == 1 & Go ==0). NextBandLinesRemaining is the number of lines to be decoded in thenext band of compressed bi-level data. 0x1C NextBandPrevLineSource 1 0x0Shadow register which is copied to Prev- LineSource when (NextBandEnable== 1 & Go == 0). 1 - use the previous line read from the SFU fordecoding the first line at the start of the next band. 0 - ignore theprevious line read from the SFU for decoding the first line at the startof the next band (an all 0's line is used instead). 0x20 NextBandEnable1 0x0 If (NextBandEnable == 1 & Go == 0) then NextBandCurrReadAdr iscopied to CurrReadAdr, NextBandLinesRemaining is copied toLinesRemaining, NextBandPrevLineSource is copied to PrevLineSource, Gois set, NextBandEnable is cleared. To start LBD processingNextBandEnable should be set. Work registers (read only for externalaccess) 0x24 CurrReadAdr[21:5] 17 — The current 256-bit aligned readaddress (256-bit within the compressed bi-level image (DRAM alignedaddress). Read only register. DRAM address) 0x28 LinesRemaining 15 —Count of number of lines remaining to be decoded. The band has finishedwhen this number reaches 0. Read only register. 0x2C PrevLineSource 1 —1 - uses the previous line read from the SFU for decoding the first lineat the start of the next band. 0 - ignores the previous line read fromthe SFU for decoding the first line at the start of the next band (anall 0's line is used instead). Read only register. 0x30 CurrWriteAdr 15— The current dot position for writing to the SFU. Read only register.0x34 FirstLineOfBand 1 — Indicates whether the current line isconsidered to be the first line of the band. Read only register.24.3.3 Starting the LBD Between Bands

The LBD should be started after the SFU. The LBD is programed with astart address for the compressed bi-level data, a decode line length,the source of the previous line and a count of how many lines to decode.The LBD's NextBandEnable bit should then be set (this will set LBD Go).The LBD decodes a single band and then stops, clearing it's Go bit andissuing a pulse on lbd_finishedband. The LBD can then be restarted forthe next band, while the HCU continues to process previously decodedbi-level data from the SFU.

There are 4 mechanisms for restarting the LBD between bands:

-   a. lbd_finishedband causes an interrupt to the CPU. The LBD will    have stopped and cleared its Go bit. The CPU reprograms the LBD,    typically the NextBandCurrReadAdr, NextBandLinesRemaining and    NextBandPrevLineSource shadow registers, and sets NextBandEnable to    restart the LBD.-   b. The CPU programs the LBD's NextBandCurrReadAdr,    NextBandLinesRemaining, and NextBandPrevLineSource shadow registers    and sets the NextBandEnable flag before the end of the current band.    At the end of the band the LBD clears Go, NextBandEnable is already    set so the LBD restarts immediately.-   c. The PCU is programmed so that lbd_finishedband triggers the PCU    to execute commands from DRAM to reprogram the LBD's    NextBandCurrReadAdr, NextBandLinesRemaining, and    NextBandPrevLineSource shadow registers and set NextBandEnable to    restart the LBD. The advantage of this scheme is that the CPU could    process band headers in advance and store the band commands in DRAM    ready for execution.-   d. This is a combination of b and c above. The PCU (rather than the    CPU in b) programs the LBD's NextBandCurrReadAdr,    NextBandLinesRemaining, and NextBandPrevLineSource shadow registers    and sets the NextBandEnable flag before the end of the current band.    At the end of the band the LBD clears Go and pulses    lbd_finishedband. NextBandEnable is already set so the LBD restarts    immediately. Simultaneously, lbd_finishedband triggers the PCU to    fetch commands from DRAM. The LBD will have restarted by the time    the PCU has fetched commands from DRAM. The PCU commands program the    LBD's shadow registers and sets NextBandEnable for the next band.    24.3.4 Top-Level Description

A block diagram of the LBD is shown in FIG. 148.

The LBD contains the following sub-blocks: TABLE 157 Functionalsub-blocks in the LBD name Description Registers and Resets PCUinterface and configuration registers. Also generates the Go and theReset signals for the rest of the LBD Stream Decoder Accesses thebi-level description from the DRAM through the DIU interface. It decodesthe bit stream into a command with arguments, which it then passes tothe command controller. Command Controller Interprets the command fromthe stream decoder and provide the line fill unit with a limit addressand color to fill the SFU Next Line Buffer. It also provides the nextedge unit starting address to look for the next edge. Next Edge UnitScans through the Previous Line Buffer using its current address to findthe next edge of a color provided by the command controller. The nextedge unit outputs this as the next current address back to the commandcontroller and sets a valid bit when this address is at the next edge.Line Fill Unit Fills the SFU Next Line Buffer with a color from itscurrent address up to a limit address. The color and limit are providedby the command controller.

In the following description the LBD decodes data for its current decodeline but writes this data into the SFU's next line buffer.

Naming of signals and logical blocks are taken from [22].

The LBD is able to stall mid-line should the SFU be unable to supply aprevious line or receive a current line frame due to band processinglatency.

All output control signals from the LBD must always be valid afterreset. For example, if the LBD is not currently decoding,lbd_sfu_advline (to the SFU) and lbd_finishedband will always be 0.

24.3.5 Registers and Resets Sub-Block Description

Since the CDU, LBD and TE all access the page band store, they share tworegisters that enable sequential memory accesses to the page band storesto be circular in nature. The CDU chapter lists these two registers. Theregister descriptions for the LBD are listed in Table.

During initialisation of the LBD, the LineLength and the LinesRemainingconfiguration values are written to the LBD. The ‘Registers and Resets’sub-block supplies these signals to the other sub-blocks in the LBD. Inthe case of LinesRemaining, this number is decremented for every linethat is completed by the LBD.

If pass through is used during a band the PassThroughEnable registerneeds to be programmed and PassThroughDotLength programmed with thelength of the compressed bits in pass through mode.

PrevLineSource is programmed during the initialisation of a band, if theprevious line supplied for the first line is a valid previous line, a 1is written to PrevLineSource so that the data is used. If a 0 is writtenthe LBD ignores the previous line information supplied and acts as if itis receiving all zeros for the previous line regardless of what the outof the SFU is.

The ‘Registers and Resets’ sub-block also generates the resets used bythe rest of the LBD and the Go bit which tells the LBD that it can startrequesting data from the DIU and commence decoding of the compresseddata stream.

24.3.6 Stream Decoder Sub-Block Description

The Stream Decoder reads the compressed bi-level image from the DRAM viathe DIU (single accesses of 256-bits) into a double 256-bit FIFO. Thebarrel shift register uses the 64-bit word from the FIFO to fill up theempty space created by the barrel shift register as it is shifting it'scontents. The bit stream is decoded into a command/arguments pair, whichin turn is passed to the command controller.

A dataflow block diagram of the stream decoder is shown in FIG. 149.

24.3.6.1 DecodeC—Decode Command

The DecodeC logic encodes the command from bits 6..0 of the bit streamto output one of three commands: SKIP, VERTICAL and RUNLENGTH. It alsoprovides an output to indicate how many bits were consumed, which feedsback to the barrel shift register.

There is a fourth command, PASS_THROUGH, which is not encoded in bits6..0, instead it is inferred in a special runlength. If the streamdecoder detects a short runlength value, i.e. a number less than 31,encoded as a medium runlength this tell the Stream Decoder that once thehorizontal command containing this runlength is decoded completely theLBD enters PASS_THROUGH mode. Following the runlength there will be anumber of bits that represent un-compressed data. The LBD will stay inPASS_THROUGH mode until all these bits have been decoded successfully,this will occur once a programmed number of bits is reached or the lineends, which ever comes first.

24.3.6.2 DecodeD—Decode Delta

The DecodeD logic decodes the run length from bits 20..3 of the bitstream. If DecodeC is decoding a vertical command, it will cause DecodeDto put constants of −3 through 3 on its output. The output delta is a 15bit number, which is generally considered to be positive, but since itneeds to only address to 13824 dots for an A4 page and 19488 dots for anA3 page (of 32,768), a 2's complement representation of −3, −2, −1 willwork correctly for the data pipeline that follows. This unit alsooutputs how many bits were consumed.

In the case of PASS_THROUGH mode, DecodeD parses the bits that representthe un-compressed data and this is used by the Line Fill Unit toconstruct the current line frame.

DecodeD parses the bits at one bit per clock cycle and passes the bit inthe less significant bit location of delta to the line fill unit.

DecodeD currently requires to know the color of the run length to decodeit correctly as black and white runs are encoded differently. The streamdecoder keeps track of the next color based on the current color and thecurrent command.

24.3.6.3 State-Machine

This state machine continuously fetches consecutive DRAM data wheneverthere is enough free space in the FIFO, thereby keeping the barrel shiftregister full so it can continually decode commands for the commandcontroller. Note in FIG. 149 that each read cycle curr_read_addr iscompared to end_of_band_store. If the two are equal, curr_read_addr isloaded with start_of_band_store (circular memory addressing). Otherwisecurr_read_addr is simply incremented. start_of_band_store andend_of_band_store need to be programed so that the distance between themis a multiple of the 256-bit DRAM word size.

When the state machine decodes a SKIP command, the state machineprovides two SKIP instructions to the command controller.

The RUNLENGTH command has two different run lengths. The two run lengthsare passed to the command controller as separate RUNLENGTH instructions.In the first instruction fetch, the first run length is passed, and thestate machine selects the DecodeD shift value for the barrel shift. Inthe second instruction fetch from the command controller anotherRUNLENGTH instruction is generated and the respective shift value isdecoded. This is achieved by forcing DecodeC to output a secondRUNLENGTH instruction and the respective shift value is decoded.

For PASS_THROUGH mode, the PASS THROUGH command is issued every time thecommand controller requests a new command. It does this until all theun-compressed bits have been processed.

24.3.7 Command Controller Sub-Block Description

The Command Controller interprets the command from the Stream Decoderand provides the line fill unit with a limit address and color to fillthe SFU Next Line Buffer. It provides the next edge unit with a startingaddress to look for the next edge and is responsible for detecting theend of line and generating the eob_cc signal that is passed to the linefill unit.

A dataflow block diagram of the command controller is shown in FIG. 150.Note that data names such as a0 and b1p are taken from [22], and theydenote the reference or starting changing element on the coding line andthe first changing element on the reference line to the right of a0 andof the opposite color to a0 respectively.

24.3.7.1 State Machine

The following is an explanation of all the states that the state machineutilizes.

i Start

This is the state that the Command Controller enters when a hard or softreset occurs or when Go has been de-asserted. This state cannot be leftuntil the reset has been removed, Go has been asserted and the NEU (NextEdge Unit), the SD (Stream Decoder) and the SFU are ready.

ii AWAIT_BUFFER

The NEU contains a buffer memory for the data it receives from the SFU.When the command controller enters this state the NEU detects this andstarts buffering data, the command controller is able to leave thisstate when the state machine in the NEU has entered the NEU_RUNNINGstate. Once this occurs the command controller can proceed to the PARSEstate.

iii PAUSE_CC

During the decode of a line it is possible for the FIFO in the streamdecoder to get starved of data if the DRAM is not able to supplyreplacement data fast enough. Additionally the SFU can also stallmid-line due to band processing latency. If either of these cases occursthe LBD needs to pause until the stream decoder gets more of thecompressed data stream from the DRAM or the SFU can receive or delivernew frames. All of the remaining states check if sdvalid goes to zero(this denotes a starving of the stream decoder) or if sfu_lbd_rdy goesto zero and that the LBD needs to pause. PAUSE_CC is the state that thecommand controller enters to achieve this and it does not leave thisstate until sdvalid and sfu_lbd_rdy are both asserted and the LBD canrecommence decompressing.

iv PARSE

Once the command controller enters the PARSE state it uses theinformation that is supplied by the stream decoder. The first clockcycle of the state sees the sdack signal getting asserted informing thestream decoder that the current register information is being used sothat it can fetch the next command.

When in this state the command controller can receive one of four validcommands:

a) Runlength or Horizontal

For this command the value given as delta is an integer that denotes thenumber of bits of the current color that must be added to the currentline.

Should the current line position, a0, be added to the delta and theresult be greater than the final position of the current frame beingprocessed by the Line Fill Unit (only 16 bits at a time), it isnecessary for the command controller to wait for the Line Fill Unit(LFU) to process up to that point. The command controller changes intothe WAIT_FOR_RUNLENGTH state while this occurs.

When the current line position, a1, and the delta together equal orexceed the LINE_LENGTH, which is programmed during initialisation, thenthis denotes that it is the end of the current line. The commandcontroller signals this to the rest of the LBD and then returns to theSTAR_(T) state.

b) Vertical

When this command is received, it tells the command controller that, inthe previous line, it needs to find a change from the current color toopposite of the current color, i.e. if the current color is white itlooks from the current position in the previous line for the next timewhere there is a change in color from white to black. It is important tonote that if a black to white change occurs first it is ignored.

Once this edge has been detected, the delta will denote which of thevertical commands to use, refer to Table. The delta will denote wherethe changing element in the current line is relative to the changingelement on the previous line, for a Vertical(2) the new changing elementposition in the current line will correspond to the two bits extra fromchanging element position in the previous line.

Should the next edge not be detected in the current frame under reviewin the NEU, then the command controller enters the WAIT_FOR_NE state andwaits there until the next edge is found.

c) Skip

A skip follow the same functionality as to Vertical(0) commands but thecolor in the current line is not changed as it is been filled out. Thestream decoder supplies what looks like two separate skip commands thatthe command controller treats the same a two Vertical(0) commands andhas been coded not to change the current color in this case.

d) Pass Through

When in pass through mode the stream decoder supplies one bit per clockcycle that is uses to construct the current frame. Once pass throughmode is completed, which is controlled in the stream decoder, the LBDcan recommence normal decompression again. The current color after passthrough mode is the same color as the last bit in un-compressed datastream. Pass through mode does not need an extra state in the commandcontroller as each pass through command received from the stream decodercan always be processed in one clock cycle.

v WAIT_FOR_RUNLENGTH

As some RUNLENGTH's can carry over more than one 16-bit frame, thismeans that the Line Fill Unit needs longer than one clock cycle to writeout all the bits represented by the RUNLENGTH.

After the first clock cycle the command controller enters into theWAIT_FOR_RUNLENGTH state until all the RUNLENGTH data has been consumed.Once finished and provided it is not the end of the line the commandcontroller will return to the PARSE state.

vi WAIT_FOR_NE

Similar to the RUNLENGTH commands the vertical commands can sometimesnot find an edge in the current 16-bit frame. After the first clockcycle the command controller enters the WAIT_FOR_NE state and remainshere until the edge is detected. Provided it is not the end of the linethe command controller will return to the PARSE state.

vii FINISH_LINE

At the end of a line the command controller needs to hold its data forthe SFU before going back to the STAR_(T) state. Command controllerremains in the FINISH_LINE state for one clock cycle to achieve this.

24.3.8 Next Edge Unit Sub-Block Description

The Next Edge Unit (NEU) is responsible for detecting color changes, oredges, in the previous line based on the current address and colorsupplied by the Command Controller. The NEU is the interface to the SFUand it buffers the previous line for detecting an edge. For an edgedetect operation the Command Controller supplies the current address,this typically was the location of the last edge, but it could also bethe end of a run length. With the current address a color is alsosupplied and using these two values the NEU will search the previousline for the next edge. If an edge is found the NEU returns thislocation to the Command Controller as the next address in the currentline and it sets a valid bit to tell the Command Controller that theedge has been detected. The Line Fill Unit uses this result to constructthe current line. The NEU operates on 16-bit words and it is possiblethat there is no edge in the current 16 bits in the NEU. In this casethe NEU will request more words from the SFU and will keep searching foran edge. It will continue doing this until it finds an edge or reachesthe end of the previous line, which is based on the LINE_LENGTH. Adataflow block diagram of the Next Edge unit is shown in FIG. 152.

24.3.8.1 NEU Buffer

The algorithm being employed for decompression is based on the wholeprevious line and is not delineated during the line. However the NextEdge Unit, NEU, can only receive 16 bits at a time from the SFU. Thispresents a problem for vertical commands if the edge occurs in thesuccessive frame, but refers to a changing element in the current frame.

To accommodate this the NEU works on two frames at the same time, thecurrent frame and the first 3 bits from the successive frame. Thisallows for the information that is needed from the previous line toconstruct the current frame of the current line.

In addition to this buffering there is also buffering right after thedata is received from the SFU as the SFU output is not registered. Thecurrent implementation of the SFU takes two clock cycles from when arequest for a current line is received until it is returned andregistered. However when NEU requests a new frame it needs it on thenext clock cycle to maintain a decoded rate of 2 bits per clock cycle. Amore detailed diagram of the buffer in the NEU is shown in FIG. 153.

The output of the buffer are two 16-bit vectors, use_prev_line_a anduse_prev_line_b, that are used to detect an edge that is relevant to thecurrent line being put together in the Line Fill Unit.

24.3.8.2 NEU Edge Detect

The NEU Edge Detect block takes the two 16 bit vectors supplied by thebuffer and based on the current line position in the current line, a0,and the current color, sd_color, it will detect if there is an edgerelevant to the current frame. If the edge is found it supplies thecurrent line position, b1p, to the command controller and the line fillunit. The configuration of the edge detect is shown in FIG. 154.

The two vectors from the buffer, use_prev_line_a and use_prev_line_b,pass into two sub-blocks, transition_wtob and transition_btow.transition_wtob detects if any white to black transitions occur in the19 bit vector supplied and outputs a 19-bit vector displaying thetransitions. transition_wtob is functionally the same astransition_btow, but it detects white to black transitions.

The two 19-bit vectors produced enter into a multiplexer and the outputof the multiplexer is controlled by color_neu. color_neu is the currentedge transition color that the edge detect is searching for.

The output of the multiplexer is masked against a 19-bit vector, themask is comprised of three parts concatenated together: decode_b_ext,decode_b and FIRST_FLU_WRITE.

The output of transition_wtob (and it complement transition_btow) areall the transitions in the 16 bit word that is under review. Thedecode_b is a mask generated from a0. In bit-wise terms all the bitsabove and including a0 are 1's and all bits below a0 are 0's. When theyare gated together it means that all the transitions below a0 areignored and the first transition after a0 is picked out as the nextedge.

The decode_b block decodes the 4 lsb of the current address (a0) into16-bit mask bits that control which of the data bits are examined. Table158 shows the truth table for this block. TABLE 158 Decode_b truth tableinput output 0000 1111111111111111 0001 1111111111111110 00101111111111111100 0011 1111111111111000 0100 1111111111110000 01011111111111100000 0110 1111111111000000 0111 1111111110000000 10001111111100000000 1001 1111111000000000 1010 1111110000000000 10111111100000000000 1100 1111000000000000 1101 1110000000000000 11101100000000000000 1111 1000000000000000

For cases when there is a negative vertical command from the streamdecoder it is possible that the edge is in the three lower significantbits of the next frame. The decode_b_ext block supplies the mask so thatthe necessary bits can be used by the NEU to detect an edge if present,Table 159 shows the truth table of this block. TABLE 159 Decode_b_exttruth table delta output Vertical(−3) 111 Vertical(−2) 111 Vertical(−1)011 OTHERS 001

FIRST_FLU_WRITE is only used in the first frame of the current line.2.2.5 a) in [22] refers to “Processing the first picture element”, inwhich it states that “The first starting picture element, a0, on eachcoding line is imaginarily set at a position just before the firstpicture element, and is regarded as a white picture element”.transition_wtob and transition_btow are set up produce this case forevery single frame. However it is only used by the NEU if it is notmasked out. This occurs when FIRST_FLU_WRITE is ‘1’ which is onlyasserted at the beginning of a line. 2.2.5 b) in [22] covers the case of“Processing the last picture element”, this case states that “The codingof the coding line continues until the position of the imaginarychanging element situated after the last actual element is coded”. Thismeans that no matter what the current color is the NEU needs to alwaysfind an edge at the end of a line. This feature is used with negativevertical commands.

The vector, end_frame, is a “one-hot” vector that is asserted during thelast frame. It asserts a bit in the end of line position, as determinedby LineLength, and this simulates an edge in this location which is ORedwith the transition's vector. The output of this, masked_data, is sentinto the encodeB_one_hot block

24.3.8.3 Encode_b_one_hot

The encode_b_one_hot block is the first stage of a two stage processthat encodes the data to determine the address of the 0 to 1 transition.Table 160 lists the truth table outlining the functionally required bythis block. TABLE 160 Encode_b_one_hot Truth Table Input outputXXXXXXXXXXXXXXXXXX1 0000000000000000001 XXXXXXXXXXXXXXXXX100000000000000000010 XXXXXXXXXXXXXXXX100 0000000000000000100XXXXXXXXXXXXXXX1000 0000000000000001000 XXXXXXXXXXXXXX100000000000000000010000 XXXXXXXXXXXXX100000 0000000000000100000XXXXXXXXXXXX1000000 0000000000001000000 XXXXXXXXXXX100000000000000000010000000 XXXXXXXXXX100000000 0000000000100000000XXXXXXXXX1000000000 0000000001000000000 XXXXXXXX100000000000000000010000000000 XXXXXXX100000000000 0000000100000000000XXXXXX1000000000000 0000001000000000000 XXXXX100000000000000000010000000000000 XXXX100000000000000 0000100000000000000XXX1000000000000000 0001000000000000000 XX100000000000000000010000000000000000 X100000000000000000 01000000000000000001000000000000000000 1000000000000000000 00000000000000000000000000000000000000

The output of encode_b_one-hot is a “one-hot” vector that will denotewhere that edge transition is located. In cases of multiple edges, onlythe first one will be picked.

24.3.8.4 Encode_b_(—)4 Bit

Encode_b_(—)4 bit is the second stage of the two stage process thatencodes the data to determine the address of the 0 to 1 transition.

Encode_b_(—)4 bit receives the “one-hot” vector from encode_b_one_hotand determines the bit location that is asserted. If there is nonepresent this means that there was no edge present in this frame. Ifthere is a bit asserted the bit location in the vector is converted to anumber, for example if bit 0 is asserted then the number is one, if bitone is asserted then the number is one, etc. The delta supplied to theNEU determines what vertical command is being processed. The formulathat is implemented to return b1p to the command controller is:   forV(n) b1p = x + n modulus16 where x is the number that was extracted fromthe “one-hot” vector and n is the vertical command.24.3.8.5 State Machine

The following is an explanation of all the states that the NEU statemachine utilizes.

i NEU_START

This is the state that NEU enters when a hard or soft reset occurs orwhen Go has been de-asserted. This state can not left until the resethas been removed, Go has been asserted and it detects that the commandcontroller has entered it's AWAIT_BUFF state. When this occurs the NEUenters the NEU_FILL_BUFF state.

ii NEU_FILL_BUFF

Before any compressed data can be decoded the NEU needs to fill up itsbuffer with new data from the SFU. The rest of the LBD waits while theNEU retrieves the first four frames from the previous line. Oncecompleted it enters the NEU_HOLD state.

iii NEU_HOLD

The NEU waits in this state for one clock cycle while data requestedfrom the SFU on the last access returns.

iv NEU_RUNNING

NEU_RUNNING controls the requesting of data from the SFU for theremainder of the line by pulsing lbd_sfu_pladvword when the LBD needs anew frame from the SFU. When the NEU has received all the word it needsfor the current line, as denoted by the LineLength, the NEU enters theNEU_EMPTY state.

v NEU_EMPTY

NEU waits in this state while the rest of the LBD finishes outputtingthe completed line to the SFU. The NEU leaves this state when Go getsdeasserted. This occurs when the end_of_line signal is detected from theLBD.

24.3.9 Line Fill Unit Sub-Block Description

The Line Fill Unit, LFU, is responsible for filling the next line bufferin the SFU. The SFU receives the data in blocks of sixteen bits. The LFUuses the color and a0 provided by the Command Controller and when it hasput together a complete 16-bit frame, it is written out to the SFU. TheLBD signals to the SFU that the data is valid by strobing thelbd_sfu_wdatavalid signal.

When the LFU is at the end of the line for the current line data itstrobes lbd_sfu_advline to indicate to the SFU that the end of the linehas occurred.

A dataflow block diagram of the line fill unit is shown in FIG. 154.

The dataflow above has the following blocks:

24.3.9.1 State Machine

The following is an explanation of all the states that the LFU statemachine utilizes.

i LFU_START

This is the state that the LFU enters when a hard or soft reset occursor when Go has been de-asserted. This state can not left until the resethas been removed, Go has been asserted and it detects that a0 is nolonger zero, this only occurs once the command controller startprocessing data from the Next Edge Unit, NEU.

ii LFU_NEW REG

LFU_NEW_REG is only entered at the beginning of a new frame. It canremain in this state on subsequent cycles if a whole frame is completedin one clock cycle. If the frame is completed the LFU will output thedata to the SFU with the write enable signal. However if a frame is notcompleted in one clock cycle the state machine will change to theLFU_COMPLETE_REG state to complete the remainder of the frame.LFU_NEW_REG handles all the lbd_sfu_wdata writes and assertslbd_sfu_wdatavalid as necessary.

iii LFU_COMPLETE_REG

LFU_COMPLETE_REG fills out all the remaining parts of the frame thatwere not completed in the first clock cycle. The command controllersupplies the a0 value and the color and the state machine uses these toderive the limit and color_sel_(—)16 bit_If which the line_fill_datablock needs to construct a frame. Limit is the four lower significantbits of a0 and color_sel_(—)16 bit_If is a 16-bit wide mask of sd_dolor.The state machine also maintains a check on the upper eleven bits of a0.If these increment from one clock cycle to the next that means that aframe is completed and the data can be written to the SFU. In the caseof the LineLength being reached the Line Fill Unit fills out theremaining part of the frame with the color of the last bit in the linethat was decoded.

24.3.9.2 line_fill_data

line_fill_data takes the limit value and the color_sel_(—)16 bit_Ifvalues and constructs the current frame that the command controller andthe next edge unit are decoding. The following pseudo code illustratethe logic followed by the line_fill_data. work_sfu_wdata is exported bythe LBD to the SFU as lbd_sfu_wdata. if (lfu_state == LFU_START) OR (lfu_state == LFU_NEW_REG) then  work_sfu_wdata = color_sel_16bit_lf  else   work_sfu_wdata[(15 −limit) downto limit] =     color_sel_16bit_lf[(15 − limit) downto limit]25 Spot FIFO Unit (SFU)25.1 Overview

The Spot FIFO Unit (SFU) provides the means by which data is transferredbetween the LBD and the HCU. By abstracting the buffering mechanism andcontrols from both units, the interface is clean between the data userand the data generator. The amount of buffering can also be increased ordecreased without affecting either the LBD or HCU. Scaling of data isperformed in the horizontal and vertical directions by the SFU so thatthe output to the HCU matches the printer resolution. Non-integerscaling is supported in both the horizontal and vertical directions.Typically, the scale factor will be the same in both directions but maybe programmed to be different.

25.2 Main Features of the SFU

The SFU replaces the Spot Line Buffer Interface (SLBI) in PEC1. The spotline store is now located in DRAM.

The SFU outputs the previous line to the LBD, stores the next lineproduced by the LBD and outputs the HCU read line. Each interface toDRAM is via a feeder FIFO. The LBD interfaces to the SFU with a datawidth of 16 bits. The SFU interfaces to the HCU with a data width of 1bit. Since the DRAM word width is 256-bits but the LBD line length is amultiple of 16 bits, a capability to flush the last multiples of 16-bitsat the end of a line into a 256-bit DRAM word size is required.Therefore, SFU reads of DRAM words at the end of a line, which do notfill the DRAM word, will already be padded.

A signal sfu_lbd_rdy to the LBD indicates that the SFU is available forwriting and reading. For the first LBD line after SFU Go has beenasserted, previous line data is not supplied until after the firstlbd_sfu_advline strobe from the LBD (zero data is supplied instead), andsfu_lbd_rdy to the LBD indicates that the SFU is available for writing.lbd_sfu_advline tells the SFU to advance to the next line.lbd_sfu_pladvword tells the SFU to supply the next 16-bits of previousline data. Until the number of lbd_sfu_pladvword strobes received isequivalent to the LBD line length, sfu_lbd_rdy indicates that the SFU isavailable for both reading and writing. Thereafter it indicates the SFUis available for writing. The LBD should not generate lbd_sfu_pladvwordor lbd_sfu_advline strobes until sfu_lbd_rdy is asserted.

A signal sfu_hcu_avail indicates that the SFU has data to supply to theHCU. Another signal hcu_sfu_advdot, from the HCU, tells the SFU tosupply the next dot. The HCU should not generate the hcu_sfu_advdotsignal until sfu_hcu_avail is true. The HCU can therefore stall waitingfor the sfu_hcu_avail signal.

X and Y non-integer scaling of the bi-level dot data is performed in theSFU.

At 1600 dpi the SFU requires 1 dot per cycle for all DRAM channels, 3dots per cycle in total (read+read+write). Therefore the SFU requirestwo 256 bit read DRAM access per 256 cycles, 1 write access every 256cycles. A single DIU read interface will be shared for reading thecurrent and previous lines from DRAM.

25.3 Bi-Level Dram Memory Buffer Between LBD, SFU and HCU

FIG. 158 shows a bi-level buffer store in DRAM. FIG. 158(a) shows theLBD previous line address reading after the HCU read line address inDRAM. FIG. 158(b) shows the LBD previous line address reading before theHCU read line address in DRAM.

Although the LBD and HCU read and write complete lines of data, thebi-level DRAM buffer is not line based. The buffering between the LBD,SFU and HCU is a FIFO of programmable size. The only line based conceptis that the line the HCU is currently reading cannot be over-writtenbecause it may need to be re-read for scaling purposes.

The SFU interfaces to DRAM via three FIFOs:

-   a. The HCUReadLineFIFO which supplies dot data to the HCU.-   b. The LBDNextLineFIFO which writes decompressed bi-level data from    the LBD.-   c. The LBDPrevLineFIFO which reads previous decompressed bi-level    data for the LBD.

There are four address pointers used to manage the bi-level DRAM buffer:

-   a. hcu_readline_rd_adr[21:5] is the read address in DRAM for the    HCUReadLineFIFO.-   b. hcu_startreadline_adr[21:5] is the start address in DRAM for the    current line being read by the HCUReadLineFIFO.-   c. lbd_nextline_wr_adr[21:5] is the write address in DRAM for the    LBDNextLineFIFO.-   d. lbd_prevline_rd_adr[21:5] is the read address in DRAM for the    LBDPrevLineFIFO.

The address pointers must obey certain rules which indicate whether theyare valid:

-   a. hcu_readline_rd_adr is only valid if it is reading earlier in the    line than lbd_nextline_wr_adr is writing i.e. the fifo is not empty-   b. The SFU (lbd_nextline_wr_adr) cannot overwrite the current line    that the HCU is reading from (hcu_startreadline_adr) i.e. the fifo    is not full, when compared with the HCU read line pointer-   c. The LBDNextLineFIFO (lbd_nextline_wr_adr) must be writing earlier    in the line than LBDPrevLineFIFO (lbd_prevline_rd_adr) is reading    and must not overwrite the current line that the HCU is reading from    i.e. the fifo is not full when compared to the PrevLineFifo read    pointer-   d. The LBDPrevLineFIFO (lbd_prevline_rd_adr) can read right up to    the address that LBDNextLineFIFO (lbd_nextline_wr_adr) is writing    i.e the fifo is not empty.-   e. At startup i.e. when sfu_go is asserted, the pointers are reset    to start_sfu_adr[21:5].-   f. The address pointers can wrap around the SFU bi-level store area    in DRAM.

As a guideline, the typical FIFO size should be a minimum of 2 linesstored in DRAM, nominally 3 lines, up to a programmable number of lines.A larger buffer allows lines to be decompressed in advance. This can beuseful for absorbing local complexities in compressed bi-level images.

25.4 DRAM Access Requirements

The SFU has 1 read interface to the DIU and 1 write interface. The readinterface is shared between the previous and current line read FIFOs.

The spot line store requires 5.1 Kbytes of DRAM to store 3 A4 lines. TheSFU will read and write the spot line store in single 256-bit DRAMaccesses. The SFU will need 256-bit double buffers for each of itsprevious, current and next line interfaces.

The SFU's DIU bandwidth requirements are summarized in Table 161. TABLE161 DRAM bandwidth requirements Peak Bandwidth Maximum number ofrequired to be Average cycles between each supported by DIU BandwidthDirection 256-bit DRAM access (bits/cycle) (bits/cycle) Read 1281 2 2Write 2562 1 11: Two separate reads of 1 bit/cycle.2: Write at 1 bit/cycle.1: Two separate reads of 1 bit/cycle2: Write at 1 bit/cycle25.5 Scaling

Scaling of bi-level data is performed in both the horizontal andvertical directions by the SFU so that the output to the HCU matches theprinter resolution. The SFU supports non-integer scaling with the scalefactor represented by a numerator and a denominator. Only scaling up ofthe bi-level data is allowed, i.e. the numerator should be greater thanor equal to the denominator. Scaling is implemented using a counter asdescribed in the pseudocode below. An advance pulse is generated to moveto the next dot (x-scaling) or line (y-scaling). if (count +denominator >= numerator) then  count = (count + denominator) −numerator  advance = 1 else  count = count + denominator  advance = 0

X scaling controls whether the SFU supplies the next dot or a copy ofthe current dot when the HCU asserts hcu_sfu_advdot. The SFU counts thenumber of hcu_sfu_advdot signals from the HCU. When the SFU has suppliedan entire HCU line of data, the SFU will either re-read the current linefrom DRAM or advance to the next line of HCU read data depending on theprogrammed Y scale factor.

An example of scaling for numerator=7 and denominator=3 is given inTable 162. The signal advance if asserted causes the next input dot tobe output on the next cycle, otherwise the same input dot is outputTABLE 162 Non-integer scaling example for scaleNum = 7, scaleDenom = 3count advance dot 0 0 1 3 0 1 6 1 1 2 0 2 5 1 2 1 0 3 4 1 3 0 0 4 3 0 46 1 4 2 0 525.6 Lead-In and Lead-Out Clipping

To account for the case where there may be two SoPEC devices, eachgenerating its own portion of a dot-line, the first dot in a line maynot be replicated the total scale-factor number of times by anindividual SoPEC. The dot will ultimately be scaled-up correctly withboth devices doing part of the scaling, one on its lead-out and theother on its lead in. Scaled up dots on the lead-out, i.e. which gobeyond the HCU linelength, will be ignored. Scaling on the lead-in, i.e.of the first valid dot in the line, is controlled by setting theXstartCount register.

At the start of each line count in the pseudo-code above is set toXstartCount. If there is no lead-in, XstartCount is set to 0 i.e. thefirst value of count in Table. If there is lead-in then XstartCountneeds to be set to the appropriate value of count in the sequence above.

25.7 Interfaces Between LDB, SFU and HCU

25.7;1 LDB-SFU Interfaces

The LBD has two interfaces to the SFU. The LBD writes the next line tothe SFU and reads the previous line from the SFU.

25.7.1.1 LBDNextLineFIFO Interface

The LBDNextLineFIFO interface from the LBD to the SFU comprises thefollowing signals:

-   -   lbd_sfu_wdata, 16-bit write data.

lbd_sfu_wdatavalID, write data valid.

lbd_sfu_advline, signal indicating LDB has advanced to the next line.

The LBD should not write to the SFU until sfu_lbd_rdy is true. The LBDcan therefore stall waiting for the sfu_lbd_rdy signal.

25.7.1.2 LBDPrevLineFIFO Interface

The LBDPrevLineFIFO interface from the SFU to the LBD comprises thefollowing signals:

-   -   sfu_lbd_pldata, 16-bit data.

The previous line read buffer interface from the LBD to the SDUcomprises the following signals:

-   -   lbd_sfu_pladvword, signal indicating to the SFU to supply the        next 16-bit word.

lbd_sfu_advline, signal indicating LDB has advanced to the next line.

Previous line data is not supplied until after the first lbd_sfu_advlinestrobe from the LBD (zero data is supplied instead). The LBD should notassert lbd_sfu_pladvword unless sfu_lbd_rdy is asserted.

25.7.1.3 Common Control Signals

sfu_lbd_rdy indicates to the LBD that the SFU is available for writing.After the first lbd_sfu_advline and before the number oflbd_sfu_pladvword strobes received is equivalent to the LBD line length,sfu_lbd_rdy indicates that the SFU is available for both reading andwriting.

Thereafter it indicates the SFU is available for writing.

The LBD should not generate lbd_sfu_pladvword or lbd_sfu_advline strobesuntil sfu_lbd_rdy is asserted.

25.7.2 SFU-HCU Current Line FIFO Interface

The interface from the SFU to the HCU comprises the following signals:

-   -   sfu_hcu_sdata, 1-bit data.    -   sfu_hcu_avail, data valid signal indicating that there is data        available in the SFU HCUReadLineFIFO.

The interface from HCU to SFU comprises the following signals:

-   -   hcu_sfu_advdot, indicating to the SFU to supply the next dot.

The HCU should not generate the hcu_sfu_advdot signal untilsfu_hcu_avail is true. The HCU can therefore stall waiting for thesfu_hcu_avail signal.

25.8 Implementation

25.8.1 Definitions of IO TABLE 163 SFU Port List Port Name Pins I/ODescription Clocks and Resets Pclk 1 In SoPEC Functional clock. prst_n 1In Global reset signal. DIU Read Interface signals sfu_diu_rreq 1 OutSFU requests DRAM read. A read request must be accompanied by a validread address. sfu_diu_radr[21:5] 17 Out Read address to DIU 17 bits wide(256-bit aligned word). diu_sfu_rack 1 In Acknowledge from DIU that readrequest has been accepted and new read address can be placed onsfu_diu_radr. diu_data[63:0] 64 In Data from DIU to SoPEC Units. First64-bits are bits 63:0 of 256 bit word. Second 64-bits are bits 127:64 of256 bit word. Third 64-bits are bits 191:128 of 256 bit word. Fourth64-bits are bits 255:192 of 256 bit word. diu_sfu_rvalid 1 In Signalfrom DIU telling SoPEC Unit that valid read data is on the diu_data bus.DIU Write Interface signals sfu_diu_wreq 1 Out SFU requests DRAM write.A write request must be accompanied by a valid write address togetherwith valid write data and a write valid. sfu_diu_wadr[21:5] 17 Out Writeaddress to DIU 17 bits wide (256-bit aligned word). diu_sfu_wack 1 InAcknowledge from DIU that write request has been accepted and new writeaddress can be placed on sfu_diu_wadr. sfu_diu_data[63:0] 64 Out Datafrom SFU to DIU. First 64-bits are bits 63:0 of 256 bit word. Second64-bits are bits 127:64 of 256 bit word. Third 64-bits are bits 191:128of 256 bit word. Fourth 64-bits are bits 255:192 of 256 bit word.sfu_diu_wvalid 1 Out Signal from PEP Unit indicating that data onsfu_diu_data is valid. PCU Interface data and control signalspcu_adr[5:2] 4 In PCU address bus. Only 4 bits are required to decodethe address space for this block pcu_dataout[31:0] 32 In Shared writedata bus from the PCU sfu_pcu_datain[31:0] 32 Out Read data bus from theSFU to the PCU pcu_rwn 1 In Common read/not-write signal from the PCUpcu_sfu_sel 1 In Block select from the PCU. When pcu_sfu_sel is highboth pcu_adr and pcu_dataout are valid sfu_pcu_rdy 1 Out Ready signal tothe PCU. When sfu_pcu_rdy is high it indicates the last cycle of theaccess. For a write cycle this means pcu_dataout has been registered bythe block and for a read cycle this means the data on sfu_pcu_datain isvalid. LBD Interface Data and Control Signals sfu_lbd_rdy 1 Out Signalindication that SFU has previous line data available and is ready to bewritten to. lbd_sfu_advline 1 In Line advance signal for both next andprevious lines. lbd_sfu_pladvword 1 In Advance word signal for previousline buffer. sfu_lbd_pldata[15:0] 16 Out Data from the previous linebuffer. lbd_sfu_wdata[15:0] 16 In Write data for next line buffer.lbd_sfu_wdatavalid 1 In Write data valid signal for next line bufferdata. HCU Interface Data and Control Signals hcu_sfu_advdot 1 In Signalindicating to the SFU that the HCU is ready to accept the next dot ofdata from SFU. sfu_hcu_sdata 1 Out Bi-level dot data. sfu_hcu_avail 1Out Signal indicating valid bi-level dot data on sfu_hcu_sdata.

25.8.2 Configuration Registers TABLE 164 SFU Configuration RegistersAddress (SFU_base+ register name #bits value on reset descriptionControl registers 0x00 Reset 1 0x1 A write to this register causes areset of the SFU. This register can be read to indicate the reset state:0 - reset in progress 1 - reset not in progress 0x04 Go 1 0x0 Writing 1to this register starts the SFU. Writing 0 to this register halts theSFU. When Go is deasserted the state- machines go to their idle statesbut all counters and configuration registers keep their values. When Gois asserted all counters are reset, but configuration registers keeptheir values (i.e. they don't get reset). The SFU must be started beforethe LBD is started. This register can be read to determine if the SFU isrunning (1 - running, 0 - stopped). Setup registers (constant for duringprocessing the page) 0x08 HCUNumDots 16 0x0000 Width of HCU line (indots). 0x0C HCUDRAMWords 8 0x00 Number of 256-bit DRAM words in a HCUline − 1. 0x10 LBDDRAMWords 8 0x00 Number of 256-bit words in a LBD line− 1. (LBD line length must be at least 128 bits). 0x14 StartSfuAdr[21:5]17 0x0000 0 First SFU location in memory. (256-bit aligned DRAM address)0x18 EndSfuAdr[21:5] 17 0x0000 0 Last SFU location in memory. (256-bitaligned DRAM address) 0x1C XstartCount 8 0x00 Value to be loaded at thestart of every line into the counter used for scaling in the Xdirection. Used to control the scaling of the first dot in a line. Thisvalue will typically equal zero, except in the case where a number ofdots are clipped on the lead in to a line. XstartCount must beprogrammed to be less than the XscaleNum value. 0x20 XscaleNum 8 0x01Numerator of spot data scale factor in X direction. 0x24 XscaleDenom 80x01 Denominator of spot data scale factor in X direction. 0x28YscaleNum 8 0x01 Numerator of spot data scale factor in Y direction.0x2C YscaleDenom 8 0x01 Denominator of spot data scale factor in Ydirection. Work registers (PCU has read-only access) 0x30HCUReadLineAdr[21:5] 17 — Current address pointer in DRAM to (256-bitHCU read data. Read only register. aligned DRAM address) 0x34HCUStartReadLineAdr[21:5] 17 — Start address in DRAM of line being(256-bit read by HCU buffer in DRAM. Read aligned only register. DRAMaddress) 0x38 LBDNextLineAdr[21:5] 17 — Current address pointer in DRAMto (256-bit LBD write data. Read only register aligned DRAM address)0x3C LBDPrevLineAdr[21:5] 17 — Current address pointer in DRAM to(256-bit LBD read data. Read only register aligned DRAM address)25.8.3 SFU Sub-Block Partition

The SFU contains a number of sub-blocks: The SFU contains a number ofsub-blocks: Name description PCU Interface PCU interface, configurationand status registers. Also generates the Go and the Reset signals forthe rest of the SFU LBD Previous Contains FIFO which is read by the LBDLine FIFO previous line interface. LBD Next Line Contains FIFO which iswritten by the FIFO LBD next line interface. HCU Read Line Contains FIFOwhich is read by the HCU interface. FIFO DIU Interface Contains DIU readinterface and DIU write interface. and Address Manages the addresspointers for the bi-level DRAM Generator buffer. Contains X and Yscaling logic.

The various FIFO sub-blocks have no knowledge of where in DRAM theirread or write data is stored. In this sense the FIFO sub-blocks arecompletely de-coupled from the bi-level DRAM buffer. All DRAM addressmanagement_is centralised in the DIU Interface and Address Generationsub-block. DRAM access is pre-emptive i.e. after a FIFO unit has made anaccess then as soon as the FIFO has space to read or data to write a DIUaccess will be requested immediately. This ensures there are nounnecessary stalls introduced e.g. at the end of an LBD or HCU line.

There now follows a description of the SFU sub-blocks.

25.8.4 PCU Interface Sub-Block

The PCU interface sub-block provides for the CPU to access SFU specificregisters by reading or writing to the SFU address space.

25.8.5 LBDPrevLineFIFO Sub-Block TABLE 165 LBDPrevLineFIFO Additional IODefinitions Port Name Pins I/O Description Internal Output plf_rdy 1 OutSignal indicating LBDPrevLineFIFO is ready to be read from. Until thefirst lbd_sfu_advline for a band has been received and after the numberof reads from DRAM for a line is received is equal to LBDDRAMWords,plf_rdy is always asserted. During the second and subsequent linesplf_rdy is deasserted whenever the LBDPrevLineFIFO has one word left inthe FIFO.. DIU and Address Generation sub-block Signals plf_diurreq 1Out Signal indicating the LBDPrevLineFIFO has 256-bits of data free.plf_diurack 1 In Acknowledge that read request has been accepted andplf_diurreq should be de-asserted. plf_diurdata 1 In Data from the DIUto LBDPrevLineFIFO. First 64-bits are bits 63:0 of 256 bit word. Second64-bits are bits 127:64 of 256 bit word. Third 64-bits are bits 191:128of 256 bit word. Fourth 64-bits is are 255:192 of 256 bit word.plf_diurrvalid 1 In Signal indicating data on plf_diurdata is valid.plf_diuidle 1 Out Signal indicating DIU state-machine is in the IDLEstate.

25.8.5.1 General Description

The LBDPrevLineFIFO sub-block comprises a double 256-bit buffer betweenthe LBD and the DIU Interface and Address Generator sub-block. The FIFOis implemented as 8 times 64-bit words. The FIFO is written by the DIUInterface and Address Generator sub-block and read by the LBD.

Whenever 4 locations in the FIFO are free the FIFO will request 256-bitsof data from the DIU Interface and Address Generation sub-block byasserting plf_diurreq. A signal plf_diurack indicates that the requesthas been accepted and plf_diurreq should be de-asserted.

The data is written to the FIFO as 64-bits on plf_diurdata[63:0] over 4clock cycles. The signal plf_diurvalid indicates that the data returnedon plf_diurdata[63:0] is valid. plf_diurvalid is used to generate theFIFO write enable, write_en, and to increment the FIFO write address,write_adr[2:0]. If the LBDPrevLineFIFO still has 256-bits free thenplf_diurreq should be asserted again.

The DIU Interface and Address Generation sub-block handles all addresspointer management and DIU interfacing and decides whether toacknowledge a request for data from the FIFO.

The state diagram of the LBDPrevLineFIFO DIU Interface is shown in FIG.163. If sfu_go is deasserted then the state-machine returns to its idlestate.

The LBD reads 16-bit wide data from the LBDPrevLineFIFO onsfu_lbd_pldata[15:0]. lbd_sfu_pladvword from the LBD tells theLBDPrevLineFIFO to supply the next 16-bit word. The FIFO control logicgenerates a signal word_select which selects the next 16-bits of the64-bit FIFO word to output on sfu_lbd_pldata[15:0]. When the entirecurrent 64-bit FIFO word has been read by the LBD lbd_sfu_pladvword willcause the next word to be popped from the FIFO. Previous line data isnot supplied until after the first lbd_sfu_advline strobe from the LBDafter sfu_go is asserted (zero data is supplied instead). Until thefirst lbd_sfu_advline strobe after sfu_go lbd_sfu_pladvword strobes areignored.

The LBDPrevLineFIFO control logic uses a counter, pl_count[7:0], tocounts the number of DRAM read accesses for the line. When the pl_countcounter is equal to the LBDDRAMWords, a complete line of data has beenread by the LBD the plf_rdy is set high, and the counter is reset. Itremains high until the next lbd_sfu_advline strobe from the LBD. Onreceipt of the lbd_sfu_advline strobe the remaining data in the 256-bitword in the FIFO is ignored, and the FIFO read_adr is rounded up ifrequired.

The LBDPrevLineFIFO generates a signal plf_rdy to indicate that it hasdata available. Until the first lbd_sfu_advline for a band has beenreceived and after the number of DRAM reads for a line is equal toLBDDRAMWords, plf_rdy is always asserted. During the second andsubsequent lines plf_rdy is deasserted whenever the LBDPrevLineFIFO hasone word left.

The last 256-bit word for a line read from DRAM can contain extrapadding which should not be output to the LBD. This is because thenumber of 16-bit words per line may not fit exactly into a 256-bit DRAMword. When the count of the number of DRAM reads for a line is equal tolbd_dram_words the LBDPrevLineFIFO must adjust the FIFO write address topoint to the next 256-bit word boundary in the FIFO for the next line ofdata. At the end of a line the read address must round up the nearest256-bit word boundary and ignore the remaining 16-bit words. This can beachieved by considering the FIFO read address, read adr[2:0], willrequire 3 bits to address 8 locations of 64-bits. The next 256-bitaligned address is calculated by inverting the MSB of the read_adr andsetting all other bits to 0. if (read_adr[1:0] /= b00 ANDlbd_sfu_advline == 1)then  read_adr[1:0] = b00  read_adr[2] =˜read_adr[2]

TABLE 166 LBDNextLineFIFO Additional IO Definition Port Name Pins I/ODescription LBDNextLineFIFO Interface Signals nlf_rdy 1 Out Signalindicating LBDNextLineFIFO is ready to be written to i.e. there is spacein the FIFO. DIU and Address Generation sub-block Signals nlf_diuwreq 1Out Signal indicating the LBDNextLineFIFO has 256-bits of data forwriting to the DIU. nlf_diuwack 1 In Acknowledge from DIU that writerequest has been accepted and write data can be output on nlf_diuwdatatogether with nlf_diuwvalid. nlf_diuwdata 1 Out Data fromLBDNextLineFIFO to DIU Interface. First 64-bits is bits 63:0 of 256 bitword Second 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit wordnlf_diuwvalid 1 In Signal indicating that data on wlf_diuwdata is valid.25.8.6.1 General Description

The LBDNextLineFIFO sub-block comprises a double 256-bit buffer betweenthe LBD and the DIU Interface and Address Generator sub-block. The FIFOis implemented as 8 times 64-bit words. The FIFO is written by the LBDand read by the DIU Interface and Address Generator. Whenever 4locations in the FIFO are full the FIFO will request 256-bits of data tobe written to the DIU Interface and Address Generator by assertingnlf_diuwreq. A signal nlf_diuwack indicates that the request has beenaccepted and nlf_diuwreq should be de-asserted. On receipt ofnlf_diuwack, the data is sent to the DIU Interface as 64-bits onnlf_diuwdata[63:0] over 4 clock cycles. The signal nlf_diuwvalidindicates that the data on nlf_diuwdata[63:0] is valid. nlf_diuwvalidshould be asserted with the smallest latency after nlf_diuwack. If theLBDNextLineFIFO still has 256-bits more to transfer then nlf_diuwreqshould be asserted again. The state diagram of the LBDNextLineFIFO DIUInterface is shown in FIG. 166. If sfu_go is deasserted then thestate-machine returns to its Idle state.

The signal nlf_rdy indicates that the LBDNextLineFIFO has space forwriting by the LBD. The LBD writes 16-bit wide data supplied onlbd_sfu_wdata[15:0]. lbd_sfu_wvalid indicates that the data is valid.

The LBDNextLineFIFO control logic counts the number of lbd_sfu_wvalidsignals and is used to correctly address into the next line FIFO. Thelbd_sfu_wvalid counter is rounded up to the nearest 256-bit word when albd_sfu_advline strobe is received from the LBD. Any data remaining inthe FIFO is flushed to DRAM with padding being added to fill a complete256-bit word.

25.8.7 sfu_lbd_rdy Generation

The signal sfu_lbd_rdy is generated by ANDing plf_rdy from theLBDPrevLineFIFO and nlf_rdy from the LBDNextLineFIFO.

sfu_lbd_rdy indicates to the LBD that the SFU is available for writingi.e. there is space available in the LBDNextLineFIFO. After the firstibd_sfu_advline and before the number of lbd_sfu_pladvword strobesreceived is equivalent to the line length, sfu_lbd_rdy indicates thatthe SFU is available for both reading, i.e. there is data in theLBDPrevLineFIFO, and writing.

Thereafter it indicates the SFU is available for writing.

25.8.8 LBD-SFU Interfaces Timing Waveform Description

In FIG. 167 and FIG. 168, shows the timing of the data valid and readysignals between the SFU and LBD. A diagram and pseudocode is given forboth read and write interfaces between the SFU and LBD.

25.8.8.1 LBD-SFU Write Interface Timing

The main points to note from FIG. 167 are:

-   -   In clock cycle 1 sfu_lbd_rdy detects that it has only space to        receive 2 more 16 bit words from the LBD after the current clock        cycle.    -   The data on lbd_sfu_wdata is valid and this is indicated by        lbd_sfu_wdatavalid being asserted.    -   In clock cycle 2 sfu_lbd_rdy is deasserted however the LBD can        not react to this signal until clock cycle 3. So in clock cycle        3 there is also valid data from the LBD which consumes the last        available location available in the FIFO in the SFU (FIFO free        level is zero).    -   In clock cycle 4 and 5 the FIFO is read and 2 words become free        in the FIFO.    -   In cycle 4 the SFU determines that the FIFO has more room and        asserts the ready signal on the next cycle.    -   The LBD has entered a pause mode and waits for sfu_lbd_rdy to be        asserted again, in cycle 5 the LBD sees the asserted ready        signal and responds by writing one unit into the FIFO, in cycle        6.    -   The SFU detects it has 2 spaces left in the FIFO and the current        cycle is an active write (same as in cycle 1), and deasserts the        ready on the next cycle.    -   In cycle 7 the LBD did not have data to write into the FIFO, and        so the FIFO remains with one space left    -   The SFU toggles the ready signal every second cycle, this allows        the LBD to write one unit at a time to the FIFO.    -   In cycle 9 the LBD responds to the single ready pulse by writing        into the FIFO and consuming the last remaining unit free.

The write interface pseudocode for generating the ready is. // readygeneration pseudocode if (fifo_free_level > 2)then  nlf_rdy = 1 elsif(fifo_free_level == 2) then  if (lbd_sfu_wdatavalid == 1)then   nlf_rdy= 0  else   nlf_rdy = 1 elsif (fifo_free_level == 1) then  if(lbd_sfu_wdatavalid == 1)then   nlf_rdy = 0  else   nlf_rdy =NOT(sfu_lbd_rdy) else  nlf_rdy  = 0 sfu_lbd_rdy = (nlf_rdy AND plf_rdy)25.8.8.2 SFU-LBD Read Interface

The read interface is similar to the write interface except that readdata (sfu_lbd_pldata) takes an extra cycle to respond to the dataadvance signal (lbd_sfu_pladvword signal).

It is not possible to read the FIFO totally empty during the processingof a line, one word must always remain in the FIFO. At the end of a linethe fifo can be read to totally empty. This functionality is controlledby the SFU with the generation of the plf_signal.

There is an apparent corner case on the read side which should behighlighted. On examination this turns out to not be an issue.

Scenario 1:

-   -   sfu_lbd_rdy will go low when there is still is still 2 pieces of        data in the FIFO. If there is a lbd_sfu_pladvword pulse in the        next cycle the data will appear on sfu_lbd_pldata[15:0].        Scenario 2:    -   sfu_lbd_rdy will go low when there is still 2 pieces of data in        the FIFO. If there is no lbd_sfu_pladvword pulse in the next        cycle and it is not the end of the page then the SFU will read        the data for the next line from DRAM and the read FIFO will fill        more, sfu_lbd_rdy will assert again, and so the data will appear        on sfu_lbd_pldata[15:0]. If it happens that the next line of        data is not available yet the sfu_lbd_pldata bus will go invalid        until the next lines data is available. The LBD does not sample        the sfu_lbd_pldata bus at this time (i.e. after the end of a        line) and it is safe to have invalid data on the bus.        Scenario 3:    -   sfu_lbd_rdy will go low when there is still 2 pieces of data in        the FIFO. If there is no lbd_sfu_pladvword pulse in the next        cycle and it is the end of the page then the SFU will do no more        reads from DRAM, sfu_lbd_rdy will remain de-asserted, and the        data will not be read out from the FIFO. However last line of        data on the page is not needed for decoding in the LBD and will        not be read by the LBD. So scenario 3 will never apply.

The pseudocode for the read FIFO ready generation // ready generationpseudocode if (pl_count == lbd_dram_words) then  plf_rdy = 1 elsif(fifo_fill_level > 3)then  plf_rdy = 1 elsif (fifo_fill_level == 3) then if (lbd_sfu_pladvword == 1)then   plf_rdy = 0  else   plf_rdy = 1 elsif(fifo_fill_level == 2) then  if (lbd_sfu_pladvword == 1)then   plf_rdy =0  else   plf_rdy = NOT(sfu_lbd_rdy) else  plf_rdy  = 0 sfu_lbd_rdy =(plf_rdy AND nlf_rdy)

25.8.9 HCUReadLineFIFO Sub-Block TABLE 167 HCUReadLineFIFO Additional IODefinition Port Name Pins I/O Description DIU and Address Generationsub-block Signals hrf_xadvance 1 In Signal from horizontal scaling unit1 - supply the next dot 1 - supply the current dot hrf_hcu_endofline 1Out Signal lasting 1 cycle indicating then end of the HCU read line.hrf_diurreq 1 Out Signal indicating the HCUReadLineFIFO has space for256-bits of DIU data. hrf_diurack 1 In Acknowledge that read request hasbeen accepted and hrf_divrreq should be de-asserted. hrf_diurdata 1 InData from HCUReadLineFIFO to DIU. First 64-bits are bits 63:0 of 256 bitword. Second 64-bits are bits 127:64 of 256 bit word. Third 64-bits arebits 191:128 of 256 bit word. Fourth 64-bits are bits 255:192 of 256 bitword. hrf_diurvalid 1 In Signal indicating data on hrf_diurdata isvalid. hrf_diuidle 1 Out Signal indicating DIU state-machine is in theIDLE state.25.8.9.1 General Description

The HCUReadLineFIFO sub-block comprises a double 256-bit buffer betweenthe HCU and the DIU Interface and Address Generator sub-block. The FIFOis implemented as 8 times 64-bit words. The FIFO is written by the DIUInterface and Address Generator sub-block and read by the HCU.

The DIU Interface and Address Generation (DAG) sub-block interface ofthe HCUReadLineFIFO is identical to the LBDPrevLineFIFO DIU interface.

Whenever 4 locations in the FIFO are free the FIFO will request 256-bitsof data from the DAG sub-block by asserting hrf_diurreq. A signalhrf_diurack indicates that the request has been accepted and hrf_diurreqshould be de-asserted.

The data is written to the FIFO as 64-bits on hrf_diurdata[63:0] over 4clock cycles. The signal hrf_diurvalid indicates that the data returnedon hrf_diurdata[63:0] is valid. hrf_diurvalid is used to generate theFIFO write enable, write_en, and to increment the FIFO write address,write_adr[2:0]. If the HCUReadLineFIFO still has 256-bits free thenhrf_diurreq should be asserted again.

The HCUReadLineFIFO generates a signal sfu_hcu_avail to indicate that ithas data available for the HCU. The HCU reads single-bit data suppliedon sfu_hcu_sdata. The FIFO control logic generates a signal bit selectwhich selects the next bit of the 64-bit FIFO word to output onsfu_hcu_sdata. The signal hcu_sfu_advdot tells the HCUReadLineFIFO tosupply the next dot (hrf_xadvance=1) or the current dot (hrf_xadvance=0)on sfu_hcu_sdata according to the hrf_xadvance signal from the scalingcontrol unit in the DAG sub-block. The HCU should not generate thehcu_sfu_advdot signal until sfu_hcu_avail is true. The HCU can thereforestall waiting for the sfu_hcu_avail signal.

When the entire current 64-bit FIFO word has been read by the HCUhcu_sfu_advdot will cause the next word to be popped from the FIFO.

The last 256-bit word for a line read from DRAM and written into theHCUReadLineFIFO can contain dots or extra padding which should not beoutput to the HCU. A counter in the HCUReadLineFIFO,hcuadvdot_count[15:0], counts the number of hcu_sfu_advdot strobesreceived from the HCU. When the count equals hcu_num_dots[15:0] theHCUReadLineFIFO must adjust the FIFO read address to point to the next256-bit word boundary in the FIFO. This can be achieved by consideringthe FIFO read address, read adr[2:0], will require 3 bits to address 8locations of 64-bits. The next 256-bit aligned address is calculated byinverting the MSB of the read_adr and setting all other bits to 0. If(hcuadvdot_count == hcu_num_dots) then  read_adr[1:0] = b00  read_adr[2]= ˜read_adr[2]

The DIU Interface and Address Generator sub-block scaling unit alsoneeds to know when hcuadvdot_count equals hcu_num_dots. This conditionis exported from the HCUReadLineFIFO as the signal hrf_hcu_endofline.When the hrf_hcu_endofline is asserted the scaling unit will decidebased on vertical scaling whether to go back to the start of the currentline or go onto the next line.

25.8.9.2 DRAM Access Limitation

The SFU must output 1 bit/cycle to the HCU. Since HCUNumDots may not bea multiple of 256 bits the last 256-bit DRAM word on the line cancontain extra zeros. In this case, the SFU may not be able to provide 1bit/cycle to the HCU. This could lead to a stall by the SFU. This stallcould then propagate if the margins being used by the HCU are notsufficient to hide it. The maximum stall can be estimated by thecalculation: DRAM service period—X scale factor * dots used from lastDRAM read for HCU line.

25.8.10 DIU

Interface and Address Generator Sub-Block TABLE 168 DIU Interface andAddress Generator Additional IO Description Port name Pins I/ODescription Internal LBDPrevLineFIFO Inputs plf_diurreq 1 In Signalindicating the LBDPrevLineFIFO has 256-bits of data free. plf_diurack 1Out Acknowledge that read request has been accepted and plf_diurreqshould be de-asserted. plf_diurdata 1 Out Data from the DIU toLBDPrevLineFIFO. First 64-bits are bits 63:0 of 256 bit word Second64-bits are bits 127:64 of 256 bit word Third 64-bits are bits 191:128of 256 bit word Fourth 64-bits are bits 255:192 of 256 bit wordplf_diurrvalid 1 Out Signal indicating data on Plf_diurdata is valid.plf_diuidle 1 In Signal indicating DIU state-machine is in the IDLEstate. Internal LBDNextLineFIFO Inputs nlf_diuwreq 1 In Signalindicating the LBDNextLineFIFO has 256-bits of data for writing to theDIU. nlf_diuwack 1 Out Acknowledge from DIU that write request has beenaccepted and write data can be output on nlf_diuwdata together withnlf_diuwvalid. nlf_diuwdata 1 In Data from LBDNextLineFIFO to DIUInterface. First 64-bits are bits 63:0 of 256 bit word Second 64-bitsare bits 127:64 of 256 bit word Third 64-bits are bits 191:128 of 256bit word Fourth 64-bits are bits 255:192 of 256 bit word nlf_diuwvalid 1In Signal indicating that data on wlf_diuwdata is valid. InternalHCUReadLineFIFO Inputs hrf_hcu_endofline 1 In Signal lasting 1 cycleindicating then end of the HCU read line. hrf_xadvance 1 Out Signal fromhorizontal scaling unit 1 - supply the next dot 1 - supply the currentdot hrf_diurreq 1 In Signal indicating the HCUReadLineFIFO has space for256-bits of DIU data. hrf_diurack 1 Out Acknowledge that read requesthas been accepted and hrf_diurreq should be de-asserted. hrf_diurdata 1Out Data from HCUReadLineFIFO to DIU. First 64-bits are bits 63:0 of 256bit word Second 64-bits are bits 127:64 of 256 bit word Third 64-bitsare bits 191:128 of 256 bit word Fourth 64-bits are bits 255:192 of 256bit word hrf_diurvalid 1 Out Signal indicating data on plf_diurdata isvalid. hrf_diuidle 1 In Signal indicating DIU state-machine is in theIDLE state.25.8.10.1 General Description

The DIU Interface and Address Generator (DAG) sub-block manages thebi-level buffer in DRAM. It has a DIU Write Interface for theLBDNextLineFIFO and a DIU Read Interface shared between theHCUReadLineFIFO and LBDPrevLineFIFO.

All DRAM address management is centralised in the DAG. DRAM access ispre-emptive i.e. after a FIFO unit has made an access then as soon asthe FIFO has space to read or data to write a DIU access will berequested immediately. This ensures there are no unnecessary stallsintroduced e.g. at the end of an LBD or HCU line.

The control logic for horizontal and vertical non-integer scaling logicis completely contained in the DAG sub-block. The scaling control unitexports the hlf_xadvance signal to the HCUReadLineFIFO which indicateswhether to replicate the current dot or supply the next dot forhorizontal scaling.

25.8.10.2 DIU Write Interface

The LBDNextLineFIFO generates all the DIU write interface signalsdirectly except for sfu_diu_wadr[21:5] which is generated by the AddressGeneration logic The DIU request from the LBDNextLineFIFO will benegated if its respective address pointer in DRAM is invalid i.e.nlf_adrvalid=0. The implementation must ensure that no erroneousrequests occur on sfu_diu_wreq.

25.8.10.3 DIU Read Interface

Both HCUReadLineFIFO and LBDPrevLineFIFO share the read interface. Ifboth sources request simultaneously, then the arbitration logicimplements a round-robin sharing of read accesses between theHCUReadLineFIFO and LBDPrevLineFIFO.

The DIU read request arbitration logic generates a signal,select_hrfplf, which indicates whether the DIU access is from theHCUReadLineFIFO or LBDPrevLineFIFO (0=HCUReadLineFIFO,1=LBDPrevLineFIFO). FIG. 171 shows select_hrfplf multiplexing thereturned DIU acknowledge and read data to either the HCUReadLineFIFO orLBDPrevLineFIFO.

The DIU read request arbitration logic is shown in FIG. 172. Thearbitration logic will select a DIU read request on hrf_diurreq orplf_diurreq and assert sfu_diu_rreq which goes to the DIU. Theaccompanying DIU read address is generated by the Address GenerationLogic. The select signal select_hrfplf will be set according to thearbitration winner (0=HCUReadLineFIFO, 1=LBDPrevLineFIFO). sfu_diu_rreqis cleared when the DIU acknowledges the request on diu_sfu_rack.Arbitration cannot take place again until the DIU state-machine of thearbitration winner is in the idle state, indicated by diu_idle. This isnecessary to ensure that the DIU read data is multiplexed back to theFIFO that requested it.

The DIU read requests from the HCUReadLineFIFO and LBDPrevLineFIFO willbe negated if their respective addresses in DRAM are invalID,hrf_adrvalid=0 or plf_adrvalid=0. The implementation must ensure that noerroneous requests occur on sfu_diu_rreq.

If the HCUReadLineFIFO and LBDPrevLineFIFO request simultaneously, thenif the request is not following immediately another DIU read portaccess, the arbitration logic will choose the HCUReadLineFIFO bydefault. If there are back to back requests to the DIU read port thenthe arbitration logic implements a round-robin sharing of read accessesbetween the HCUReadLineFIFO and LBDPrevLineFIFO.

A pseudo-code description of the DIU read arbitration is given below. // history is of type {none, hrf, plf}, hrf is HCUReadLineFIFO, plf isLBDPrevLineFIFO  // initialisation on reset  select_hrfplf = 0 //default choose hrf  history = none // no DIU read access immediatelypreceding  // state-machine is busy between asserting sfu_diu_rreq anddiu_idle = 1  // if DIU read requester state-machine is in idle statethen de-assert busy  if (diu_idle == 1) then   busy = 0  //ifacknowledge received from DIU then de-assert DIU request  if(diu_sfu_rack == 1) then   //de-assert request in response toacknowledge   sfu_diu_rreq = 0  // if not busy then arbitrate betweenincoming requests  // if request detected then assert busy  if (busy ==0) then   //if there is no request   if (hrf_diurreq == 0) AND(plf_diurreq == 0) then   sfu_diu_rreq = 0   history = none   // elsethere is a request   else {   // assert busy and request DIU read access  busy = 1   sfu_diu_rreq = 1  // arbitrate in round-robin fashion between the requestors  // if only HCUReadLineFIFO requesting choose HCUReadLineFIFO   if(hrf_diurreq == 1) AND (plf_diurreq == 0) then    history = hrf   select_hrfplf = 0   // if only LBDPrevLineFIFO requesting chooseLBDPrevLineFIFO   if (hrf_diurreq == 0) AND (plf_diurreq == 1) then   history = plf    select_hrfplf = 1   //if both HCUReadLineFIFO andLBDPrevLineFIFO requesting   if (hrf_diurreq == 1) AND (plf_diurreq== 1) then    // no immediately preceding request choose HCUReadLineFIFO   if (history == none) then     history = hrf     select_hrfplf = 0   // if previous winner was HCUReadLineFIFO choose LBDPrevLineFIFO   elsif (history == hrf) then     history = plf     select_hrfplf = 1   // if previous winner was LBDPrevLineFIFO choose HCUReadLineFIFO   elsif (history == plf) then     history = hrf    select_hrfplf = 0  // end there is a request   }25.8.10.4 Address Generation Logic

The DIU interface generates the DRAM addresses of data read and writtenby the SFU's FIFOs.

A write request from the LBDNextLineFIFO on nlf_diuwreq causes a writerequest from the DIU Write Interface. The Address Generator supplies theDRAM write address on sfu_diu_wadr[21:5]A winning read request from theDIU read request arbitration logic causes a read request from the DIURead Interface. The Address Generator supplies the DRAM read address onsfu_diu_radr[21:5].

The address generator is configured with the number of DRAM words toread in a HCU line, hcu_dram_words, the first DRAM address of the SFUarea, start_sfu_adr[21:5], and the last DRAM address of the SFU area,end_sfu_adr[21:5].

Note hcu_dram_words configuration register specifies the the number ofDRAM words consumed per line in the HCU, while lbd_dram_words specifiesthe number of DRAM words generated per line by the LBD. These values arenot required to be the same.

For example the LBD may store 10 DRAM words per line(lbd_dram_words=10), but the HCU may consume 5 DRAM words per line. Insuch case the hcu_dram_words would be set to 5 and the HCU Read LineFIFO would trigger a new line after it had consumed 5 DRAM words (viahrf_hcu_endofline).

Address Generation

There are four address pointers used to manage the bi-level DRAM buffer:

-   a. hcu_readline_rd_adr is the read address in DRAM for the    HCUReadLineFIFO.-   b. hcu_startreadline_adr is the start address in DRAM for the    current line being read by the HCUReadLineFIFO.-   c. lbd_nextline_wr_adr is the write address in DRAM for the    LBDNextLineFIFO.-   d. lbd_prevline_rd_adr is the read address in DRAM for the    LBDPrevLineFIFO.

The current value of these address pointers are readable by the CPU.

Four corresponding address valid flags are required to indicate whetherthe address pointers are valID, based on whether the FIFOs are full orempty.

-   a. hlf_adrvalID, derived from hrf_nlf_fifo_emp-   b. hlf_start_adrvalID, derived from start_hrd_nlf_fifo_emp-   c. nlf_adrvalid. derived from nlf_plf_fifo_full and    nlf_hrf_fifo_full-   d. plf_adrvalid. derived from plf_nlf_fifo_emp

DRAM requests from the FIFOs will not be issued to the DIU until theappropriate address flag is valid.

Once a request has been acknowledged, the address generation logic cancalculate the address of the next 256-bit word in DRAM, ready for thenext request.

Rules for Address Pointers

The address pointers must obey certain rules which indicate whether theyare valid:

-   a. hcu_readline_rd_adr is only valid if it is reading earlier in the    line than lbd_nextline_wr_adr is writing i.e. the fifo is not empty-   b. The SFU (lbd_nextline_wr_adr) cannot overwrite the current line    that the HCU is reading from (hcu_startreadline_adr) i.e. the fifo    is not full, when compared with the HCU read line pointer-   c. The LBDNextLineFIFO (lbd_nextline_wr_adr) must be writing earlier    in the line than LBD-PrevLineFIFO (lbd_prevline_rd_adr) is reading    and must not overwrite the current line that the HCU is reading from    i.e. the fifo is not full when compared to the PrevLineFifo read    pointer-   d. The LBDPrevLineFIFO (lbd_prevline_rd_adr) can read right up to    the address that LBDNextLineFIFO (lbd_nextline_wr_adr) is writing    i.e the fifo is not empty.-   e. At startup i.e. when sfu_go is asserted, the pointers are reset    to start_sfu_adr[21:5].-   f. The address pointers can wrap around the SFU bi-level store area    in DRAM.    Address Generator Pseudo-Code:

Initialization: Initialization: if (sfu_go rising edge) then //initialise address pointers to start of SFU address space lbd_prevline_rd_adr = start_sfu_adr[21:5]  lbd_nextline_wr_adr =start_sfu_adr[21:5]  hcu_readline_rd_adr = start_sfu_adr[21:5] hcu_startreadline_adr = start_sfu_adr[21:5]  lbd_nextline_wr_wrap = 0 lbd_prevline_rd_wrap = 0  hcu_startreadline_wrap = 0 hcu_readline_rd_wrap = 0  } Determine FIFO fill and empty status: //calculate which FIFOs are full and emptyplf_nlf_fifo_emp  =  (lbd_prevline_rd_adr == lbd_nextline_wr_adr) AND      (lbd_prevline_rd_wrap == lbd_nextline_wr_wrap)nlf_plf_fifo_full = (lbd_nextline_wr_adr == lbd_prevline_rd_adr) AND      (lbd_prevline_rd_wrap != lbd_nextline_wr_wrap)nlf_hrf_fifo_full = (lbd_nextline_wr_adr == hcu_startreadline_adr ) AND      (hcu_startreadline_wrap != lbd_nextline_wr_wrap ) // hcu startaddress can jump addresses and so needs comparitor if(hcu_startreadline_wrap == lbd_nextline_wr_wrap) then start_hrf_nlf_fifo_emp=    (hcu_startreadline_adr >=lbd_nextline_wr_adr) else start_hrf_nlf_fifo_emp  =  NOT(hcu_startreadline_adr >=lbd_nextline_wr_adr)// hcu read address can jump addresses and so needs comparitor if(hcu_readline_rd_wrap == lbd_nextline_wr_wrap) then hrf_nlf_fifo_emp =      (hcu_readline_rd_adr >=lbd_nextline_wr_adr)else hrf_nlf_fifo_emp   =   NOT(hcu_readline_rd_adr >=lbd_nextline_wr_adr)Address pointer updating: // LBD Next line FIFO // if DIU writeacknowledge and LBDNextLineFIFO is not full with reference to PLF andHRF if (diu_sfu_wack == 1 AND nlf_plf_fifo_full != 1 ANDnlf_hrf_fifo_full !=1 ) then  if  (lbd_nextline_wr_adr  ==  end sfuadr)  then // if end of SFU address range  lbd_nextline_wr_adr =start_sfu_adr // go to start of SFU address range  lbd_nextline_wr_wrap=NOT (lbd_nextline_wr_wrap) // invert the wrap bit  else lbd_nextline_wr_adr++ // increment address pointer // LBD PrevLine FIFO//if DIU read acknowledge and LBDPrevLineFIFO is not emptyif (diu_sfu_rack == 1 AND select_hrfplf == 1 AND plf_nlf_fifo_emp !=1)then  if (lbd_prevline_rd_adr == end_sfu_adr) then  lbd_prevline_rd_adr= start_sfu_adr // go to start of SFU address range lbd_prevline_rd_wrap= NOT (lbd_prevline_rd_wrap) // invert the wrap bit else  lbd_prevline_rd_adr++ // increment address pointer // HCUReadLine FIFO // if DIU read acknowledge and HCUReadLineFIFO fifo is notempty if (diu_sfu_rack == 1 AND select_hrfplf == 0 AND hrf_nlf_fifo_emp!= 1) then  // going to update hcu read line address  if(hrf_hcu_endofline == 1) AND (hrf_yadvance == 1) then { // read the nextline from DRAM  // advance to start of next HCU line in DRAM hcu_startreadline_adr = hcu_startreadline_adr + lbd_dram_words offset = hcu_startreadline_adr − end_sfu_adr − 1 // allow for addresswraparound  if (offset >= 0) then   hcu_startreadline_adr =start_sfu_adr + offset      hcu_startreadline_wrap=NOT(hcu_startreadline_wrap)  hcu_readline_rd_adr = hcu_startreadline_adr hcu_readline_rd_wrap= hcu_startreadline_wrap  } elsif (hrf_hcu_endofline == 1) AND (hrf_yadvance == 0) then hcu_readline_rd_adr = hcu_startreadline_adr // restart and re-use thesame line  hcu_readline_rd_wrap= hcu_startreadline_wrap  elsif (hcureadline rd adr == end sfu adr) then // check if the FIFO needs to wrapspace  hcu_readline_rd_adr = start_sfu_adr // go to start of SFU addressspace  hcu_readline_rd_wrap= NOT (hcu_readline_rd_wrap)  else hcu_readline_rd_adr ++ // increment address pointer25.8.10.4.1 X Scaling of Data for HCUReadLineFIFO

The signal hcu_sfu_advdot tells the HCUReadLineFIFO to supply the nextdot or the current dot on sfu_hcu_sdata according to the hrf_xadvancesignal from the scaling control unit. When hrf_xadvance is 1 theHCUReadLineFIFO should supply the next dot. When hrf_xadvance is 0 theHCUReadLineFIFO should supply the current dot.

The algorithm for non-integer scaling is described in the pseudocodebelow. Note, x_scale_count should be loaded with x_start_count afterreset and at the end of each line. The end of the line is indicated byhrf_hcu_endofline from the HCUReadLineFIFO.  if (hcu_sfu_advdot == 1)then  if (x_scale_count + x_scale_denom − x_scale_num >= 0) then  x_scale_count = x_scale_count + x_scale_denom − x_scale_num  hrf_xadvance = 1  else   x_scale_count = x_scale_count + x_scale_denom  hrf_xadvance = 0  else  x_scale_count = x_scale_count  hrf_xadvance =025.8.10.4.2 Y Scaling of Data for HCUReadLineFIFO

The HCUReadLineFIFO counts the number of hcu_sfu_advdot strobes receivedfrom the HCU. When the count equals hcu_num_dots the HCUReadLineFIFOwill assert hrf_hcu_endofline for a cycle.

The algorithm for non-integer scaling is described in the pseudocodebelow. Note, y_scale_count should be loaded with zero after reset.  if(hrf_hcu_endofline == 1) then if (y_scale_count + y_scale_denom − y_scale_num >= 0) then  y_scale_count = y_scale_count + y_scale_denom − y_scale_num  hrf_yadvance = 1  else   y_scale_count = y_scale_count + y_scale_denom  hrf_yadvance = 0  else  y_scale_count = y_scale_count  hrf_yadvance =0

When the hrf_hcu_endofline is asserted the Y scaling unit will decidewhether to go back to the start of the current line, by settinghrf_yadvance=0, or go onto the next line, by setting hrf_yadvance=1.

FIG. 176 shows an overview of X and Y scaling for HCU data.

26 Tag Encoder (TE)

26.1 Overview

The Tag Encoder (TE) provides functionality for Netpage-enabledapplications, and typically requires the presence of IR ink (although Kink can be used for tags in limited circumstances). The TE encodes fixeddata for the page being printed, together with specific tag data valuesinto an error-correctable encoded tag which is subsequently printed ininfrared or black ink on the page. The TE places tags on a triangulargrID, and can be programmed for both landscape and portraitorientations.

Basic tag structures are normally rendered at 1600 dpi, while tag datais encoded into an arbitrary number of printed dots. The TE supportsinteger scaling in the Y-direction while the TFU supports integerscaling in the X-direction. Thus, the TE can render tags at resolutionsless than 1600 dpi which can be subsequently scaled up to 1600 dpi.

The output from the TE is buffered in the Tag FIFO Unit (TFU) which isin turn used as input by the HCU. In addition, a te_finishedband signalis output to the end of band unit once the input tag data has beenloaded from DRAM. The high level data path is shown by the block diagramin FIG. 177.

After passing through the HCU, the tag plane is subsequently printedwith an infrared-absorptive ink that can be read by a Netpage sensingdevice. Since black ink can be IR absorptive, limited functionality canbe provided on offset-printed pages using black ink on otherwise blankareas of the page—for example to encode buttons. Alternatively aninvisible infrared ink can be used to print the position tags over thetop of a regular page. However, if invisible IR ink is used, care mustbe taken to ensure that any other printed information on the page isprinted in infrared-transparent CMY ink, as black ink will obscure theinfrared tags. The monochromatic scheme was chosen to maximize dynamicrange in blurry reading environments.

When multiple SoPEC chips are used for printing the same side of a page,it is possible that a single tag will be produced by two SoPEC chips.This implies that the TE must be able to print partial tags.

The throughput requirement for the SoPEC TE is to produce tags at halfthe rate of the PEC1 TE.

Since the TE is reused from PEC1, the SoPEC TE over-produces by a factorof 2.

In PEC1, in order to keep up with the HCU which processes 2 dots percycle, the tag data interface has been designed to be capable ofencoding a tag in 63 cycles. This is actually accomplished inapproximately 52 cycles within PEC1. If the SoPEC TE were to be modifiedfrom two dots production per cycle to a nominal one dot per cycle itshould not lose the 63/52 cycle performance edge attained in the PEC1TE.

26.2 What are Tags?

The first barcode was described in the late 1940's by Woodland andSilver, and finally patented in 1952 (U.S. Pat. No. 2,612,994) whenelectronic parts were scarce and very expensive. Now however, with theadvent of cheap and readily available computer technology, nearly everyitem purchased from a shop contains a barcode of some description on thepackaging. From books to CDs, to grocery items, the barcode provides aconvenient way of identifying an object by a product number. The exactinterpretation of the product number depends on the type of barcode.Warehouse inventory tracking systems let users define their own productnumber ranges, while inventory in shops must be more universally encodedso that products from one company don't overlap with products fromanother company. Universal Product Codes (UPC) were introduced in themid 1970's at the request of the National Association of Food Chains forthis very reason. Barcodes themselves have been specified in a largenumber of formats. The older barcode formats contain characters that aredisplayed in the form of lines. The combination of black and white linesdescribe the information the barcodes contains. Often there are twotypes of lines to form the complete barcode: the characters (theinformation itself) and lines to separate blocks for better opticalrecognition. While the information may change from barcode to barcode,the lines to separate blocks stays constant. The lines to separateblocks can therefore be thought of as part of the constant structuralcomponents of the barcode.

Barcodes are read with specialized reading devices that then pass theextracted data onto the computer for further processing. For example, apoint-of-sale scanning device allows the sales assistant to add thescanned item to the current sale, places the name of the item and theprice on a display device for verification etc. Light-pens, gun readers,scanners, slot readers, and cameras are among the many devices used toread the barcodes.

To help ensure that the data extracted was read correctly, checksumswere introduced as a crude form of error detection. More recent barcodeformats, such as the Aztec 2D barcode developed by Andy Longacre in 1995(U.S. Pat. No. 5,591,956), but now released to the public domain, useredundancy encoding schemes such as Reed-Solomon. Reed Solomon encodingis adequately discussed in [28], [30] and [34]. The reader is advised torefer to these sources for background information. Very often the degreeof redundancy encoding is user selectable.

More recently there has also been a move from the simple one dimensionalbarcodes (line based) to two dimensional barcodes. Instead of storingthe information as a series of lines, where the data can be extractedfrom a single dimension, the information is encoded in two dimensions.Just as with the original barcodes, the 2D barcode contains bothinformation and structural components for better optical recognition.FIG. 178 shows an example of a QR Code (Quick Response Code), developedby Denso of Japan (U.S. Pat. No. 5,726,435). Note the barcode cell iscomprised of two areas: a data area (depends on the data being stored inthe barcode), and a constant position detection pattern. The constantposition detection pattern is used by the reader to help locate the cellitself, then to locate the cell boundaries, to allow the reader todetermine the original orientation of the cell (orientation can bedetermined by the fact that there is no 4th corner pattern).

The number of barcode encoding schemes grows daily. Yet very often thehardware for producing these barcodes is specific to the particularbarcode format. As printers become more and more embedded, there is anincreasing desire for real-time printing of these barcodes. Inparticular, Netpage enabled applications require the printing of 2Dbarcodes (or tags) over the page, preferably in infra-red ink. The tagencoder in SoPEC uses a generic barcode format encoding scheme which isparticularly suited to real-time printing. Since the barcode encodingformat is generic, the same rendering hardware engine can be used toproduce a wide variety of barcode formats.

Unfortunately the term “barcode” is interpreted in different ways bydifferent people. Sometimes it refers only to the data area component,and does not include the constant position detection pattern. In othercases it refers to both data and constant position detection pattern.

We therefore use the term tag to refer to the combination of data andany other components (such as position detection pattern, blank spaceetc. surround) that must be rendered to help hold or locate/read thedata. A tag therefore contains the following components:

-   -   data area(s). The data area is the whole reason that the tag        exists. The tag data area(s) contains the encoded data        (optionally redundancy-encoded, perhaps simply checksummed)        where the bits of the data are placed within the data area at        locations specified by the tag encoding scheme.    -   constant background patterns, which typically includes a        constant position detection pattern. These help the tag reader        to locate the tag. They include components that are easy to        locate and may contain orientation and perspective information        in the case of 2D tags. Constant background patterns may also        include such patterns as a blank area surrounding the data area        or position detection pattern. These blank patterns can aid in        the decoding of the data by ensuring that there is no        interference between tags or data areas.

In most tag encoding schemes there is at least some constant backgroundpattern, but it is not necessarily required by all. For example, if thetag data area is enclosed by a physical space and the reading means usesa non-optical location mechanism (e.g. physical alignment of surface todata reader) then a position detection pattern is not required.

Different tag encoding schemes have different sized tags, and havedifferent allocation of physical tag area to constant position detectionpattern and data area. For example, the QR code has 3 fixed blocks atthe edges of the tag for position detection pattern (see FIG. 178) and adata area in the remainder. By contrast, the Netpage tag structure (seeFIGS. 179 and 180) contains a circular locator component, an orientationfeature, and several data areas. FIG. 179(a) shows the Netpage tagconstant background pattern in a resolution independent form. FIG.179(b) is the same as FIG. 179(a), but with the addition of the dataareas to the Netpage tag. FIG. 180 is an example of dot placement andrendering to 1600 dpi for a Netpage tag. Note that in FIG. 180 a singlebit of data is represented by many physical output dots to form a blockwithin the data area.

26.2.1 Contents of the Data Area

The data area contains the data for the tag.

Depending on the tag's encoding format, a single bit of data may berepresented by a number of physical printed dots. The exact number ofdots will depend on the output resolution and the targetreading/scanning resolution. For example, in the QR code (see FIG. 178),a single bit is represented by a dark module or a light module, wherethe exact number of dots in the dark module or light module depends onthe rendering resolution and target reading/scanning resolution. Forexample, a dark module may be represented by a square block of printeddots (all on for binary 1, or all off for binary 0), as shown in FIG.181.

The point to note here is that a single bit of data may be representedin the printed tag by an arbitrary printed shape. The smallest shape isa single printed dot, while the largest shape is theoretically the wholetag itself, for example a giant macrodot comprised of many printed dotsin both dimensions.

An ideal generic tag definition structure allows the generation of anarbitrary printed shape from each bit of data.

26.2.2 What do the Bits Represent?

Given an original number of bits of data, and the desire to place thosebits into a printed tag for subsequent retrieval via a reading/scanningmechanism, the original number of bits can either be placed directlyinto the tag, or they can be redundancy-encoded in some way. The exactform of redundancy encoding will depend on the tag format.

The placement of data bits within the data area of the tag is directlyrelated to the redundancy mechanism employed in the encoding scheme. Theidea is generally to place data bits together in 2D so that burst errorsare averaged out over the tag data, thus typically being correctable.For example, all the bits of Reed-Solomon codeword would be spread outover the entire tag data area so to minimize being affected by a bursterror.

Since the data encoding scheme and shape and size of the tag data areaare closely linked, it is desirable to have a generic tag formatstructure. This allows the same data structure and rendering embodimentto be used to render a variety of tag formats.

26.2.2.1 Fixed and Variable Data Components

In many cases, the tag data can be reasonably divided into fixed andvariable components. For example, if a tag holds N bits of data, some ofthese bits may be fixed for all tags while some may vary from tag totag.

For example, the Universal product code allows a country code and acompany code. Since these bits don't change from tag to tag, these bitscan be defined as fixed, and don't need to be provided to the tagencoder each time, thereby reducing the bandwidth when producing manytags.

Another example is Netpage tags. A single printed page contains a numberof Netpage tags. The page-id will be constant across all the tags, eventhough the remainder of the data within each tag may be different foreach tag. By reducing the amount of variable data being passed toSoPEC's tag encoder for each tag, the overall bandwidth can be reduced.

Depending on the embodiment of the tag encoder, these parameters will beeither implicit or explicit, and may limit the size of tags renderableby the system. For example, a software tag encoder may be completelyvariable, while a hardware tag encoder such as SoPEC's tag encoder mayhave a maximum number of tag data bits.

26.2.2.2 Redundancy-Encode the Tag Data within the Tag Encoder

Instead of accepting the complete number of TagData bits encoded by anexternal encoder, the tag encoder accepts the basicnon-redundancy-encoded data bits and encodes them as required for eachtag. This leads to significant savings of bandwidth and on-chip storage.

In SoPEC's case for Netpage tags, only 120 bits of original data areprovided per tag, and the tag encoder encodes these 120 bits into 360bits. By having the redundancy encoder on board the tag encoder theeffective bandwidth and internal storage required is reduced to only 33%of what would be required if the encoded data was read directly.

26.3 Placement of Tags on a Page

The TE places tags on the page in a triangular grid arrangement as shownin FIG. 182.

The triangular mesh of tags combined with the restriction of no overlapof columns or rows of tags means that the process of tag placement isgreatly simplified. For a given line of dots, all the tags on that linecorrespond to the same part of the general tag structure. The triangularplacement can be considered as alternative lines of tags, where one lineof tags is inset by one amount in the dot dimension, and the other lineof dots is inset by a different amount. The dot inter-tag gap is thesame in both lines of tag, and is different from the line inter-tag gap.

Note also that as long as the tags themselves can be rotated, portraitand landscape printing are essentially the same—the placement parametersof line and dot are swapped, but the placement mechanism is the same.

The general case for placement of tags therefore relies on a number ofparameters, as shown in FIG. 183.

The parameters are more formally described in Table 169. Note that theseare placement parameters and not registers. TABLE 169 Tag placementparameters parameter description restrictions Tag height The number ofdot lines in a tag's bounding box minimum 1 Tag width The number of dotsin a single line of the tag's bounding minimum 1 box. The number of dotsin the tag itself may vary depending on the shape of the tag, but thenumber of dots in the bounding box will be constant (by definition). Dotinter-tag gap The number of dots from the edge of one tag's boundingminimum = 0 box to the start of the next tag's bounding box, in the dotdirection. Line inter-tag The number of dot lines from the edge of onetag's minimum = 0 gap bounding box to the start of the next tag'sbounding box, in the line direction. Start Position Defines the statusof the top left dot on the page - is an — offset in dot & row within thetag or the inter-tag gap. AltTagLinePosition Defines the status for thestart of the alternate row of tags. — Is an offset in dot within the tagor within the dot inter-tag gap (the row position is always 0).26.4 Basic Tag Encoding Parameters

SoPEC's tag encoder imposes range restrictions on tag encodingparameters as a direct result of on-chip buffer sizes. Table 170 liststhe basic encoding parameters as well as range restrictions whereappropriate. Although the restrictions were chosen to take the mostlikely encoding scenarIOs into account, it is a simple matter to adjustthe buffer sizes and corresponding addressing to allow arbitraryencoding parameters in future implementations. TABLE 170 Encodingparameters name definition maximum value imposed by TE W page width 2¹⁴dotpairs or 20.48 inches at 1600 dpi S tag size typical tag size is 2 mm× 2 mm maximum tag size is 384 dots × 384 dots before scaling i.e. 6 mm× 6 mm at 1600 dpi N number of dots in each dimension of 384 dots beforescaling the tag E redundancy encoding for tag data Reed-Solomon GF(2⁴)at 5:10 or 7:8 D_(F) size of fixed data (unencoded)  40 or 56 bits R_(F)size of redundancy-encoded fixed 120 bits data D_(V) size of variabledata (unencoded) 120 or 112 bits R_(V) size of redundancy-encodedvariable 360 or 240 bits data T tags per page width 256

The fixed data for the tags on a page need only be supplied to the TEonce. It can be supplied as 40 or 56 bits of unencoded data and encodedwithin the TE as described in Section 26.4.1. Alternatively it can besupplied as 120 bits of pre-encoded data (encoded arbitrarily).

The variable data for the tags on a page are those 112 or 120 data bitsthat are variable for each tag. Variable tag data is supplied as part ofthe band data, and is always encoded by the TE as described in Section26.4.1, but may itself be arbitrarily pre-encoded.

26.4.1 Redundancy Encoding

The mapping of data bits (both fixed and variable) to redundancy encodedbits relies heavily on the method of redundancy encoding employed.Reed-Solomon encoding was chosen for its ability to deal with bursterrors and effectively detect and correct errors using a minimum ofredundancy. Reed Solomon encoding is adequately discussed in [28], [30]and [34]. The reader is advised to refer to these sources for backgroundinformation.

In this implementation of the TE we use Reed-Solomon encoding over theGalois Field GF(2⁴). Symbol size is 4 bits. Each codeword contains 154-bit symbols for a codeword length of 60 bits.

The primitive polynomial is p(x)=x⁴+x+1, and the generator polynomial isg(x)=(x+α)(x+α²) . . . (x+α^(2t)), where t=the number of symbols thatcan be corrected.

Of the 15 symbols, there are two possibilities for encoding:

-   -   RS(15, 5): 5 symbols original data (20 bits), and 10 redundancy        symbols (40 bits). The 10 redundancy symbols mean that we can        correct up to 5 symbols in error. The generator polynomial is        therefore g(x)=(x+α)(x+α²) . . . (x+α¹⁰).    -   RS(15, 7): 7 symbols original data (28 bits), and 8 redundancy        symbols (32 bits). The 8 redundancy symbols mean that we can        correct up to 4 symbols in error. The generator polynomial is        g(x)=(x+α)(x+α²) . . . (x+α⁸).

In the first case, with 5 symbols of original data, the total amount oforiginal data per tag is 160 bits (40 fixed, 120 variable). This isredundancy encoded to give a total amount of 480 bits (120 fixed, 360variable) as follows:

-   -   Each tag contains up to 40 bits of fixed original data.        Therefore 2 codewords are required for the fixed data, giving a        total encoded data size of 120 bits. Note that this fixed data        only needs to be encoded once per page.    -   Each tag contains up to 120 bits of variable original data.        Therefore 6 codewords are required for the variable data, giving        a total encoded data size of 360 bits.

In the second case, with 7 symbols of original data, the total amount oforiginal data per tag is 168 bits (56 fixed, 112 variable). This isredundancy encoded to give a total amount of 360 bits (120 fixed, 240variable) as follows:

-   -   Each tag contains up to 56 bits of fixed original data.        Therefore 2 codewords are required for the fixed data, giving a        total encoded data size of 120 bits. Note that this fixed data        only needs to be encoded once per page.    -   Each tag contains up to 112 bits of variable original data.        Therefore 4 codewords are required for the variable data, giving        a total encoded data size of 240 bits.

The choice of data to redundancy ratio depends on the application.

26.5 Data Structures Used by Tag Encoder

26.5.1 Tag Format Structure

The Tag Format Structure (TFS) is the template used to render tags,optimized so that the tag can be rendered in real time. The TFS containsan entry for each dot position within the tag's bounding box. Each entryspecifies whether the dot is part of the constant background pattern orpart of the tag's data component (both fixed and variable).

The TFS is very similar to a bitmap in that it contains one entry foreach dot position of the tag's bounding box. The TFS therefore hasTagHeight×TagWidth entries, where TagHeight matches the height of thebounding box for the tag in the line dimension, and TagWidth matches thewidth of the bounding box for the tag in the dot dimension. A singleline of TFS entries for a tag is known as a tag line structure.

The TFS consists of TagHeight number of tag line structures, one foreach 1600 dpi line in the tag's bounding box. Each tag line structurecontains three contiguous tables, known as tables A, B, and C. Table Acontains 384 2-bit entries, one entry for each of the maximum number ofdots in a single line of a tag (see Table). The actual number of entriesused should match the size of the bounding box for the tag in the dotdimension, but all 384 entries must be present. Table B contains 329-bit data addresses that refer to (in order of appearance) the datadots present in the particular line. All 32 entries must be present,even if fewer are used. Table C contains two 5-bit pointers into tableB, and therefore comprises 10 bits. Padding of 214 bits is added. Thetotal length of each tag line structure is therefore 5×256-bit DRAMwords. Thus a TFS containing TagHeight tag line structures requires aTagHeight*160 bytes. The structure of a TFS is shown in FIG. 184.

A full description of the interpretation and usage of Tables A, B and Cis given in section 26.8.3 on page 444.

26.5.1.1 Scaling a Tag

If the size of the printed dots is too small, then the tag can be scaledin one of several ways. Either the tag itself can be scaled by N dots ineach dimension, which increases the number of entries in the TFS. As analternative, the output from the TE can be scaled up by pixelreplication via a scale factor greater than 1 in the both the TE andTFU.

For example, if the original TFS was 21×21 entries, and the scaling werea simple 2×2 dots for each of the original dots, we could increase theTFS to be 42×42. To generate the new TFS from the old, we would repeateach entry across each line of the TFS, and then we would repeat eachline of the TFS. The net number of entries in the TFS would be increasedfourfold (2×2).

The TFS allows the creation of macrodots instead of simple scaling.Looking at FIG. 185 for a simple example of a 3×3 dot tag, we may wantto produce a physically large printed form of the tag, where each of theoriginal dots was represented by 7×7 printed dots. If we simplyperformed replication by 7 in each dimension of the original TFS, eitherby increasing the size of the TFS by 7 in each dimension or putting ascale-up on the output of the tag generator output, then we would have 9sets of 7×7 square blocks. Instead, we can replace each of the originaldots in the TFS by a 7×7 dot definition of a rounded dot. FIG. 186 showsthe results.

Consequently, the higher the resolution of the TFS the more printed dotscan be printed for each macrodot, where a macrodot represents a singledata bit of the tag. The more dots that are available to produce amacrodot, the more complex the pattern of the macrodot can be. As anexample, Figure n page 461 on page Error! Bookmark not defined. showsthe Netpage tag structure rendered such that the data bits arerepresented by an average of 8 dots×8 dots (at 1600 dpi), but the actualshape structure of a dot is not square. This allows the printed Netpagetag to be subsequently read at any orientation.

26.5.2 Raw Tag Data

The TE requires a band of unencoded variable tag data if variable datais to be included in the tag bit-plane. A band of unencoded variable tagdata is a set of contiguous unencoded tag data records, in order ofencounter top left of printed band from top left to lower right.

An unencoded tag data record is 128 bits arranged as follows: bits 0-111or 0-119 are the bits of raw tag data, bit 120 is a flag used by the TE(TagIsPrinted), and the remaining 7 bits are reserved (and should be 0).Having a record size of 128 bits simplifies the tag data access sincethe data of two tags fits into a 256-bit DRAM word. It also means thatthe flags can be stored apart from the tag data, thus keeping the rawtag data completely unrestricted. If there is an odd number of tags inline then the last DRAM read will contain a tag in the first 128 bitsand padding in the final 128 bits.

The TagIsPrinted flag allows the effective specification of a tagresolution mask over the page. For each tag position the TagIsPrintedflag determines whether any of the tag is printed or not. This allowsarbitrary placement of tags on the page. For example, tags may only beprinted over particular active areas of a page. The TagIsPrinted flagallows only those tags to be printed. TagIsPrinted is a 1 bit flag withvalues as shown in Table 171. TABLE 171 TagIsPrinted values Valuedescription 0 Don't print the tag in this tag position. Output 0 foreach dot within the tag bounding box. 1 Print the tag as specified bythe various tag structures.26.5.3 DRAM Storage Requirements

The total DRAM storage required by a single band of raw tag data dependson the number of tags present in that band. Each tag requires 128 bits.Consequently if there are N tags in the band, the size in DRAM is 16Nbytes.

The maximum size of a line of tags is 163×128 bits. When maximallypacked, a row of tags contains 163 tags (see Table) and extends over aminimum of 126 print lines. This equates to 282 KBytes over a Letterpage.

The total DRAM storage required by a single TFS is TagHeight/7 KBytes(including padding). Since the likely maximum value for TagHeight is 384(given that SoPEC restricts TagWidth to 384), the maximum size in DRAMfor a TFS is 55 KBytes.

26.5.4 DRAM Access Requirements

The TE has two separate read interfaces to DRAM for raw tag data, TD,and tag format structure, TFS.

The memory usage requirements are shown in Table 172. Raw tag data isstored in the compressed page store TABLE 172 Memory usage requirementsBlock Size Description Compressed 2048 Kbytes Compressed data page storefor Bilevel, page store contone and raw tag data. Tag Format  55 Kbyte55 kB in PEC1 for 384 dot line tags (the Structure (384 dot linebenchmark) at 1600 dpi tags @ 1600 dpi) 2.5 mm tags ( 1/10th inch) @1600 dpi require 160 dot lines = 160/384 × 55 or 23 kB 2.5 mm tags @ 800dpi require 80/384 × 55 = 12 kB

The TD interface will read 256-bits from DRAM at a time. Each 256-bitread returns 2 times 128-bit tags. The TD interface to the DIU will be a256-bit double buffer. If there is an odd number of tags in line thenthe last DRAM read will contain a tag in the first 128 bits and paddingin the final 128 bits.

The TFS interface will also read 256-bits from DRAM at a time. The TFSrequired for a line is 136 bytes. A total of 5 times 256-bit DRAM readsis required to read the TFS for a line with 192 unused bits in the fifth256-bit word. A 136-byte double-line buffer will be implemented to storethe TFS data.

The TE's DIU bandwidth requirements are summarized in Table 173. TABLE173 DRAM bandwidth requirements Maximum number of Peak Average Blockcycles between each Bandwidth Bandwidth Name Direction 256-bit DRAMaccess (bits/cycle) (bits/cycle) TD Read Single 256 bit reads1. 1.021.02 TFS Read Single 256 bit reads2. 0.093 0.093 TFS is 136 bytes. Thismeans there is unused data in the fifth 256 bit read. A total of 5 readsis required.1: Each 2 mm tag lasts 126 dot cycles and requires 128 bits. This is arate of 256 bits every 252 cycles.2: 17×64 bit reads per line in PEC1 is 5×256 bit reads per line in SoPECwith unused bits in the last 256-bit read.

26.5.5 TD and TFS Bandstore Wrapping TABLE 174 Bandstore Inputs from CDUPort Name Pins I/O Description cdu_endofbandstore[21:5] 17 In Address ofthe end of the current band of data. 256-bit word aligned DRAM address.cdu_startofbandstore[21:5] 17 In Address of the start of the currentband of data. 256-bit word aligned DRAM address.

Both TD and TFS storage in DRAM can wrap around the bandstore area. Thebounds of the band store are described by inputs from the CDU shown inTable 174. The TD and TFS DRAM interfaces therefore support bandstorewrapping. If the TD or TFS DRAM interface increments an address it ischecked to see if it matches the end of bandstore address. If so, thenthe address is mapped to the start of the bandstore.

26.5.6 Tag Sizes

SoPEC allows for tags to be between 0 to 384 dots. A typical 2 mm tagrequires 126 dots. Short tags do not change the internal bandwidth orthroughput behaviours at all. Tag height is specified so as to allow theDRAM storage for raw tag data to be specified. Minimum tag width is acondition imposed by throughput limitations, so if the width is toosmall TE cannot consistently produce 2 dots per cycle across severaltags (also there are raw tag data bandwidth implications). Thinner tagsstill work, they just take longer and/or need scaling.

26.6 Implementation

26.6.1 Tag Encoder Architecture

A block diagram of the TE can be seen below.

The TE writes lines of bi-level tag plane data to the TFU for laterreading by the HCU. The TE is responsible for merging the encoded tagdata with the tag structure (interpreted from the TFS). Y-integerscaling of tags is performed in the TE with X-integer scaling of thetags performed in the TFU. The encoded tag layer is generated 2 bits ata time and output to the TFU at this rate. The HCU however only consumes1 bit per cycle from the TFU. The TE must provide support for 126 dotTags (2 mm densely packed) with 108 Tags per line with 128 bits per tag.

The tag encoder consists of a TFS interface that loads and decodes TFSentries, a tag data interface that loads tag raw data, encodes it, andprovides bit values on request, and a state machine to generateappropriate addressing and control signals. The TE has two separate readinterfaces to DRAM for raw tag data, TD, and tag format structure, TFS.

It is possible that the raw tag data interface, the TD, to the DIU couldbe replaced by a hardware state machine at a later stage. This wouldallow flexibility in the generation of tags. Support for Y scaling needsto be added to the PEC1 TE. The PEC1 TE already allows stalling at itsoutput during a line when tfu_te_oktowrite is deasserted.

26.6.2 Y-Scaling Output Lines

In order to support scaling in the Y direction the followingmodifications to the PEC1 TE are suggested to the Tag Data Interface,Tag Format Structure Interface and TE Top Level:

-   -   for Tag Data Interface: program the configuration registers of        Table, firstTagLineHeight and tagMaxLine with true value i.e.        not multiplied up by the scale factor YScale. Within the Tag        Data interface there are two counters, countx and county that        have a direct bearing on the rawTagDataAddr generation. countx        decrements as tags are read from DRAM. It is reset to        NumTags[RtdTagSense] at start of each line of tags. county is        decremented as each line of tags is completely read from DRAM        i.e. countx=0. Scaling may be performed by counting the number        of times countx reaches zero and only decrementing county when        this number reaches YScale. This will cause the TagData        Interface to read each line of tag data NumTags[RtdTagSense]*        YScale times.    -   for Tag Format Structure Interface: The implication of Y-scaling        for the TFS is that each Tag Line Structure is used YScale        times. This may be accomplished in either of two ways:    -   For each Tag Line Structure read it once from DRAM and reuse        YScale times. This involves gating the control of TFS buffer        flipping with YScale. Because of the way in which this        advTfsLine and advTagLine related functionality is coded in the        PEC1 TFS this solution is judged to be error-prone.    -   Fetch each TagLineStructure YScale times. This solution involves        controlling the activity of currTfsAddr with YScale.        -   In SoPEC the TFS must supply five addresses to the DIU to            read each individual Tag Line Structure. The DIU returns            4*64-bit words for each of the 5 accesses. This is different            from the behaviour in PEC1, where one address is given and            17 data-words were returned by the DIU.        -   Since the behaviour of the currTfsAddr must be changed to            meet the requirements of the SoPEC DIU it makes sense to            include the Y-Scaling into this change i.e. a count of the            number of completed sets of 5 accesses to the DIU is            compared to YScale. Only when this count equals YScale can            currTfsAddr be loaded with the base address of the next            lines Tag Line Structure in DRAM, otherwise it is re-loaded            with the base address of the current lines Tag Line            Structure in DRAM.    -   For Top Level: The Top Level of the TE has a counter, LinePos,        which is used to count the number of completed output lines when        in a tag gap or in a line of tags. At the start (i.e. top-left        hand dot-pair) of a gap or tag LinePos is loaded with either        TagGapLine or TagMaxLine. The value of LinePos is decremented at        last dot-pair in line. Y-Scaling may be accomplished by gating        the decrement of LinePos based on YScale value        26.6.3 TE Physical Hierarchy

FIG. 188 above illustrates the structural hierarchy of the TE. The toplevel contains the Tag Data Interface (TDI), Tag Format Structure (TFS),and an FSM to control the generation of dot pairs along with a clockedprocess to carry out the PCU read/write decoding. There is also someadditional logic for muxing the output data and generating other controlsignals.

At the highest level, the TE state machine processes the output lines ofa page one line at a time, with the starting position either in aninter-tag gap or in a tag (a SoPEC may be only printing part of a tagdue to multiple SoPECs printing a single line).

If the current position is within an inter-tag gap, an output of 0 isgenerated. If the current position is within a tag, the tag formatstructure is used to determine the value of the output dot, using theappropriate encoded data bit from the fixed or variable data buffers asnecessary. The TE then advances along the line of dots, moving throughtags and inter-tag gaps according to the tag placement parameters.

26.6.4 IO Definitions TABLE 175 TE Port List Port Name Pins I/ODescription Clocks and Resets Pclk 1 In SoPEC Functional clock. prst_n 1In Global reset signal. Bandstore Signals cdu_endofbandstore[21:5] 17 InAddress of the end of the current band of data. 256-bit word alignedDRAM address. cdu_startofbandstore[21:5] 17 In Address of the start ofthe current band of data. 256-bit word aligned DRAM address.te_finishedband 1 Out TE finished band signal to PCU and ICU. PCUInterface data and control signals pcu_addr[8:2] 7 In PCU address bus. 7bits are required to decode the address space for this block.pcu_dataout[31:0] 32 In Shared write data bus from the PCU.te_pcu_datain[31:0] 32 Out Read data bus from the TE to the PCU. pcu_rwn1 In Common read/not-write signal from the PCU. pcu_te_sel 1 In Blockselect from the PCU. When pcu_te_sel is high both pcu_addr andpcu_dataout are valid. te_pcu_rdy 1 Out Ready signal to the PCU. Whente_pcu_rdy is high it indicates the last cycle of the access. For awrite cycle this means pcu_dataout has been registered by the block andfor a read cycle this means the data on te_pcu_datain is valid. TD (rawTag Data) DIU Read Interface signals td_diu_rreq 1 Out TD requests DRAMread. A read request must be accompanied by a valid read address.td_diu_radr[21:5] 17 Out TD read address to DIU. 17 bits wide (256-bitaligned word). diu_td_rack 1 In Acknowledge from DIU that TD readrequest has been accepted and new read address can be placed onte_diu_radr. diu_data[63:0] 64 In Data from DIU to TE. First 64-bits arebits 63:0 of 256 bit word; Second 64-bits are bits 127:64 of 256 bitword; Third 64-bits are bits 191:128 of 256 bit word; Fourth 64-bits arebits 255:192 of 256 bit word. diu_td_rvalid 1 In Signal from DIU tellingTD that valid read data is on the diu_data bus. TFS (Tag FormatStructure) DIU Read Interface signals tfs_diu_rreq 1 Out TFS requestsDRAM read. A read request must be accompanied by a valid read address.tfs_diu_radr[21:5] 17 Out TFS Read address to DIU 17 bits wide (256-bitaligned word). diu_tfs_rack 1 In Acknowledge from DIU that TFS readrequest has been accepted and new read address can be placed ontfs_diu_radr. diu_data[63:0] 64 In Data from DIU to TE. First 64-bitsare bits 63:0 of 256 bit word; Second 64-bits are bits 127:64 of 256 bitword; Third 64-bits are bits 191:128 of 256 bit word; Fourth 64-bits arebits 255:192 of 256 bit word. diu_tfs_rvalid 1 In Signal from DIUtelling TFS that valid read data is on the diu_data bus. TFU Interfacedata and control signals tfu_te_oktowrite 1 In Ready signal indicatingTFU has space available and is ready to be written to. Also assertedfrom the point that the TFU has recieved its expected number of bytesfor a line until the next te_tfu_wradvline te_tfu_wdata[7:0] 8 Out Writedata for TFU. te_tfu_wdatavalid 1 Out Write data valid signal. Thissignal remains high whenever there is valid output data on te_tfu_wdatate_tfu_wradvline 1 Out Advance line signal strobed when the last byte ina line is placed on te_tfu_wdata26.6.5 Configuration Registers

The configuration registers in the TE are programmed via the PCUinterface. Refer to section 21.8.2 on page 321 for the description ofthe protocol and timing diagrams for reading and writing registers inthe TE. Note that since addresses in SoPEC are byte aligned and the PCUonly supports 32-bit register reads and writes the lower 2 bits of thePCU address bus are not required to decode the address space for the TE.Table 176 lists the configuration registers in the TE. Registers whichaddress DRAM are 64-bit DRAM word aligned as this is the case for thePEC1 TE. SoPEC assumes a 256-bit DRAM word size. If the TE can be easilymodified then the DRAM word addressing should be modified to 256-bitword aligned addressing. Otherwise, software should program these the64-bit word aligned addresses on a 256-bit DRAM word boundary. TABLE 176TE Configuration Registers Address TE_base+ register name #bits value onreset description Control registers 0x00 Reset 1 1 A write to thisregister causes a reset of the TE. This register can be read to indicatethe reset state: 0 - reset in progress 1 - reset not in progress 0x04 Go1 0 Writing 1 to this register starts the TE. Writing 0 to this registerhalts the TE. When Go is deasserted the state-machines go to their idlestates but all counters and configuration registers keep their values.When Go is asserted all counters are reset, but configuration registerskeep their values (i.e. they don't get reset). NextBandEnable is clearedwhen Go is asserted. The TFU must be started before the TE is started.This register can be read to determine if the TE is running (1 =running, 0 = stopped). Setup registers (constant for processing of apage) 0x40 TfsStartAdr 19 0 Points to the first word of the (64-bitfirst TFS line in DRAM. aligned DRAM address - should start at a 256-bitaligned location) 0x44 TfsEndAdr 19 0 Points to the first word of the(64-bit last TFS line in DRAM. aligned DRAM address - should start at a256-bit aligned location) 0x48 TfsFirstLineAdr 19 0 Points to the firstword of the (64-bit first TFS line to be aligned encountered on thepage. If DRAM the start of the page is in an address) inter-tag gap,then this value will be the same as TFSStartAdr since the first tag linereached will be the top line of a tag. 0x4C DataRedun 1 0 Defines thedata to redundancy ratio for the Reed Solomon encoder. Symbol size isalways 4 bits, Code- word size is always 15 symbols (60 bits). 0 - 5data symbols (20 bits), 10 redundancy symbols (40 bits) 1 -7 datasymbols (28 bits), 8 redundancy symbols (32 bits) 0x50 Decode2DEn 1 0Determines whether or not the data bits are to be 2D decoded rather thanredundancy encoded (each 2 bits of the data bits becomes 4 output databits). 0 = redundancy encode data 1 = decode each 2 bits of data into 4bits 0x54 VariableData 1 0 Defines whether or not there Present isvariable data in the tags. If there is none, no attempt is made to readtag data, and tag encoding should only reference fixed tag data. 0x58EncodeFixed 1 0 Determines whether or not the lower 40 (or 56) bits offixed data should be encoded into 120 bits or simply used as is. 0x5CTagMaxDotpairs 8 0 The width of a tag in dot- pairs, minus 1. Minimum 0,Maximum = 191. 0x60 TagMaxLine 9 0 The number of lines in a tag,minus 1. Minimum 0, Maximum = 383. 0x64 TagGapDot 14 0 The number of dotpairs between tags in the dot dimension minus 1. Only valid ifTagGapPresent[bit 0] = 1. 0x68 TagGapLine 14 0 Defines the number ofdotlines between tags in the line dimension minus 1. Only valid ifTagGapPresent[bit1] = 1. 0x6C DotPairsPerLine 14 0 Number of output dotpairs to generate per tag line. 0x70 DotStartTagSense 2 0 Determines forthe first/even (bit 0) and second/odd (bit 1) rows of tags whether ornot the first dot position of the line is in a tag. 1 = in a tag, 0 = inan inter-tag gap. 0x74 TagGapPresent 2 0 Bit 0 is 1 if there is aninter- tag gap in the dot dimension, and 0 if tags are tightly packed.Bit 1 is 1 if there is an inter- tag gap in the line dimension, and 0 iftags are tightly packed. 0x78 YScale 8 1 Tag scale factor in Ydirection. Output lines to the TFU will be generated YScale times. 0x80to DotStartPos 2x14 0 Determines for the first/even 0x84 (0) andsecond/odd (1) rows of tags the number of dotpairs remaining minus 1, ineither the tag or inter-tag gap at the start of the line. 0x88 to 0x8CNumTags 2x8  0 Determines for the first/even and second/odd rows of tagshow many tags are present in a line (equals number of tags minus 1).Setup band related registers 0xC0 NextBandStartTagDataAdr Holds thevalue of (64-bit StartTagDataAdr for the next aligned band. This valueis copied to DRAM StartTagDataAdr when address - DoneBand is 1 andshould start at NextBandEnable is 1, or a 256-bit when Go transitionsfrom 0 to aligned location) 1. 0xC4 NextBandEndOfTagData Holds the valueof (64-bit EndOfTagData for the next aligned band. This value is copiedto DRAM EndOfTagData when address) DoneBand is 1 and NextBandEnable is1, or when Go transitions from 0 to 1. 0xC8 NextBandFirstTagLineHeight 90 Holds the value of FirstTagLineHeight for the next band. This value iscopied to FirstTagLineHeight when DoneBand gets is 1 and NextBandEnableis 1, or when Go transitions from 0 to 1. 0xCC NextBandEnable WhenNextBandEnable is 1 and DoneBand is 1, then when te_finishedband is setat the end of a band: NextBandStartTagDataAdr is copied toStartTagDataAdr NextBandEndOfTagData is copied to EndOfTagDataNextBandFirstTagLineHeight is copied to FirstTag LineHeight DoneBand iscleared NextBandEnable is cleared. NextBandEnable is cleared when Go isasserted. Read-only band related registers 0xD0 DoneBand 1 0 Specifieswhether the tag data interface has finished loading all the tag data forthe band. It is cleared to 0 when Go transitions from 0 to 1. When thetag data interface has finished loading all the tag data for the band,the te_finishedband signal is given out and the DoneBand flag is set. IfNextBandEnable is1 at this time then startTagDataAdr, endOfTagData andfirstTaglineHeight are updated with the values for the next band andDoneBand is cleared. Processing of the next band starts immediately. IfNextBandEnable is 0 then the remainder of the TE will continue to run,,while the read control unit waits for NextBandEnable to be set before itrestarts. Read only. 0xD4 StartTagDataAdr 19 0 The start address of the(64-bit current row of raw tag data. aligned This is initially points tothe DRAM first word of the band's tag address - data, which should bealigned should start at to a 128-bit boundary (i.e. the a 256-bit lowerbit of this address aligned location) should be 0). Read only. 0xD8EndOfTagData 19 0 Points to the address of the (64-bit final tag for theband. When aligned all the tag data up to and DRAM including addressaddress) endOfTagData has been read in, the te_finishedband signal isgiven and the doneBand flag is set. Read only. 0xDC FirstTagLineHeight 90 The number of lines minus 1 in the first tag encountered in this band.This will be equal to TagMaxLine if the band starts at a tag boundary.Read only. Work registers (set before starting the TE and must not betouched between bands) 0x100 LineInTag 1 0 Determines whether or not thefirst line of the page is in a line of tags or in an inter-tag gap. 1 -in a tag, 0 - in an inter-tag gap. 0x104 LinePos 14 0 The number oflines remaining minus 1, in either the tag or the inter-tag gap in atthe start of the page. 0x110 to TagData 4x32 0 This 128 bit registermust be 0x11C set up initially with the fixed data record for the page.This is either the lower 40 (or 56) bits (and the encodeFixed registershould be set), or the lower 120 bits (and encodedFixed should beclear). The tagData[0] register contains the lower 32 bits and thetagData[3] register contains the upper 32 bits. This register is usedthroughout the tag encoding process to hold the next tag's variabledata. Work registers (set internally) Read-only from the point of viewof PCU register access 0x140 DotPos 14 0 Defines the number of dotpairsremaining in either the tag or inter-tag gap. Does not need to be setup.0x144 CurrTagPlaneAdr 14 0 The dot-pair number being generated. 0x148DotsInTag 1 0 Determines whether the current dot pair is in a tag or not1 - in a tag, 0 - in an inter-tag gap. 0x14C TagAltSense 1 0 Determineswhether the production of output dots is for the first (and subsequenteven) or second (and subsequent odd) row of tags. 0x154 CurrTFSAdr 19 0Points to the start next line of (64-bit the TFS to be read in. alignedDRAM address) 0x158 ReadsRemaining 4 0 Number of reads remaining in thecurrent burst from the raw tag data interface 0x15C CountX 8 0 Thenumber of tags remaining to be read (minus 1) by the raw tag datainterface for the current line. 0x160 CountY 9 0 The number of times(minus 1) the tag data for the current line of tags needs to be read inby the raw tag data interface. 0x164 RtdTagSense 1 0 Determines whetherthe raw tag data interface is currently reading even rows of tags (=0)or odd rows of tags (=1) with respect to the start of the page. Notethat this can be different from tagAltSense since the raw tag datainterface is reading ahead of the production of dots. 0x168RawTagDataAdr 19 0 The current read address (64-bit within the unencodedraw tag aligned data. DRAM address)

The PCU accessible registers are divided amongst the TE top level andthe TE sub-blocks. This is achieved by including write decoders in thesub-blocks as well as the top level, see FIG. 189. In order to performreads the sub-block registers are fed to the top level where the readdecode is carried out on all the PCU accessible TE registers.

26.6.5.1 Starting the TE and Restarting the TE Between Bands

The TE must be started after the TFU.

For the first band of data, users set up NextBandStartTagDataAdr,NextBandEndTagData and NextBandFirstTagLineHeight as well as other TEconfiguration registers. Users then set the TE's Go bit to startprocessing of the band. When the tag data for the band has finishedbeing decoded, the te_finishedband interrupt will be sent to the PCU andICU indicating that the memory associated with the first band is nowfree. Processing can now start on the next band of tag data.

In order to process the next band NextBandStartTagDataAdr,NextBandEndTagData and NextBandFirstTagLineHeight need to be updatedbefore writing a 1 to NextBandEnable. There are 4 mechanisms forrestarting the TE between bands:

-   a. te_finishedband causes an interrupt to the CPU. The TE will have    set its DoneBand bit. The CPU reprograms the    NextBandStartTagDataAdr, NextBandEndTagData and    NextBandFirstTagLineHeight registers, and sets NextBandEnable to    restart the TE.-   b. The CPU programs the TE's NextBandStartTagDataAdr,    NextBandEndTagData and NextBandFirstTagLineHeight registers and sets    the NextBandEnable flag before the end of the current band. At the    end of the current band the TE sets DoneBand. As NextBandEnable is    already 1, the TE starts processing the next band immediately.-   c. The PCU is programmed so that te_finishedband triggers the PCU to    execute commands from DRAM to reprogram the NextBandStaifTagDataAdr,    NextBandEndTagData and NextBandFirstTagLineHeight registers and set    the NextBandEnable bit to start the TE processing the next band. The    advantage of this scheme is that the CPU could process band headers    in advance and store the band commands in DRAM ready for execution.-   d. This is a combination of b and c above. The PCU (rather than the    CPU in b) programs the TE's NextBandStartTagDataAdr,    NextBandEndTagData and NextBandFirstTagLineHeight registers and sets    the NextBandEnable bit before the end of the current band. At the    end of the current band the TE sets DoneBand and pulses    te_finishedband. As NextBandEnable is already 1, the TE starts    processing the next band immediately. Simultaneously,    te_finishedband triggers the PCU to fetch commands from DRAM. The TE    will have restarted by the time the PCU has fetched commands from    DRAM. The PCU commands program the TE next band shadow registers and    sets the NextBandEnable bit.

After the first tag on the page, all bands have their first tag start atthe top i.e. NextBandFirstTagLineHeight=TagMaxLine. Therefore the samevalue of NextBandFirstTagLineHeight will normally be used for all bands.Certainly, NextBandFirstTagLineHeight should not need to change afterthe second time it is programmed.

26.6.6 TE Top Level FSM

The following diagram illustrates the states in the FSM.

At the highest level, the TE state machine steps through the outputlines of a page one line at a time, with the starting position either inan inter-tag gap (signal dotsintag=0) or in a tag (signals tfsvalid andtdvalid and lineintag=1) (a SoPEC may be only printing part of a tag dueto multiple SoPECs printing a single line).

If the current position is within an inter-tag gap, an output of 0 isgenerated. If the current position is within a tag, the tag formatstructure is used to determine the value of the output dot, using theappropriate encoded data bit from the fixed or variable data buffers asnecessary. The TE then advances along the line of dots, moving throughtags and inter-tag gaps according to the tag placement parameters.

Table 177 highlights the signals used within the FSM. TABLE 177 Signalsused within TE top level FSM Signal Name Function pclk Sync clock usedto register all data within the FSM prst_n, te_reset Reset signalsadvtagline 1 cycles pulse indicating to TDI and TFS sub-blocks to moveonto the next line of Tag data currdotlineadr[13:0] Address counterstarting 2 pclk ahead of currtagplaneadr to generate the correct dotpairfor the current line dotpos Counter to identify how many dotpairs widethe tag/gap is dotsintag Signal identifying whether the dotpair are in atag(1)/gap(0) lineintag_temp Identical to lineintag but generated 1 pclkearlier linepos_shadow Shadow register for linepos due to linepos beingwritten to by 2 different processes talaltsense Flag which alternatesbetween tag/gap lines te_state FSM state variable teplanebuf 6-bit shiftregister used to format dotpairs into a byte for the TFU wradvlineAdvance line signal strobed when the last byte in a line is placed onte_tfu_wdata

Due to the 2 system clock delay in the TFS (both Table A and Table Boutputs are registered) the TE FSM is working 2 system clock cyclesAHEAD of the logic generating the write data for the TFU. As a resultthe following control signals had to be single/double registered on thesystem clock.

The tag_dot_line state can be broken down into 3 different stages.

Stage1:—The state tag_dot_line is entered due to the go signal becomingactive. This state controls the writing of dotbytes to the TFU. As longas the tag line buffer address is not equal to the dotpairsperlineregister value and tfu_te_oktowrite is active, and there is valid TFSand TD available or taggaps, dotpairs are buffered into bytes andwritten to the TFU. The tag line buffer address is used internally butnot supplied to the TFU since the TFU is a FIFO rather than the linestore used in PEC1.

While generating the dotline of a tag/gap line (lineintag flag=1) thedot position counter dotpos is decremented/reloaded (with tagmaxdotpairsor taggapdot) as the TE moves between tags/gaps. The dotsintag flag istoggled between tags/gaps (0 for a gap, 1 for a tag). This patterncontinues until the end of a dotline approaches(currdotlineadr==dotpairsperline).

2 system clock cycles before the end of the dotline the lineintag andtagaltsense signals must be prepared for the next dotline be it in atag/gap dotline or a purely gap dotline.

Stage2:—At this point the end of a dot line is reached so it is time todecrement the linepos counter if still in a tag/gap row or reload thelinepos register, dotpos counter and reprogram the dotsintag flag ifgoing onto another tag/gap or pure gap row. Any signal with the _tempextension means this register is updated a cycle early in order for thereal register to get its correct value while switching between dot linesand tag rows when dotpos and linepos counters reach zero i.e whendotpos=0 the end of a tag/gap has been reached, when linepos=0 the endof a tag row is reached. This stage uses the signals lineintag temp andtagaltsense which were generated one system clock cycle earlier in Stage1.

Stage3:—This stage implements the writing of dotpairs to the correctpart of the 6-bit shift register based on the LSBs of currtagplaneadrand also implements the counter for the currtagplaneadr. Thecurrtagplaneadr is reset on reachingcurrtagplaneadr=(dotpairsperline−1). All the qualifier signals e.gdotsintag for this stage are delayed by 2 system clock cycles i.e. thecurrtagplaneadr (which is the internal write address not needed by theTFU) cannot be incremented until the dotpairs are available which isalways 2 system clock cycles later than when currdotlineadr isincremented.

The wradvline and advtagline pulses are generated using the same logic(currently separated in the PEC1 Tag Encoder VHDL for clarity). Both ofthese pulses used to update further registers hence the reason they donot use the delayed by 2 system clock cycle qualifiers.

26.6.7 Combinational Logic

The TDI is responsible for providing the information data for a tagwhile the TFSI is responsible for deciding whether a particular dot onthe tag should be printed as background pattern or tag information.Every dot within a tag's boundary is either an information dot or partof the background pattern.

The resulting lines of dots are stored in the TFU.

The TFSI reads one Tag Line Structure (TLS) from the DIU for every dotline of tags. Depending on the current printing position within the tag(indicated by the signal tagdotnum), the TFS interface outputs dotinformation for two dots and if necessary the corresponding readaddresses for encoded tag data. The read address are supplied to the TDIwhich outputs the corresponding data values.

These data values (tdi_etd0 and tdi_etd1) are then combined with the dotinformation (tfsi_ta_dot0 and tfsi_ta_dot1) to produce the dot valuesthat will actually be printed on the page (dots), see FIG. 192.

The signal lastdotintag is generated by checking that the dots are in atag (dotsintag=1) and that the dotposition counter dotpos is equal tozero. It is also used by the TFS to load the index address register withzeros at the end of a tag as this is always the starting index whengoing from one tag to the next. lastdotintag is gated with advtagline inthe TFSi (Table C) where adv_tfs_line pulse is used to update the TableC address reg for the new tag line—this is because lastdotintag occurs acycle earlier than adv_tfs_line which would result in the wrong Table Cvalue for the last dotpair. lastdotintag is also used in the TDi FSM(etd_switch state) to pulse the etd_advtag signal hence switchingbuffers in the ETDi for the next tag.

The signal lastdotintag1 is identical to lastdotintag except it iscombinatorially generated (1 cycle earlier than lastdotintag, except atthe end of a tagline). lastdotintag1 signal is only used in the TDi toreset the tdvalid signal on the cycle when dotpos=0. Note theUNSIGNED(currdotlineadr)=UNSIGNED(dotpairsperline)−1 notUNSIGNED(currdotlineadr)=UNSIGNED(dotpairsperline)−2 as in thelastdotintag_gen process as this is an combinatorial process.

The dotposvalid signal is created based on being in a tag line(lineintag1=1), dots being in a tag (dotsintag1=1), having a valid tagformat structure available (tfsvalid1=1) and having encoded tag dataavailable (tdvalid1=1). Note that each of the qualifier signals aredelayed by 1 pclk cycle due to the registering of Table A output datainto Table C where dotposvalid is used. The dotposvalid signal is usedas an enable to load the Table C address register with the next indexinto Table B which in turn provides the 2 addresses to make 2 dotsavailable.

The signal te_tfu_wdatavalid can only be active if in a taggap or ifvalid tag data is available (tdvalid2 and tfsvalid2) and thecurrtagpplaneadr(1:0) equal 11 i.e. a byte of data has been generated bycombining four dotpairs.

The signal tagdotnum tells the TFS how many dotpairs remain in atag/gap. It is calculated by subtracting the value in the dotpos counterfrom the value programmed in the tagmaxdotpairs register.

26.7 Tag Data Interface (TDI)

26.7.1 I/O Specification TABLE 178 TDI Port List signal name I/ODescription Clocks and Resets pclk In SoPEC system clock prst_n InActive-low, synchronous reset in pclk domain. DIU Read Interface Signalsdiu_data[63:0] In Data from DRAM. td_diu_rreq Out Data request to DRAM.td_diu_radr[21:5] Out Read address to DRAM. diu_td_rack In Dataacknowledge from DRAM. diu_td_rvalid In Data valid signal from DRAM. PCUInterface Data, Control Signals and pcu_dataout[31:0] In PCU writes thisdata. pcu_addr[8:2] In PCU accesses this address. pcu_rwn In Globalread/write-not signal from PCU. pcu_te_sel In PCU selects TE for r/waccess. pcu_te_reset In PCU reset. td_te_doneband Out PCU readableregisters. td_te_dataredun td_te_decode2den td_te_variabledatapresenttd_te_encodefixed td_te_numtags0 td_te_numtags1 td_te_starttagdataadrtd_te_rawtagdataadr td_te_endoftagdata td_te_firsttaglineheighttd_te_tagdata0 td_te_tagdata1 td_te_tagdata2 td_te_tagdata3 td_te_countxtd_te_county td_te_rtdtagsense td_te_readsremaining TFS (Tag FormatStructure) tfsi_adr0[8:0] In Read address for dot0 tfsi_adr1[8:0] InRead address for dot1 Bandstore Signals cdu_startofbandstore[24:0] InStart memory area allocated for page bands cdu_endofbandstore[24:0] InLast address of the memory allocated for page bands te_finishedband OutTag encoder band finished26.7.2 Introduction

The tag data interface is responsible for obtaining the raw tag data andencoding it as required by the tag encoder. The smallest typical tagplacement is 2 mm×2 mm, which means a tag is at least 126 1600 dpi dotswide.

In PEC1, in order to keep up with the HCU which processes 2 dots percycle, the tag data interface has been designed to be capable ofencoding a tag in 63 cycles. This is actually accomplished inapproximately 52 cycles within PEC1. For SoPEC the TE need only produceone dot per cycle; it should be able to produce tags in no more thantwice the time taken by the PEC1 TE. Moreover, any change inimplementation from two dots to one dot per cycle should not lose the63/52 cycle performance edge attained in the PEC1 TE.

As shown in FIG. 198, the tag data interface contains a raw tag datainterface FSM that fetches tag data from DRAM, two symbol-at-a-timeGF(2⁴) Reed-Solomon encoders, an encoded data interface and a statemachine for controlling the encoding process. It also contains a tagDataregister that needs to be set up to hold the fixed tag data for thepage.

The type of encoding used depends on the registers TE_encodefixed,TE_dataredun and TE_decode2den the options being,

-   -   (15,5) RS coding, where every 5 input symbols are used to        produce 15 output symbols, so the output is 3 times the size of        the input. This can be performed on fixed and variable tag data.    -   (15,7) RS coding, where every 7 input symbols are used to        produce 15 output symbols, so for the same number of input        symbols, the output is not as large as the (15,5) code (for more        details see section 26.7.6 on page 435). This can be performed        on fixed and variable tag data.    -   2D decoding, where each 2 input bits are used to produce 4        output bits. This can be performed on fixed and variable tag        data.    -   no coding, where the data is simply passed into the Encoded Data        Interface. This can be performed on fixed data only.

Each tag is made up of fixed tag data (i.e. this data is the same foreach tag on the page) and variable tag data (i.e. different for each tagon the page).

Fixed tag data is either stored in DRAM as 120-bits when it is alreadycoded (or no coding is required), 40-bits when (15,5) coding is requiredor 56-bits when (15,7) coding is required. Once the fixed tag data iscoded it is 120-bits long. It is then stored in the Encoded Tag DataInterface. The variable tag data is stored in the DRAM in uncoded form.When (15,5) coding is required, the 120-bits stored in DRAM are encodedinto 360-bits. When (15,7) coding is required, the 112-bits stored inDRAM are encoded into 240-bits. When 2D decoding is required the120-bits stored in DRAM are converted into 240-bits. In each case theencoded bits are stored in the Encoded Tag Data Interface.

The encoded fixed and variable tag data are eventually used to print thetag.

The fixed tag data is loaded in once from the DRAM at the start of apage. It is encoded as necessary and is then stored in one of the8×15-bits registers/RAMs in the Encoded Tag Data Interface. This dataremains unchanged in the registers/RAMs until the next page is ready tobe processed.

The 120-bits of unencoded variable tag data for each tag is stored infour 32-bit words. The TE re-reads the variable tag data, for aparticular tag from DRAM, every time it produces that tag. The variabletag data FIFO which reads from DRAM has enough space to store 4 tags.

26.7.2.1 Bandstore Wrapping

Both TD and TFS storage in DRAM can wrap around the bandstore area. Thebounds of the band store are described by inputs from the CDU shown inTable. The TD and TFS DRAM interfaces therefore support bandstorewrapping. If the TD or TFS DRAM interface increments an address it ischecked to see if it matches the end of bandstore address. If so, thenthe address is mapped to the start of the bandstore.

26.7.3 Data Flow

An overview of the dataflow through the TDI can be seen in FIG. 198below.

The TD interface consists of the following main sections:

-   -   the Raw Tag Data Interface—fetches tag data from DRAM;    -   the tag data register;    -   2 Reed Solomon encoders—each encodes one 4-bit symbol at a time;    -   the Encoded Tag Data Interface—supplies encoded tag data for        output;    -   Two 2D decoders.

The main performance specification for PEC1 is that the TE must be ableto output data at a continuous rate of 2 dots per cycle.

26.7.4 Raw Tag Data Interface

The raw tag data interface (RTDI) provides a simple means of accessingraw tag data in DRAM. The RTDI passes tag data into a FIFO where it canbe subsequently read as required. The 64-bit output from the FIFO can beread directly, with the value of the wr_rd_counter being used toset/reset as the enable signal (rtdAvail). The FIFO is clocked out withreceipt of an rtdRd signal from the TS FSM.

FIG. 199 shows a block diagram of the raw tag data interface.

26.7.4.1 RTDI FSM

The RTDI state machine is responsible for keeping the raw tag FIFO full.The state machine reads the line of tag data once for each printlinethat uses the tag. This means a given line of tag data will be readTagHeight times. Typically this will be 126 times or more, based on anapproximately 2 mm tag. Note that the first line of tag data may be readfewer times since the start of the page may be within a tag. In additionodd and even rows of tags may contain different numbers of tags. Section26.6.5.1 outlines how to start the TE and restart it between bands.Users must set the NextBandStartTagDataAdr, NextBandEndOfTagData,NextBandFirstTagLineHeight and numTags[0], numTags[1] registers beforestarting the TE by asserting Go.

To restart the tag encoder for second and subsequent bands of a page,the NextBandStartTagDataAdr, NextBandEndOfTagData andNextBandFirstTagLineHeight registers need to be updated (typicallynumTags[0] and numTags[1] will be the same if the previous band containsan even number of tag rows) and NextBandEnable set. See Section 26.6.5.1for a full description of the four ways of reprogramming the TE betweenbands.

The tag data is read once for every printline containing tags. Whenmaximally packed, a row of tags contains 163 tags (see Table n page465on page 408).

The RTDI State Flow diagram is shown in FIG. 200. An explanation of thestates follows: idle state:—Stay in the idle state if there is novariable data present. If there is variable data present and there areat least 4 spaces left in the FIFO then request a burst of 2 tags fromthe DRAM (1*256 bits). Counter countx is assigned the number of tags ina even/odd line which depends on the value of register rtdtagsense.Down-counter county is assigned the number of dot lines high a tag willbe (min 126). Initially it must be set the firsttaglineheight value asthe TE may be between pages (i.e. a partial tag). For normal taggeneration county will take the value of tagmaxline register.

diu_access:—The diu_access state will generate a request to the DRAM ifthere are at least 4 spaces in the FIFO. This is indicated by thecounter wr_rd_counter which is incremented/decremented on writes/readsof the FIFO. As long as wr_rd_counter is less than 4 (FIFO is 8 high)there must be 4 locations free. A control signal called td_diu_radrvalidis generated for the duration of the DRAM burst access. Addresses aresent in bursts of 1. The counter burst_count controls this signal, (willinvolve modification to existing TE code.) If there is an odd number oftags in line then the last DRAM read will contain a tag in the first 128bits and padding in the final 128 bits.

fifo_load:—This state controls the addressing to the DRAM. Counterscountx and county are used to monitor whether the TE is processing aline of dots within a row of tags. When countx is zero it means all tagdots for this row are complete. When county is zero it means the TE ison the last line of dots (prior to Y scaling) for this row of tags. Whena row of tags is complete the sense of rtdtagsense is inverted(odd/even). The rawtagdataadr is compared to the te_endoftagdataaddress. If rawtagdataadr=endoftagdata the doneband signal is set, thefinishedband signal is pulsed, and the FSM enters the rtd_stall stateuntil the doneband signal is reset to zero by the PCU by which time therawtagdata, endoftagedata and firsttaglineheight registers are setupwith new values to restart the TE. This state is used to count the64-bit reads from the DIU. Each time diu_td_rvalid is highrtd_data_count is incremented by 1. The compare ofrtd_data_count=rtd_num is necessary to find out when either all 4*64-bitdata has been received or n*64-bit data (depending on a match ofrawtagdataadr=endoftagdata in the middle of a set of 4*64-bit valuesbeing returned by the DIU. rtd_stall:—This state waits for the thedoneband signal to be reset (see page 426 for a description of how thisoccurs). Once reset the FSM returns to the idle state. This states alsoperforms the same count on the diu_data read as above in the case wherediu_td_rvalid has not gone high by the time the addressing is completeand the end of band data has been reached i.e.rawtagdataadr=endoftagdata

26.7.5 TDI State Machine

The tag data state machine has two processing phases. The firstprocessing phase is to encode the fixed tag data stored in the 128-bit(2×64-bit) tag data register. The second is to encode tag data as it isrequired by the tag encoder.

When the Tag Encoder is started up, the fixed tag data is alreadypreloaded in the 128 bit tag data record. If encodeFixed is set, thenthe 2 codewords stored in the lower bits of the tag data record need tobe encoded: 40 bits if dataRedun=0, and 56 bits if dataRedun=1. IfencodeFixed is clear, then the lower 120 bits of the tag data recordmust be passed to the encoded tag data interface without being encoded.

When encodeFixed is set, the symbols derived from codeword 0 are writtento codeword 6 and the symbols derived from codeword 1 are written tocodeword 7. The data symbols are stored first and then the remainingredundancy symbols are stored afterwards, for a total of 15 symbols.Thus, when dataRedun=0, the 5 symbols derived from bits 0-19 are writtento symbols 0-4, and the redundancy symbols are written to symbols 5-14.When dataRedun=1, the 7 symbols derived from bits 0-27 are written tosymbols 0-6, and the redundancy symbols are written to symbols 7-14.

When encodeFixed is clear, the 120 bits of fixed data is copied directlyto codewords 6 and 7. The TDI State Flow diagram is shown in FIG. 202.An explanation of the states follows.

idle:—In the idle state wait for the tag encoder go signal—top_go=1. Thefirst task is to either store or encode the Fixed data. Once the Fixeddata is stored or encoded/stored the donefixed flag is set. If there isno variable data the FSM returns to the idle state hence the reason tocheck the donefixed flag before advancing i.e. only store/encode thefixed data once.

fixed_data:—In the fixed_data state the FSM must decode whether todirectly store the fixed data in the ETDi or if the fixed data needs tobe either (15:5) (40-bits) or (15:7) (56-bits) RS encoded or 2D decoded.The values stored in registers encodefixed and dataredun and decode2dendetermine what the next state should be.

bypass to etdi:—The bypass_to_etdi takes 120-bits of fixeddata(pre-encoded) from the tag_data(127:0) register and stores it in the15*8 (by 2 for simultaneous reads) buffers. The data is passed from thetag data register through 3 levels of muxing (level1, level2, level3)where it enters the RS0/RS1 encoders (which are now in a straightthrough mode (i.e. control_(—)5 and control_(—)7 are zero hence the datapasses straight from the input to the output). The MSBs of theetd_wr_adr must be high to store this data as codewords 6,7.

etd_buf_switch:—This state is used to set the tdvalid signal and pulsethe etd_adv_tag signal which in turn is used to switch the read writesense of the ETDi buffers (wrsb0). The firsttime signal is used toidentify the first time a tag is encoded. If zero it means read the tagdata from the RTDi FIFO and encode. Once encoded and stored the FSMreturns to this state where it evaluates the sense of tdvalid. Firsttime around it will be zero so this sets tdvalid and returns to thereadtagdata state to fill the 2nd ETDi buffer. After this the FSMreturns to this state and waits for the lastdotintag signal to arrive.In between tags when the lastdotingtag signal is received theetd_adv_tag is pulsed and the FSM goes to the readtagdata state. Howeverif the lastdotintag signal arrives at the end of a line there is anextra 1 cycle delay introduced in generating the etd_adv_tag pulse (viaetd_adv_tag_endofline) due to the pipelining in the TFS. This allows allthe previous tag to be read from the correct buffer and seamlesstransfer to the other buffer for the next line.

readtagdata:—The readtagdata state waits to receive a rtdavail signalfrom the raw tag data interface which indicates there is raw tag dataavailable. The tag_data register is 128-bits so it takes 2 pulses of thertdrd signal to get the 2*64-bits into the tag_data register. If thertdavail signal is set rtdrd is pulsed for 1 cycle and the FSM stepsonto the loadtagdata state. Initially the flag first64 bits will bezero. The 64-bits of rtd are assigned to the tag_data[63:0] and the flagfirst64 bits is set to indicate the first raw tag data read is complete.The FSM then steps back to the read_tagdata state where it generates thesecond rtdrd pulse. The FSM then steps onto the loadtagdata state forwhere the second 64-bits of rawtag data are assigned totag_data[128:64]. loadtagdata:—The loadtagdata state writes the raw tagdata into the tag_data register from the RTDi FIFO. The first64 bitsflag is reset to zero as the tag_data register now contains 120/112 bitsof variable data. A decode of whether to (15:5) or (15:7) RS encode or2D decode this data decides the next state.

rs_(—)15_(—)5:—The rs_(—)15_(—)5 (Reed Solomon (15:5) mode) state eitherencodes 40-bit Fixed data or 120-bit Variable data and provides theencoded tag data write address and write enable (etd_wr_adr and etdwerespectively). Once the fixed tag data is encoded the donefixed flag isset as this only needs to be done once per page. The variabledatapresentregister is then polled to see if there is variable data in the tags. Ifthere is variable data present then this data must be read from the RTDiand loaded into the tag_data register. Else the tdvalid flag must be setand FSM returns to the idle state. control_(—)5 is a control bit for theRS Encoder and controls feedforward and feedback muxes that enable(15:5) encoding.

The rs_(—)15_(—)5 state also generates the control signals for passing120-bits of variable tag data to the RS encoder in 4-bit symbols perclock cycle. rs_counter is used both to control the level1_mux and actas the 15-cycle counter of the RS Encoder. This logic cycles for a totalof 3*15 cycles to encode the 120-bits.

rs_(—)15_(—)7:—The rs_(—)15_(—)7 state is similar to the rs_(—)15_(—)5state except the level1_mux has to select 7 4-bit symbols instead of 5.

decode_(—)2d 15_(—)5, decode_(—)2d_(—)15_(—)7:—The decode_(—)2d statesprovides the control signals for passing the 120-bit variable data tothe 2D decoder. The 2 lsbs are decoded to create 4 bits. The 4 bits fromeach decoder are combined and stored in the ETDi. Next the 2 MSBs aredecoded to create 4 bits. Again the 4 bits from each decoder arecombined and stored in the ETDi.

As can be seen from Figure n page 488 on page Error! Bookmark notdefined. there are 3 stages of muxing between the Tag Data register andthe RS encoders or 2D decoders. Levels 1-2 are controlled by level1_muxand level2_mux which are generated within the TDi FSM as is the writeaddress to the ETDi buffers (etd_wr_adr)

FIGS. 203 through 208 illustrate the mappings used to store the encodedfixed and variable tag data in the ETDI buffers.

26.7.6 Reed Solomon (RS) Encoder

26.7.7 Introduction

A Reed Solomon code is a non binary, block code. If a symbol consists ofm bits then there are q=2^(m) possible symbols defining the codealphabet. In the TE, m=4 so the number of possible symbols is q=16.

An (n,k) RS code is a block code with k information symbols and ncode-word symbols. RS codes have the property that the code word n islimited to at most q+1 symbols in length.

In the case of the TE, both (15,5) and (15,7) RS codes can be used. Thismeans that up to 5 and 4 symbols respectively can be corrected.

Only one type of RS coder is used at any particular time. The RS coderto be used is determined by the registers TE_dataredun andTE_decode2den:

-   -   TE_dataredun=0 and TE_decode2den=0, then use the (15,5) RS coder    -   TE_dataredun=1 and TE_decode2den=0, then use the (15,7) RS coder

For a (15,k) RS code with m=4, k 4-bit information symbols applied tothe coder produce 15 4-bit codeword symbols at the output. In the TE,the code is systematic so the first k codeword symbols are the same theas the k input information symbols.

A simple block diagram can be seen in.

26.7.8 I/O Specification

A I/O diagram of the RS encoder can be seen in.

26.7.9 Proposed Implementation

In the case of the TE, (15,5) and (15,7) codes are to be used with4-bits per symbol.

The primitive polynomial is p(x)=x⁴x+x+1

In the case of the (15,5) code, this gives a generator polynomial ofg(x)=(x+a)(x+a ²)(x+a ³)(x+a ⁴)(x+a ⁵)(x+a ⁶)(x+a ⁷)(x+a ⁸)(x+a ⁹)(x+a¹⁰)g(x)=x ¹⁰ +a ² x ⁹ +a ³ x ⁸ +a ⁹ x ⁷ +a ⁶ x ⁶ +a ¹⁴ x ⁵ +a ² x ⁴ +ax ³+a ⁶ x ² +ax+a ¹⁰g(x)=x ¹⁰ +g ₉ x ⁹ +g ₈ x ⁸ +g ₇ x ⁷ +g ₆ x ⁶ +g ₅ x ⁵ +g ₄ x ⁴ +g ₃ x ³+g ₂ x ² +g ₁ x+g ₀

In the case of the (15,7) code, this gives a generator polynomial ofh(x)=(x+a)(x+a ²)(x+a ³)(x+a ⁴)(x+a ⁵)(x+a ⁶)(x+a ⁷)(x+a ⁸)h(x)=x ⁸ +a ¹⁴ x ⁷ +a ² x ⁶ +a ⁴ x ⁵ +a ² x ⁴ +a ¹³ x ³ +a ⁵ x ² +a ¹¹x+a ⁶h(x)=x ⁸ +h ₇ x ⁷ +h ₆ x ⁶ +h ₅ x ⁵ +h ₄ x ⁴ +h ₃ x ³ +h ₂ x ² +h ₁ x+h₀

The output code words are produced by dividing the generator polynomialinto a polynomial made up from the input symbols.

This division is accomplished using the circuit shown in FIG. 211.

The data in the circuit are Galois Field elements so addition andmultiplication are performed using special circuitry. These areexplained in the next sections.

The RS coder can operate either in (15,5) or (15,7) mode. The selectionis made by the registers TE_dataredun and TE_decode2den.

When operating in (15,5) mode control_(—)7 is always zero and whenoperating in (15,7) mode control_(—)5 is always zero.

Firstly consider (15,5) mode i.e. TE_dataredun is set to zero.

For each new set of 5 input symbols, processing is as follows:

The 4-bits of the first symbol d₀ are fed to the input portrs_data_in(3:0) and control_(—)5 is set to 0. mux2 is set so as to usethe output as feedback. control_(—)5 is zero so mux4 selects the input(rs_data_in) as the output (rs_data_out). Once the data has settled (<<1cycle), the shift registers are clocked. The next symbol d₁ is thenapplied to the input, and again after the data has settled the shiftregisters are clocked again. This is repeated for the next 3 symbols d₂,d₃ and d₄. As a result, the first 5 outputs are the same as the inputs.After 5 cycles, the shift registers now contain the next 10 requiredoutputs. control_(—)5 is set to 1 for the next 10 cycles so that zerosare fed back by mux2 and the shift register values are fed to the outputby mux3 and mux4 by simply clocking the registers.

A timing diagram is shown below.

Secondly consider (15,7) mode i.e. TE_dataredun is set to one.

In this case processing is similar to above except that control_(—)7stays low while 7 symbols (d₀, d₁ . . . d₆) are fed in. As well as beingfed back into the circuit, these symbols are fed to the output.

After these 7 cycles, control_(—)7 is set to 1 and the contents of theshift registers are fed to the output.

A timing diagram is shown below.

The enable signal can be used to start/reset the counter and the shiftregisters.

The RS encoders can be designed so that encoding starts on a risingenable edge. After 15 symbols have been output, the encoder stops untila rising enable edge is detected. As a result there will be a delaybetween each codeword.

Alternatively, once the enable goes high the shift registers are resetand encoding will proceed until it is told to stop. rs_data_in must besupplied at the correct time. Using this method, data can becontinuously output at a rate of 1 symbol per cycle, even over a fewcodewords.

Alternatively, the RS encoder can request data as it requires.

The performance criterion that must be met is that the following must becarried out within 63 cycles

-   -   load one tag's raw data into TE_tagdata    -   encode the raw tag data    -   store the encoded tag data in the Encoded Tag Data Interface

In the case of the raw fixed tag data at the start of a page, there isno definite performance criterion except that it should be encoded andstored as fast as possible.

26.7.10 Galois Field Elements and Their Representation

A Galois Field is a set of elements in which we can do addition,subtraction, multiplication and division without leaving the set.

The TE uses RS encoding over the Galois Field GF(2⁴). There are 2⁴elements in GF(2⁴) and they are generated using the primitive polynomialp(x)=x⁴+x+1.

The 16 elements of GF(2⁴) can be represented in a number of differentways. Table 179 shows three possible representations—the power,polynomial and 4-tuple representation. TABLE 179 GF(2⁴) representations4-tuple power Polynomial representation representation Representation(a0 a1 a2 a3) 0 0 (0 0 0 0) 1 1 (1 0 0 0) A x (0 1 0 0) α²

(0 0 1 0) α³ x³ (0 0 0 1) α⁴ 1 + x (1 1 0 0) α⁵ x + x² (0 1 1 0) a⁶ x² +x³ (0 0 1 1) α⁷ 1 + x

+ x³ (1 1 0 1) α⁸ 1 + x² (1 0 1 0) α⁹ x

+ x³ (0 1 0 1) α¹⁰ 1 + x + x² (1 1 1 0) α¹¹ x + x² + x³ (0 1 1 1) α¹²1 + x + x² + x³ (1 1 1 1) α¹³ 1 + x² + x³ (1 0 1 1) α¹⁴ 1 + x³ (1 0 0 1)26.7.11 Multiplication of GF(2⁴) Elements

The multiplication of two field elements α^(a) and α^(b) is defined as

-   -   α¹=α^(a).α^(b)=α^((a+b)modulo 15)        Thus        α¹.α²=α³        α⁵.α¹⁰=α¹⁵        α⁶.α¹²=α³

So if we have the elements in exponential form, multiplication is simplya matter of modulo 15 addition.

If the elements are in polynomial/tuple form, the polynomials must bemultiplied and reduced mod x⁴+x+1.

Suppose we wish to multiply the two field elements in GF(2⁴):α^(a) =a ₃ x ³ +a ₂ x ² +a ₁ x ¹ +a ₀α^(b) =b ₃ x ³ +b ₂ x ² +b ₁ x ¹ +b ₀

-   -   where a₁, b_(i) are in the field (0,1) (i.e. modulo 2        arithmetic)

Multiplying these out and using x⁴+x+1=0 we get:α^(a + b) = [(a₀b₃ + a₁b₂ + a₂b₁ + a₃b₀) + a₃b₃]x³+  [(a₀b₂ + a₁b₁ + a₂b₀) + a₃b₃ + (a₃b₂ + a₂b₃)]x²+  [(a₀b₁ + a₁b₀) + (a₃b₂ + a₂b₃) + (a₁b₃ + a₂b₂ + a₃b₁)]x+  [(a₀b₀ + a₁b₃ + a₂b₂ + a₃b₁)]α^(a + b) = [a₀b₃ + a₁b₂ + a₂b₁ + a₃(b₀ + b₃)]x³+  [a₀b₂ + a₁b₁ + a₂(b₀ + b₃) + a₃(b₂ + b₃)]x²+  [a₀b₁ + a₁(b₀ + b₃) + a₂(b₂ + b₃) + a₃(b₁ + b₂)]x+  [(a₀b₀ + a₁b₃ + a₂b₂ + a₃b₁)]

If we wish to multiply an arbitrary field element by a fixed fieldelement we get a more simple form. Suppose we wish to multiply α^(b) byα³.

In this case α³=x³ so (a0 a1 a2 a3)=(0001). Substituting this into theabove equation givesα^(c)=(b ₀ +b ₃)x ³+(b ₂ +b ₃)x ²+(b ₁ +b ₂)x+b ₁

This can be implemented using simple XOR gates as shown in FIG. 214

26.7.12 Addition of GF(2⁴) Elements

If the elements are in their polynomial/tuple form, polynomials aresimply added.

Suppose we wish to add the two field elements in GF(2⁴):α⁸ =a ₃ x ³ +a ₂ x ² +a ₁ x+a ₀α^(b) =b ₃ x ³ +b ₂ z ² +b ₁ x+b ₀

-   -   where a_(i), b_(i) are in the field (0,1) (i.e. modulo 2        arithmetic)        α^(c)=α^(a)+α^(b)=(a ₃ +b ₃)x ³+(a ₂ +b ₂)x2+(a ₁ +b ₁)x+(a ₀ +b        ₀)

Again this can be implemented using simple XOR gates as shown in FIG.215

26.7.13 Reed Solomon Implementation

The designer can decide to create the relevant addition andmultiplication circuits and instantiate them where necessary.Alternatively the feedback multiplications can be combined as follows.Consider the multiplicationα^(a).α^(b)=α^(c)

-   -   or in terms of polynomials        (a ₃ x ³ +a ₂ x ² +a ₁ x+a ₀).(b ₃ x ³ +b ₂ x ² +b ₁ x+b ₀)=(c ₃        x ³ +c ₂ x ² +c ₁ x+c ₀)

If we substitute all of the possible field elements in for α^(a) andexpress α^(c) in terms of α^(b), we get the table of results shown inTable 180. TABLE 180 α^(c) multiplied by all field elements, expressedin terms of α^(b) αa = a3x3 + a2x2 + a1x + a0 fixed field c3x3 + c2x2 +c1x + c0 element (a0 a1 a2 a3) c0 c1 c2 c3 0 (0 0 0 0) 1 (1 0 0 0) b₀ b₁b₂ b₃ a (0 1 0 0) b₃ b₀ + b₃ b₁ b₂ α² (0 0 1 0) b₂ b₂ + b₃ b₀ + b₃ b₁ α³(0 0 0 1) b₁ b₁ + b₂ b₂ + b₃ b₀ + b₃ α⁴ (1 1 0 0) b₀ + b₃ b₀ + b₁ + b₃b₁ + b₂ b₂ + b₃ α⁵ (0 1 1 0) b₂ + b₃ b₀ + b₂ b₀ + b₁ + b₃ b₁ + b₂ a⁶ (00 1 1) b₁ + b₂ b₁ + b₃ b₀ + b₂ b₀ + b₁ + b₃ α⁷ (1 1 0 1) b₀ + b₁ + b₃b₀ + b₂ + b₃ b₁ + b₃ b₀ + b₂ α⁸ (1 0 1 0) b₀ + b₂ b₁ + b₂ + b₃ b₀ + b₂ +b₃ b₁ + b₃ α⁹ (0 1 0 1) b₁ + b₃ b₀ + b₁ + b₂ + b₃ b₁ + b₂ + b₃ b₀ + b₂ +b₃ α¹⁰ (1 1 1 0) b₀ + b₂ + b₃ b₀ + b₁ + b₂ b₀ + b₁ + b₂ + b₃ b₁ + b₂ +b₃ α¹¹ (0 1 1 1) b₁ + b₂ + b₃ b₀ + b₁ b₀ + b₁ + b₂ b₀ + b₁ + b₂ + b₃ α¹²(1 1 1 1) b₀ + b₁ + b₂ + b₃ b₀ b₀ + b₁ b₀ + b₁ + b₂ α¹³ (1 0 1 1) b₀ +b₁ + b₂ b₃ b₀ b₀ + b₁ α¹⁴ (1 0 0 1) b₀ + b₁ b₂ b₃ b₀the following signals are required:

-   -   b₀, b₁, b₂, b₃,    -   (b₀+b₁), (b₀+b₂), (b₀+b₃), (b₁+b₂), (b₁+b₃), (b₂+b₃),    -   (b₀+b₁+b₂), (b₀+b₁+b₃), (b₀+b₂+b₃), (b₁+b₂+b₃),    -   (b₀+b₁+b₂+b₃)

The implementation of the circuit can be seen in Figure. The maincomponents are XOR gates, 4-bit shift registers and multiplexers.

The RS encoder has 4 input lines labelled 0, 1, 2 & 3 and 4 output lineslabelled 0, 1, 2 & 3. This labelling corresponds to the subscripts ofthe polynomial/4-tuple representation. The mapping of 4-bit symbols fromthe TE tagdata register into the RS is as follows:

-   -   the LSB in the TE_tagdata is fed into line0    -   the next most significant LSB is fed into line1    -   the next most significant LSB is fed into line2    -   the MSB is fed into line3

The RS output mapping to the Encoded tag data interface is similiar. Twoencoded symbols are stored in an 8-bit address. Within these 8 bits:

-   -   line0 is fed into the LSB (bit 0/4)    -   line1 is fed into the next most significant LSB (bit 1/5)    -   line2 is fed into the next most significant LSB (bit 2/6)    -   line3 is fed into the MSB (bit 3/7)        267.14 2D Decoder

The 2D decoder is selected when TE_decode2den=1. It operates on variabletag data only. its function is to convert 2-bits into 4-bits accordingto Table 181. TABLE 181 Operation of 2D decoder input output 0 0 0 0 0 10 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 026.7.15 Encoded Tag Data Interface

The encoded tag data interface contains an encoded fixed tag data storeinterface and an encoded variable tag data store interface, as shown inFIG. 217.

The two reord units simply reorder the 9 input bits to map low-ordercodewords into the bit selection component of the address as shown inTable 182. Reordering of write addresses is not necessary since theaddresses are already in the correct format. TABLE 182 Reord unit inputoutput bit# bit interpretation bit interpretation 8 A select 1 of 8codewords A select 1 of 4 codeword tables 7 B B 6 C D select 1 of 15symbols 5 D select 1 of 15 symbols E 4 E F 3 F G 2 G C select 1 of 8bits 1 H select 1 of 4 bits H 0 I I

The encoded fixed data interface is a single 15×8-bit RAM with 2 readports and 1 write port. As it is only written to during page setup time(it is fixed for the duration of a page) there is no need forsimultaneous read/write access. However the fixed data store must becapable of decoding two simultaneous reads in a single cycle. FIG. 218shows the implementation of the fixed data store.

The encoded variable tag data interface is a double buffered 3×15×8-bitRAM with 2 read ports and 1 write port. The double buffering allows onetag's data to be read (two reads in a single cycle) while the next tag'svariable data is being stored. Write addressing is 6 bits: 2 bits ofaddress for selecting 1 of 3, and 4 bits of address for selecting 1 of15. Read addressing is the same with the addition of 3 more address bitsfor selecting 1 of 8.

FIG. 219 shows the implementation of the encoded variable tag datastore. Double buffering is implemented via two sub-buffers. Each time anAdvTag pulse is received, the sense of which sub-buffer is being readfrom or written to changes. This is accomplished by a 1-bit flag calledwrsb0. Although the initial state of wrsb0 is irrelevant, it must invertupon receipt of an AdvTag pulse. The structure of each sub-buffer isshown in FIG. 220.

26.8 Tag Format Structure (TFS) Interface

26.8.1 Introduction

The TFS specifies the contents of every dot position within a tagsborder i.e.:

-   -   is the dot part of the background?    -   is the dot part of the data?

The TFS is broken up into Tag Line Structures (TLS) which specify thecontents of every dot position in a particular line of a tag. Each TLSconsists of three tables—A, B and C (see FIG. 221).

For a given line of dots, all the tags on that line correspond to thesame tag line structure.

Consequently, for a given line of output dots, a single tag linestructure is required, and not the entire TFS. Double buffering allowsthe next tag line structure to be fetched from the TFS in DRAM while theexisting tag line structure is used to render the current tag line.

The TFS interface is responsible for loading the appropriate line of thetag format structure as the tag encoder advances through the page. It isalso responsible for producing table A and table B outputs for twoconsecutive dot positions in the current tag line.

-   -   There is a TLS for every dot line of a tag.    -   All tags that are on the same line have the exact same TLS.    -   A tag can be up to 384 dots wide, so each of these 384 dots must        be specified in the TLS.    -   The TLS information is stored in DRAM and one TLS must be read        into the TFS Interface for each line of dots that are outputted        to the Tag Plane Line Buffers.    -   Each TLS is read from DRAM as 5 times 256-bit words with 214        padded bits in the last 256-bit DRAM read.

26.8.2 I/O Specification TABLE 183 Tag Format Structure Interface PortList signal name signal type description Pclk In SoPEC system clockprst_n In Active-low, synchronous reset in pclk domain top_go In Gosignal from TE top level DRAM diu_data[63:0] In Data from DRAMdiu_tfs_rack In Data acknowledge from DRAM diu_tfs_rvalid In Data validfrom DRAM tfs_diu_rreq Out Read request to DRAM tfs_diu_radr[21:5] OutRead address to DRAM tag encoder top level top_advtagline In Pulsedafter the last line of a row of tags top_tagaltsense In For even tagrows = 0 i.e. 0, 2, 4 . . For odd tag rows = 1 i.e. 1, 3, 5 . . .top_lastdotintag In Last dot in tag is currently being processedtop_dotposvalid In Current dot position is a tag dot and its structuredata and tag data is available top_tagdotnum[7:0] In Counts from zero upto TE_tagmaxdotpairs (min. = 1, max. = 192) tfsi_valid Out TLS tables A,B and C, ready for use tfsi_ta_dot0[1:0] Out Even entry from Table Acorresponding to top_tagdotnum tfsi_ta_dot1[1:0] Out Odd entry fromTable A corresponding to top_tagdotnum tag encoder top level (PCU readdecoder) tfs_te_tfsstartadr[23:0] Out TFS tfsstartadr registertfs_te_tfsendadr[23:0] Out TFS tfsendadr registertfs_te_tfsfirstlineadr[23:0] Out TFS tfsfirstlineadr registertfs_te_currtfsadr[23:0] Out TFS currtfsadr register TDItfsi_tdi_adr0[8:0] Out Read address for dot0 (even dot)tfsi_tdi_adr1[8:0] Out Read address for dot1 (odd dot)26.8.2.1 State Machine

The state machine is responsible for generating control signals for thevarious TFS table units, and to load the appropriate line from the TFS.The states are explained below.

idle:—Wait for top_go to become active. Pulse adv_tfs_line for 1 cycleto reset tawradr and tbwradr registers. Pulsing adv_tfs_line will switchthe read/write sense of Table B so switching Table A here as well tokeep things the same i.e. wrta0=NOT(wrta0).

diu_access:—In the diu_access state a request is sent to the DIU. Oncean ack signal is received Table A write enable is asserted and the FSMmoves to the tls_load state.

tls_load:—The DRAM access is a burst of 5 256-bit accesses, ultimatelyreturned by the DIU as 5*(4*64 bit) words. There will be 192 padded bitsin the last 256-bit DRAM word. The first 12 64-bit words reads are forTable A, words 12 to 15 and some of 16 are for Table B while part ofread 16 data is for Table C. The counter read_num is used to identifywhich data goes to which table. The table B data is stored temporarilyin a 288-bit register until the tls_update state hence tbwe does notbecome active until read_num=16).

-   -   The DIU data goes directly into Table A (12*64).    -   The DIU data for Table B is loaded into a 288-bit register.    -   The DIU data goes directly into Table C.

tls_update:—The 288-bits in Table B need to written to a 32*9 buffer.The tls_update state takes care of this using the read_num counter.

tls_next—This state checks the logic level of tfsvalid and switches theread/write senses of Table A (wrta0) and Table B a cycle later (usingthe adv_tfs_line pulse). The reason for switching Table A a cycle earlyis to make sure the top_level address via tagdotnum is pointing to thecorrect buffer. Keep in mind the top_level is working a cycle ahead ofTable A and 2 cycles ahead of Table B.

If tfsValid is 1, the state machine waits until the advTagLine signal isreceived. When it is received, the state machine pulses advTFSLine (toswitch read/write sense in tables A, B, C), and starts reading the nextline of the TFS from currTFSAdr.

If tfsValid is 0, the state machine pulses advTFSLine (to switchread/write sense in tables A, B, C) and then jumps to thetls_tfsvalid_set state where the signal tfsValid is set to 1 (allowingthe tag encoder to start, or to continue if it had been stalled). Thestate machine can then start reading the next line of the TFS fromcurrTFSAdr.

tls_tfsvalid_next:—Simply sets the tfsvalid signal and returns the FSMto the diu_access state.

If an advTagLine signal is received before the next line of the TFS hasbeen read in, tfsValid is cleared to 0 and processing continues asoutlined above.

26.8.2.2 Bandstore Wrapping

Both TD and TFS storage in DRAM can wrap around the bandstore area. Thebounds of the band store are described by inputs from the CDU shown inTable. The TD and TFS DRAM interfaces therefore support bandstorewrapping. If the TD or TFS DRAM interface increments an address it ischecked to see if it matches the end of bandstore address. If so, thenthe address is mapped to the start of the bandstore.

The TFS state flow diagram is shown in below.

26.8.3 Generating a Tag From Tables A, B and C

The TFS contains an entry for each dot position within the tag'sbounding box. Each entry specifies whether the dot is part of theconstant background pattern or part of the tag's data component (bothfixed and variable).

The TFS therefore has TagHeight×TagWidth entries, where TagHeight is theheight of the tag in dot-lines and TagWidth is the width of the tag indots. The TFS entries that specify a single dot-line of a tag are knownas a Tag Line Structure.

The TFS contains a TLS for each of the 1600 dpi lines in the tag'sbounding box. Each TLS contains three contiguous tables, known as tablesA, B and C.

Table A contains 384 2-bit entries i.e. one entry for each dot in asingle line of a tag up to the maximum width of a tag. The actual numberof entries used should match the size of the bounding box for the tag inthe dot dimension, but all 384 entries must be present.

Table B contains 32 9-bit data address that refer to (in order ofappearance) the data dots present in the particular line. Again, all 32entries must be present, even if fewer are used.

Table C contains two 5-bit pointers into table B and is followed by 22unused bits. The total length of each TLS is therefore 34 32-bit words.

Each output dot value is generated as follows: Each entry in Table Aconsists of 2-bits-bit0 and bit1. These 2-bits are interpreted accordingto Table 184, Table 185 and Table 186. TABLE 184 Interpretation of bit0from entry in Table A bit 0 interpretation 0 the output bit comesdirectly from bit1 (see Table). 1 the output bit comes from a data bit.Bit1 is used in conjunction with Tag Line Structure Table B to determinewhich data bit will be output.

TABLE 185 Interpretation of bit1 from entry in table A when bit0 = 0 bit1 interpretation 0 output 0 1 output 1

TABLE 186 Interpretation of bit1 from entry in table A when bit0 = 1 bit1 interpretation 0 output data bit pointed to by current index intoTable B. 1 output data bit pointed to by current index into Table B, andadvance index by 1.

If bit0=0 then the output dot for this entry is part of the constantbackground pattern. The dot value itself comes from bit1 i.e. if bit1=0then the output is 0 and if bit1=1 then the output is 1. If bit0=1 thenthe output dot for this entry comes from the variable or fixed tag data.Bit1 is used in conjunction with Tables B and C to determine data bitsto use.

To understand the interpretation of bit1 when bit0=1 we need to knowwhat is stored in Table B. Table B contains the addresses of all thedata bits that are used in the particular line of a tag in order ofappearance. Therefore, up to 32 different data bits can appear in a lineof a tag. The address of the first data dot in a tag will be given bythe address stored in entry 0 of Table B. As we advance along thevarious data dots we will advance through the various Table B entries.Each Table B entry is 9-bits long and each points to a specific variableor fixed data bit for the tag. Each tag contains a maximum of 120 fixedand 360 variable data bits, for a total of 480 data bits. To aid addressdecoding, the addresses are based on the RS encoded tag data. Tablelists the interpretation of the 9-bit addresses. TABLE 187Interpretation of 9-bit tag data address in Table B bit pos namedescription 8 CodeWordSelect Select 1 of 8 codewords. Codewords 0, 1, 2,3, 4, 5 are variable data. Codewords 6, 7 are fixed data. 7 6 5SymbolSelect Select 1 of 15 symbols (1111 invalid) 4 3 2 1 BitSelectSelect 1 of 4 bits from the selected symbols 0

If the fixed data is supplied to the TE in an unencoded form, thesymbols derived from codeword 0 of fixed data are written to codeword 6and the symbols derived from fixed data codeword 1 are written tocodeword 7. The data symbols are stored first and then the remainingredundancy symbols are stored afterwards, for a total of 15 symbols.Thus, when 5 data symbols are used, the 5 symbols derived from bits 0-19are written to symbols 0-4, and the redundancy symbols are written tosymbols 5-14. When 7 data symbols are used, the 7 symbols derived frombits 0-27 are written to symbols 0-6, and the redundancy symbols arewritten to symbols 7-14

However, if the fixed data is supplied to the TE in a pre-encoded form,the encoding could theoretically be anything. Consequently the 120 bitsof fixed data is copied to codewords 6 and 7 as shown in Table 188.TABLE 188 Mapping of fixed data to codeword/symbols when no redundancyencoding output symbol output input bits range codeword  0-19 0-4 620-39 0-4 7 40-59 5-9 6 60-79 5-9 7 80-99 10-14 6 100-119 10-14 7

It is important to note that the interpretation of bit1 from Table A(when bit0-1) is relative. A 5-bit index is used to cycle through thedata address in Table B. Since the first tag on a particular line may ormay not start at the first dot in the tag, an initial value for theindex into Table B is needed. Subsequent tags on the same line willalways start with an index of 0, and any partial tag at the end of aline will simply finish before the entire tag has been rendered. Theinitial index required due to the rendering of a partial tag at thestart of a line is supplied by Table C. The initial index will bedifferent for each TLS and there are two possible initial indexes sincethere are effectively two types of rows of tags in terms of initialoffsets.

Table C provides the appropriate start index into Table B (2 5-bitindices). When rendering even rows of tags, entry 0 is used as theinitial index into Table B, and when rendering odd rows of tags, entry 1is used as the initial index into Table B. The second and subsequenttags start at the left most dots position within the tag, so can use aninitial index of 0.

26.8.4 Architecture

A block diagram of the Tag Format Structure Interface can be seen inFIG. 223.

26.8.4.1 Table A Interface

The implementation of table A is two 16×64-bit RAMs with a small amountof control logic, as shown in FIG. 224. While one RAM is read from forthe current line's table A data (4 bits representing 2 contiguous tableA entries), the other RAM is being written to with the next line's tableA data (64-bits at a time).

Note:—The Table A data to be printed (if each LSB=0) must be passed tothe top_level 2 cycles after the read of Table A due to the 2-stagepipelining in the TFS from registering Table A and Table B outputs hencethis extra registering stage for the generation of ta_dot0_(—)1cyclelater and ta_dot1_(—)1 cyclelater.

Each time an AdvTFSLine pulse is received, the sense of which RAM isbeing read from or written to changes. This is accomplished by a 1-bitflag called wrta0. Although the initial state of wrta0 is irrelevant, itmust invert upon receipt of an AdvTFSLine pulse. A 4-bit counter calledtaWrAdr keeps the write address for the 12 writes that occur after thestart of each line (specified by the AdvTFSLine control input). The tawe(table A write enable) input is set whenever the data in is to bewritten to table A. The taWrAdr address counter automatically incrementswith each write to table A. Address generation for tawe and taWrAdr isshown in Table 189.

26.8.4.2 Table C Interface

A block diagram of the table C interface is shown below in FIG. 226.

The address generator for table C contains a 5 bit address register adrthat is set to a new address at the start of processing the tag (eitherof the two table C initial values based on tagAltSense at the start ofthe line, and 0 for subsequent tags on the same line). Each cycle twoaddresses into table B are generated based on the two 2-bit inputs (in0and in1). As shown in Section 189, the output address tbRdAdr0 is alwaysadr and tbRdAdr1 is one of adr and adr+1, and at the end of the cycleadr takes on one of adr, adr+1, and adr+2. TABLE 189 AdrGen lookup tableinputs outputs in0 in1 adr0Sel adr1Sel adrSel 00 00 X¹⁸ X adr 00 01 Xadr adr 00 10 X X adr 00 11 X adr adr+1 01 00 adr X adr 01 01 adr adradr 01 10 adr X adr 01 11 adr adr adr+1 10 00 X X adr 10 01 X adr adr 1010 X X adr 10 11 X adr adr+1 11 00 adr X adr+1 11 01 adr adr+1 adr+1 1110 adr X adr+1 11 11 adr adr+1 adr+2¹⁸X = don't care state.26.8.4.3 Table B Interface

The table B interface implementation generates two encoded tag dataaddresses (tfsi_adr0, tfsu_adr1) based on two table B input addresses(tbRdAdr0, tbRdAdr1). A block diagram of table B can be seen in FIG.227.

Table B data is initially loaded into the 288-bit table B temporaryregister via the TFS FSM. Once all 288-bit entries have been loaded fromDRAM, the data is written in 9-bit chunks to the 32*9 register arraysbased on tbwradr.

Each time an AdvTFSLine pulse is received, the sense of which sub bufferis being read from or written to changes. This is accomplished by a1-bit flag called wrtb0. Although the initial state of wrtb0 isirrelevant, it must invert upon receipt of an AdvTFSLine pulse.

Note:—The output addresses from Table B are registered.

27 Tag FIFO Unit (TFU)

27.1 Overview

The Tag FIFO Unit (TFU) provides the means by which data is transferredbetween the Tag Encoder (TE) and the HCU. By abstracting the bufferingmechanism and controls from both units, the interface is clean betweenthe data user and the data generator.

The TFU is a simple FIFO interface to the HCU. The Tag Encoder willprovide support for arbitrary Y integer scaling up to 1600 dpi. Xinteger scaling of the tag dot data is performed at the output of theFIFO in the TFU. There is feedback to the TE from the TFU to allowstalling of the TE during a line. The TE interfaces to the TFU with adata width of 8 bits. The TFU interfaces to the HCU with a data width of1 bit.

The depth of the TFU FIFO is chosen as 16 bytes so that the FIFO canstore a single 126 dot tag.

27.1.1 Interfaces Between TE, TFU and HCU

27.1.1.1 TE-TFU Interface

The interface from the TE to the TFU comprises the following signals:

-   -   te_tfu_wdata, 8-bit write data.    -   te_tfu_wdatavalID, write data valid.    -   te_tfu_wradvline, accompanies the last valid 8-bit write data in        a line.

The interface from the TFU to TE comprises the following signal:

-   -   tfu_te_oktowrite, indicating to the TE that there is space        available in the TFU FIFO.

The TE writes data to the TFU FIFO as long as the TFU's tfu_te_oktowriteoutput bit is set. The TE write will not occur unless data isaccompanied by a data valid signal.

27.1.1.2 TFU-HCU Interface

The interface from the TFU to the HCU comprises the following signals:

-   -   tfu_hcu_tdata, 1-bit data.    -   tfu_hcu_avail, data valid signal indicating that there is data        available in the TFU FIFO.

The interface from HCU to TFU comprises the following signal:

-   -   hcu_tfu_ready, indicating to the TFU to supply the next dot.        27.1.1.2.1 X Scaling

Tag data is replicated a scale factor (SF) number of times in the Xdirection to convert the final output to 1600 dpi. Unlike both the CFUand SFU, which support non-integer scaling, the scaling is integer only.Replication in the X direction is performed at the output of the TFUFIFO on a dot-by-dot basis.

To account for the case where there may be two SoPEC devices, eachgenerating its own portion of a dot-line, the first dot in a line maynot be replicated the total scale-factor number of times by anindividual TFU. The dot will ultimately be scaled-up correctly with bothdevices doing part of the scaling, one on its lead-out and the other onits lead in.

Note two SoPEC TEs may be involved in producing the same byte of outputtag data straddling the printhead boundary. The HCU of the left SoPECwill accept from its TE the correct amount of dots, ignoring any dots inthe last byte that do not apply to its printhead. The TE of the rightSoPEC will be programmed the correct number of dots into the tag and itsoutput will be byte aligned with the left edge of the printhead.

27.2 Definitions OF I/O TABLE 190 TFU Port List Port Name Pins I/ODescription Clocks and Resets Pclk 1 In SoPEC Functional clock. Prst_n 1In Global reset signal. PCU Interface data and control signalsPcu_adr[4:2] 2 In PCU address bus. Only 3 bits are required to decodethe address space for this block. Pcu_dataout[31:0] 32 In Shared writedata bus from the PCU. Tfu_pcu_datain[31:0] 32 Out Read data bus fromthe TFU to the PCU. Pcu_rwn 1 In Common read/not-write signal from thePCU. Pcu_tfu_sel 1 In Block select from the PCU. When pcu_tfu_sel ishigh both pcu_adr and pcu_dataout are valid. Tfu_pcu_rdy 1 Out Readysignal to the PCU. When tfu_pcu_rdy is high it indicates the last cycleof the access. For a write cycle this means pcu_dataout has beenregistered by the block and for a read cycle this means the data ontfu_pcu_datain is valid. TE Interface data and control signalsTe_tfu_wdata[7:0] 8 In Write data for TFU FIFO. Te_tfu_wdatavalid 1 InWrite data valid signal. Te_tfu_wradvline 1 In Advance line signalstrobed when the last byte in a line is placed on te_tfu_wdatatfu_te_oktowrite 1 Out Ready signal indicating TFU has space availablein it's FIFO and is ready to be written to. HCU Interface data andcontrol signals Hcu_tfu_advdot 1 In Signal indicating to the TFU thatthe HCU is ready to accept the next dot of data from TFU. tfu_hcu_tdata1 Out Data from the TFU FIFO. tfu_hcu_avail 1 Out Signal indicatingvalid data available from TFU FIFO.

27.3 Configuration Registers TABLE 191 TFU Configuration Registers valueAddress on TFU_Base + register name #bits reset description Controlregisters 0x00 Reset 1 1 A write to this register causes a reset of theTFU. This register can be read to indicate the reset state: 0 - reset inprogress 1 - reset not in progress. 0x04 Go 1 see Writing 1 to thisregister starts the TFU. text Writing 0 to this register halts the TFU.When Go is deasserted the state- machines go to their idle states butall counters and configuration registers keep their values. When Go isasserted all counters are reset, but configuration registers keep theirvalues (i.e. they don't get reset). The TFU must be started before theTE is started. This register can be read to determine if the TFU isrunning (1 = running, 0 = stopped). Setup registers (constant duringprocessing of page) 0x08 XScale 8 1 Tag scale factor in X direction.0x0C XFracScale 8 1 Tag scale factor in X direction for the first dot ina line (must be programmed to be less than or equal to XScale) 0x10TEByteCount 12 0 The number of bytes to be accepted from the TE perline. Once this number of bytes have been received subsequent bytes areignored until there is a strobe on the te_tfu_wradvline 0x14 HCUDotCount16 0 The number of (optionally) x-scaled dots per line to be supplied tothe HCU. Once this number has been reached the remainder of the currentFIFO byte is ignored.27.4 Detailed Description

The FIFO is a simple 16-byte store with read and write pointers, and acontents store, FIG. 229. 16 bytes is sufficient to store a single 126dot tag.

Each line a total of TEByteCount bytes is read into the FIFO. Allsubsequent bytes are ignored until there is a strobe on thete_tfu_wradvline signal, whereupon bytes for the next line are stored.On the HCU side, a total of HCUDotCount dots are produced at the output.Once this count is reached any more dots in the FIFO byte currentlybeing processed are ignored. For the first dot in the next line thestart of line scale factor, XFracScale, is used.

The behaviour of these signals and the control signals between the TFUand the TE and HCU is detailed below.   // Concurrently Executed Code:  // TE always allowed to write when there's either (a)room  or  (b)  no  room  and  all   // bytes for that line have beenreceived.   if ((FifoCntnts != FifoMax) OR (FifoCntnts == FifoMax andByteToRx == 0)) then    tfu_te_oktowrite = 1   else    tfu_te_oktowrite= 0   // Data presented to HCU when there is (a) data inFIFO  and  (b)  the  HCU  has  not   // received all dots for a line  if (FifoCntnts != 0) AND (BitToTx != 0)then    tfu_hcu_avail = 1  else    tfu_hcu_avail = 0   // Output mux of FIFO data   tfu_hcu_tdata= Fifo[FifoRdPnt][RdBit]   // Sequentially Executed Code:  if (te_tfu_wdatavalid == 1) AND (FifoCntnts != FifoMax) AND (ByteToRx!= 0) then    Fifo[FifoWrPnt] = te_tfu_wdata    FifoWrPnt ++   FifoContents ++    ByteToRx −−   if (te_tfu_wradvline == 1) then   ByteToRx = TEByteCount   if (hcu_tfu_advdot == 1 and FifoCntnts != 0)then {    BitToTx ++    if (RepFrac == 1) then     RepFrac = Xscale    if (RdBit = 7) then      RdBit = 0      FifoRdPnt ++     FifoContents −−     else      RdBit++    else     RepFrac−−   if(BitToTx == 1) then {     RepFrac = XFracScale     RdBit = 0    FifoRdPnt ++     FifoContents−−     BitToTx = HCUDotCount     }    }

What is not detailed above is the fact that, since this is a circularbuffer, both the fifo read and write-pointers wrap-around to zero afterthey reach two. Also not detailed is the fact that if there is a changeof both the read and write-pointer in the same cycle, the fifo contentscounter remains unchanged.

28 Alftoner Compositor Unit (HCU)

28.1 Overview

The Halftoner Compositor Unit (HCU) produces dots for each nozzle in thedestination printhead taking account of the page dimensions (includingmargins). The spot data and tag data are received in bi-level form whilethe pixel contone data received from the CFU must be dithered to abi-level representation. The resultant 6 bi-level planes for each dotposition on the page are then remapped to 6 output planes and output dotat a time (6 bits) to the next stage in the printing pipeline, namelythe dead nozzle compensator (DNC).

28.2 Data Flow

FIG. 230 shows a simple dot data flow high level block diagram of theHCU. The HCU reads contone data from the CFU, bi-level spot data fromthe SFU, and bi-level tag data from the TFU.

Dither matrices are read from the DRAM via the DIU. The calculatedoutput dot (6 bits) is read by the DNC.

The HCU is given the page dimensions (including margins), and is onlystarted once for the page. It does not need to be programmed in betweenbands or restarted for each band. The HCU will stall appropriately ifits input buffers are starved. At the end of the page the HCU willcontinue to produce 0 for all dots as long as data is requested by theunits further down the pipeline (this allows later units to convenientlyflush pipelined data).

The HCU performs a linear processing of dots calculating the 6-bitoutput of a dot in each cycle. The mapping of 6 calculated bits to 6output bits for each dot allows for such example mappings. ascompositing of the spot0 layer over the appropriate contone layer(typically black), the merging of CMY into K (if K is present in theprinthead), the splitting of K into CMY dots if there is no K in theprinthead, and the generation of a fixative output bitstream.

28.3 Dram Storage Requirements

SoPEC allows for a number of different dither matrix configurations upto 256 bytes wide. The dither matrix is stored in DRAM. Using either asingle or double-buffer scheme a line of the dither matrix must be readin by the HCU over a SoPEC line time. SoPEC must produce 13824 dots perline for A4/Letter printing which takes 13824 cycles.

The following give the storage and bandwidths requirements for some ofthe possible configurations of the dither matrix.

-   -   4 Kbyte DRAM storage required for one 64×64 (preferred) byte        dither matrix    -   6.25 Kbyte DRAM storage required for one 80×80 byte dither        matrix    -   16 Kbyte DRAM storage required for four 64×64 byte dither        matrices    -   64 Kbyte DRAM storage required for one 256×256 byte dither        matrix

It takes 4 or 8 read accesses to load a line of dither matrix into thedither matrix buffer, depending on whether we're using a single ordouble buffer (configured by DoubleLineBuff register).

28.4 Implementation

A block diagram of the HCU is given in FIG. 231.

28.4.1 Definition of I/O TABLE 192 HCU port list and description Portname Pins I/O Description Clocks and reset Pclk 1 In System clock.prst_n 1 In System reset, synchronous active low. PCU interfacepcu_hcu_sel 1 In Block select from the PCU. When pcu_hcu_sel is highboth pcu_adr and pcu_dataout are valid. pcu_rwn 1 In Commonread/not-write signal from the PCU. pcu_adr[7:2] 6 In PCU address bus.Only 6 bits are required to decode the address space for this block.pcu_dataout[31:0] 32 In Shared write data bus from the PCU. hcu_pcu_rdy1 Out Ready signal to the PCU. When hcu_pcu_rdy is high it indicates thelast cycle of the access. For a write cycle this means pcu_dataout hasbeen registered by the block and for a read cycle this means the data onhcu_pcu_datain is valid. hcu_pcu_datain[31:0] 32 Out Read data bus tothe PCU. DIU interface hcu_diu_rreq 1 Out HCU read request, active high.A read request must be accompanied by a valid read address. diu_hcu_rack1 In Acknowledge from DIU, active high. Indicates that a read requesthas been accepted and the new read address can be placed on the addressbus, hcu_diu_radr. hcu_diu_radr[21:5] 17 Out HCU read address. 17 bitswide (256-bit aligned word). diu_hcu_rvalid 1 In Read data valid, activehigh. Indicates that valid read data is now on the read data bus,diu_data. diu_data[63:0] 64 In Read data from DIU. CFU interfacecfu_hcu_avail 1 In Indicates valid data present on cfu_hcu_c[3-0]datalines. cfu_hcu_c0data[7:0] 8 In Pixel of data in contone plane 0.cfu_hcu_c1data[7:0] 8 In Pixel of data in contone plane 1.cfu_hcu_c2data[7:0] 8 In Pixel of data in contone plane 2.cfu_hcu_c3data[7:0] 8 In Pixel of data in contone plane 3.hcu_cfu_advdot 1 Out Informs the CFU that the HCU has captured the pixeldata on cfu_hcu_c[3-0]data lines and the CFU can now place the nextpixel on the data lines. SFU interface sfu_hcu_avail 1 In Indicatesvalid data present on sfu_hcu_sdata. sfu_hcu_sdata 1 In Bi-level dotdata. hcu_sfu_advdot 1 Out Informs the SFU that the HCU has captured thedot data on sfu_hcu_sdata and the SFU can now place the next dot on thedata line. TFU interface tfu_hcu_avail 1 In Indicates valid data presenton tfu_hcu_tdata. tfu_hcu_tdata 1 In Tag dot data. hcu_tfu_advdot 1 OutInforms the TFU that the HCU has captured the dot data on tfu_hcu_tdataand the TFU can now place the next dot on the data line. DNC interfacednc_hcu_ready 1 In Indicates that DNC is ready to accept data from theHCU. hcu_dnc_avail 1 Out Indicates valid data present on hcu_dnc_data.hcu_dnc_data[5:0] 6 Out Output bi-level dot data in 6 ink planes.28.4.2 Configuration Registers

The configuration registers in the HCU are programmed via the PCUinterface. Refer to section 21.8.2 on page 321 for the description ofthe protocol and timing diagrams for reading and writing registers inthe HCU. Note that since addresses in SoPEC are byte aligned and the PCUonly supports 32-bit register reads and writes, the lower 2 bits of thePCU address bus are not required to decode the address space for theHCU. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of hcu_pcu_datain. Theconfiguration registers of the HCU are listed in Table 193. TABLE 193HCU Registers Value Address on (HCU_base +) Register Name #bits ResetDescription Control registers 0x00 Reset 1 0x1 A write to this registercauses a reset of the HCU. 0x04 Go 1 0x0 Writing 1 to this registerstarts the HCU. Writing 0 to this register halts the HCU. When Go isasserted all counters, flags etc. are cleared or given their initialvalue, but configuration registers keep their values. When Go isdeasserted the state-machines go to their idle states but all countersand configuration registers keep their values. The HCU should be startedafter the CFU, SFU, TFU, and DNC. This register can be read to determineif the HCU is running (1 = running, 0 = stopped). Setup registers(constant for during processing) 0x10 AvailMask 4 0x0 Mask used todetermine which of the dotgen units etc. are to be checked before a dotis generated by the HCU within the specified margins for the specifiedcolor plane. If the specified dotgen unit is stalled, then the HCU willalso stall. See Table for bit allocation and definition. 0x14 TMMask 40x0 Same as AvailMask, but used in the top margin area before theappropriate target page is reached. 0x18 PageMarginY 32 0x0000_0000 Thefirst line considered to be off the page. 0x1C MaxDot 16 0x0000 This isthe maximum dot number − 1 present across a page. For example if a pagecontains 13824 dots, then MaxDot will be 13823. 0x20 TopMargin 320x0000_0000 The first line on a page to be considered within the targetpage for contone and spot data. (0 = first printed line of page) 0x24BottomMargin 32 0x0000_0000 The first line in the target bottom marginfor contone and spot data (i.e. first line after target page). 0x28LeftMargin 16 0x0000 The first dot on a line within the target page forcontone and spot data. 0x2C RightMargin 16 0xFFFF The first dot on aline within the target right margin for contone and spot data. 0x30TagTopMargin 32 0x0000_0000 The first line on a page to be consideredwithin the target page for tag data. (0 = first printed line of page)0x34 TagBottomMargin 32 0x0000_0000 The first line in the target bottommargin for tag data (i.e. first line after target page). 0x38TagLeftMargin 16 0x0000 The first dot on a line within the target pagefor tag data. 0x3C TagRightMargin 16 0xFFFF The first dot on a linewithin the target right margin for tag data. 0x44 StartDMAdr[21:5] 170x0_0000 Points to the first 256-bit word of the first line of thedither matrix in DRAM. 0x48 EndDMAdr[21:5] 17 0x0_0000 Points to thelast address of the group of four 256- bit reads (or 8 if singlebuffering) that reads in the last line of the dither matrix. 0x4CLineIncrement 5 0x2 The number of 256-bit words in DRAM from the startof one line of the dither matrix and the start of the next line, i.e.the value by which the DRAM address is incremented at the start of aline so that it points to the start of the next line of the dithermatrix. 0x50 DMInitIndexC0 8 0x00 If using the single-buffer scheme thisregister represents the initial index within 256-byte dither matrix linebuffer for contone plane 0. If using double-buffer scheme, only the 7lsbs are used. 0x54 DMLwrIndexC0 8 0x00 If using the single-bufferscheme this register represents the lower index within 256-byte dithermatrix line buffer for contone plane 0. If using double-buffer scheme,only the 7 lsbs are used. 0x58 DMUprIndexC0 8 0x3F If using thesingle-buffer scheme this register represents the upper index within256-byte dither matrix line buffer for contone plane 0. After readingthe data at this location the index wraps to DMLwrIndexC0. If usingdouble-buffer scheme, only the 7 lsbs are used. 0x5C DMInitIndexC1 80x00 If using the single-buffer scheme this register represents theinitial index within 256-byte dither matrix line buffer for contoneplane 1. If using double-buffer scheme, only the 7 lsbs are used. 0x60DMLwrIndexC1 8 0x00 If using the single-buffer scheme this registerrepresents the lower index within 256-byte dither matrix line buffer forcontone plane 1. If using double-buffer scheme, only the 7 lsbs areused. 0x64 DMUprIndexC1 8 0x3F If using the single-buffer scheme thisregister represents the upper index within 256-byte dither matrix linebuffer for contone plane 1. After reading the data at this location theindex wraps to DMLwrIndexC1. If using double-buffer scheme, only the 7lsbs are used. 0x68 DMInitIndexC2 8 0x00 If using the single-bufferscheme this register represents the initial index within 256-byte dithermatrix line buffer for contone plane 2. If using double-buffer scheme,only the 7 lsbs are used. 0x6C DMLwrIndexC2 8 0x00 If using thesingle-buffer scheme this register represents the lower index within256-byte dither matrix line buffer for contone plane 2. If usingdouble-buffer scheme, only the 7 lsbs are used. 0x70 DMUprIndexC2 8 0x3FIf using the single-buffer scheme this register represents the upperindex within 256-byte dither matrix line buffer for contone plane 2.After reading the data at this location the index wraps to DMLwrIndexC2.If using double-buffer scheme, only the 7 lsbs are used. 0x74DMInitIndexC3 8 0x00 If using the single-buffer scheme this registerrepresents the initial index within 256-byte dither matrix line bufferfor contone plane 3. If using double-buffer scheme, only the 7 lsbs areused. 0x78 DMLwrIndexC3 8 0x00 If using the single-buffer scheme thisregister represents the lower index within 256-byte dither matrix linebuffer for contone plane 3. If using double-buffer scheme, only the 7lsbs are used. 0x7C DMUprIndexC3 8 0x3F If using the single-bufferscheme this register represents the upper index within 256-byte dithermatrix line buffer for contone plane 3. After reading the data at thislocation the index wraps to DMLwrIndexC3. If using double-buffer scheme,only the 7 lsbs are used. 0x80 DoubleLineBuf 1 0x1 Selects the ditherline buffer mode to be single or double buffer. 0 - single line buffermode 1 - double line buffer mode 0x84 to 0x98 IOMappingLo 6x320x0000_0000 The dot reorg mapping for output inks 0 to 5. For each ink's64-bit IOMapping value, IOMappingLo represents the low order 32 bits.0x9C to 0xB0 IOMappingHi 6x32 0x0000_0000 The dot reorg mapping foroutput inks 0 to 5. For each ink's 64-bit IOMapping value, IOMappingHirepresents the high order 32 bits. 0xB4 to 0xC0 cpConstant 4x8  0x00 Theconstant contone value to output for contone plane N when printing inthe margin areas of the page. This value will typically be 0. 0xC4sConstant 1 0x0 The constant bi-level value to output for spot whenprinting in the margin areas of the page. This value will typically be0. 0xC8 tConstant 1 0x0 The constant bi-level value to output for tagdata when printing in the margin areas of the page. This value willtypically be 0. 0xCC DitherConstant 8 0xFF The constant value to use fordither matrix when the dither matrix is not available, i.e. when thesignal dm_avail is 0. This value will typically be 0xFF so thatcpConstant can easily be 0x00 or 0xFF without requiring a dither matrix(DitherConstant is primarily used for threshold dithering in the marginareas). Debug registers (read only) 0xD0 HcuPortsDebug 14 N/A Bit 13 =tfu_hcu_avail Bit 12 = hcu_tfu_advdot Bit 11 = sfu_hcu_avail Bit 10 =hcu_sfu_advdot Bit 9 = cfu_hcu_avail Bit 8 = hcu_cfu_advdot Bit 7 =dnc_hcu_ready Bit 6 = hcu_dnc_avail Bits 5-0 = hcu_dnc_data 0xD4HcuDotgenDebug 15 N/A Bit 14 = after_top_margin Bit 13 =in_tag_target_page Bit 12 = in_target_page Bit 11 = tp_avail Bit 10 =s_avail Bit 9 = cp_avail Bit 8 = dm_avail Bit 7 = advdot Bits 5-0 = [tp,s, cp3, cp2, cp1, cp0] (i.e. 6 bit input to dot reorg units) 0xD8HcuDitherDebug1 17 N/A Bit 17 = advdot Bit 16 = dm_avail Bit 15-8 =cp1_dither_val Bits 7-0 = cp0_dither_val 0xDC HcuDitherDebug2 17 N/A Bit17 = advdot Bit 16 = dm_avail Bit 15-8 = cp3_dither_val Bits 7-0 =cp2_dither_vall28.4.3 Control Unit

The control unit is responsible for controlling the overall flow of theHCU. It is responsible for determining whether or not a dot will begenerated in a given cycle, and what dot will actually begenerated—including whether or not the dot is in a margin area, and whatdither cell values should be used at the specific dot location. A blockdiagram of the control unit is shown in FIG. 232.

The inputs to the control unit are a number of avail flags specifyingwhether or not a given dotgen unit is capable of supplying ‘real’ datain this cycle. The term ‘real’ refers to data generated from externalsources, such as contone line buffers, bi-level line buffers, and tagplane buffers. Each dotgen unit informs the control unit whether or nota dot can be generated this cycle from real data. It must also checkthat the DNC is ready to receive data.

The contone/spot margin unit is responsible for determining whether thecurrent dot coordinate is within the target contone/spot margins, andthe tag margin unit is responsible for determining whether the currentdot coordinate is within the target tag margins.

The dither matrix table interface provides the interface to DRAM for thegeneration of dither cell values that are used in the halftoning processin the contone dotgen unit.

28.4.3.1 Determine advdot

The HCU does not always require contone planes, bi-level or tag planesin order to produce a page. For example, a given page may not have abi-level layer, or a tag layer. In addition, the contone and bi-levelparts of a page are only required within the contone and bi-level pagemargins, and the tag part of a page is only required within the tag pagemargins. Thus output dots can be generated without contone, bi-level ortag data before the respective top margins of a page has been reached,and 0s are generated for all color planes after the end of the page hasbeen reached (to allow later stages of the printing pipeline to flush).

Consequently the HCU has an AvailMask register that determines which ofthe various input avail flags should be taken notice of during theproduction of a page from the first line of the target page, and aTMMask register that has the same behaviour, but is used in the linesbefore the target page has been reached (i.e. inside the target topmargin area). The dither matrix mask bit TMask[0] is the exception, itapplies to all margins areas not just the top margin. Each bit in theAvailMask refers to a particular avail bit: if the bit in the AvailMaskregister is set, then the corresponding avail bit must be 1 for the HCUto advance a dot. The bit to avail correspondence is shown in Table 194.Care should be taken with TMMask—if the particular data is not availableafter the top margin has been reached, then the HCU will stall. Notethat the avail bits for contone and spot colors are ANDed within_target_page after the target page area has been reached to allow dotproduction in the contone/spot margin areas without needing any data inthe CFU and SFU. The avail bit for tag color is ANDed within_tag_target_page after the target tag page area has been reached toallow dot production in the tag margin areas without needing any data inthe TFU. TABLE 194 Correspondence between bit in AvailMask and availflag bit # in AvailMask avail flag description 0 dm_avail dither matrixdata available 1 cp_avail contone pixels available 2 s_avail spot coloravailable 3 tp_avail tag plane available

Each of the input avail bits is processed with its appropriate mask bitand the after_top_margin flag (note the dither matrix is the exceptionit is processed with in_target_page). The output bits are ANDed togetheralong with Go and output_buff_full (which specifies whether the outputbuffer is ready to receive a dot in this cycle) to form the output bitadvdot. We also generate wr_advdot. In this way, if the output buffer isfull or any of the specified avail flags is clear, the HCU will stall.When the end of the page is reached, in_page will be deasserted and theHCU will continue to produce 0 for all dots as long as the DNC requestsdata. A block diagram of the determine advdot unit is shown in FIG. 233.

The advance dot block also determines if current page needs dithermatrix, it indicates to the dither matrix table interface block via thedm_read_enable signal. If no dither is required in the margins or in thetarget page then dm_read_enable will be 0 and no dither will be read infor this page.

28.4.3.2 Position Unit

The position unit is responsible for outputting the position of thecurrent dot (curr_pos, curr_line) and whether or not this dot is thelast dot of a line (advline). Both curr_pos and curr_line are set to 0at reset or when Go transitions from 0 to 1. The position unit relies onthe advdot input signal to advance through the dots on a page. Wheneveran advdot pulse is received, curr_pos gets incremented. If curr_posequals max_dot then an advline pulse is generated as this is the lastdot in a line, curr_line gets incremented, and the curr_pos is reset to0 to start counting the dots for the next line.

The position unit also generates a filtered version of advline calleddm_advline to indicate to the dither matrix pointers to increment to thenext line. The dm_advline is only incremented when dither is requiredfor that line. if ((after_top_margin AND avail_mask[0]) OR tm_mask[0])then   dm_advline = advline else   dm_advline = 028.4.3.3 Margin Unit

The responsibility of the margin unit is to determine whether thespecific dot coordinate is within the page at all, within the targetpage or in a margin area (see FIG. 234). This unit is instantiated forboth the contone/spot margin unit and the tag margin unit.

The margin unit takes the current dot and line position, and returnsthree flags.

-   -   the first, in_page is 1 if the current dot is within the page,        and 0 if it is outside the page.    -   the second flag, in_target_page, is 1 if the dot coordinate is        within the target page area of the page, and 0 if it is within        the target top/left/bottom/right margins.    -   the third flag, after_top_margin, is 1 if the current dot is        below the target top margin, and 0 if it is within the target        top margin.

A block diagram of the margin unit is shown in FIG. 235.

28.4.3.4 Dither Matrix Table Interface

The dither matrix table interface provides the interface to DRAM for thegeneration of dither cell values that are used in the halftoning processin the contone dotgen unit. The control flag dm_read_enable enables thereading of the dither matrix table line structure from DRAM. Ifdm_read_enable is 0, the dither matrix is not specified in DRAM and noDRAM accesses are attempted. The dither matrix table interface has anoutput flag dm_avail which specifies if the current line of thespecified matrix is available. The HCU can be directed to stall whendm_avail is 0 by setting the appropriate bit in the HCU's AvailMask orTMMask registers. When dm_avail is 0 the value in the DitherConstantregister is used as the dither cell values that are output to thecontone dotgen unit.

The dither matrix table interface consists of a state machine thatinterfaces to the DRAM interface, a dither matrix buffer that providesdither matrix values, and a unit to generate the addresses for readingthe buffer. FIG. 236 shows a block diagram of the dither matrix tableinterface.

28.4.3.5 Dither Data Structure in DRAM

The dither matrix is stored in DRAM in 256-bit words, transferred to theHCU in 64-bit words and consumed by the HCU in bytes. Table 195 showsthe 64-bit words mapping to 256-bit word addresses, and Table 196 showsthe 8-bits dither value mapping in the 64-bits word. TABLE 195 DitherData stored in DRAM Address[21:5] Data[255:0] 00000 D3 D2 D1 D0[255:192] [191:128] [127:64] [63:0] 00001 D7 D6 D5 D4 [255:192][191:128] [127:64] [63:0] 00010 D11 D10 D9 D8 [255:192] [191:128][127:64] [63:0] 00011 D15 D14 D13 D12 [255:192] [191:128] [127:64][63:0] 00100 D19 D18 D17 D16 [255:192] [191:128] [127:64] [63:0] etc

When the HCU first requests data from DRAM, the 64-bits word transferorder will be D0,D1,D2,D3. On the second request the transfer order willbe D4,D5,D6,D7 and so on for other requests. TABLE 196 Dither datastored in HCUs line buffer Dither index[7:0] Data[7:0] 00 D0[7:0] 01D0[15:8] 02 D0[23:16] 03 D0[31:24] 04 D0[39:32] 05 D0[47:40] 06D0[55:48] 07 D0[63:56] 08 D1[7:0] 09 D1[15:8] 0A D1[23:16] 0B D1[31:24]0C D1[39:32] 0D D1[47:40] 0E D1[55:48] 0F D1[63:56] 10 D2[7:0] 11D2[15:8] 12 D2[23:16] 13 D2[32:24] 14 D2[39:32] 15 D2[47:40] 16D2[55:48] 17 D2[63:56] 18 D3[7:0] 19 D3[15:8] 1A D3[23:16] 1B D3[31:24]1C D3[39:32] 1D D3[47:40] 1E D3[55:48] 1F D3[63:56] 20 D4[7:0] 21D4[15:8] 22 D4[23:16] 23 D4[31:24] 24 D4[39:32] 25 D4[47:40] 26D4[55:48] 27 D4[63:56] 28 D5[7:0] 29 D5[15:8] 2A D5[23:16] 2B D5[31:24]2C D5[39:32] 2D D5[47:40] 2E D5[55:48] 2F D5[63:56] etc. etc.26.4.3.5.1 Dither Matrix Buffer

The state machine loads dither matrix table data a line at a time fromDRAM and stores it in a buffer. A single line of the dither matrix iseither 256 or 128 8-bit entries, depending on the programmable bitDoubleLineBuf. If this bit is enabled, a double-buffer mechanism isemployed such that while one buffer is read from for the current line'sdither matrix data (8 bits representing a single dither matrix entry),the other buffer is being written to with the next line's dither matrixdata (64-bits at a time). Alternatively, the single buffer scheme can beused, where the data must be loaded at the end of the line, thusincurring a delay.

The single/double buffer is implemented using a 256 byte 3-port registerarray, two reads, one write port, with the reads clocked at double thesystem clock rate (320 MHz) allowing 4 reads per clock cycle.

The dither matrix buffer unit also provides the mechanism for keepingtrack of the current read and write buffers, and providing the mechanismsuch that a buffer cannot be read from until it has been written to. Inthis case, each buffer is a line of the dither matrix, i.e. 256 or 128bytes.

The dither matrix buffer maintains a read and write pointer for thedither matrix. The output value dm_avail is derived by comparing theread and write pointers to determine when the dither matrix is notempty. The write pointer wr_adr is incremented each time a 64-bit wordis written to the dither matrix buffer and the read pointer rd_ptr isincremented each time dm_advline is received. If double_line_buf is 0the rd_ptr will increment by 2, otherwise it will increment by 1. If thedither matrix buffer is full then no further writes will be allowed(buff_full=1), or if the buffer is empty no further buffer reads areallowed (buff_emp=1).

The read addresses are byte aligned and are generated by the readaddress generator. A single dither matrix entry is represented by 8 bitsand an entry is read for each of the four contone planes in parallel. Ifdouble buffer is used (double_line_buf=1) the read address is derivedfrom 7-bit address from the read address generator and 1-bit from theread pointer. If double_line_buf=0 then the read address is the full8-bits from the read address generator. if (double_line_buf == 1 )then read_port[7:0] = {rd_ptr[0],rd_adr[6:0]}     // concatenation else read_port[7:0] = rd_adr[7:0]28.4.3.5.2 Read Address Generator

For each contone plane there is a initial, lower and upper index to beused when reading dither cell values from the dither matrix doublebuffer. The read address for each plane is used to select a byte fromthe current 256-byte read buffer. When Go gets set (0 to 1 transition),or at the end of a line, the read addresses are set to theircorresponding initial index. Otherwise, the read address generatorrelies on advdot to advance the addresses within the inclusive rangespecified the lower and upper indices, represented by the followingpseudocode: if (advdot == 1) then  if (advline == 1) then   rd_adr =dm_init_index  elsif (rd_adr == dm_upr_index) then   rd_adr =dm_lwr_index  else   rd_adr ++ else  rd_adr = rd_adr28.4.3.5.3 State Machine

The dither matrix is read from DRAM in single 256-bit accesses,receiving the data from the DIU over 4 clock cycles (64-bits per cycle).The protocol and timing for read accesses to DRAM is described insection 20.9.1 on page 240. Read accesses to DRAM are implemented bymeans of the state machine described in FIG. 238.

All counters and flags should be cleared after reset or when Gotransitions from 0 to 1. While the Go bit is 1, the state machine relieson the dm_read_enable bit to tell it whether to attempt to read dithermatrix data from DRAM. When dm_read_enable is clear, the state machinedoes nothing and remains in the idle state. When dm_read_enable is set,the state machine continues to load dither matrix data, 256-bits at atime (received over 4 clock cycles, 64 bits per cycle), while there isspace available in the dither matrix buffer, (buff_full !=1).

The read address and line_start_adr are initially set to start_dm_adr.The read address gets incremented after each read access. It takes 4 or8 read accesses to load a line of dither matrix into the dither matrixbuffer, depending on whether we're using a single or double buffer. Acount is kept of the accesses to DRAM. When a read access completes andaccess_count equals 3 or 7, a line of dither matrix has just been loadedfrom and the read address is updated to line_start_adr plusline_increment so it points to the start of the next line of dithermatrix. (line_start_adr is also updated to this value). If the readaddress equals end_dm_adr then the next read address will bestart_dm_adr, thus the read address wraps to point to the start of thearea in DRAM where the dither matrix is stored.

The write address for the dither matrix buffer is implemented by meansof a modulo-32 counter that is initially set to 0 and incremented whendiu_hcu_rvalid is asserted.

FIG. 237 shows an example of setting start_dm_adr and end_dm_adr valuesin relation to the line increment and double line buffer settings. Thecalculation of end_dm_adr is // end_dm_adr calculation dm_height =Dither matrix height in lines if (double_line_buf == 1)    // end_dm_adr[21:5] = start_dm_adr[21:5] + (((dm_height − 1)*line_inc) +3) << 5) else  end_dm_adr[21:5] = start_dm_adr[21:5] + (((dm_height −1)*line_inc) + 7) << 5)28.4.4 Contone Dotgen Unit

The contone dotgen unit is responsible for producing a dot in up to 4color planes per cycle. The contone dotgen unit also produces a cp_availflag which specifies whether or not contone pixels are currentlyavailable, and the output hcu_cfu_advdot to request the CFU to providethe next contone pixel in up to 4 color planes.

The block diagram for the contone dotgen unit is shown in FIG. 239.

A dither unit provides the functionality for dithering a single contoneplane. The contone image is only defined within the contone/spot marginarea. As a result, if the input flag in_target_page is 0, then aconstant contone pixel value is used for the pixel instead of thecontone plane.

The resultant contone pixel is then halftoned. The dither value to beused in the halftoning process is provided by the control data unit. Thehalftoning process involves a comparison between a pixel value and itscorresponding dither value. If the 8-bit contone value is greater thanor equal to the 8-bit dither matrix value a 1 is output. If not, then a0 is output. This means each entry in the dither matrix is in the range1-255 (0 is not used).

Note that constant use is dependant on the in_target_page signal only,if in_target_page is 1 then the cfu_hcu_c*_data should be allowed topass through, regardless of the stalling behaviour or the avail_mask[1]setting. This allows a constant value to be setup on the CFU outputdata, and the use of different constants while inside and outside thetarget page. The hcu_cfu_advdot will always be zero if the avail_mask[1]is zero.

28.4.5 Spot Dotgen Unit

The spot dotgen unit is responsible for producing a dot of bi-level dataper cycle. It deals with bi-level data (and therefore does not need tohalftone) that comes from the LBD via the SFU. Like the contone layer,the bi-level spot layer is only defined within the contone/spot marginarea. As a result, if input flag in_target_page is 0, then a constantdot value (typically this would be 0) is used for the output dot.

The spot dotgen unit also produces a s_avail flag which specifieswhether or not spot dots are currently available for this spot plane,and the output hcu_sfu_advdot to request the SFU to provide the nextbi-level data value. The spot dotgen unit can be represented by thefollowing pseudocode: s_avail = sfu_hcu_avail if (in_target_page == 1AND avail_mask[2] == 0 )OR   (in_target_page == 0) then  hcu_sfu_advdot= 0 else  hcu_sfu_advdot = advdot if (in_target_page == 1) then  sp =sfu_hcu_sdata else  sp = sp_constant

Note that constant use is dependant on the in target_page signal only,if in_target_page is 1 then the sfu_hcu_data should be allowed to passthrough, regardless of the stalling behaviour or the avail_mask setting.This allows a constant value to be setup on the SFU output data, and theuse of different constants while inside and outside the target page. Thehcu_sfu_advdot will always be zero if the avail_mask[2] is zero.

28.4.6 Tag Dotgen Unit

This unit is very similar to the spot dotgen unit (see Section 28.4.5)in that it deals with bi-level data, in this case from the TE via theTFU. The tag layer is only defined within the tag margin area. As aresult, if input flag in_tag_target_page is 0, then a constant dotvalue, tp_constant (typically this would be 0), is used for the outputdot. The tagplane dotgen unit also produces a tp_avail flag whichspecifies whether or not tag dots are currently available for thetagplane, and the output hcu_tfu_advdot to request the TFU to providethe next bi-level data value.

The hcu_tfu_advdot generation is similar to the SFU and CFU, except itdepends only on in_target_page and advdot. It does not take into accountthe avail mask when inside the target page.

28.4.7 Dot Reorg Unit

The dot reorg unit provides a means of mapping the bi-level dithereddata, the spot0 color, and the tag data to output inks in the actualprinthead. Each dot reorg unit takes a set of 6 1-bit inputs andproduces a single bit output that represents the output dot for thatcolor plane.

The output bit is a logical combination of any or all of the input bits.This allows the spot color to be placed in any output color plane(including infrared for testing purposes), black to be merged into cyan,magenta and yellow (in the case of no black ink in the Memjetprinthead), and tag dot data to be placed in a visible plane. An outputfor fixative can readily be generated by simply combining desired inputbits.

The dot reorg unit contains a 64-bit lookup to allow complete freedomwith regards to mapping. Since all possible combinations of input bitsare accounted for in the 64 bit lookup, a given dot reorg unit can takethe mapping of other reorg units into account. For example, a blackplane reorg unit may produce a 1 only if the contone plane 3 or spotcolor inputs are set (this effectively composites black bi-level overthe contone). A fixative reorg unit may generate a 1 if any 2 of theoutput color planes is set (taking into account the mappings produced bythe other reorg units). If dead nozzle replacement is to be used (seesection 29.4.2 on page 473), the dot reorg can be programmed to directthe dots of the specified color into the main plane, and 0 into theother. If a nozzle is then marked as dead in the DNC, swapping the bitsbetween the planes will result in 0 in the dead nozzle, and the requireddata in the other plane.

If dead nozzle replacement is to be used, and there are no tags, the TEcan be programmed with the position of dead nozzles and the resultantpattern used to direct dots into the specified nozzle row. If only fixedbackground TFS is to be used, a limited number of nozzles can bereplaced. If variable tag data is to be used to specify dead nozzles,then large numbers of dead nozzles can be readily compensated for.

The dot reorg unit can be used to average out the nozzle usage when tworows of nozzles share the same ink and tag encoding is not being used.The TE can be programmed to produce a regular pattern (e.g. 0101 on oneline, and 1010 on the next) and this pattern can be used as a directiveas to direct dots into the specified nozzle row.

Each reorg unit contains a 64-bit IOMapping value programmable as two32-bit HCU registers, and a set of selection logic based on the 6-bitdot input (2⁶=64 bits), as shown in FIG. 240. The mapping of input bitsto each of the 6 selection bits is as defined in Table 197. TABLE 197Mapping of input bits to 6 selection bits address bit likely of lookuptied to interpretation 0 bi-level dot from contone layer 0 cyan 1bi-level dot from contone layer 1 magenta 2 bi-level dot from contonelayer 2 yellow 3 bi-level dot from contone layer 3 black 4 bi-levelspot0 dot black 5 bi-level tag dot infra-red28.4.8 Output Buffer

The output buffer de-couples the stalling behaviour of the feeder unitsfrom the stalling behaviour of the DNC. The larger the buffer thegreater de-coupling. Currently the output buffer size is 2, but could beincreased if needed at the cost of extra area.

If the Go bit is set to 0 no read or write of the output buffer ispermitted. On a low to high transition of the Go bit the contents of theoutput buffer are cleared.

The output buffer also implements the interface logic to the DNC. Ifthere is data in the output buffer the hcu_dnc_avail signal will be 1,otherwise is will be 0. If both hcu_dnc_avail and dnc_hcu_ready are 1then data is read from the output buffer.

On the write side if there is space available in the output buffer thelogic indicates to the control unit via the output_buff_full signal. Thecontrol unit will then allow writes to the output buffer via thewr_advdot signal. If the writes to the output buffer are after the endof a page (indicated by in_page equal to 0) then all dots written intothe output buffer are set to zero.

28.4.8.1 HCU to DNC Interface

FIG. 241 shows the timing diagram and representative logic of the HCU toDNC interface. The hcu_dnc_avail signal indicate to the DNC that the HCUhas data available. The dnc_hcu_ready signal indicates to the HCU thatthe DNC is ready to accept data. When both signals are high data istransferred from the HCU to the DNC. Once the HCU indicates it has dataavailable (setting the hcu_dnc_avail signal high) it can only set thehcu_dnc_avail low again after a dot is accepted by the DNC.

28.4.9 Feeder to HCU Interfaces

FIG. 242 shows the feeder unit to HCU interface timing diagram, and FIG.243 shows representative logic of the interface with the registerpositions. sfu_hcu_data and sfu_hcu_avail are always registered whilethe sfu_hcu_advdot is not. The hcu_sfu_avail signal indicates to the HCUthat the feeder unit has data available, and sfu_hcu_advdot indicates tothe feeder unit that the HCU has captured the last dot. The HCU cannever produce an advance dot pulse while the avail is low. The diagramsshow the example of the SFU to HCU interface, but the same interface isused for the other feeder units TFU and CFU.

29 Dead Nozzle Compensator (DNC)

29.1 Overview

The Dead Nozzle Compensator (DNC) is responsible for adjusting Memjetdot data to take account of non-functioning nozzles in the Memjetprinthead. Input dot data is supplied from the HCU, and the correcteddot data is passed out to the DWU. The high level data path is shown bythe block diagram in FIG. 244.

The DNC compensates for a dead nozzles by performing the followingoperations:

-   -   Dead nozzle removal, i.e. turn the nozzle off    -   Ink replacement by direct substitution i.e. K->K    -   Ink replacement by indirect substitution i.e. K->CMY    -   Error diffusion to adjacent nozzles    -   Fixative corrections

The DNC is required to efficiently support up to 5% dead nozzles, underthe expected DRAM bandwidth allocation, with no restriction on wheredead nozzles are located and handle any fixative correction due tonozzle compensations. Performance must degrade gracefully after 5% deadnozzles.

29.2 Dead Nozzle Identification

Dead nozzles are identified by means of a position value and a maskvalue. Position information is represented by a 10-bit delta encodedformat, where the 10-bit value defines the number of dots between deadnozzle columns¹⁹. With the delta information it also reads the 6-bitdead nozzle mask (dn_mask) for the defined dead nozzle position. Eachbit in the dn_mask corresponds to an ink plane. A set bit indicates thatthe nozzle for the corresponding ink plane is dead. The dead nozzletable format is shown in FIG. 245. The DNC reads dead nozzle informationfrom DRAM in single 256-bit accesses. A 10-bit delta encoding scheme ischosen so that each table entry is 16 bits wide, and 16 entries fitexactly in each 256-bit read. Using 10-bit delta encoding means that themaximum distance between dead nozzle columns is 1023 dots. It ispossible that dead nozzles may be spaced further than 1023 dots fromeach other, so a null dead nozzle identifier is required. A null deadnozzle identifier is defined as a 6-bit dn_mask of all zeros. These nulldead nozzle identifiers should also be used so that:¹⁹for a 10-bit delta value of d, if the current column n is a deadnozzle column then the next dead nozzle column is given by n+(d+1).

-   -   the dead nozzle table is a multiple of 16 entries (so that it is        aligned to the 256-bit DRAM locations)    -   the dead nozzle table spans the complete length of the line,        i.e. the first entry dead nozzle table should have a delta from        the first nozzle column in a line and the last entry in the dead        nozzle table should correspond to the last nozzle column in a        line.

Note that the DNC deals with the width of a page. This may or may not bethe same as the width of the printhead (the PHI may introduce somemargining to the page so that its dot output matches the width of theprinthead). Care must be taken when programming the dead nozzle table sothat dead nozzle positions are correctly specified with respect to thepage and printhead.

29.3 Dram Storage and Bandwidth Requirement

The memory required is largely a factor of the number of dead nozzlespresent in the printhead (which in turn is a factor of the printheadsize). The DNC is required to read a 16-bit entry from the dead nozzletable for every dead nozzle. Table 198 shows the DRAM storage andaverage²⁰ bandwidth requirements for the DNC for different percentagesof dead nozzles and different page sizes.²⁰Average bandwidth assumes an even spread of dead nozzles. Clumps ofdead nozzles may cause delays due to insufficient available DRAMbandwidth. These delays will occur every line causing an accumulativedelay over a page.TABLE 198 Dead Nozzle storage and average bandwidth requirements Deadnozzle table % Dead Memory Bandwidth Page size Nozzles (KBytes)(bits/cycle) A4^(a)  5% 1.4^(c) 0.8^(d) 10% 2.7 1.6 15% 4.1 2.4 A3^(b) 5% 1.9 0.8 10% 3.8 1.6 15% 5.7 2.4^(a)Bi-lithic printhead has 13824 nozzles per color providing full bleedprinting for A4/Letter^(b)Bi-lithic printhead has 19488 nozzles per color providing full bleedprinting for A3^(c)16 bits × 13824 nozzles × 0.05 dead^(d)(16 bits read/20 cycles) = 0.8 bits/cycle29.4 Nozzle Compensation

DNC receives 6 bits of dot information every cycle from the HCU, 1 bitper color plane. When the dot position corresponds to a dead nozzlecolumn, the associated 6-bit dn_mask indicates which ink plane(s)contains a dead nozzle(s). The DNC first deletes dots destined for thedead nozzle. It then replaces those dead dots, either by placing thedata destined for the dead nozzle into an adjacent ink plane (directsubstitution) or into a number of ink planes (indirect substitution).After ink replacement, if a dead nozzle is made active again then theDNC performs error diffusion. Finally, following the dead nozzlecompensation mechanisms the fixative, if present, may need to beadjusted due to new nozzles being activated, or dead nozzles beingremoved.

29.4.1 Dead Nozzle Removal

If a nozzle is defined as dead, then the first action for the DNC is toturn off (zeroing) the dot data destined for that nozzle. This is doneby a bit-wise ANDing of the inverse of the dn_mask with the dot value.

29.4.2 Ink Replacement

Ink replacement is a mechanism where data destined for the dead nozzleis placed into an adjacent ink plane of the same color (directsubstitution, i.e. K->K_(alternative)), or placed into a number of inkplanes, the combination of which produces the desired color (indirectsubstitution, i.e. K->CMY). Ink replacement is performed by filteringout ink belonging to nozzles that are dead and then adding back in anappropriately calculated pattern. This two step process allows theoptional re-inclusion of the ink data into the original dead nozzleposition to be subsequently error diffused. In the general case,fixative data destined for a dead nozzle should not be left activeintending it to be later diffused.

The ink replacement mechanism has 6 ink replacement patterns, one perink plane, programmable by the CPU. The dead nozzle mask is ANDed withthe dot data to see if there are any planes where the dot is active butthe corresponding nozzle is dead. The resultant value forms an enable,on a per ink basis, for the ink replacement process. If replacement isenabled for a particular ink, the values from the correspondingreplacement pattern register are ORed into the dot data. The output ofthe ink replacement process is then filtered so that error diffusion isonly allowed for the planes in which error diffusion is enabled. Theoutput of the ink replacement logic is ORed with the resultant dot afterdead nozzle removal. See Figure n page 565 on page Error! Bookmark notdefined. for implementation details.

For example if we consider the printhead color configurationC,M,Y,K₁,K₂,IR and the input dot data from the HCU is b101100. Assumingthat the K₁ ink plane and IR ink plane for this position are dead so thedead nozzle mask is b000101. The DNC first removes the dead nozzle byzeroing the K₁ plane to produce b101000. Then the dead nozzle mask isANDed with the dot data to give b000100 which selects the inkreplacement pattern for K₁ (in this case the ink replacement pattern forK₁ is configured as b000010, i.e. ink replacement into the K₂ plane).Providing error diffusion for K₂ is enabled, the output from the inkreplacement process is b000010. This is ORed with the output of deadnozzle removal to produce the resultant dot b101010. As can be seen thedot data in the defective K₁ nozzle was removed and replaced by a dot inthe adjacent K₂ nozzle in the same dot position, i.e. directsubstitution.

In the example above the K₁ ink plane could be compensated for byindirect substitution, in which case ink replacement pattern for K₁would be configured as b111000 (substitution into the CMY color planes),and this is ORed with the output of dead nozzle removal to produce theresultant dot b111000. Here the dot data in the defective K, ink planewas removed and placed into the CMY ink planes.

29.4.3 Error Diffusion

Based on the programming of the lookup table the dead nozzle may be leftactive after ink replacement. In such cases the DNC can compensate usingerror diffusion. Error diffusion is a mechanism where dead nozzle dotdata is diffused to adjacent dots.

When a dot is active and its destined nozzle is dead, the DNC willattempt to place the data into an adjacent dot position, if one isinactive. If both dots are inactive then the choice is arbitrary, and isdetermined by a pseudo random bit generator. If both neighbor dots arealready active then the bit cannot be compensated by diffusion.

Since the DNC needs to look at neighboring dots to determine where toplace the new bit (if required), the DNC works on a set of 3 dots at atime. For any given set of 3 dots, the first dot received from the HCUis referred to as dot A, and the second as dot B, and the third as dotC. The relationship is shown in FIG. 246.

For any given set of dots ABC, only B can be compensated for by errordiffusion if B is defined as dead. A 1 in dot B will be diffused intoeither dot A or dot C if possible. If there is already a 1 in dot A ordot C then a 1 in dot B cannot be diffused into that dot.

The DNC must support adjacent dead nozzles. Thus if dot A is defined asdead and has previously been compensated for by error diffusion, thenthe dot data from dot B should not be diffused into dot A. Similarly, ifdot C is defined as dead, then dot data from dot B should not bediffused into dot C.

Error diffusion should not cross line boundaries. If dot B contains adead nozzle and is the first dot in a line then dot A represents thelast dot from the previous line. In this case an active bit on a deadnozzle of dot B should not be diffused into dot A. Similarly, if dot Bcontains a dead nozzle and is the last dot in a line then dot Crepresents the first dot of the next line. In this case an active bit ona dead nozzle of dot B should not be diffused into dot C.

Thus, as a rule, a 1 in dot B cannot be diffused into dot A if

-   -   a 1 is already present in dot A,    -   dot A is defined as dead,    -   or dot A is the last dot in a line.

Similarly, a 1 in dot B cannot be diffused into dot C if

-   -   a 1 is already present in dot C,    -   dot C is defined as dead,    -   or dot C is the first dot in a line.

If B is defined to be dead and the dot value for B is 0, then nocompensation needs to be done and dots A and C do not need to bechanged.

If B is defined to be dead and the dot value for B is 1, then B ischanged to 0 and the DNC attempts to place the 1 from B into either A orC:

-   -   If the dot can be placed into both A and C, then the DNC must        choose between them. The preference is given by the current        output from the random bit generator, 0 for “prefer left”        (dot A) or 1 for “prefer right” (dot C).    -   If dot can be placed into only one of A and C, then the 1 from B        is placed into that position.

If dot cannot be placed into either one of A or C, then the DNC cannotplace the dot in either position. TABLE 199 Error Diffusion Truth Tablewhen dot B is dead Input A C OR OR A dead C dead OR OR Output A last inline B C first in line Rand'a A B C 0 0 0 X A input 0 C input 0 0 1 X Ainput 0 C input 0 1 0 0 1′b 0 C input 0 1 0 1 A input 0 1 0 1 1 X 1 0 Cinput 1 0 0 X A input 0 C input 1 0 1 X A input 0 C input 1 1 0 X Ainput 0 1 1 1 1 X A input 0 C inputTable 199 shows the truth table for DNC error diffusion operation whendot B is defined as dead.a. Output from random bit generator. Determines direction of errordiffusion (0 = left, 1 = right)b. Bold emphasis is used to show the DNC inserted a 1

Table 199 shows the truth table for DNC error diffusion operation whendot B is defined as dead.

-   a. Output from random bit generator. Determines direction of error    diffusion (0=left, 1=right)-   b. Bold emphasis is used to show the DNC inserted a 1

The random bit value used to arbitrarily select the direction ofdiffusion is generated by a 32-bit maximum length random bit generator.The generator generates a new bit for each dot in a line regardless ofwhether the dot is dead or not. The random bit generator can beinitialized with a 32-bit programmable seed value.

29.4.4 Fixative Correction

After the dead nozzle compensation methods have been applied to the dotdata, the fixative, if present, may need to be adjusted due to newnozzles being activated, or dead nozzles being removed. For each outputdot the DNC determines if fixative is required (using theFixativeRequiredMask register) for the new compensated dot data word andwhether fixative is activated already for that dot. For the DNC to do soit needs to know the color plane that has fixative, this is specified bythe FixativeMask1 configuration register. Table 200 indicates theactions to take based on these calculations. TABLE 200 Truth table forfixative correction Fixative Present Fixative required Action 1 1 Outputdot as is. 1 0 Clear fixative plane. 0 1 Attempt to add fixative. 0 0Output dot as is.

The DNC also allows the specification of another fixative plane,specified by the FixativeMask2 configuration register, withFixativeMask1 having the higher priority over FixativeMask2. Whenattempting to add fixative the DNC first tries to add it into the planesdefined by FixativeMask1. However, if any of these planes is dead thenit tries to add fixative by placing it into the planes defined byFixativeMask2.

Note that the fixative defined by FixativeMask1 and FixativeMask2 couldpossibly be multi-part fixative, i.e. 2 bits could be set inFixativeMask1 with the fixative being a combination of both inks.

29.5 Implementation

A block diagram of the DNC is shown in FIG. 247.

29.5.1 Definitions of I/O TABLE 201 DNC port list and description Portname Pins I/O Description Clocks and Resets Pclk 1 In System Clock.prst_n 1 In System reset, synchronous active low. PCU interfacepcu_dnc_sel 1 In Block select from the PCU. When pcu_dnc_sel is highboth pcu_adr and pcu_dataout are valid. pcu_rwn 1 In Commonread/not-write signal from the PCU. pcu_adr[6:2] 5 In PCU address bus.Only 5 bits are required to decode the address space for this block.pcu_dataout[31:0] 32 In Shared write data bus from the PCU. dnc_pcu_rdy1 Out Ready signal to the PCU. When dnc_pcu_rdy is high it indicates thelast cycle of the access. For a write cycle this means pcu_dataout hasbeen registered by the block and for a read cycle this means the data ondnc_pcu_datain is valid. dnc_pcu_datain[31:0] 32 Out Read data bus tothe PCU. DIU interface dnc_diu_rreq 1 Out DNC unit requests DRAM read. Aread request must be accompanied by a valid read address.dnc_diu_radr[21:5] 17 Out Read address to DIU, 256-bit word aligned.diu_dnc_rack 1 In Acknowledge from DIU that read request has beenaccepted and new read address can be placed on dnc_diu_radrdiu_dnc_rvalid 1 In Read data valid, active high. Indicates that validread data is now on the read data bus, diu_data. diu_data[63:0] 64 InRead data from DIU. HCU interface dnc_hcu_ready 1 Out Indicates that DNCis ready to accept data from the HCU. hcu_dnc_avail 1 In Indicates validdata present on hcu_dnc_data. hcu_dnc_data[5:0] 6 In Output bi-level dotdata in 6 ink planes. DWU interface dwu_dnc_ready 1 In Indicates thatDWU is ready to accept data from the DNC. dnc_dwu_avail 1 Out Indicatesvalid data present on dnc_dwu_data. dnc_dwu_data[5:0] 6 Out Outputbi-level dot data in 6 ink planes.29.5.2 Configuration Registers

The configuration registers in the DNC are programmed via the PCUinterface. Refer to section 21.8.2 on page 321 for the description ofthe protocol and timing diagrams for reading and writing registers inthe DNC. Note that since addresses in SoPEC are byte aligned and the PCUonly supports 32-bit register reads and writes, the lower 2 bits of thePCU address bus are not required to decode the address space for theDNC. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of dnc_pcu_datain. Table 202lists the configuration registers in the DNC. TABLE 202 DNCconfiguration registers Address Value on (DNC_base+) Register name #bitsreset Description Control registers 0x00 Reset 1 0x1 A write to thisregister causes a reset of the DNC. 0x04 Go 1 0x0 Writing 1 to thisregister starts the DNC. Writing 0 to this register halts the DNC. WhenGo is asserted all counters, flags etc. are cleared or given theirinitial value, but configuration registers keep their values. When Go isdeasserted the state- machines go to their idle states but all countersand configuration registers keep their values. This register can be readto determine if the DNC is running (1 = running, 0 = stopped). Setupregisters (constant during processing) 0x10 MaxDot 16 0x0000 This is themaximum dot number −1 present across a page. For example if a pagecontains 13824 dots, then MaxDot will be 13823. Note that this numbermay or may not be the same as the number of dots across the printhead assome margining may be introduced in the PHI. 0x14 LSFR 32 0x0000_0000The current value of the LFSR register used as the 32-bit maximum lengthrandom bit generator. Users can write to this register to program a seedvalue for the 32-bit maximum length random bit generator. Must not beall 1s for taps implemented in XNOR form. (It is expected that writing aseed value will not occur during the operation of the LFSR). This LSFRvalue could also have a possible use as a random source in program code.0x20 FixativeMask1 6 0x00 Defines the higher priority fixative plane(s).Bit 0 represents the settings for plane 0, bit 1 for plane 1 etc. Foreach bit: 1 = the ink plane contains fixative. 0 = the ink plane doesnot contain fixative. 0x24 FixativeMask2 6 0x00 Defines the lowerpriority fixative plane(s). Bit 0 represents the settings for plane 0,bit 1 for plane 1 etc. Used only when FixativeMask1 planes are dead. Foreach bit: 1 = the ink plane contains fixative. 0 = the ink plane doesnot contain fixative. 0x28 FixativeRequired 6 0x00 Identifies the inkplanes that require Mask fixative. Bit 0 represents the settings forplane 0, bit 1 for plane 1 etc. For each bit: 1 = the ink plane requiresfixative. 0 = the ink plane does not require fixative (e.g. ink isself-fixing) 0x30 DnTableStartAdr[21:5] 17 0x0_0000 Start address ofDead Nozzle Table in DRAM, specified in 256-bit words. 0x34DnTableEndAdr[21:5] 17 0x0_0000 End address of Dead Nozzle Table inDRAM, specified in 256-bit words, i.e. the location containing the lastentry in the Dead Nozzle Table. The Dead Nozzle Table should be alignedto a 256-bit boundary, if necessary it can be padded with null entries.0x40-0x54 PlaneReplacePattern[5:0] 6x6 0x00 Defines the ink replacementpattern for each of the 6 ink planes. PlaneReplacePattern[0] is the inkreplacement pattern for plane 0, PlaneReplacePattern[1] is the inkreplacement pattern for plane 1, etc. For each 6-bit replacement patternfor a plane, a 1 in any bit positions indicates the alternative inkplanes to be used for this plane. 0x58 DiffuseEnable 6 0x3F Defineswhether, after ink replacement, error diffusion is allowed to beperformed on each plane. Bit 0 represents the settings for plane 0, bit1 for plane 1 etc. For each bit: 1 = error diffusion is enabled 0 =error diffusion is disabled Debug registers (read only) 0x60DncOutputDebug 8 N/A Bit 7 = dwu_dnc_ready Bit 6 = dnc_dwu_avail Bits5-0 = dnc_dwu_data 0x64 DncReplaceDebug 14 N/A Bit 13 = edu_ready Bit 12= iru_avail Bits 11-6 = iru_dn_mask Bits 5-0 = iru_data 0x68DncDiffuseDebug 14 N/A Bit 13 = dwu_dnc_ready Bit 12 = dnc_dwu_availBits 11-6 = edu_dn_mask Bits 5-0 = edu_data29.5.3 Ink Replacement Unit

FIG. 248 shows a sub-block diagram for the ink replacement unit.

29.5.3.1 Control Unit

The control unit is responsible for reading the dead nozzle table fromDRAM and making it available to the DNC via the dead nozzle FIFO. Thedead nozzle table is read from DRAM in single 256-bit accesses,receiving the data from the DIU over 4 clock cycles (64-bits per cycle).The protocol and timing for read accesses to DRAM is described insection 20.9.1 on page 240. Reading from DRAM is implemented by means ofthe state machine shown in FIG. 249. All counters and flags should becleared after reset. When Go transitions from 0 to 1 all counters andflags should take their initial value. While the Go bit is 1, the statemachine requests a read access from the dead nozzle table in DRAMprovided there is enough space in its FIFO.

A modulo-4 counter, rd_count, is used to count each of the 64-bitsreceived in a 256-bit read access. It is incremented wheneverdiu_dnc_rvalid is asserted. When Go is 1, dn_table_radr is set todn_table_start_adr. As each 64-bit value is returned, indicated bydiu_dnc_rvalid being asserted, dn_table_radr is compared todn_table_end_adr.

-   -   If rd_count equals 3 and dn_table_radr equals dn_table_end_adr,        then dn_table_radr is updated to dn_table_start_adr.    -   If rd_count equals 3 and dn_table_radr does not equal        dn_table_end_adr, then dn_table_radr is incremented by 1.

A count is kept of the number of 64-bit values in the FIFO. Whendiu_dnc_rvalid is 1 data is written to the FIFO by asserting wr_en, andfifo_contents and fifo_wr_adr are both incremented.

When fifo_contents[3:0] is greater than 0 and edu_ready is 1,dnc_hcu_ready is asserted to indicate that the DNC is ready to acceptdots from the HCU. If hcu_dnc_avail is also 1 then a dotadv pulse issent to the GenMask unit, indicating the DNC has accepted a dot from theHCU, and iru_avail is also asserted. After Go is set, a single preloadpulse is sent to the GenMask unit once the FIFO contains data.

When a rd_adv pulse is received from the GenMask unit, fifo_rd_adr[4:0]is then incremented to select the next 16-bit value. Iffifo_rd_adr[1:0]=11 then the next 64-bit value is read from the FIFO byasserting rd_en, and fifo_contents[3:0] is decremented.

29.5.3.2 Dead Nozzle FIFO

The dead nozzle FIFO conceptually is a 64-bit input, and 16-bit outputFIFO to account for the 64-bit data transfers from the DIU, and theindividual 16-bit entries in the dead nozzle table that are used in theGenMask unit. In reality, the FIFO is actually 8 entries deep and64-bits wide (to accommodate two 256-bit accesses).

On the DRAM side of the FIFO the write address is 64-bit aligned whileon the GenMask side the read address is 16-bit aligned, i.e. the upper 3bits are input as the read address for the FIFO and the lower 2 bits areused to select 16 bits from the 64 bits (1st 16 bits read corresponds tobits 15-0, second 16 bits to bits 31-16 etc.).

29.5.3.3 GenMask Unit

The GenMask unit generates the 6-bit dn_mask that is sent to the replaceunit. It consists of a 10-bit delta counter and a mask register.

After Go is set, the GenMask unit will receive a preload pulse from thecontrol unit indicating the first dead nozzle table entry is availableat the output of the dead nozzle FIFO and should be loaded into thedelta counter and mask register. A rd_adv pulse is generated so that thenext dead nozzle table entry is presented at the output of the deadnozzle FIFO. The delta counter is decremented every time a dotadv pulseis received. When the delta counter reaches 0, it gets loaded with thecurrent delta value output from the dead nozzle FIFO, i.e. bits 15-6,and the mask register gets loaded with mask output from the dead nozzleFIFO, i.e. bits 5-0. A rd_adv pulse is then generated so that the nextdead nozzle table entry is presented at the output of the dead nozzleFIFO.

When the delta counter is 0 the value in the mask register is output asthe dn_mask, otherwise the dn_mask is all 0s.

The GenMask unit has no knowledge of the number of dots in a line, itsimply loads a counter to count the delta from one dead nozzle column tothe next. Thus as described in section 29.2 on page 472 the dead nozzletable should include null identifiers if necessary so that the deadnozzle table covers the first and last nozzle column in a line.

29.5.3.4 Replace Unit

Dead nozzle removal and ink replacement are implemented by thecombinatorial logic shown in FIG. 250. Dead nozzle removal is performedby bit-wise ANDing of the inverse of the dn_mask with the dot value.

The ink replacement mechanism has 6 ink replacement patterns, one perink plane, programmable by the CPU. The dead nozzle mask is ANDed withthe dot data to see if there are any planes where the dot is active butthe corresponding nozzle is dead. The resultant value forms an enable,on a per ink basis, for the ink replacement process. If replacement isenabled for a particular ink, the values from the correspondingreplacement pattern register are ORed into the dot data. The output ofthe ink replacement process is then filtered so that error diffusion isonly allowed for the planes in which error diffusion is enabled.

The output of the ink replacement process is ORed with the resultant dotafter dead nozzle removal. If the dot position does not contain a deadnozzle then the dn_mask will be all 0s and the dot, hcu_dnc_data, willbe passed through unchanged.

29.5.4 Error Diffusion Unit

FIG. 251 shows a sub-block diagram for the error diffusion unit.

29.5.4.1 Random Bit Generator

The random bit value used to arbitrarily select the direction ofdiffusion is generated by a maximum length 32-bit LFSR. The tap pointsand feedback generation are shown in FIG. 252. The LFSR generates a newbit for each dot in a line regardless of whether the dot is dead or not,i.e shifting of the LFSR is enabled when advdot equals 1. The LFSR canbe initialised with a 32-bit programmable seed value, random_seed. Thisseed value is loaded into the LFSR whenever a write occurs to theRandomSeed register. Note that the seed value must not be all 1 s asthis causes the LFSR to lock-up.

29.5.4.2 Advance Dot Unit

The advance dot unit is responsible for determining in a given cyclewhether or not the error diffuse unit will accept a dot from the inkreplacement unit or make a dot available to the fixative correct unitand on to the DWU. It therefore receives the dwu_dnc_ready controlsignal from the DWU, the iru_avail flag from the ink replacement unit,and generates dnc_dwu_avail and edu_ready control flags.

Only the dwu_dnc_ready signal needs to be checked to see if a dot can beaccepted and asserts edu_ready to indicate this. If the error diffuseunit is ready to accept a dot and the ink replacement unit has a dotavailable, then a advdot pulse is given to shift the dot into thepipeline in the diffuse unit. Note that since the error diffusionoperates on 3 dots, the advance dot unit ignores dwu_dnc_ready initiallyuntil 3 dots have been accepted by the diffuse unit. Similarlydnc_dwu_avail is not asserted until the diffuse unit contains 3 dots andthe ink replacement unit has a dot available.

29.5.4.3 Diffuse Unit

The diffuse unit contains the combinatorial logic to implement the truthtable from Table. The diffuse unit receives a dot consisting of 6 colorplanes (1 bit per plane) as well as an associated 6-bit dead nozzle maskvalue.

Error diffusion is applied to all 6 planes of the dot in parallel. Sinceerror diffusion operates on 3 dots, the diffuse unit has a pipeline of 3dots and their corresponding dead nozzle mask values.

The first dot received is referred to as dot A, and the second as dot B,and the third as dot C. Dots are shifted along the pipeline wheneveradvdot is 1. A count is also kept of the number of dots received. It isincremented whenever advdot is 1, and wraps to 0 when it reachesmax_dot. When the dot count is 0 dot C corresponds to the first dot in aline. When the dot count is 1 dot A corresponds to the last dot in aline.

In any given set of 3 dots only dot B can be defined as containing adead nozzle(s). Dead nozzles are identified by bits set in iru_dn_mask.If dot B contains a dead nozzle(s), the corresponding bit(s) in dot A,dot C, the dead nozzle mask value for A, the dead nozzle mask value forC, the dot count, as well as the random bit value are input to the truthtable logic and the dots A, B and C assigned accordingly. If dot B doesnot contain a dead nozzle then the dots are shifted along the pipelineunchanged.

29.5.5 Fixative Correction Unit

The fixative correction unit consists of combinatorial logic toimplement fixative correction as defined in Table 203. For each outputdot the DNC determines if fixative is required for the new compensateddot data word and whether fixative is activated already for that dot. FixativePresent = ((FixativeMask1 | FixativeMask2) & edu_data) != 0 FixativeRequired = (FixativeRequiredMask & edu_data) != 0

It then looks up the truth table to see what action, if any, needs to betaken. TABLE 203 Truth table for fixative correction Fixative FixativePresent required Action Output 1 1 Output dot as is. dnc_dwu_data =edu_data 1 0 Clear fixative plane. dnc_dwu_data = (edu_data) &˜(FixativeMask1 | FixativeMask2) 0 1 Attempt to add fixative. if(FixativeMask1 & DnMask) != 0  dnc_dwu_data = (edu_data) |(FixativeMask2 & ˜DnMask) else  dnc_dwu_data = (edu_data) |(FixativeMask1) 0 0 Output dot as is. dnc_dwu_data = edu_data

When attempting to add fixative the DNC first tries to add it into theplane defined by FixativeMask1. However, if this plane is dead then ittries to add fixative by placing it into the plane defined byFixativeMask2. Note that if both FixativeMask1 and FixativeMask2 areboth all 0s then the dot data will not be changed.

30 Dotline Writer Unit (DWU)

30.1 Overview

The Dotline Writer Unit (DWU) receives 1 dot (6 bits) of colorinformation per cycle from the DNC. Dot data received is bundled into256-bit words and transferred to the DRAM. The DWU (in conjunction withthe LLU) implements a dot line FIFO mechanism to compensate for thephysical placement of nozzles in a printhead, and provides data ratesmoothing to allow for local complexities in the dot data generatepipeline.

30.2 Physical Requirement Imposed by the Printhead

The physical placement of nozzles in the printhead means that in onefiring sequence of all nozzles, dots will be produced over several printlines. The printhead consists of 12 rows of nozzles, one for each colorof odd and even dots. Odd and even nozzles are separated by D₂ printlines and nozzles of different colors are separated by D₁ print lines.See FIG. 254 for reference. The first color to be printed is the firstrow of nozzles encountered by the incoming paper. In the example this iscolor 0 odd, although is dependent on the printhead type (see [10] forother printhead arrangments). Paper passes under printhead movingdownwards.

For example if the physical separation of each half row is 80 μmequating to D₁=D₂=5 print lines at 1600 dpi. This means that in onefiring sequence, color 0 odd nozzles will fire on dotline L, color 0even nozzles will fire on dotline L-D₁, color 1 odd nozzles will fire ondotline L-D₁-D₂ and so on over 6 color planes odd and even nozzles. Thetotal number of lines fired over is given as 0+5+5 . . . +5=0+11×5=55.See FIG. 255 for example diagram.

It is expected that the physical spacing of the printhead nozzles willbe 80 μm (or 5 dot lines), although there is no dependency on nozzlespacing. The DWU is configurable to allow other line nozzle spacings.TABLE 204 Relationship between Nozzle color/sense and line firing Evenline Odd line encountered encountered first first Color Sense line senseline Color 0 Even L even L-5 Odd L-5 odd L Color 1 Even L-10 even L-15Odd L-15 odd L-10 Color 2 Even L-20 even L-25 Odd L-25 odd L-20 Color 3Even L-30 even L-35 Odd L-35 odd L-30 Color 4 Even L-40 even L-45 OddL-45 odd L-40 Color 5 Even L-50 even L-55 Odd L-55 odd L-5030.3 Line Rate De-Coupling

The DWU block is required to compensate for the physical spacing betweenlines of nozzles. It does this by storing dot lines in a FIFO (in DRAM)until such time as they are required by the LLU for dot data transfer tothe printhead interface. Colors are stored separately because they areneeded at different times by the LLU. The dot line store must storeenough lines to compensate for the physical line separation of theprinthead but can optionally store more lines to allow system level datarate variation between the read (printhead feed) and write sides (dotdata generation pipeline) of the FIFOs.

A logical representation of the FIFOs is shown in FIG. 256, where N isdefined as the optional number of extra half lines in the dot line storefor data rate de-coupling.

30.4 Dot Line Store Storage Requirements

For an arbitrary page width of d dots (where d is even), the number ofdots per half line is d/2.

For interline spacing of D₂ and inter-color spacing of D₁, with C colorsof odd and even half lines, the number of half line storage is(C−1)(D₂+D₁)+D1.

For N extra half line stores for each color odd and even, the storage isgiven by (N*C*2).

The total storage requirement is ((C−1)(D₂+D₁)+D1+(N*C*2))*d/2 in bits.

Note that when determining the storage requirements for the dot linestore, the number of dots per line is the page width and not necessarilythe printhead width. The page width is often the dot margin number ofdots less than the printhead width. They can be the same size for fullbleed printing.

For example in an A4 page a line consists of 13824 dots at 1600 dpi, or6912 dots per half dot line. To store just enough dot lines to accountfor an inter-line nozzle spacing of 5 dot lines it would take 55 halfdot lines for color 5 odd, 50 dot lines for color 5 even and so on,giving 55+50+45 . . . 10+5+0=330 half dot lines in total. If it isassumed that N=4 then the storage required to store 4 extra half linesper color is 4×12=48, in total giving 330+48=378 half dot lines. Eachhalf dot line is 6912 dots, at 1 bit per dot give a total storagerequirement of 6912 dots×378 half dot lines/8 bits=Approx 319 Kbytes.Similarly for an A3 size page with 19488 dots per line, 9744 dots perhalf line×378 half dot lines/8=Approx 899 Kbytes. TABLE 205 Storagerequirement for dot line store Lines Storage Lines Storage Page Nozzlerequired (N = 0) required (N = 4) size Spacing (N = 0) Kbytes (N = 4)Kbytes A4 4 264 223 312 263 5 330 278 378 319 A3 4 264 628 312 742 5 330785 378 899

The potential size of the dot line store makes it unfeasible to beimplemented in on-chip SRAM, requiring the dot line store to beimplemented in embedded DRAM. This allows a configurable dotline storewhere unused storage can be redistributed for use by other parts of thesystem.

30.5 Nozzle Row Skew

Due to construction limitations of the bi-lithic printhead it ispossible that nozzle rows may be misaligned relative to each other. Oddand even rows, and adjacent color rows may be horizontally misaligned byup to 2 dot positions. Vertical misalignment can also occur but iscompensated for in the LLU and not considered here. The DWU is requiredto compensate for the horizontal misalignment.

Dot data from the HCU (through the DNC) produces a dot of 6 colors alldestined for the same physical location on paper. If the nozzle rows inthe printhead are aligned as shown in FIG. 254 then no adjustment of thedot data is needed.

A conceptual misaligned printhead is shown in FIG. 257. The exact shapeof the row alignment is arbitrary, although is most likely to be sloping(if sloping, it could be sloping in either direction). The DWU isrequired to adjust the shape of the dot streams to take account of thejoin between printhead ICs. The introduction of the join shape beforethe data is written to the DRAM means that the PHI sees a singlecrossover point in the data since all lines are the same length and thecrossover point (since all rows are of equal length) is a verticalline—i.e. the crossover is at the same time for all even rows, and atthe same time for all odd rows as shown in FIG. 258.

To insert the shape of the join into the dot stream, for each line wemust first insert the dots for non-printable area 1, then the printablearea data (from the DNC), and then finally the dots for non-printablearea 2. This can also be considered as: first produce the dots fornon-printable area 1 for line n, and then a repetition of:

-   -   produce the dots for the printable area for line n (from the        DNC)    -   produce the dots for the non-printable area 2 (for line n)        followed by the dots of non-printable area 1 (for line n+1)

The reason for considering the problem this way is that regardless ofthe shape of the join, the shape of non-printable area 2 merged with theshape of non-printable area 1 will always be a rectangle since thewidths of non-printable areas 1 and 2 are identical and the lengths ofeach row are identical. Hence step 2 can be accomplished by simplyinserting a constant number (MaxNozzleSkew) of 0 dots into the stream.

For example, if the color n even row non-printable area 1 is of lengthX, then the length of color n even row non-printable area 2 will be oflength MaxNozzleSkew−X. The split between non-printable areas 1 and 2 isdefined by the NozzleSkew registers.

Data from the DNC is destined for the printable area only, the DWU mustgenerate the data destined for the non-printable areas, and insert DNCdot data correctly into the dot data stream before writing dot data tothe fifos. The DWU inserts the shape of the misalignment into the dotstream by delaying dot data destined to different nozzle rows by therelative misalignment skew amount.

30.6 Local Buffering

An embedded DRAM is expected to be of the order of 256 bits wide, whichresults in 27 words per half line of an A4 page, and 54 words per halfline of A3. This requires 27 words×12 half colors (6 colors odd andeven)=324×256-bit DRAM accesses over a dotline print time, equating to 6bits per cycle (equal to DNC generate rate of 6 bits per cycle). Eachhalf color is required to be double buffered, while filling one bufferthe other buffer is being written to DRAM. This results in 256 bits×2buffers×12 half colors i.e. 6144 bits in total.

The buffer requirement can be reduced, by using 1.5 buffering, where theDWU is filling 128 bits while the remaining 256 bits are being writtento DRAM. While this reduces the required buffering locally it increasesthe peak bandwidth requirement to the DRAM. With 2× buffering theaverage and peak DRAM bandwidth requirement is the same and is 6 bitsper cycle, alternatively with 1.5× buffering the average DRAM bandwidthrequirement is 6 bits per cycle but the peak bandwidth requirement is 12bits per cycle. The amount of buffering used will depend on the DRAMbandwidth available to the DWU unit.

Should the DWU fail to get the required DRAM access within the specifiedtime, the DWU will stall the DNC data generation. The DWU will issue thestall in sufficient time for the DNC to respond and still not cause aFIFO overrun. Should the stall persist for a sufficiently long time, thePHI will be starved of data and be unable to deliver data to theprinthead in time. The sizing of the dotline store FIFO and internalFIFOs should be chosen so as to prevent such a stall happening.

30.7 Dotline Data in Memory

The dot data shift register order in the printhead is shown in FIG. 254(the transmit order is the opposite of the shift register order). In theexample the type 0 printhead IC transmit order is increasing even colordata followed by decreasing odd color data. The type 1 printhead ICtransmit order is decreasing odd color data followed by increasing evencolor data. For both printhead ICs the even data is always increasingorder and odd data is always decreasing. The PHI controls whichprinthead IC data gets shifted to.

From this it is beneficial to store even data in increasing order inDRAM and odd data in decreasing order. While this order suits theexample printhead, other printheads exist where it would be beneficialto store even data in decreasing order, and odd data in increasingorder, hence the order is configurable. The order that data is stored inmemory is controlled by setting the ColorLineSense register.

The dot order in DRAM for increasing and decreasing sense is shown inFIG. 260 and FIG. 261 respectively. For each line in the dot store theorder is the same (although for odd lines the numbering will bedifferent the order will remain the same). Dot data from the DNC isalways received in increasing dot number order. For increasing sense dotdata is bundled into 256-bit words and written in increasing order inDRAM, word 0 first, then word 1, and so on to word N, where N is thenumber of words in a line.

For decreasing sense dot data is also bundled into 256-bit words, but iswritten to DRAM in decreasing order, i.e. word N is written first thenword N−1 and so on to word 0. For both increasing and decreasing sensethe data is aligned to bit 0 of a word, i.e. increasing sense alwaysstarts at bit 0, decreasing sense always finishes at bit 0.

Each half color is configured independently of any other color. TheColorBaseAdr register specifies the position where data for a particulardotline FIFO will begin writing to. Note that for increasing sensecolors the ColorBaseAdr register specifies the address of the first wordof first line of the fifo, whereas for decreasing sense colors theColorBaseAdr register specifies the address of last word of the firstline of the FIFO.

Dot data received from the DNC is bundled in 256-bit words andtransferred to the DRAM. Each line of data is stored consecutively inDRAM, with each line separated by ColorLineInc number of words.

For each line stored in DRAM the DWU increments the line count andcalculates the DRAM address for the next line to store.

This process continues until ColorFifoSize number of lines are stored,after which the DRAM address will wrap back to the ColorBaseAdr address.

As each line is written to the FIFO, the DWU increments theFifoFillLevel register, and as the LLU reads a line from the FIFO theFifoFillLevel register is decremented. The LLU indicates that it hascompleted reading a line by a high pulse on the llu_dwu_line_rd line.

When the number of lines stored in the FIFO is equal to theMaxWriteAhead value the DWU will indicate to the DNC that it is nolonger able to receive data (i.e. a stall) by deasserting thedwu_dnc_ready signal.

The ColorEnable register determines which color planes should beprocessed, if a plane is turned off, data is ignored for that plane andno DRAM accesses for that plane are generated.

30.8 Specifying Dot FIFOs

The dot line FIFOs when accessed by the LLU are specified differentlythan when accessed by the DWU. The DWU uses a start address and numberof lines value to specify a dot FIFO, the LLU uses a start and endaddress for each dot FIFO. The mechanisms differ to allow more efficientimplementations in each block.

As a result of limitations in the LLU the dot FIFOs must be specifiedcontiguously and increasing in DRAM. See section 31.6 on page 504 forfurther information.

30.9 Implementation

30.9.1 Definitions of I/O TABLE 206 DWU I/O Definition Port name PinsI/O Description Clocks and Resets Pclk 1 In System Clock prst_n 1 InSystem reset, synchronous active low DNC Interface dwu_dnc_ready 1 OutIndicates that DWU is ready to accept data from the DNC. dnc_dwu_avail 1In Indicates valid data present on dnc_dwu_data. dnc_dwu_data[5:0] 6 InInput bi-level dot data in 6 ink planes. LLU Interface dwu_llu_line_wr 1Out DWU line write. Indicates that the DWU has completed a full linewrite. Active high llfu_dwu_line_rd 1 In LLU line read. Indicates thatthe LLU has completed a line read. Active high. PCU Interfacepcu_dwu_sel 1 In Block select from the PCU. When pcu_dwu_sel is highboth pcu_adr and pcu_dataout are valid. pcu_rwn 1 In Commonread/not-write signal from the PCU. pcu_adr[7:2] 6 In PCU address bus.Only 6 bits are required to decode the address space for this block.pcu_dataout[31:0] 32 In Shared write data bus from the PCU. dwu_pcu_rdy1 Out Ready signal to the PCU. When dwu_pcu_rdy is high it indicates thelast cycle of the access. For a write cycle this means pcu_dataout hasbeen registered by the block and for a read cycle this means the data ondwu_pcu_datain is valid. dwu_pcu_datain[31:0] 32 Out Read data bus tothe PCU. DIU Interface dwu_diu_wreq 1 Out DWU requests DRAM write. Awrite request must be accompanied by a valid write address together withvalid write data and a write valid. dwu_diu_wadr[21:5] 17 Out Writeaddress to DIU 17 bits wide (256-bit aligned word) diu_dwu_wack 1 InAcknowledge from DIU that write request has been accepted and new writeaddress can be placed on dwu_diu_wadr dwu_diu_data[63:0] 64 Out Datafrom DWU to DIU. 256-bit word transfer over 4 cycles First 64-bits isbits 63:0 of 256 bit word Second 64-bits is bits 127:64 of 256 bit wordThird 64-bits is bits 191:128 of 256 bit word Fourth 64-bits is bits255:192 of 256 bit word dwu_diu_wvalid 1 Out Signal from DWU indicatingthat data on dwu_diu_data is valid.30.9.2 DWU Partition30.9.3 Configuration Registers

The configuration registers in the DWU are programmed via the PCUinterface. Refer to section 21.8.2 on page 321 for a description of theprotocol and timing diagrams for reading and writing registers in theDWU. Note that since addresses in SoPEC are byte aligned and the PCUonly supports 32-bit register reads and writes, the lower 2 bits of thePCU address bus are not required to decode the address space for theDWU. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of dwu_pcu_data. Table 207 liststhe configuration registers in the DWU. TABLE 207 DWU registersdescription Address DWU_base+ Register #bits Reset Description ControlRegisters 0x00 Reset 1 0x1 Active low synchronous reset, self de-activating. A write to this register will cause a DWU block reset. 0x04Go 1 0x0 Active high bit indicating the DWU is programmed and ready touse. A low to high transition will cause DWU block internal states toreset (configuration registers are not reset). Dot Line StoreConfiguration 0x08-0x34 ColorBaseAdr[11:0][21:5] 12x17 0x000 00Specifies the base address (in words) in memory where data from aparticular half color (N) will be placed. For increasing sense colorsthe ColorBase- Adr register specifies the address of the first word offirst line of the fifo, whereas for decreasing sense colors theColorBaseAdr register specifies the address of last word of the firstline of the fifo. 0x38-0x64 ColorFifoSize[11:0] 12x8 0x00 Indicates thenumber of lines in the FIFO before the line increment will wrap aroundin memory. Bus 0, 1 - Even, Odd line color 0 Bus 2, 3 - Even, Odd linecolor 1 Bus 4, 5 - Even, Odd line color 2 Bus 6, 7 - Even, Odd linecolor 3 Bus 8, 9 - Even, Odd line color 4 Bus 10, 11 - Even, Odd linecolor 5 0x68 ColorLineSense 2 0x2 Specifies whether data written to DRAMfor this half color is increasing or decreasing sense 0 - Decreasingsense 1 - Increasing sense Bit 0 Defines even color sense, Bit 1 Definesodd color sense. 0x6C ColorEnable 6 0x3F Indicates whether a particularcolor is active or not. When inactive no data is written to DRAM forthat color. 0 - Color off 1 - Color on One bit per color, bit 0 is Color0 and so on. 0x70 MaxWriteAhead 8 0x00 Specifies the maximum number oflines that the DWU can be ahead of the LLU 0x74 LineSize 16 0x000 0Indicates the number of dots per line produced by the DWU. 0x78MaxNozzle 4 0x0 Specifies the number of dot-pairs the Skew DWU needs togenerate to flush the data skew buffers. Corresponds to thenon-printable area of the printhead. 0x7C-0xA8 NozzleSkew 12x4 0x0Specifies the relative skew of dot data nozzle rows in the printhead.Valid range is 0 (no skew) through to 12. Units represent dot-pairs, askew of 1 for a row represents two dots on the page. Bus 0, 1 - Even,Odd line color 0 Bus 2, 3 - Even, Odd line color 1 Bus 4, 5 - Even, Oddline color 2 Bus 6, 7 - Even, Odd line color 3 Bus 8, 9 - Even, Odd linecolor 4 Bus 10, 11 - Even, Odd line color 5 0xAC ColorLineInc 8 0x00Specifies the number of words (256-bit words) per dot line −1. WorkingRegisters 0xB0 LineDotCnt 16 0x000 0 Indicates the number of remainingdots in the current line. (Read Only) 0xB4 FifoFillLevel 8 0x00 Numberof lines in the FIFO, written to but not read. (Read Only)

A low to high transition of the Go register causes the internal statesof the DWU to be reset. All configuration registers will remain thesame. The block indicates the transition to other blocks via thedwu_go_pulse signal.

30.9.4 Data Skew

The data skew block inserts the shape of the printhead join into the dotdata stream by delaying dot data by the relative nozzle skew amount(given by nozzle_skew). It generates zero fill data introducedintroduced into the dot data stream to achieve the relative skew (andalso to flush dot data from the delay registers).

The data skew block consists of 12 12-bit shift registers, one per colorodd and even. The shift registers are in groups of 6, one group for evencolors, and one for odd colors. Each time a valid data word is receivedfrom the DNC the dot data is shifted into either the odd or even groupof shift registers. The odd_even_sel register determines which group ofshift registers are valid for that cycle and alternates for each newvalid data word. When a valid word is received for a group of shiftregisters, the shift register is shifted by one location with the newdata word shifted into the registers (the top word in the register willbe discarded).

When the dot counter determines that the data skew block should zerofill (zero_fill), the data skew block will shift zero dot data into theshift registers until the line has completed. During this time the DNCwill be stalled by the de-assertion of the dwu_dnc_ready signal.

The data skew block selects dot data from the shift registers and ispassed to the buffer address generator block. The data bits selected isdetermined by the configured index values in the NozzleSkew registers.// determine when data is valid data_valid = (((dnc_dwu_avail ==1)OR(zero_fill == 1)) AND (dwu_ready ==1)) // implement the zero fillmux if (zero_fill == 1) then  dot_data_in = 0 else  dot_data_in =dnc_dwu_data // the data delay buffers if (dwu_go_pulse ==1) then data_delay[1:0][11:0][5:0]  = 0      // reset all delay bufferodd=1,even=0  odd_even_sel       = 0 elsif (data_valid == 1) then { odd_even_sel = ˜odd_even_sel  // upVdate the odd/even buffers, withshift  data_delay[odd_even_sel][11:1][5:0]=data_delay[odd_even_sel][10:0][5:0] // shift data  data delay[odd evensel][0][5:0]  =  dot data in[5:0] // shift in new data  // select thecorrect output data  for (i=0;i<6; i++) {   // skew selector  skew  =   nozzle skew[   {i,odd even sel}   ] // temporary variable  // data select array, include data delay and input dot data  data_select[12:0]  =  {data_delay[odd_even_sel][11:0], dot_data_in}  // mux output the data word to next block (13 to 1 mux)   dot_data[i]= data_select[skew][i]   }  }30.9.5 Fifo Fill Level

The DWU keeps a running total of the number of lines in the dot storeFIFO. Each time the DWU writes a line to DRAM (determined by the DIUinterface subblock and signalled via line_wr) it increments thefilllevel and signals the line increment to the LLU (pulse ondwu_llu_line_wr). Conversely if it receives an active llu_dwu_line_rdpulse from the LLU, the filllevel is decremented. If the filllevelincreases to the programmed max level (max_write_ahead) then the DWUstalls and indicates back to the DNC by de-asserting the dwu_dnc_readysignal.

If one or more of the DIU buffers fill, the DIU interface signals thefill level logic via the buf_full signal which in turn causes the DWU tode-assert the dwu_dnc_ready signal to stall the DNC. The buf_fullsignals will remain active until the DIU services a pending request fromthe full buffer, reducing the buffer level.

When the dot counter block detects that it needs to insert zero filldots (zero_fill equals 1) the DWU will stall the DNC while the zero dotsare being generated (by de-asserting dwu_dnc_ready), but will allow thedata skew block to generate zero fill data (the dwu_ready signal).dwu_dnc_ready  =  ˜((buf_full==  1)  OR  (filllevel  == max_write_ahead) OR (zero_fill == 1))dwu_ready       = ˜((buf_full== 1)  OR  (filllevel == max_write_ahead ))

The DWU does not increment the fill level until a complete line of dotdata is in DRAM not just a complete line received from the DNC. Thisensures that the LLU cannot start reading a partial line from DRAMbefore the DWU has finished writing the line.

The fill level is reset to zero each time a new page is started, onreceiving a pulse via the dwu_go_pulse signal.

The line fifo fill level can be read by the CPU via the PCU at any timeby accessing the FifoFillLevel register.

30.9.6 Buffer Address Generator

30.9.6.1 Buffer Address Generator Description

The buffer address generator subblock is responsible for accepting datafrom the data skew block and writing it to the DIU buffers in thecorrect order.

The buffer address and active bit-write for a particular dot data writeis calculated by the buffer address generator based on the dot count ofthe current line, programmed sense of the color and the line size.

All configuration registers should be programmed while the Go bit is setto zero, once complete the block can be enabled by setting the Go bit toone. The transition from zero to one will cause the internal states toreset.

If the color_line_sense signal for a color is one (i.e. increasing) thenthe bit-write generation is straight forward as dot data is aligned witha 256-bit boundary. So for the first dot in that color, the bit 0 of thewr_bit bus will be active (in buffer word 0), for the second dot bit 1is active and so on to the 255^(th) dot where bit 63 is active (inbuffer word 3). This is repeated for all 256-bit words until the finalword where only a partial number of bits are written before the word istransferred to DRAM.

If color_line_sense signal for a color is zero (i.e. decreasing) thebit-write generation for that color is adjusted by an offset calculatedfrom the pre-programmed line length (line_size). The offset adjusts thebit write to allow the line to finish on a 256-bit boundary. For exampleif the line length was 400, for the first dot received bit 7 (linelength is halved because of odd/even lines of color) of the wr_bit isactive (buffer word 3), the second bit 6 (buffer word 3), to the200^(th) dot of data with bit 0 of wr_bit active (buffer word 0).

30.9.6.2 Bit-Write Decode

The buffer address generator contains 2 instances of the bit-writedecode, one configured for odd dot data the other for even. The counter(either up or down counter) used to generate the addresses is selectedby the color_line_sense signal. Each block determines if it is active onthis cycle by comparing its configured type with the current dot countaddress and the data_active signal.

The wr_bit bus is a direct decoding of the lower 6 count bits(count[6:1]), and the DIU buffer address is the remaining higher bits ofthe counter (count[10:7]).

The signal generation is given as follows: // determine the counter touse if (color_line_sense == 1 )  count = up_cnt[10:0] else  count =dn_cnt[10:0] // determine if active, based on instance type wr_en      =data_active & (count[0] {circumflex over ( )} odd_even_type) // odd =1,even =0 // determine the bit write value wr_bit[63:0]   =decode(count[6:1]) // determine the buffer 64-bit address wr_adr[3:0]  =count[10:7]30.9.6.3 Up Counter Generator

The up counter increments for each new dot and is used to determine thewrite position of the dot in the DIU buffers for increasing sense data.At the end of each line of dot data (as indicated by line_fin), thecounter is rounded up to the nearest 256-bit word boundary. This causesthe DIU buffers to be flushed to DRAM including any partially filled256-bit words. The counter is reset to zero if the dwu_go_pulse is one.// Up-Counter Logic if (dwu_go_pulse == 1) then {  up_cnt[10:0] = 0elsif (line_fin == 1 ) then  // round up  if (up_cnt[8:1] != 0)  up_cnt[10:9]++  else   up_cnt[10:9]  // bit-selector  up_cnt[7:0]=0elsif (data_valid == 1) then  up_cnt[7:0]++30.9.6.4 Down Counter Generator

The down counter logic decrements for each new dot and is used todetermine the write position of the dot in the DUI buffers fordecreasing sense data. When the dwu_go_pulse bit is one the lower bits(i.e. 8 to 0) of the counter are reset to line size value (line_size),and the higher bits to zero. The bits used to determine the bit-writevalues and 64-bit word addresses in the DIU buffers begin at line sizeand count down to zero. The remaining higher bits are used to determinethe DIU buffer 256-bit address and buffer fill level, begin at zero andcount up. The counter is active when valid dot data is present, i.e.data_valid equals 1.

When the end of line is detected (line_fin equals 1) the counter isrounded to the next 256-bit word, and the lower bits are reset to theline size value. //Down-Counter Logic if (dwu_go_pulse == 1) then dn_cnt[8:0] = line_size[8:0]  dn_cnt[10:9] = 0 elsif (line_fin == 1 )then  // perform rounding up  if (dn_cnt[8:1] != 0)   dn_cnt[10:9]++ else   dn_cnt[10:9]  // bit-select is reset dn_cnt[8:0]=line_size[8:0]  // bit select bits elsif (data_valid == 1)then  dn_cnt[8:0] −−  dn_cnt[10:9]++30.9.6.5 Dot Counter

The dot counter simply counts each active dot received from the dataskew block. It sets the counter to line_size and decrements each time avalid dot is received. When the count equals zero the line_fin signal ispulsed and the counter is reset to line_size.

When the count is less than the max_nozzle_skew* 2 value the dot counterindicates to the data skew block to zero fill the remainder of the line(via the zero_fill signal). Note that the max_nozzle_skew units aredot-pairs as opposed to dots, hence the by 2 multiplication forcomparison with the dot counter.

The counter is reset to line_size when dwu_go_pulse is 1.

30.9.7 DIU Buffer

The DIU buffer is a 64 bit×8 word dual port register array with bitwrite capability. The buffer could be implemented with flip-flops shouldit prove more efficient.

30.9.8 DIU Interface

30.9.8.1 DIU Interface General Description

The DIU interface determines when a buffer needs a data word to betransferred to DRAM. It generates the DRAM address based on the dot lineposition, the color base address and the other programmed parameters. Awrite request is made to DRAM and when acknowledged a 256-bit data wordis transferred. The interface determines if further words need to betransferred and repeats the transfer process.

If the FIFO in DRAM has reached its maximum level, or one of the buffershas temporarily filled, the DWU will stall data generation from the DNC.

A similar process is repeated for each line until the end of page isreached. At the end of a page the CPU is required to reset the internalstate of the block before the next page can be printed. A low to hightransition of the Go register will cause the internal block reset, whichcauses all registers in the block to reset with the exception of theconfiguration registers. The transition is indicated to subblocks by apulse on dwu_go_pulse signal.

30.9.8.2 Interface Controller

The interface controller state machine waits in Idle state until anactive request is indicated by the read pointer (via the req_activesignal). When an active request is received the machine proceeds to theColorSelect state to determine which buffers need a data transfer. Inthe ColorSelect state it cycles through each color and determines if thecolor is enabled (and consequently the buffer needs servicing), ifenabled it jumps to the Request state, otherwise the color_cnt isincremented and the next color is checked.

In the Request state the machine issues a write request to the DIU andwaits in the Request state until the write request is acknowledged bythe DIU (diu_dwu_wack). Once an acknowledge is received the statemachine clocks through 4 cycles transferring 64-bit data words eachcycle and incrementing the corresponding buffer read address. Aftertransferring the data to the DIU the machine returns to the ColorSelectstate to determine if further buffers need servicing. On the transitionthe controller indicates to the address generator (adr_update) to updatethe address for that selected color.

If all colors are transferred (color_cnt equal to 6) the state machinereturns to Idle, updating the last word flags (group_fin) and requestlogic (req_update).

The dwu_diu_wvalid signal is a delayed version of the buf_rd_en signalto allow for pipeline delays between data leaving the buffer and beingclocked through to the DIU block.

The state machine will return from any state to Idle if the reset or thedwu_go_pulse is 1.

30.9.8.3 Address Generator

The address generator block maintains 12 pointers (color adr[11:0]) toDRAM corresponding to current write address in the dot line store foreach half color. When a DRAM transfer occurs the address pointer is usedfirst and then updated for the next transfer for that color. The pointerused is selected by the req_sel bus, and the pointer update is initiatedby the adr_update signal from the interface controller.

The pointer update is dependent on the sense of the color of thatpointer, the pointer position in a line and the line position in theFIFO. The programming of the color_base_adr needs to be adjusteddepending of the sense of the colors. For increasing sense colors thecolor_base_adr specifies the address of the first word of first line ofthe fifo, whereas for decreasing sense colors the color_base_adrspecifies the address of last word of the first line of the FIFO.

For increasing colors, the initialization value (i.e. when dwu_go_pulseis 1) is the color_base_adr.

For each word that is written to DRAM the pointer is incremented. If theword is the last word in a line (as indicated by last_wd from that readpointers) the pointer is also incremented. If the word is the last wordin a line, and the line is the last line in the FIFO (indicated byfifo_end from the line counter) the pointer is reset to color_base_adr.

In the case of decreasing sense colors, the initialization value (i.e.when dwu_go_pulse is 1) is the color_base_adr. For each line ofdecreasing sense color data the pointer starts at the line end anddecrements to the line start. For each word that is written to DRAM thepointer is decremented. If the word is the last word in a line thepointer is incremented by color_line_inc*2+1. One line length to accountfor the line of data just written, and another line length for the nextline to be written. If the word is the last word in a line, and the lineis the last line in the FIFO the pointer is reset to the initializationvalue (i.e. color_base_adr).

The address is calculated as follows: if (dwu_go_pulse == 1) then color_adr[11:0] = color_base_adr[11:0][21:5] elsif (adr_update == 1)then {  // determine the color  color = req_sel[3:0]  // line end andfifo wrap  if ((fifo_end[color] == 1) AND (last_wd == 1)) then {   //line end and fifo wrap   color_adr[color] = color_base_adr[color][21:5]  } elsif ( last_wd == 1) then {   // just a line end no fifo wrap  if (color_line_sense[color % 2] == 1) then  // increasing sense   color_adr[color] ++   else                   // decreasing sense   color_adr[color]  =  color_adr[color]   +   ( color_line_inc * 2) + 1  }  else {   // regular word write  if (color_line_sense[color % 2] == 1) then  // increasing sense   color_adr[color]++   else               // decreasing sense   color_adr[color]−−   }  } // select the correct address, for thistransfer dwu_diu_wadr = color_adr[req_sel]30.9.8.4 Line Count

The line counter logic counts the number of dot data lines stored inDRAM for each color. A separate pointer is maintained for each color. Aline pointer is updated each time the final word of a line istransferred to DRAM. This is determined by a combination of adr_updateand last_wd signals. The pointer to update is indicated by the req_selbus.

When an update occurs to a pointer it is compared to zero, if it isnon-zero the count is decremented, otherwise the counter is reset tocolor_fifo_size. If a counter is zero the fifo_end signals is set highto indicates to the address generator block that the line is the lastline of this colors fifo.

If the dwu_go_pulse signal is one the counters are reset tocolor_fifo_size. if (dwu_go_pulse == 1) then  line_cnt[11:0] =color_fifo_size[11:0] elsif ((adr_update == 1) AND (last_wd == 1)) then{  // determine the pointer to operate on  color = req_sel[3:0]  //update the pointer  if (line_cnt[color] == 0) then   line_cnt[color] =color_fifo_size[color]  else   line_cnt[i] −−  } // count is zero itsthe last line of fifo for(i=0 ;i <12;i++){  fifo_end[i] = (line_cnt[i]== 0)  }30.9.8.5 Read Pointer

The read pointer logic maintains the buffer read address pointers. Theread pointer is used to determine which 64-bit words to read from thebuffer for transfer to DRAM.

The read pointer logic compares the read and write pointers of each DIUbuffer to determine which buffers require data to be transferred toDRAM, and which buffers are full (the buf_full signal).

Buffers are grouped into odd and even buffers groups. If an odd bufferrequires DRAM access the odd_pend signals will be active, if an evenbuffer requires DRAM access the even_pend signals will be active. Ifboth odd and even buffers require DRAM access at exactly the same time,the even buffers will get serviced first. If a group of odd buffers arebeing serviced and an even buffer becomes pending, the odd group ofbuffers will be completed before the starting the even group, and viceversa.

If any buffer requires a DRAM transfer, the logic will indicate to theinterface controller via the req_active signal, with the odd_even_selsignal determining which group of buffers get serviced. The interfacecontroller will check the color_enable signal and issue DRAM transfersfor all enabled colors in a group. When the transfers are complete ittells the read pointer logic to update the requests pending via requpdate signal.

The req_sel[3:0] signal tells the address generator which buffer isbeing serviced, it is constructed from the odd_even_sel signal and thecolor_cnt[2:0] bus from the interface controller. When data is beingtransferred to DRAM the word pointer and read pointer for thecorresponding buffer are updated. The req_sel determines which pointershould be incremented. // determine if request is active even if (wr_adr[0][3:2] != rd_adr[0][3:2] )  even_pend = 1 else  even_pend = 0 //determine if request is active odd if ( wr_adr[1][3:2] != rd_adr[1][3:2])  even_pend = 1 else  even_pend = 0 // determine if any buffer is fullif ((wr_adr[0][3:0] − rd_adr[0][3:0]) > 7)OR((wr_adr[1][3:0] −rd_adr[1][3:0])> 7)) then  buf_full = 1 // fixed servicing order, onlyupdate when controller dictates so if (req_update == 1) then {  if(even_pend == 1) then      // even always first   odd_even_sel = 0  req_active = 1  elsif (odd_pend == 1 ) then   // then check odd  odd_even_sel = 0   req_active = 1  else               // nothingactive   odd_even_sel = 0   req_active = 0  } // selected requestorreq_sel[3:0]  =  {color_cnt[2:0]  ,  odd_even_sel}   // concatentation

The read address pointer logic consists of 2 2-bit counters and a wordselect pointer. The pointers are reset when dwu_go_pulse is one. Theword pointer (word_ptr) is common to all buffers and is used to read outthe 64-bit words from the DIU buffer. It is incremented when buf_rd_enis active. When a group of buffers are updated the state machineincrements the read pointer (rd_ptr[odd_even_sel]) via the group_finsignal. A concatenation of the read pointer and the word pointer are useto construct the buffer read address. The read pointers are not reset atthe end of each line. // determine which pointer to update if(dwu_go_pulse == 1) then  rd_ptr[1:0]  = 0  word_ptr   = 0 elsif(buf_rd_en == 1) then {  word_ptr++            // word pointer updateelsif (group_fin == 1) then  rd_ptr[odd_even_sel]++        // update theread pointer // create the address from the pointer,and word readerrd_adr[odd_even_sel] = {rd_ptr[odd_even_sel],word_ptr} // concatenation

The read pointer block determines if the word being read from the DIUbuffers is the last word of a line. The buffer address generatorindicate the last dot is being written into the buffers via the line finsignal. When received the logic marks the 256-bit word in the buffers asthe last word. When the last word is read from the DIU buffer andtransferred to DRAM, the flag for that word is reflected to the addressgenerator. // line end set the flags if (dwu_go_pulse == 1) then last_flag[1:0][1:0] = 0 elsif (line_fin == 1 ) then  // determines thecurrent 256-bit word even been written to  last_flag[0][wr_adr[0][2]] =1  // even group flag  // determines the current 256-bit word odd beenwritten to  last_flag[1][wr_adr[1][2]] = 1  // odd group flag // lastword reflection to address generator last_wd =last_flag[odd_even_sel][rd_ptr[req_sel][0]] // clear the flag if(group_fin == 1 ) then  last_flag[odd_even_sel][rd_ptr[req_sel][0]] = 0

When a complete line has been written into the DIU buffers (but has notyet been transferred to DRAM), the buffer address generator block willpulse the line_fin signal. The DWU must wait until all enabled buffersare transferred to DRAM before signaling the LLU that a complete line isavailable in the dot line store (dwu_llu_line_wr signal). When theline_fin is received all buffers will require transfer to DRAM. Due tothe arbitration, the even group will get serviced first then the odd. Asa result the line finish pulse to the LLU is generated from thelast_flag of the odd group. // must be odd,odd group transfer completeand the last word dwu_llu_line_wr = odd_even_sel AND group_fin ANDlast_wd31 Line Loader Unit (LLU)31.1 Overview

The Line Loader Unit (LLU) reads dot data from the line buffers in DRAMand structures the data into even and odd dot channels destined for thesame print time. The blocks of dot data are transferred to the PHI andthen to the printhead. FIG. 267 shows a high level data flow diagram ofthe LLU in context.

31.2 Physical Requirement Imposed by the Printhead

The DWU re-orders dot data into 12 separate dot data line FIFOs in theDRAM. Each FIFO corresponds to 6 colors of odd and even data. The LLUreads the dot data line FIFOs and sends the data to the printheadinterface. The LLU decides when data should be read from the dot dataline FIFOs to correspond with the time that the particular nozzle on theprinthead is passing the current line. The interaction of the DWU andLLU with the dot line FIFOs compensates for the physical spread ofnozzles firing over several lines at once. For further explanation seeSection 30 Dotline Writer Unit (DWU) and Section 32 Printhead Interface(PHI). FIG. 268 shows the physical relationship of nozzle rows and theline time the LLU starts reading from the dot line store.

Within each line of dot data the LLU is required to generate an even andodd dot data stream to the PHI block. FIG. 269 shows the even and dotstreams as they would map to an example bi-lithic printhead. The PHIblock determines which stream should be directed to which printhead IC.

31.3 Dot Generate and Transmit Order

The structure of the printhead ICs dictate the dot transmit order toeach printhead IC. The LLU reads data from the dot line FIFO, generatesan even and odd dot stream which is then re-ordered (in the PHI) intothe transmit order for transfer to the printhead.

The DWU separates dot data into even and odd half lines for each colorand stores them in DRAM. It can store odd or even dot data in increasingor decreasing order in DRAM. The order is programmable but fordescriptive purposes assume even in increasing order and odd indecreasing order. The dot order structure in DRAM is shown in FIG. 261.

The LLU contains 2 dot generator units. Each dot generator reads dotdata from DRAM and generates a stream of odd or even dots. The dot ordermay be increasing or decreasing depending on how the DWU was programmedto write data to DRAM. An example of the even and odd dot data streamsto DRAM is shown in FIG. 270. In the example the odd dot generator isconfigured to produce odd dot data in decreasing order and the even dotgenerator produces dot data_in increasing order.

The PHI block accepts the even and odd dot data streams and reconstructsthe streams into transmit order to the printhead.

The LLU line size refers to the page width in dots and not necessarilythe printhead width. The page width is often the dot margin number ofdots less than the printhead width. They can be the same size for fullbleed printing.

31.4 LLU Start-Up

At the start of a page the LLU must wait for the dot line store in DRAMto fill to a configured level (given by FifoReadThreshold) beforestarting to read dot data. Once the LLU starts processing dot data for apage it must continue until the end of a page, the DWU (and other PEPblocks in the pipeline) must ensure there is always data in the dot linestore for the LLU to read, otherwise the LLU will stall, causing the PHIto stall and potentially generate a print error. The FifoReadThresholdshould be chosen to allow for data rate mismatches between the DWU writeside and the LLU read side of the dot line FIFO. The LLU will notgenerate any dot data until FifoReadThreshold level in the dot line FIFOis reached.

Once the FifoReadThreshold is reached the LLU begins page processing,the FifoReadThreshold is ignored from then on.

When the LLU begins page processing it produces dot data for all colors(although some dot data color may be null data). The LLU compares theline count of the current page, when the line count exceeds theColorRelLine configured value for a particular color the LLU will startreading from that colors FIFO in DRAM. For colors that have not exceededthe ColorRelLine value the LLU will generate null data (zero data) andnot read from DRAM for that color. ColorRelLine[N] specifies the numberof lines separating the N^(th) half color and the first half color toprint on that page. For the example printhead shown in FIG. 268, color 0odd will start at line 0, the remaining colors will all have null data.Color 0 odd will continue with real data until line 5, when color 0 oddand even will contain real data the remaining colors will contain nulldata. At line 10, color 0 odd and even and color 1 odd will contain realdata, with remaining colors containing null data. Every 5 lines a newhalf color will contain real data and the remaining half colors nulldata until line 55, when all colors will contain real data. In theexample ColorRelLine[O]=5, ColorRelLine[1]=0, ColorRelLine[2]=15,ColorRelLine[3]=10. etc.

It is possible to turn off any one of the color planes of data (via theColorEnable register), in such cases the LLU will generate zeroed dotdata information to the PHI as normal but will not read data from theDRAM.

31.4.1 LLU Bandwidth Requirements

The LLU is required to generate data for feeding to the printheadinterface, the rate required is dependent on the printhead constructionand on the line rate configured. The maximum data rate the LLU canproduce is 12 bits of dot data per cycle, but the PHI consumes at 12bits every 2 pclk cycles out of 3, i.e. 8 bits per pclk cycle. Thereforethe DRAM bandwidth requirement for a double buffered LLU is 8 bits percycle on average. If 1.5 buffering is used then the peak bandwidthrequirement is doubled to 16 bits per cycle but the average remains at 8bits per cycle. Note that while the LLU and PHI could produce data atthe 8 bits per cycle rate, the DWU can only produce data at 6 bits percycle rate.

31.5 Vertical Row Skew

Due to construction limitations of the bi-lithic printhead it ispossible that nozzle rows may be misaligned relative to each other. Oddand even rows, and adjacent color rows may be horizontally misaligned byup to 2 dot positions. Vertical misalignment can also occur between bothprinthead ICs used to construct the printhead. The DWU compensates forthe horizontal misalignment (see Section 30.5), and the LLU compensatesfor the vertical misalignment. For each color odd and even the LLUmaintains 2 pointers into DRAM, one for feeding printhead A(CurrentPtrA) and other for feeding printhead B (CurrentPtrB). Bothpointers are updated and incremented in exactly the same way, but differin their initial value programming. They differ by vertical skew numberof lines, but point to the same relative position within a line.

At the start of a line the LLU reads from the FIFO using CurrentPtrAuntil the join point between the printhead ICs is reached (specified byJoinPoint), after which the LLU reads from DRAM using CurrentPtrB. Ifthe JoinPoint coincides with a 256-bit word boundary, the swap over frompointer A to pointer B is straightforward. If the JoinPoint is not on a256-bit word boundary, the LLU must read the 256-bit word of data fromCurrentPtrA location, generate the dot data up to the join point andthen read the 256-bit word of data from CurrentPtrB location andgenerate dot data from the join point to the word end. This means thatif the JoinPoint is not on a 256-bit boundary then the LLU is requiredto perform an extra read from DRAM at the join point and not incrementthe address pointers.

31.5.1 Dot Line FIFO Initialization

For each dot line FIFO there are 2 pointers reading from it, each skewedby a number of dot lines in relation to the other (the skew amount couldbe positive or negative). Determining the exact number of valid lines inthe dot line store is complicated by two pointers reading from differentpositions in the FIFO. It is convenient to remove the problem bypre-zeroing the dot line FIFOs effectively removing the need todetermine exact data validity. The dot FIFOs can be initialized in anumber of ways, including

-   -   the CPU writing 0s,    -   the LBD/SFU writing a set of 0 lines (16 bits per cycle),    -   the HCU/DNC/DWU being programmed to produce 0 data        31.6 Specifying Dot FIFOS

The dot line FIFOs when accessed by the LLU are specified differentlythan when accessed by the DWU. The DWU uses a start address and numberof lines value to specify a dot FIFO, the LLU uses a start and endaddress for each dot FIFO. The mechanisms differ to allow more efficientimplementations in each block.

The start address for each half color N is specified by theColorBaseAdr[N] registers and the end address (actually the end addressplus 1) is specified by the ColorBaseAdr[N+1]. Note there are 12 colorsin total, 0 to 11, the ColorBaseAdr[12] register specifies the end ofthe color 11 dot FIFO and not the start of a new dot FIFO. As a resultthe dot FIFOs must be specified contiguously and increasing in DRAM.

31.7 Implementation

31.7.1 LLU Partition

31.7.2 Definitions of I/O TABLE 208 LLU I/O definition Port name PinsI/O Description Clocks and Resets Pclk 1 In System clock prst_n 1 InSystem reset, synchronous active low PHI Interfacellu_phi_data[1:0][5:0] 2x6 Out Dot Data from LLU to the PHI, each bit isa color plane 5 downto 0. Bus 0 - Even dot data stream Bus 1 - Odd dotdata stream Data is active when corresponding bit is active inllu_phi_avail bus phi_llu_ready[1:0] 2 In Indicates that PHI is ready toaccept data from the LLU 0 - Even dot data stream 1 - Odd dot datastream llu_phi_avail[1:0] 2 Out Indicates valid data present oncorresponding llu_phi_data. 0 - Even dot data stream 1 - Odd dot datastream DIU Interface llu_diu_rreq 1 Out LLU requests DRAM read. A readrequest must be accompanied by a valid read address. llu_diu_radr[21:5]17 Out Read address to DIU 17 bits wide (256-bit aligned word).diu_llu_rack 1 In Acknowledge from DIU that read request has beenaccepted and new read address can be placed on llu_diu_radrdiu_data[63:0] 64 In Data from DIU to LLU. Each access is 256-bitsreceived over 4 clock cycles First 64-bits is bits 63:0 of 256 bit wordSecond 64-bits is bits 127:64 of 256 bit word Third 64-bits is bits191:128 of 256 bit word Fourth 64-bits is bits 255:192 of 256 bit worddiu_llu_rvalid 1 In Signal from DIU telling LLU that valid read data ison the diu_data bus DWU Interface dwu_llu_line_wr 1 In DWU line write.Indicates that the DWU has completed a full line write. Active highllu_dwu_line_rd 1 Out LLU line read. Indicates that the LLU hascompleted a line read. Active high. PCU Interface pcu_llu_sel 1 In Blockselect from the PCU. When pcu_llu_sel is high both pcu_adr andpcu_dataout are valid. pcu_rwn 1 In Common read/not-write signal fromthe PCU. pcu_adr[7:2] 6 In PCU address bus. Only 6 bits are required todecode the address space for this block. pcu_dataout[31:0] 32 In Sharedwrite data bus from the PCU. llu_pcu_rdy 1 Out Ready signal to the PCU.When llu_pcu_rdy is high it indicates the last cycle of the access. Fora write cycle this means pcu_dataout has been registered by the blockand for a read cycle this means the data on llu_pcu_datain is valid.llu_pcu_datain[31:0] 32 Out Read data bus to the PCU.31.7.3 Configuration Registers

The configuration registers in the LLU are programmed via the PCUinterface. Refer to section 21.8.2 on page 321 for a description of theprotocol and timing diagrams for reading and writing registers in theLLU. Note that since addresses in SoPEC are byte aligned and the PCUonly supports 32-bit register reads and writes, the lower 2 bits of thePCU address bus are not required to decode the address space for theLLU. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of llu_pcu_datain. Table 209lists the configuration registers in the LLU. TABLE 209 LLU registersdescription Address LLU_base+ Register #bits Reset Description ControlRegisters 0x00 Reset 1 0x1 Active low synchronous reset, self de-activating. A write to this register will cause a LLU block reset. 0x04Go 1 0x0 Active high bit indicating the LLU is programmed and ready touse. A low to high transition will cause LLU block internal states toreset. Configuration 0x08-0x38 ColorBaseAdr[12:0][21:5] 13x17 0x000 00Specifies the base address (in words) in memory where data from aparticular half color (N) will be placed. Also specifies the endaddress + 1 (256- bit words) in memory where fifo data for a particularhalf color ends. For color N the start address is ColorBaseAdr[N] andthe end address +1 is ColorBase- Adr[N+1] 0x3C ColorEnable 6 0x3FIndicates whether a particular color is active or not. When inactive nodata is written to DRAM for that color. 0 - Color off 1 - Color on Onebit per color, bit 0 is Color 0 and so on. 0x40 LineSize 16 0x000 0Indicates the number of dots per line. 0x44 FifoReadThreshold 8 0x00Specifies the number of lines that should be in the FIFO before the LLUstarts reading. 0x48-0x74 ColorRelLine[11:0] 12x8 0x00 Specifies therelative number of lines to wait from the first before starting to readdot data from the corresponding dot data FIFO Bus 0, 1 - Even, Odd linecolor 0 Bus 2, 3 - Even, Odd line color 1 Bus 4, 5 - Even, Odd linecolor 2 Bus 6, 7 - Even, Odd line color 3 Bus 8, 9 - Even, Odd linecolor 4 Bus 10, 11 - Even, Odd line color 5 0x78-0x7C JoinPoint 2x160x000 0 Specifies the join point in dots between both printhead ICs. Bus0 - Even dot generator join point Bus 1 - Odd dot generator join point0x80-0x84 JoinWord 2x8 0x00 Specifies the join point in words betweenboth printhead ICs. Bus 0 - Even dot generator join point Bus 1 - Odddot generator join point 0x90-0xBC CurrentAdrA[11:0][21:5] 12x17 0x000 0Current Address pointers associated with printhead A Bus 0, 1 - Even,Odd line color 0 Bus 2, 3 - Even, Odd line color 1 Bus 4, 5 - Even, Oddline color 2 Bus 6, 7 - Even, Odd line color 3 Bus 8, 9 - Even, Odd linecolor 4 Bus 10, 11 - Even, Odd line color 5 Working registers 0xC0-0xECCurrentAdrB[11:0][21:5] 12x17 0x000 0 Current Address pointersassociated with printhead B Bus 0, 1 - Even, Odd line color 0 Bus 2, 3 -Even, Odd line color 1 Bus 4, 5 - Even, Odd line color 2 Bus 6, 7 -Even, Odd line color 3 Bus 8, 9 - Even, Odd line color 4 Bus 10, 11 -Even, Odd line color 5 Working registers Working Registers 0xF0FifoFillLevel 8 0x00 Number of lines in the dot line FIFO, line writtenin but not read out. (Read Only)

A low to high transition of the Go register causes the internal statesof the LLU to be reset. All configuration registers will remain thesame. The block indicates the transition to other blocks via thellu_go_pulse signal.

31.7.4 Dot Generator

The dot generator block is responsible for reading dot data from the DIUbuffers and sending the dot data in the correct order to the PHI block.The dot generator waits for llu_en signal from the fifo fill levelblock, once active it starts reading data from the 6 DIU buffers andgenerating dot data for feeding to the PHI.

In the LLU there are two instances of the dot generator, one generatingodd data and the other generating even data.

At any time the ready bit from the PHI could be de-asserted, if thishappens the dot generator will stop generating data, and wait for theready bit to be re-asserted.

31.7.4.1 Dot Count

In normal operation the dot counter will wait for the llu_en and theready to be active before starting to count. The dot count will producedata as long as the phi_llu_ready is active. If the phi_llu_ready signalgoes low the count will be stalled.

The dot counter increments for each dot that is processed per line. Itis used to determine the line finish position, and the bit select valuefor reading from the DIU buffers. The counter is reset after each lineis processed (line_fin signal). It determines when a line is finished bycomparing the dot count with the configured line size divided by 2 (notethat odd numbers of dots will be rounded down). // define the linefinish if (dot_cnt[14:0] == line_size[15:1] )then  line_fin = 1 else line_fin = 0 // determine if word is valid dot_active = ((llu_en == 1)AND (phi_llu_ready == 1) AND (buf_emp == 0)) // counter logic if(llu_go_pulse == 1) then  dot_cnt = 0 elsif ((dot_active == 1)AND(line_fin == 1)) then  dot_cnt = 0 elsif (dot_active == 1) then dot_cnt = dot_cnt + 1 else  dot_cnt = dot_cnt // calculate the wordselect bits bit_sel[5:0]        := dot_cnt[5:0]

The dot generator also maintains a read buffer pointer which isincremented each time a 64-bit word is processed. The pointer is used toaddress the correct 64-bit dot data word within the DIU buffers. Thepointer is reset when llu_go_pulse is 1. Unlike the dot counter the readpointer is not reset each line but rounded up the nearest 256-bit word.This allows for more efficient use of the DIU buffers at line finish.

When the dot counter reaches the join point for the dot generator(join_point), it jumps to the next 256 bit word in the DIU buffer butcontinues to read from the next bit position within that word. If thejoin point coincides with a word boundary, no 256-bit increment isrequired. // read pointer logic if (llu_go_pulse == 1) then  read_adr =0 elsif ((dot_active == 1)AND((dot_cnt[7:0] == 255)OR(line_fin ==1)))then  // end of line round up  read_adr[3:2] ++  read_adr[1:0] = 0elsif   ((dot_active   ==   1)AND(dot_cnt   ==join_point)AND(dot_cnt[5:0] == 63)) then  // join point jump 256 bits read_adr[1:0] ++                    // regular increment  read_adr[3:2]++                 // join point 256 incrementelsif   ((dot_active   ==   1)AND(dot_cnt   ==join_point)AND(dot_cnt[5:0] != 63)) then  // join point jump 256 bits,bottom bits remain the same  read_adr[3:2] ++                 // joinpoint 256 increment only elsif ((dot_active == 1)AND(dot_cnt[5:0] ==63)) then  read_adr[3:0] ++                    // regular increment31.7.5 Fifo Fill Level

The LLU keeps a running total of the number of lines in the dot linestore FIFO. Every time the DWU signals a line end (dwu_llu_line_wractive pulse) it increments the filllevel. Conversely if the LLU detectsa line end (line_rd pulse) the filllevel is decremented and the lineread is signalled to the DWU via the llu_dwu_line_rd signal.

The LLU fill level block is used to determine when the dot line hasenough data stored before the LLU should begin to start reading. The LLUat page start is disabled. It waits for the DWU to write lines to thedot line FIFO, and for the fill level to increase. The LLU remainsdisabled until the fill level has reached the programmed threshold (fiforead thres). When the threshold is reached it signals the LLU to startprocessing the page by setting llu_en high. Once the LLU has startedprocessing dot data for a page it will not stop if the filllevel fallsbelow the threshold, but will stall is filllevel falls to zero.

The line fifo filllevel can be read by the CPU via the PCU at any timeby accessing the FifoFillLevel register. The CPU must toggle the Goregister in the LLU for the block to be correctly initialized at pagestart and the fifo level reset to zero. if (llu_go_pulse == 1) then filllevel = 0 elsif ((line_rd == 1) AND (dwu_llu_line_wr == 1)) then // do nothing elsif (line_rd == 1) then  filllevel −− elsif(dwu_llu_line_wr == 1) then  filllevel ++ // determine the threshold,and set the LLU going if (llu_go_pulse == 1) OR (filllevel == 0 )) then llu_en = 0 elsif (filllevel == fifo_read_threshold ) then  llu_en = 131.7.6 DIU Interface31.7.6.1 DIU Interface Description

The DIU interface block is responsible for determining when dot dataneeds to be read from DRAM, keeping the dot generators supplied withdata and calculating the DRAM read address based on configuredparameters, FIFO fill levels and position in a line.

The fill level block enables DIU requests by activating llu_en signal.The DIU interface controller then issues requests to the DIU for the LLUbuffers to be filled with dot line data (or fill the LLU buffers withnull data without requesting DRAM access, if required).

At page start the DIU interface determines which buffers should befilled with null data and which should request DRAM access. New requestsare issued until the dot line is completely read from DRAM.

For each request to the DRAM the address generator calculates where inthe DRAM the dot data should be read from. The color_enable busdetermines which colors are enabled, the interface never issues DRAMrequests for disabled colors.

31.7.6.2 Interface Controller

The interface controller co-ordinates and issues requests for datatransfers from DRAM. The state machine waits in Idle state until it isenabled by the LLU controller (llu_en) and a request for data transferis received from the write pointer block.

When an active request is received (req_active equals 1) the statemachine jumps to the ColorSelect state to determine which colors(color_cnt) in the group need a data transfer. A group is defined as allodd colors or all even colors. If the color isn't enabled (color_enable)the count just increments, and no data is transferred. If the color isenabled, the state machine takes one of two options, either a null datatransfer or an actual data transfer from DRAM. A null data transferwrites zero data to the DIU buffer and does not issue a request to DRAM.

The state machine determines if a null transfer is required by checkingthe color_start signal for that color.

If a null transfer is required the state machine doesn't need to issue arequest to the DIU and so jumps directly to the data transfer states(Data0 to Data3). The machine clocks through the 4 states each timewriting a null 64-bit data word to the buffer. Once complete the statemachine returns to the ColorSelect state to determine if furthertransfers are required.

If the color_start is active then a data transfer is required. The statemachine jumps to the Request state and issue a request to the DIUcontroller for DRAM access by setting llu_diu_rreq high. The DIUresponds by acknowledging the request (diu_llu_rack equals 1) and thensending 4 64-bit words of data. The transition from Request to Data0state signals the address generator to update the address pointer(adr_update). The state machine clocks through Data0 to Data3 stateseach time writing the 64-bit data into the buffer selected by thereq_sel bus. Once complete the state machine returns to the ColorSelectstate to determine if further transfers are required.

When in the ColorSelect state and all data transfers for colors in thatgroup have been serviced (i.e. when color_cnt is 6) the state machinewill return to the Idle state. On transition it will update the wordcounter logic (word_dec) and enabled the request logic (req_update).

A reset or llu_go_pulse set to 1 will cause the state machine to jumpdirectly to Idle. The controller will remain in Idle state until it isenabled by the LLU controller via the llu_en signal. This prevents theDIU attempting the fill the DIU buffers before the dot line store FIFOhas filled over its threshold level. μ31.7.6.3 Color Activate

The color activate logic maintains an absolute line count indicating theline number currently being processed by the LLU. The counter is resetwhen the llu_go_pulse is 1 and incremented each time a line_rd pulse isreceived. The count value (line_cnt) is used to determine when to startreading data for a color.

The count is implemented as follows: if ( llu_go_pulse == 1) then line_cnt = 0 elsif ( line_rd == 1) then  line_cnt ++

The color activate logic compares line count with the relative linevalue to determine when the LLU should start reading data from DRAM fora particular half color. It signals the interface controller block whichcolors are active for this dot line in a page (via the color_start bus).It is used by the interface controller to determine which DIU buffersrequire null data.

Once the color_start bit for a color is set it cannot be cleared in thenormal page processing process. The bits must be reset by the CPU at theend of a page by transitioning the Go bit and causing a pulse on thellu_go_pulse signal.

Any color not enabled by the color_enable bus will never have itscolor_start bit set. for (i=0; i<12;i++){  if ( llu_go_pulse == 1) then  col_on[i] = 0  elsif ( color_enable[i % 6] == 1 ) then   col_on[i] = 0 elsif ( line_cnt == color_rel_line[i]) then   col_on[i] = 1  } //select either odd or even colors if ( odd_even_sel == 1 ) then // oddselected  color_start[5:0]                    ={col_on[11],col_on[9],col_on[7],col_on[5],col_on[3],col_on[1 ]} else //even selected  color_start[5:0]                    ={col_on[10],col_on[8],col_on[6],col_on[4],col_on[2],col_on[0 ]}31.7.6.4 Address Generator

The address generator block maintains 24 pointers (current_adr_a[11:0]and current_adr_b[11:0]) to DRAM corresponding to 2 read addresses inthe dot line FIFO for each half color. The current_adr a group ofpointers are used when the dot generator is feeding printhead channel A,and the current_adr_b group of pointers are used when the dot generatoris feeding printhead channel B. For each DRAM access the 2 addresspointers are updated but only one can be used for an access. The wordcounter block determines which pointer group should be used to accessDRAM, via the pointer select signals (ptr_sel). In certain cases (e.g.the join point is not 256-bit aligned and the word is on the join point)the address pointers should not be updated for an access, the wordcounter block determines the exception cases and indicates to theaddress generator to skip the update via the join_stall signal.

When a DRAM transfer occurs the address pointer is used first and thenupdated for the next transfer for the color. The pointer used isselected by the req_sel and ptr_sel buses, and the pointer update isinitiated by the adr_update signal from the interface controller.

The address update is calculated as follows (pointer group A logic isshown but the same logic is used to update the B pointer group a clockcycle later): // update the A pointers if (ptra_wr_en == 1)then         // write from the configuration block current_adr_a[ptr_adr] = ptr_wr_data; elsif ( adr_update_a == 1) then{  // address update from state machine  if ((req_sel == NULL )OR(join_stall == 1)) then   // do nothing  else   // temporary variablesetup   next_adr = current_adr_a[req_sel] + 1  start_adr =color_base_adr[req_sel]  end_adr = color_base_adr[req_sel + 1]  //determine how to update the pointer  if (next_adr == end_adr) then  current_adr_a[req_sel] = start_adr  else   current_adr_a[req_sel] =next_adr }

The correct address to use for a transfer is selected by the ptr_selsignals from the word counter block. They indicate which set of addresspointers should be used based on the current word being transferred fromthe DRAM and the configured join point values (join_word). // select theaddress pointer to use for access if (req_sel[0] == 1) then // oddpointer selector  if (ptr_sel[1] == 1) then   llu_diu_radr =current_adr_b[req_sel]  // latter part of line  else   llu_diu_radr =current_adr_a[req_sel]  // former part of line else // even pointerselector  if (ptr_sel[0] == 1) then   llu_diu_radr =current_adr_b[req_sel]  // latter part of line  else   llu_diu_radr =current_adr_a[req_sel]  // former part of line31.7.6.5 Write Pointer

The write pointer logic maintains the buffer write address pointers,determines when the DIU buffers need a data transfer and signals whenthe DIU buffers are empty. The write pointer determines the address inthe DIU buffer that the data should be transferred to.

The write pointer logic compares the read and write pointers of each DIUbuffer to determine which buffers require data to be transferred fromDRAM, and which buffers are empty (the buf_emp signals).

Buffers are grouped into odd and even buffers, if an odd buffer requiresDRAM access the odd_pend signals will be active, if an even bufferrequires DRAM access the even_pend signals will be active. If both oddand even buffers require DRAM access at exactly the same time, the evenbuffers will get serviced first. If a group of odd buffers are beingserviced and an even buffer becomes pending, the odd group of bufferswill be completed before the starting the even group, and vice versa.

If any buffer requires a DRAM transfer, the logic will indicate to theinterface controller via the req_active signal, with the odd_even_selsignal determining which group of buffers get serviced. The interfacecontroller will check the color_enable signal and issue DRAM transfersfor all enabled colors in a group. When the transfers are complete ittells the write pointer logic to update the request pending viareq_update signal.

The req_sel[3:0] signal tells the address generator which buffer isbeing serviced, it is constructed from the odd_even_sel signal and thecolor_cnt[2:0] bus from the interface controller. When data is beingtransferred to DRAM the word pointer and write pointer for thecorresponding buffer are updated. The req_sel determines which pointershould be incremented.

The write pointer logic operates the same way regardless of whether thetransfer is null or not. // determine which buffers need updatesbuf_emp[1:0] = 0 odd_pend = 0 even_pend = 0 if ( wr_adr[0][3:2] ==rd_adr[0][3:2] )   even_pend = 1 if ( wr_adr[1][3:2] == rd_adr[1][3:2] )  odd_pend = 1 // determine if buffers are empty if ((wr_adr[0][3:0] ==rd_adr[0][3:0])) then   buf_emp[0] = 1 if ((wr_adr[1][3:0] ==rd_adr[1][3:0])) then   buf_emp[1] = 1// fixed servicing order, only update when controller dictates so if(req_update == 1) then {  if (even_pend == 1) then // even always first  odd_even_sel = 0   req_active = 1  elsif (odd_pend == 1 ) then // thencheck odd   odd_even_sel = 0   req_active = 1  else // nothing active  odd_even_sel = 0   req_active = 0  } // selected requestorreq_sel[3:0] = {color_cnt[2:0],odd_even_sel}    // concatentation

The write address pointer logic consists of 2 2-bit counters and a wordselect pointer. The counters are reset when llu_go_pulse is one. Theword pointer (word_ptr) is common to all buffers and is used to write64-bit words into the DIU buffer. It is incremented when buf_rd_en isactive.

When a group of buffers are updated the state machine increments thewrite pointer (wr_ptr[odd_even_sel]) via the group_fin signal. Aconcatenation of the write pointer and the word pointer are use toconstruct the buffer write address. The write pointers are not reset atthe end of each line. // determine which pointer to update if(llu_go_pulse == 1) then  wr_ptr[1:0] = 0  word_ptr = 0 elsif (buf_rd_en== 1) then  word_ptr++  wr_en[req_sel] = 1 elsif (group_fin = 1 ) then wr_ptr[odd_even_sel]++ //  create the address from the write pointerand word pointer wr_adr[odd_even_sel] ={wr_ptr[odd_even_sel],word_ptr}   // concatenation31.7.6.6 Word Count

The word count logic maintains 2 counters to track the number of wordstransferred from DRAM per line, one counter for odd data, and onecounter for even. On receipt of a llu_go_pulse, the counters areinitialized to a join_word value (number of words to the join point forthat printhead channel) and the pointer select values to zero (ptr_sel).When a group of words are transferred to DRAM as indicated by theword_dec signal from the interface controller, the corresponding counteris decremented. The counter to decrement is indicated by theodd_even_sel signal from the write pointer block (even=0, odd=1).

When a counter is zero and the ptr_sel is zero, the counter isre-initialized to the second join_word value and ptr_sel is inverted.The counter continues to count down to zero each time a word_dec signalis received. When a counter is zero and the ptr_sel is one, it signalsthe end of a line (the last_wd signal) and initializes the counter tothe first join_point value for the next line transfer.

The ptr_sel signal is used in the address generator to select thecorrect address pointer to use for that particular access. // determinewhich counter to decrement if (llu_go_pulse == 1) then word_cnt[0] =join_word[0] // even count ptr_sel[0]  = 0 // even generator starts withpointer A word_cnt[1] = join_word[1] // odd count ptr_sel[1]  = 0 // oddgenerator starts with pointer A elsif (word_dec == 1) then { // need todecrement one word counter if (odd_even_sel == 0) then // even counterupdate if (word_cnt[0] == 0) then word_cnt[0] = join_word[ptr_sel[0]] //re-initialize pointer ptr_sel[0] = ˜(ptr_sel[0]) if (ptr_sel[0]== 1)then // determine if this the last word last_wd = 1 else word_cnt[0] −−// normal decrement else  // odd counter update if (word_cnt[1] == 0)then word_cnt[1] = join_word[ptr_sel[1]] // re-initialize pointerptr_sel[1] = ˜(ptr_sel[1]) if (ptr_sel[1]== 1) then // determine if thisthe last word last_wd = 1 else word_cnt[1] −−  // normal decrement }

The word count logic also determines if the current word to betransferred is the join word, and if so it determines if it is alignedon a 256-bit boundary or not. If the join point is aligned to a boundarythere is no need to prevent the address counter from incrementing,otherwise the address pointers are stalled for that word transfer(join_stall). join_stall = (((ptr_sel[0] == 0)AND (word_cnt[0] == 0)AND(join_point[0][7:0] != 0))   AND ((ptr_sel[1] == 0)AND (word_cnt[1] ==0)AND (join_point[1][7:0] != 0)))

The word count logic also determines when a complete line has been readfrom DRAM, it then signals the fifo fill level logic in both the LLU andDWU (via line_rd signal) that a complete line has been read by the LLU(llu_dwu_line_rd). // line finish logic if (llu_go_pulse == 1) then line_fin = 0  line_rd = 0 elsif ((last_wd == 1) AND (line_fin == 0))then  line_fin = 1        // first group last_wd finish pulse  line_rd =0 elsif ((last_wd == 1) AND (line_fin == 1)) then  line_fin = 0        // second group last_wd finish pulse  line_rd = 1 else  line_fin= line_fin      // stay the same  line_rd = 032 Printhead Interface (PHI)32.1 Overview

The Printhead interface (PHI) accepts dot data from the LLU andtransmits the dot data to the printhead, using the printhead interfacemechanism. The PHI generates the control and timing signals necessary toload and drive the bi-lithic printhead. The CPU determines the lineupdate rate to the printhead and adjusts the line sync frequency toproduce the maximum print speed to account for the printhead IC's sizeratio and inherent latencies in the syncing system across multipleSoPECs.

The PHI also needs to consider the order in which dot data is loaded inthe printhead. This is dependent on the construction of the printheadand the relative sizes of printhead ICs used to create the printhead.See Bi-lithic Printhead Reference document for a complete description ofprinthead types [10].

The printing process is a real-time process. Once the printing processhas started, the next printline's data must be transferred to theprinthead before the next line sync pulse is received by the printhead.Otherwise the printing process will terminate with a buffer underrunerror.

The PHI can be configured to drive a single printhead IC with or withoutsynchronization to other SoPECs. For example the PHI could drive asingle IC printhead (i.e. a printhead constucted with one IC only), ordual IC printhead with one SoPEC device driving each printhead IC.

The PHI interface provides a mechanism for the CPU to directly controlthe PHI interface pins, allowing the CPU to access the bi-lithicprinthead to:

-   -   determine printhead temperature    -   test for and determine dead nozzles for each printhead IC    -   initialize each printhead IC    -   pre-heat each printhead IC

FIG. 277 shows a high level data flow diagram of the PHI in context.

32.2 Printhead Modes of Operation

The printhead has 8 different modes of operations (although some modesare re-used). The mode of operation is defined by the state of theoutput pins phi_lsyncl and phi_readl and the internal printhead moderegister. The modes of operation are defined in Table 210. TABLE 210Printhead modes of operation Name Internal Mode phi_readl phi_lsynclState Description NORMAL XXX 1 1 N/A Normal print mode, dot data isclocked into the printhead shift register, on each falling edge ofphi_srclk DOT_LOAD/ XXX 1 0 phi_frclk=0 Dot Load Mode, data stored inthe FIRE_INIT dot shift register is transferred into the dot latch onthe falling edge of phi_lsyncl, and latched in on the rising edge ofphi_lsyncl phi_srclk=1 Fire load mode. Parameter for generating firepattern are loaded into generator, data on phi_ph_data[1:0][0] isclocked into the generator on each rising edge of phi_frclk NOZZLE_RESET001 0 1 N/A Reset Nozzle Test mode. Reset the state on nozzle test.CMOS_TEST 111 0 1 N/A CMOS test mode. FIRE_GEN 000 0 1 N/A FireInitialise mode. The initialised generator creates the fire pattern andshift select pattern. The pattern is clocked into the fire shiftregister and select shift register on the rising edge of phi_frclkTEMP_TEST 010 0 0 N/A Temperature test output. NOZZLE_TEST 001 0 0 N/ANozzle test output. The result of a nozzle test is output onphi_frclk_i.32.3 Data Rate Equalization

The LLU can generate dot data at the rate of 12 bits per cycle, where acycle is at the system clock frequency. In order to achieve the targetprint rate of 30 sheets per minute, the printhead needs to print a lineevery 100 μs (calculated from 300 mm @ 65.2 dots/mm divided by 2seconds=˜100 μsec). For a 7:3 constructed printhead this means that 9744cycles at 320 Mhz is quick enough to transfer the 6-bit dot data (at 2bits per cycle). The input FIFOs are used to de-couple the read andwrite clock domains as well as provide for differences between consumeand fill rates of the PHI and LLU.

Nominally the system clock (pclk) is run at 160 Mhz and the printheadinterface clock (doclk) is at 320 Mhz.

If the PHI was to transfer data at the full printhead interface rate,the transfer of data to the shorter printhead IC would be completedsooner than the longer printhead IC. While in itself this isn't an issueit requires that the LLU be able to supply data at the maximum rate forshort duration, this requires uneven bursty access to DRAM which isundesirable. To smooth the LLU DRAM access requirements over time thePHI transfers dot data to the printhead at a pre-programmed rate,proportional to the ratio of the shorter to longer printhead ICs.

The printhead data rate equalization is controlled by PrintheadRate[1:0]registers (one per printhead IC). The register is a 16 bit bitmap ofactive clock cycles in a 16 clock cycle window. For example if theregister is set to 0xFFFF then the output rate to the printhead will befull rate, if it's set to 0xF0F0 then the output rate is 50% where thereis 4 active cycles followed by 4 inactive cycles and so on. If theregister was set to 0x0000 the rate would be 0%. The relative datatransfer rate of the printhead can be varied from 0-100% with agranularity of 1/16 steps. TABLE 211 Example rate equalization valuesfor common printheads Printhead Printhead A Printhead Ratio A:B rate (%)B rate (%) 8:2 0xFFFF (100%) 0x1111 (25%) 7:3 0xFFFF (100%) 0x5551(43.7%) 6:4 0xFFFF (100%) 0xF1F2 (68.7%) 5:5 0xFFFF (100%) 0xFFFF (100%)

If both printhead ICs are the same size (e.g. a 5:5 printhead) it may bedesirable to reduce the data rate to both printhead ICs, to reduce theread bandwidth from the DRAM.

32.4 Dot Generate and Transmit Order

Several printhead types and arrangements exists (see [10] for otherarrangements). The PHI is capable of driving all possibleconfigurations, but for the purposes of simplicity only one arrangement(arrangement 1- see [10] for definition) is described in the followingexamples. The structure of the printhead ICs dictate the dot transmitorder to each printhead IC. The PHI accepts two streams of dot data fromthe LLU, one even stream the other odd. The PHI constructs the dottransmit order streams from the dot generate order received from theLLU. Each stream of data has already been arranged in increasing ordecreasing dot order sense by the DWU. The exact sense choice isdependent on the type of printhead ICs used to construct the printhead,but regardless of configuration the odd and even stream should be ofopposing sense. The dot transmit order is shown in FIG. 281. Dot data isshifted into the printhead in the direction of the arrow, so from thediagram (taking the type 0 printhead IC) even dot data is transferred inincreasing order to the mid point first (0, 2, 4, . . . , m−6, m−4,m−2), then odd dot data in decreasing order is transferred (m−1, m−3,m−5, . . . , 5, 3, 1). For the type 1 printhead IC the order isreversed, with odd dots in increasing order transmitted first, followedby even dot data in decreasing order. Note for any given color the oddand even dot data transferred to the printhead ICs are from differentdot lines, in the example in the diagram they are separated by 5 dotlines. Table 212 shows the transmit dot order for some common A4printheads. Different type printheads may have the sense reversed andmay have an odd before even transmit order or vice versa. TABLE 212Example printhead ICs, and dot data transmit order for A4 (13824 dots)page Size Dots Dot Order Type 0 Printhead IC 8 11160 0, 2, 4, 8 . . .,5574, 5576, 5578 5579, 5577, 5575 . . ., 7, 5, 3, 1 7 9744 0, 2, 4, 8 .. ., 4866, 4868, 4870 4871, 4869, 4867 . . ., 7, 5, 3, 1 6 8328 0, 2, 4,8 . . ., 4158, 4160, 4162 4163, 4161, 4159 . . ., 7, 5, 3, 1 5 6912 0,2, 4, 8 . . ., 3450, 3452, 3454 3455, 3453, 3451 . . ., 7, 5, 3, 1 45496 0, 2, 4, 8 . . ., 2742, 2744, 2746 2847, 2845, 2843 . . ., 7, 5, 3,1 3 4080 0, 2, 4, 8 . . ., 2034, 2036, 2038 2039, 2037, 2035 . . ., 7,5, 3, 1 2 2664 0, 2, 4, 8 . . ., 1326, 1328, 1330 1331, 1329, 1327 . .., 7, 5, 3, 1 Type 1 Printhead IC 8 11160 13823, 13821, 13819 . . .,1332, 1334, 1336 . . ., 13818, 13820, 1337, 1335, 1333 13822 7 974413823, 13821, 13819 . . ., 2040, 2042, 2044 . . ., 13818, 13820 2045,2043, 2041 13822 6 8328 13823, 13821, 13819 . . ., 2848, 2850, 2852 . .., 13818, 13820, 2853, 2851, 2849 13822 5 6912 13823, 13821, 13819 . .., 3456, 3458, 3460 . . ., 13818, 13820 3461, 3459, 3457 13822 4 549613823, 13821, 13819 . . ., 4164, 4166, 4168 . . ., 13818, 13820 4169,4167, 4165 13822 3 4080 13823, 13821, 13819 . . ., 4872, 4874, 4876 . .., 13818, 13820 4877, 4875, 4873 13822 2 2664 13823, 13821, 13819 . . .,5580, 5582, 5584 . . ., 13818, 13820 5585, 5583, 5581 1382232.4.1 Dual Printhead IC

The LLU contains 2 dot generator units. Each dot generator reads dotdata from DRAM and generates a stream of dots in increasing ordecreasing order. A dot generator can be configured to produce odd oreven dot data streams, and the dot sense is also configurable. In FIG.281 the odd dot generator is configured to produce odd dot data indecreasing order and the even dot generator produces dot data inincreasing order. The LLU takes care of any vertical misalignmentbetween the 2 printhead ICs, presenting the PHI with the appropriatedata ready to be transmitted to the printhead.

In order to reconstruct the dot data streams from the generate order tothe transmit order, the connection between the generators andtransmitters needs to be switched at the mid point. At line start theodd dot generator feeds the type 1 printhead, and the even dot generatorfeeds the type 0 printhead. This continues until both printheads havereceived half the number of dots they require (defined as the midpoint). The mid point is calculated from the configured printhead sizeregisters (PrintheadSize). Once both printheads have reached the midpoint, the PHI switches the connections between the dot generators andthe printhead, so now the odd dot generator feeds the type 0 printheadand the even dot generator feeds the type 1 printhead. This continuesuntil the end of the line.

It is possible that both printheads will not be the same size and as aresult one dot generator may reach the mid point before the other. Insuch cases the quicker dot generator is stalled until both dotgenerators reach the mid point, the connections are switched and bothdot generators are restarted.

Note that in the example shown in FIG. 281 the dot generators couldgenerate an A4 line of data in 6912 cycles, but because of the mismatchin the printhead IC sizes the transmit time takes 9744 cycles.

32.4.2 Single Printhead IC

In some cases only one printhead IC may be connected to the PHI. In FIG.282 the dot generate and transmit order is shown for a single ICprinthead of 9744 dots width. While the example shows the printhead ICconnected to channel A, either channel could be used. The LLU generatesodd and even dot streams as normal, it has no knowledge of the physicalprinthead configuration. The PHI is configured with the printhead size(PrintheadSize[1] register) for channel B set to zero and channel A isset to 9744.

Note that in the example shown in FIG. 283 the dot generators couldgenerate an 7 inch line of data in 4872 cycles, but because theprinthead is using one IC, the transmit time takes 9744 cycles, the samespeed as an A4 line with a 7:3 printhead.

32.4.3 Summary of Generate and Transmit Order Requirements

In order to support all the possible printhead arrangements, the PHI (inconjuction with the LLU/DWU) must be capable of re-ordering the bitsaccording to the following criteria:

-   -   Be able to output the even or odd plane first.    -   Be able to output even and odd planes independently.    -   Be able to reverse the sequence in which the color planes of a        single dot are output to the printhead.        32.5 Print Sequence

The PHI is responsible for accepting dot data streams from the LLU,restructuring the dot data sequence and transferring the dot data toeach printhead within a line time (i.e before the next line sync).

Before a page can be printed the printhead ICs must be initialized. Theexact initialization sequence is configuration dependent, but willinvolve the fire pattern generation initialization and other optionalsteps. The initialization sequence is implemented in software.

Once the first line of data has been transferred to the printhead, thePHI will interrupt the CPU by asserting the phi_icu_print_rdy signal.The interrupt can be optionally masked in the ICU and the CPU can pollthe signal via the PCU or the ICU. The CPU must wait for a print readysignal in all printing SoPECs before starting printing.

Once the CPU in the PrintMaster SoPEC is satisfied that printing shouldstart, it triggers the LineSyncMaster SoPEC by writing to the PrintStartregister of all printing SoPECs. The transition of the PrintStartregister in the LineSyncMaster SoPEC will trigger the start of lsynclpulse generation. The PrintMaster and LineSyncMaster SoPEC are notnecessarily the same device, but often are the same. For a more in depthdefinition see section 12.1.1 Multi-SoPEC systems on page 105.

Writing a 1 to the PrintStart register enables the generation of theline sync in the LineSyncMaster which is in turn used to align allSoPECs in a multi-SoPEC system. All printhead signaling is aligned tothe line sync. The PrintStart is only used to align the first line syncin a page.

When a SoPEC receives a line sync pulse it means that the linepreviously transferred to the printhead is now printing, so the PHI canbegin to transfer the next line of data to the printhead. When thetransfer is complete the PHI will wait for the next line sync pulsebefore repeating the cycle. If a line sync arrives before a completeline is transferred to the printhead (i.e. a buffer error) the PHIgenerates a buffer underrun interrupt, and halts the block.

For each line in a page the PHI must transfer a full line of data to theprinthead before the next line sync is generated or received.

32.5.1 Sync Pulse Control

If the PHI is configured as the LineSyncMaster SoPEC it will startgenerating line sync signals LsyncPre number of pclk cycles afterPrintStart register rising transition is detected. All other signals inthe PHI interface are referenced from the rising edge of phi_lsynclsignal.

If the SoPEC is in line sync slave mode it will receive a line syncpulse from the LineSyncMaster SoPEC through the phi_lsyncl pin whichwill be programmed into input mode. The phi_lsyncl input pin is treatedas an asynchronous input and is passed through a de-glitch circuit ofprogrammable de-glitch duration (LsyncDeglitchCnt).

The phi_lsyncl will remain low for LsyncLow cycles, and then high forLsyncHigh cycles. The phi_lsyncl profile is repeated until the page iscomplete. The period of the phi_lsyncl is given by LsyncLow+LsyncHighcycles. Note that the LsyncPre value is only used to vary the timebetween the generation of the first phi_lsyncl and the PageStartindication from the CPU. See FIG. 284 for reference diagram.

If the SoPEC device is in line sync slave mode, the LsyncHigh registerspecifies the minimum allowed phi_lsyncl period. Any phi_lsyncl pulsesreceived before the LsyncHigh has expired will trigger a buffer underrunerror.

32.5.2 Shift Register Signal Control

Once the PHI receives the line sync pulse, the sequence of data transferto the printhead begins. All PHI control signals are specified from therising edge of the line sync.

The phi_srclk (and consequently phi_ph_data) is controlled by theSrclkPre, SrclkPost registers. The SrclkPre specifies the number of pclkcycles to wait before beginning to transfer data to the printhead. Oncedata transfer has started, the profile of the phi_srclk is controlled byPrintheadRate register and the status of the PHI input FIFO. For exampleit is possible that the input FIFO could empty and no data would betransferred to the printhead while the PHI was waiting. After all thedata for a printhead is transferred to the PHI, it counts SrclkPostnumber of pclk cycles. If a new phi_lsyncl falling edge arrives beforethe count is complete the PHI will generate a buffer underrun interrupt(phi_icu_underrun).

32.5.3 Firing Sequence Signal Control

The profile of the phi_frclk pulses per line is determined by 4registers FrclkPre, FrclkLow, FrclkHigh, FrclkNum. The FrclkPre registerspecifies the number of cycles between line sync rising edge and thephi_frclk pulse high. It remains high for FrclkHigh cycles and then lowfor FrclkLow cycles. The number of pulses generated per line isdetermined by FrclkNum register. The total number of cycles required tocomplete a firing sequence should be less than the phi_lsyncl periodi.e. ((FrclkHigh+FrclkLow)*FrclkNum)+FrclkPre<(LsyncLow+LsyncHigh). Notethat when in CPU direct control mode (PrintheadCpuCtrl=1) andPrintheadCpuCtrlMode[x]=1, the frclk generator is triggered by thetransition of the FireGenSoftTrigger[0]0 bit from 0 to 1. FIG. 284details the timing parameters controlling the PHI. All timing parametersare measured in number of pclk cycles.

32.5.4 Page Complete

The PHI counts the number of lines processed through the interface. Theline count is initialised to the PageLenLine and decrements each time aline is processed. When the line count is zero it pulses the phiicu_page_finish signal. A pulse on the phi_icu_page_finish automaticallyresets the PHI Go register, and can optionally cause an interrupt to theCPU. Should the page terminate abnormally, i.e. a buffer underrun, theGo register will be reset and an interrupt generated.

32.5.5 Line Sync Interrupt

The PHI will generate an-interrupt to the CPU after a predefined numberof line syncs have occured. The number of line syncs to count isconfigured by the LineSyncInterrupt register. The interrupt can bedisabled by setting the register to zero.

32.6 Dot Line Margin

The PHI block allows the generation of margins either side of thereceived page from the LLU block. This allows the page width used withinPEP blocks to differ from the physical printhead size.

This allows SoPEC to store data for a page minus the margins, resultingin less storage requirements in the shared DRAM and reduced memorybandwidth requirements. The difference between the dot data line sizeand the line length generated by the PHI is the dot line margin length.There are two margins specified for any sheet, a margin per printhead ICside.

The margin value is set by programming the DotMargin register perprinthead IC. It should be noted that the DotMargin register representshalf the width of the actual margin (either left or right margindepending on paper flow direction). For example, if the margin in dotsis 1 inch (1600 dots), then DotMargin should be set to 800. The reasonfor this is that the PHI only supports margin creation cases 1 and 3described below.

See example in FIG. 284.

In the example the margin for the type 0 printhead IC is set at 100 dots(DotMargin==100), implying an actual margin of 200 dots.

If case one is used the PHI takes a total of 9744 phi_srclk cycles toload the dot data into the type 0 printhead. It also requires 9744 dotsof data from the LLU which in turn gets read from the DRAM. In this casethe first 100 and last 100 dots would be zero but are processed thoughthe SoPEC system consuming memory and DRAM bandwidth at each step.

In case 2 the LLU no longer generates the margin dots, the PHI generatesthe zeroed out dots for the margining. The phi_srclk still needs totoggle 9744 times per line, although the LLU only needs to generate 9544dots giving the reduction in DRAM storage and associated bandwidth.

The case 2 senario is not supported by the PHI because the same effectcan be supported by means of case 1 and case 3.

If case 3 is used the benefits of case 2 are achieved, but the phi_srclkno longer needs to toggle the full 9744 clock cycles. The phi_srclkcycles count can be reduced by the margin amount (in this case9744-100=9644 dots), and due to the reduction in phi_srclk cycles thephi_lsyncl period could also be reduced, increasing the line processingrate and consequently increasing print speed. Case 3 works by shiftingthe odd (or even) dots of a margin from line Y to become the even (orodd) dots of the margin for line Y-4, (Y-5 adjusted due to being printedone line later). This works for all lines with the exception of thefirst line where there has been no previous line to generate the zeroedout margin. This situation is handled by adding the line reset sequenceto the printhead initialization procedure, and is repeated between pagesof a document.

32.7 Dot Counter

For each color the PHI keeps a dot usage count for each of the colorplanes (called AccumDotCount). If a dot is used in particular colorplane the corresponding counter is incremented. Each counter is 32 bitswide and saturates if not reset. A write to the DotCountSnap registercauses the AccumDotCount[N] values to be transferred to the DotCount[N]registers (where N is 5 to 0, one per color). The AccumDotCountregisters are cleared on value transfer.

The DotCount[N] registers can be written to or read from by the CPU atany time. On reset the counters are reset to zero.

The dot counter only counts dots that are passed from the LLU throughthe PHI to the printhead.

Any dots generated by direct CPU control of the PHI pins will not becounted.

32.8 CPU IO Control

The PHI interface provides a mechanism for the CPU to directly controlthe PHI interface pins, allowing the CPU to access the bi-lithicprinthead:

-   -   Determine printhead temperature    -   Test for and determine dead nozzles for each printhead IC    -   Printhead IC initialization    -   Printhead pre-heat function

The CPU can gain direct control of the printhead interface connectionsby setting the PrintheadCpuCtrl register to one. Once enabled theprinthead bits are driven directly by the PrintheadCpuOut controlregister, where the values in the register are reflected directly on theprinthead pins and the status of the printhead input pins can be readdirectly from the PrintheadCpuIn. The direction of pins is controlled byprogramming PrintheadCpuDir register.

The register to pin mapping is as follows: TABLE 213 CPU control andstatus registers mapping to printhead interface Register Name bitsPrinthead pin PrintHeadCpuOut 0 phi_lsyncl_o 1 phi_frclk_o 2 Reserved4:3 phi_ph_data_o[0][1:0] 6:5 phi_ph_data_o[1][1:0] 8:7 phi_srclk[1:0] 9phi_readl PrintHeadCpuDir 0 phi_lsyncl_e direction control 1 - outputmode 0 - input mode 1 phi_frclk_e direction control 1 - output mode 0 -input mode 2 Reserved PrintHeadCpuIn 0 phi_lsyncl_i 1 phi_frclk_i 2Reserved

It is important to note that once in PrintheadCpuCtrl mode it is theresponsibility of the CPU to drive the printhead correctly and notcreate situations where the printhead could be destroyed such asactivating all nozzles together.

The phi_srclk is a double data rate clock (DDR) and as such will clockdata on both edges in the printhead.

Note the following procedures are based on current printheadcapabilities, and are subject to change.

32.9 Implementation

32.9.1 Definitions of I/O TABLE 214 Printhead interface I/O definitionPort name Pins I/O Description Clocks and Resets Pclk 1 In System ClockDoclk 1 In Data out clock (2x pclk) used to transfer data to printheadprst_n 1 In System reset, synchronous active low. Synchronous to pclkdorst_n 1 In System reset, synchronous active low. Synchronous to doclkGeneral phi_icu_print_rdy 1 Out Indicates that the first line of data istransferred to the printhead Active high. phi_icu_page_finish 1 OutIndicates that data for a complete page has transferred. Active highphi_icu_underrun 1 Out Indicates the PHI has detected a buffer underrun.Active high phi_icu_linesync_int 1 Out Indicates the PHI has detectedLineSyncInterrupt number of line syncs. Debug debug_data_valid 1 InOutput debug data valid to be muxed on to the PHI pin debug_cntrl 1 InControl signal for the PHI to indicate whether or not the debug datavalid (and pclk) should be selected by the pin mux. Active high. LLUInterface llu_phi_data[1:0][5:0] 2x6 In Dot Data from LLU to the PHI,each bit is a color plane 5 downto 0. Bus 0 - Even dot data stream Bus1 - Odd dot data stream Data is active when corresponding bit is activein llu_phi_avail bus phi_llu_ready[1:0] 2 Out Indicates that PHI isready to accept data from the LLU 0 - Even dot data stream 1 - Odd dotdata stream llu_phi_avail[1:0] 2 In Indicates valid data present oncorresponding llu_phi_data. 0 - Even dot data stream 1 - Odd dot datastream Printhead Interface phi_ph_data[1:0][1:0] 2x2 Out Dot data outputto printhead. Each bus to each printhead contains 2 bits of data Bus 0 -Printhead channel A Bus 1 - Printhead channel B phi_srclk[1:0] 2 Out Dotdata shift clock used to clock in printhead data, data is shifted onboth edges of clock(i.e. double data rate DDR). Bus 0 - Printheadchannel A Bus 1 - Printhead channel B phi_readl 1 Out Common printheadmode control. Used in conjunction with phi_lsyncl to determine theprinthead mode 0 - SoPEC receiving, printhead driving 1 - SoPEC driving,printhead receiving phi_frclk_o 1 Out Common Fire pattern clock needs totoggle once per fire cycle phi_frclk_e 1 In phi_frclk_o output enable,when high phi_frclk_o pin is driving phi_frclk_I 1 In phi_frclk_i inputfrom printhead phi_lsyncl_o 1 Out Capture dot data for next print line,output mode phi_lsyncl_e 1 In phi_lsyncl output enable, when highphi_lsyncl pin is driving phi_lsyncl_i 1 In Line Sync Pulse from MasterSoPEC PCU Interface pcu_phi_sel 1 In Block select from the PCU. Whenpcu_phi_sel is high both pcu_adr and pcu_dataout are valid. pcu_rwn 1 InCommon read/not-write signal from the PCU. pcu_adr[7:2] 6 In PCU addressbus. Only 6 bits are required to decode the address space for thisblock. pcu_dataout[31:0] 32  In Shared write data bus from the PCU.phi_pcu_rdy 1 Out Ready signal to the PCU. When phi_pcu_rdy is high itindicates the last cycle of the access. For a write cycle this meanspcu_dataout has been registered by the block and for a read cycle thismeans the data on phi_pcu_datain is valid. phi_pcu_datain[31:0] 32  OutRead data bus to the PCU.32.9.2 PHI Sub-Block Partition32.9.3 Configuration Registers

The configuration registers in the PHI are programmed via the PCUinterface. Refer to section 21.8.2 on page 321 for a description of theprotocol and timing diagrams for reading and writing registers in thePHI. Note that since addresses in SoPEC are byte aligned and the PCUonly supports 32-bit register reads and writes, the lower 2 bits of thePCU address bus are not required to decode the address space for thePHI. When reading a register that is less than 32 bits wide zeros shouldbe returned on the upper unused bit(s) of phi_pcu_datain. Table 215lists the configuration registers in the PHI TABLE 215 PHI registersdescription Address PHI_base+ Register #bits Reset Description ControlRegisters 0x00 Reset 1 0x1 Active low synchronous reset, selfdeactivating. A write to this register will cause a PHI block reset.0x04 Go 1 0x0 Active high bit indicating the PHI is programmed and readyto use. A low to high transition will cause PHI block internal state toreset. Will be automatically reset if a page finish or a buffer underrunis detected. General Control 0x08 PageLenLine 32 0x0000_0000 Specifiesthe number of dot lines in a page. Indicates the number of lines left toprocess in this page while the PHI is running (Working register) 0x0cPrintStart 1 0x0 A high level enables printing to start via thegeneration of line syncs in a master, and acceptance of line syncs in aslave. Can be set in advance of the print ready signal. 0x10-0x14DotMargin[1:0] 2x16 0x0000 Specifies for each printhead IC, the width ofthe margin in dots divided by 2. Value must be divisible by 2 (i.e. thelow bit must be 0) 0 - Printhead IC Channel A 1 - Printhead IC Channel B0x18-0x2C DotCount[5:0] 6x32 0x0000_0000 Indicates the number of Dotsused for a particular color, where N specifies a color from 0 to 5.Value valid after a write access to DotCountSnap 0x30 DotCountSnap 1 0x0Write access causes the AccumDotCount values to be transferred to theDotCount registers. The AccumDotCount are reset afterwards.(Reads aszero) 0x34 PhiHeadSwap 1 0x0 Controls which signals are connected toprinthead channels A and B 0 - Normal, specifies bit 0 is channel A, bit1 is channel B 1 - Swapped, specifies bit 0 is channel B, bit 1 ischannel A. 0x38 PhiMode 1 0x0 Indicates whether the PHI is operating inmaster or slave mode 0 - Slave Mode 1 - Master Mode 0x3C-0x40PhiSerialOrder 2x1 0x0 Specifies the serialization order of dots beforetransfer to the printhead. Bus 0 - Printhead Channel A Bus 1 - PrintheadChannel B If set to zero the order is dot[1:0], then dot[3:2] thendot[5:4]. If set to one then the order is dot[5:4], dot[3:2], dot[1:0].0x44-0x48 PrintHeadSize 2x16 0x0000 Specifies the number of non-margindots in the printhead ICs (must be even). If margining is to be usedthen the configured PrintHeadSize should be adjusted by the dot marginvalue i.e. PrintHeadSize = (Physical- PrintHeadSize − (DotMargin * 2)).Value must be divisible by 2 (i.e. the low bit must be 0) Bus 0 -Specifies printhead on Channel A Bus 1 - Specifies printhead on ChannelB CPU Direct PHI Control (See Table 213.) 0x4C PrintHeadCpuIn 3 0x0 PHIinterface pins input status. Only active in direct CPU mode (Read OnlyRegister) 0x50 PrintHeadCpuDir 3 0x0 PHI interface pins directioncontrol. Only active in direct CPU mode 0x54 PrintHeadCpu 10 0x000 PHIinterface pins output control. Only Out active in direct CPU mode 0x58PrintHeadCpuCtrl 1 0x1 Control direct access CPU access to the PHI pins0 - Normal Mode 1 - Direct CPU Control mode 0x5C Print- 1 0x0 Specifiesif the pin is controlled by the HeadCpuCtrlMode PrintHeadCpuOut registeror by the Fire generator logic. Only active when PrintHeadCpuCtrl is 1and pin is in output mode. Bit 0 - controls the frclk pin When the bitis 0 - Pin is controlled by PrintHeadCpuOut 1 - Pin is controlled byFire Generator Logic Line Sync Control 0x60 LsyncHigh 24 0x00_0000 InMaster mode specifies the number of pclk cycles phi_lsyncl should remainhigh. In Slave mode specifies the minimum number of pclk cycles betweenLsync pulses. Lsync pulses of a shorter period will cause the PHI tohalt due to buffer underrun. 0x64 LsyncLow 16 0x0000 Number of pclkcycles phi_lsyncl should remain low. 0x68 LsyncPre 16 0x0000 Number ofpclk cycles between PrintStart rising transition and the generatedphi_lsyncl falling edge 0x6C LsyncDeglitchCnt 4 0x3 Number of pclkcycles to filter the incoming Lsync pulse from the master. Only used inslave mode. 0x70 LineSyncInterrupt 16 0x0000 Number of line syncs tooccur before generating an interrupt. When set to zero interrupt isdisabled. Shift Register Control 0x74 SrclkPre 14 0x0000 Number of pclkcycles between phi_lsyncl falling edge and phi_srclk pulse generation,or printhead data transfer 0x78 SrclkPost 14 0x0000 Number of pclkcycles allowed margin from last srclk pulse in a line to before nextline sync 0x7C-0x80 PrintHeadRate[1:0] 2x16 0xFFFF Specifies the activeto inactive ratio of phi_srclk for the printhead ICs. A 1 indicatesActive. Bus 0 - Printhead IC channel A Bus 1 - Printhead IC channel B0x84 DotOrderMode 1 0x0 Specifies the dot transmit order to theprinthead Channel A. Printhead Channel B is always the opposing order.0 - Even before Odd dots 1 - Odd before Even dots Fire Control 0x98FrclkPre 14 0x0000 Number of pclk cycles after lsyncl transitions from 0to 1 to phi_frclk pulse generation 0x9C FrclkLow 14 0x0000 Number ofpclk cycles phi_frclk should remain low. 0xA0 FrclkHigh 14 0x0000 Numberof pclk cycles phi_frclk should remain high. 0xA4 FrclkNum 16 0x0000Number of phi_frclk pulses per line time. 0xA8 FireGenSoftTrigger 1 0x0Only active when PrintHeadCpuCtrlMode is set to 1, PrintHeadCpuCtrl is 1and pin is in output mode. Bit 0 controls frclk generator. A 0 to 1transition on a bit triggers the corresponding generator to create theprogrammed pulse profile (configured by FrclkNum, FrclkHigh, FrclkLow,FrclkPre registers) when complete the bit gets reset to 0. WorkingRegisters 0xAC-0xB0 LineDotCnt 2x16 0x0000 Indicates the number of dotprocessed in the current line Bus 0 - Printhead Channel A Bus 1 -Printhead Channel B (Read Only Registers)

The configuration registers in the PHI block are clocked at pclk ratesbut some blocks in the PHI are clocked by different and asynchronousclocks. Configuration values are not re-synchronized, it is thereforeimportant that the Go register be set to zero while updatingconfiguration values. This prevents logic from entering unknown statesdue to metastable clock domain transfers.

Some registers can be written to at any time such as the direct CPUcontrol registers (PrintheadCpuIn, PrintheadCpuDir, PrintheadCpuOut andPrintheadCpuCtrl), the Go register and the PrintStart register. Allregisters can be read from at any time.

32.9.4 Dot Counter

The dot counter keeps a running count of the number of dots fired foreach color plane. The counters are 32 bits wide and will saturate. Whenthe CPU wants to read the dot count for a particular color plane it mustwrite to the DotCountSnap register. This causes all 6 running countervalues to be transferred to the DotCount registers in the configurationregisters block. The running counter values are reset. // reset if beingsnapped if (dot_cnt_snap == 1) then{  dot_count[5:0] =accum_dot_count[5:0]  accum_dot_count[5:0] = 0  } // update the countsfor (color=0;color < 6;color++) {  if (accum_dot_count[color] !=0xffff_ffff) {   // data valid, first dot stream   data_valid  = ((phi_llu_ready[0]  ==  1)  AND (llu_phi_avail[0] == 1))   if((data_valid == 1) AND (llu_phi_data[0][color] == 1)) then   accum_dot_count[color] ++   // data valid, second dot stream  data_valid  =  ((phi_llu_ready[1]  ==  1)  AND (llu_phi_avail[1] ==1))   if ((data_valid == 1) AND (llu_phi_data[1][color] == 1)) then   accum_dot_count[color] ++   }  }32.9.5 Sync Generator

The sync generator logic has two modes of operation, master and slavemode. In master mode (configured by the PhiMode register) it generatesthe lsyncl_o output based on configured values and control triggers fromthe PHI controller. In slave mode it de-glitches the incoming lsyncl_isignal, and filters the lsyncl signal with the minimum configuredperiod.

After reset or a pulse on phi_go_pulse the machine returns to the Resetstate, regardless of what state it's currently in.

The state machine waits until it's enabled (sync_en==1) by the PHIcontroller state machine. When enabled it can proceed to the SyncPre orSyncWait depending on whether the state machine is configured in masteror slave mode. In master mode it generates the lsyncl pulses, in slavemode it receives and filters the lsyncl pulses from the master syncgenerator.

On transition to the SyncPre state a counter is loaded with the LsyncPrevalue, and while in the SyncPre the counter is decremented. When thecount is zero the machine proceeds to the SyncLow state loading thecounter with LsyncLow value.

The machine waits in the SyncLow state until the counter has decrementedto zero. It proceeds to the SyncHigh state pulsing the line_st signal ontransition and counts LsyncHigh number of cycles. This indicates to thePHI controller the line start aligned to the lsyncl positive edge. Whilein LsyncLow state the lsyncl_o output is set to 0 and in SyncHigh thelsyncl_o output is set to 1. When the count is zero and the current lineis not the last (last_line==0), the machine returns to the SyncLow stateto begin generating a new line sync pulse. The transition pulses theline_fin signal to the PHI controller.

The loop is repeated until the current line is the last (last_line==1),and the machine returns to the Reset state to wait for the next pagestart.

In slave mode the state machine proceeds to the SyncWait state whenenabled. It waits in this state until a-lsync_pulse_rise is receivedfrom the input de-glitch circuit. When a pulse is detected the machinejumps to the SyncPeriod state and begins counting down the LsyncHighnumber of clock cycles before returning to the SyncWait state. Note inslave mode the LsyncHigh specifies the minimum number of pclk cyclesbetween Lsync pulses. On transition from the SyncWait to the SyncPeriodstate the line_st signal to the PHI controller is pulsed to indicate theline start. While in the SyncPeriod state if a lsync_pulse_fall isdetected the state machine will signal a sync error (via sync_err) tothe PHI controller and cause a buffer underrun interrupt.

32.9.5.1 Lsyncl Input De-Glitch

The lsync_i input is considered an asynchronous input to the PHI, and ispassed through a synchronizer to reduce the possibility of metastablestates occurring before being passed to the de-glitch logic.

The input de-glitch logic rejects input states of duration less than theconfigured number of clock cycles (lsync_deglitch_cnt), input states ofgreater duration are reflected on the output, and are negative andpositive edge detected to produce the lsync_pulse_fall andlsync_pulse_rise signal to the main generator state machine. The counterlogic is given by if ( lsync_i != lsync_i_delay) then  cnt   =lsync_deglitch_cnt  output_en = 0 elsif (cnt == 0 ) then  cnt   = cnt output_en = 1 else  cnt −− output_en = 032.9.5.2 Line Sync Interrupt Logic

The line sync interrupt logic counts the number of line syncs that occur(either internally or externally generated line syncs) and determineswhether to generate an interrupt or not. The number of line syncs itcounts before an interrupt is generated is configured by theLineSyncInterrupt register. The interrupt is disabled ifLineSyncInterrupt is set to zero. // implement the interrupt counter if(phi_go_pulse ==1) then  line_count = 0 elsif (line_st == 1) AND(line_count == 0)) then   line_count = linecount_int elsif ((line_st== 1) AND (line_count != 0)) then   line_count −− // determine when topulse the interrupt if (linesync_int == 0 ) then // interrupt disabled phi_icu_linesync_int = 0; elsif ((line_st == 1) AND (line_count == 1))then  phi_icu_linesync_int = 132.9.6 Fire Generator

The fire generator block creates the signal profile for the phi_frclksignal to the printhead. The frclk is based on configured values and istimed in relation to the fire_st pulse from the PHI controller block.Should the phi_frclk state machine receive a fire_st pulse before it hascompleted the sequence the machine will restart regardless of itscurrent state.

Alternatively the frclk state machine can be triggered to generate theirconfigured pulse profile by software. A low to high transition on theFireGenSoftTrigger register will cause a pulse on soft_frclk_sttriggering the state machine to begin generating the pulse profile. Whenthe state machine has completed its sequence it will clear theFireGenSoftTrigger register bit (via soft_fire_clr signal). TheFireGenSoftTrigger register will only be active when the printheadinterface is in CPU direct control mode (PrintheadCpuCtrl=1), the firegenerator is in software trigger mode (PrintheadCpuCtrlMode[x]=1) andthe pin is configured to be output mode (PrintheadCpuDir[x]=1).

The fire generator consists of a state machine for creating thephi_frclk signal. The phi_frclk signal is generated relative to thelsyncl signal.

The machine is reset to the Reset state when phi_go_pulse==1 or thereset is active, regardless of the current state.

The machine waits in the reset state until it receives a fire_st pulsefrom the PHI controller (or an soft_fire_st from the configurationregisters). The controller will generate a fire_st pulse at thebeginning of each dot line. On the state transition the cycle counter isloaded with the FrclkPre value and the repeat counter is loaded with theFrclkNum value.

The state machine waits in the FirePre state until the cycle counter iszero, after which it jumps to the FireHigh state and loads the cyclecounter with FrclkHigh value. Again the state machine waits until thecount is zero and then proceeds to the FireLow state. On transition thecycle counter is loaded with the FireLow value. The state machine waitsin the FireLow state while the cycle counter is decremented.

When the cycle counter reaches zero and the repeat_count is non-zero,the repeat_count is decremented, the cycle counter is loaded with theFrclkHigh value and the state machine jumps to the FireHigh state torepeat the phi_frclk generation cycle. The loop is repeated until therepeat_count is zero. In such cases_the state machine goes to the resetstate resetting FireGenSoftTrigger (via the soft_fire_clr signal)register on the transition and waits for the next fire_st pulse.

When in the Reset state the fire_rdy signal is active to indicate to thecontroller that the fire generator is ready.

32.9.7 PHI Controller

The PHI controller is responsible for controlling all functions of thePHI block on a line by line basis. It controls and synchronizes the syncgenerator, the fire generator, and datapath unit, as well as signallingback to the CPU the PHI status. It also contains a line counter todetermine when a full page has completed printing.

The PHI controller state machine is reset to Reset state by a reset orphi_go_pulse==1.

It will remain in reset until the block is enabled by phi_go==1. Onceenabled the state machine will jump to the FirstLine state, trigger thetransfer of one line of data to the printhead (data_st==1) and the linecounter will be initialized to the page length (PageLenLine). Once theline is transferred (data_fin from the datapath unit) the machine willgo to PrintStart state and signal the CPU using an interrupt that thePHI is ready to begin printing (phi_icu_print_rdy). The line counterwill also be decremented. It will then wait in the PrintStart stateuntil the CPU acknowledges the print ready signal and enables printingby writing to the PrintStart register.

The state machine proceeds to the SyncWait state and waits for a linestart condition (line_st==1). The line start condition is differentdepending on whether the PHI is configured as being in a master or slaveSoPEC (the PhiMode register). In either case the sync generatordetermines the correct line start source and signals the PHI controllervia the line_st signal. Once received the machine proceeds to theLineTrans state, with the transition triggering the fire generator tostart (fire_st), the datapath unit to start (data_st) and the syncgenerator to start (sync_st).

While in the LineTrans state the fire, sync and datapath unit will beproducing line data. When finished processing a line the datapath unitwill assert the line finished (data_fin) signal. If the line counter isnot equal to 1 (i.e. not the last line) the state machine will jump backto the SyncWait state and wait for the start condition for the nextline. The line counter will be decremented. If the line counter is onethen the machine will proceed to the LastLine state.

The LastLine state generates one more line of fire pulses to print thelast line held in the shift registers of the printhead. Once complete(fire_fin==1) the state machine returns to the reset state and waits forthe next page of data. On page completion the state machine generates aphi_icu_page_finish interrupt to signal to the CPU that the page hascompleted, the phi_icu_page_finish will also cause the Go register toreset automatically.

While the state machine is in the LineTrans state (or in FirstLine stateand the PHI is in slave mode) and waiting for the datapath unit tocomplete line processing, it is possible (e.g. an excessive PEP stall)that a line finish condition occurs (line_fin==1) but the datapath unitis not ready. In this case an underrun error is generated. The statemachine goes to the Underrun state and generates a phi_icu_underruninterrupt to the CPU. The PHI cannot recover from a buffer underrunerror, the CPU must reset the PEP blocks and re-start printing. Thephi_icu_underrun will also cause the Go register to reset automatically.

32.9.8 CPU IO Control

The CPU IO control block is responsible for providing direct CPU controlof the IO pins via the configuration registers. It also accepts theinput signals from the printhead and re-synchronizes them to the pclkdomain, and debug signals from the RDU and muxes them to output pins.Table contains the direct mapping of configuration registers toprinthead IO pins. Direct CPU control is enabled only whenPrintheadCpuCtrl is set to one. In normal operation (i.e.PrintheadCpuCtrl==0) the printhead frclk pin is always in output mode(phi_frclk_e=1), the phi_lsyncl will be in output if the SoPEC is themaster, i.e. phi_lsyncl_e=phi_mode, and readl will be set high.

The PrintheadCpuCtrlMode register determine whether the frclk pin shouldbe driven by the fire generator logic or direct from the CPUPrintheadCpuOut register.

The pseudocode for the CPU IO control is: if (printhead_cpu_ctrl == 1)then // CPU access enabled // outputs if (PrintHeadCpuCtrlMode[0] == 1)then // fire generator controlled phi_frclk_o = frclk else // normaldirect CPU control phi_frclk_o = printhead_cpu_out[1]phi_ph_data_o[0][1:0] = printhead_cpu_out[4:3] phi_ph_data_o[1][1:0] =printhead_cpu_out[6:5] phi_srclk[1:0] = printhead_cpu_out[8:7] phi_readl= printhead_cpu_out[9] // direction control phi_lsyncl_e =printhead_cpu_dir[0] phi_frclk_e = printhead_cpu_dir[1] // inputassignments printhead_cpu_in[0] = synchronize(phi_lsyncl_i)printhead_cpu_in[1] = synchronize(phi_frclk_i) else // normalconnections // outputs phi_ph_data_o[0][1:0] = ph_data[0][1:0]phi_ph_data_o[1][1:0] = ph_data[1][1:0] phi_lsyncl_o = lsync_o phi_readl= 1 phi_srclk[1:0] = srclk[1:0] phi_frclk_o = frclk // direction controlphi_frclk_e = 1 phi_lsyncl_e = phi_mode  // depends on Master or Slavemode // inputs lsyncl_i = phi_lsync_i // connected regardless // debugoverrides any other connections if (debug_cntrl[0] == 1) thenphi_frclk_o = debug_data_valid phi_frclk_e = 1 phi_readl = pclk

The debug signalling is controlled by the RDU block (see Section 11.8Realtime Debug Unit (RDU)), the 10 control in the PHI muxes debug dataonto the PHI pins based on the control signals from the RDU.

32.9.9 Datapath Unit

32.9.10 Dot Order Controller

The dot order controller is responsible for controlling the dot orderblocks. It monitors the status of each block and determines the switchover point, at which the connections from odd and even dot streams toprinthead channels are swapped.

The machine is reset to the Reset state when phi_go_pulse==1 or thereset is active. The machine will wait until it receives a data st pulsefrom the PHI controller before proceeding to the LineStart state. On thetransition to the LineStart state it will reset the dot counter in eachdot order block via the dot_cnt_rst signal.

While in the LineStart state both dot order blocks are enabled(gen_en==1). The dot order blocks process data until each of them reachtheir mid point. The mid point of a line is defined by the configuredprinthead size (i.e. print_head_size). When a dot order block reachesthe mid point it immediately stops processing and waits for theremaining dot order block. When both dot order blocks are at the midpoint (mid_pt==11) the controller clocks through the LineMid state toallow the pipeline to empty and immediately goes to LineEnd state.

In the LineEnd state the mode_sel is switched and the dot order blocksre-enabled, in this state the dot order blocks are reading data from theopposite LLU dot data stream as in LineStart state. The controllerremains in the LineEnd state until both dot order blocks have processeda line i.e. line_fin==11.

On completion of both blocks the controller returns to the Reset stateand again awaits the next data_st pulse from the PHI controller. When inReset state the machine signals the PHI controller that it's ready tobegin processing dot data via the dot_order_rdy signal.

The dot order controller selects which dot streams should feed whichprinthead channels. The order can be changed by configuring theDotOrderMode register. In all cases Channel A and Channel B must be inopposing dot order modes. Table 216 shows the possible modes ofoperation. TABLE 216 Mode selection in Dot order controller. ChannelMode_sel DotOrderMode Dot transmit order A 0 0 Even before Odd (EBOmode), even dot stream feeds Channel A printhead, first half line. 0 1Odd before Even (OBE mode), odd dot stream feeds Channel A printhead,first half line. 1 0 Even before Odd (EBO mode), even dot stream feedsChannel A printhead, second half line. 1 1 Odd before Even (OBE mode),odd dot stream feeds Channel A printhead, second half line. B 0 0 Oddbefore Even (OBE mode), odd dot stream feeds Channel B printhead, secondhalf line 0 1 Even before Odd (EBO mode), even dot stream feeds ChannelB printhead, second half line. 1 0 Odd before Even (OBE mode), odd dotstream feeds Channel B printhead, first half line. 1 1 Even before Odd(EBO mode), even dot stream feeds Channel B printhead, first half line.32.9.10.1 Dot Order Unit

The dot order control accepts dot data from either dot stream from theLLU and writes the dot data into the dot buffer. It has two modes ofoperation, odd before even (OBE) and even before odd (EBO). In the OBEmode data from the odd stream dot data is accepted first then even, inEBO mode it's vice versa. The mode is configurable by the DotOrderModeregister.

The dot order unit maintains a dot count that is decremented each time anew dot is received from the LLU. The dot order controller resets thedot counter to the print_head_size[15:0] at the start of a new line viathe dot_cnt_rst signal. The dot count is compared with the printheadsize (print_head_size[15:0] divided by 2) to determine the mid point(mid_Pt) and the line finish point (line_fin) when the dot counter iszero.

The mid point is defined as the half the number of dots in a particularprinthead, and is derived from the the print_head_size bus by dividingby 2 and rounding down. // define the mid point if (dot_cnt[15:0] ==print_head_size[15:1] )then   mid_pt = 1 else   mid_pt = 0

The dot order unit logic maintains the dot data write pointer. Each timea new dot is written to the dot buffer the write pointer is incremented.The fill level of the dot buffer is determined by comparing the read andwrite pointers. The fill level is used to determine when to backpressurethe LLU (ready signal) due to the dot buffer filling. A suitablethreshold value is determined to allow for the full LLU pipeline toempty into the dot buffer.

The dot order stalling control is given by: // determine the ready/availsignal to use, based on mode select if (mode_sel == 1) then  dot_active= llu_phi_avail[0] AND ready  wr_data = llu_phi_data[0] else  dot_active= llu_phi_avail[1] AND ready  wr_data = llu_phi_data[1] // update thecounters if (dot_active == 1) then {  wr_en = 1  wr_adr ++  if (dot_cnt== 0) then   dot_cnt = print_head_size  else   dot_cnt−−  }

The dot writer needs to determine when to stall the LLU dot data stream.A number of factors could stall the dot stream in the LLU such as bufferfilling, waiting for the mid point, waiting for the line finish or thedot order controller is waiting for the line start condition from thePHI controller.

The stall logic is given by: // determine when to stall the LLUgenerator fill_level = wr_adr − rd_adr if (fill_level > (32 − THRESHOLD))then  // THRESHOLD is open value  ready = 0        // buffer is closeto full elsif ( gen_en == 0) then  ready = 0         // stalled by thedatapath controller else  ready = 1        // everything good no stall32.9.10.2 Data Generator

The data generator block reads data from the dot buffer and feeds dotdata to the printhead at a configured rate (set by the PrintheadRate).It also generates the margin zero data and aligns the dot datageneration to the synchronization pulse from the PHI controller.

The data generator controller waits in Reset state until it receives aline start pulse from the PHI controller (data_st signal). Once a startpulse is received it proceeds to the SrclkPre state loading a counterwith the SrclkPre value. While in this state it decrements the counter.No data is read or output at this stage. When the count is zero themachine proceeds to the DataGen1 state.

On transition it loads the counter with the printhead size(print_head_size). If margining is to be used then the configured printhead_size should be adjusted by the dot margin value i.e.print_head_size=(physical_print_head_size−(dot_margin*2)).

Dot data is transferred to the printhead serializer in dot-pairs, withone dot-pair transferred every 3 pclk cycles. To construct a dot datapair the state machine reads one dot in the DataGen1 state, one dot inthe DataGen2 state and waits for one clock cycle in the DataGen3 whilethe data is transferred to the data serializer. The counter willdecrement for every dot data word transferred. The exact data rate isdictated by the dot buffer fill levels and the configured printhead rate(PrintheadRate). When in DataGen3 state the machine determines if itshould waits for 3 cycles or transfer another dot pair to the dataserializer. The generator determines the rate by comparing the ratecounter (rate_cnt) with the configured PrintheadRate value. If the bitselected by the rate_cnt in the print_head_rate bus is one data istransferred, otherwise the 3 cycles are skipped (Wait1, Wait2 andWait3). If the PrintheadRate is set to all zeros then no data will everget transferred. The rate counter is decremented (rate_cnt) while in theDataGen2 and Wait2 states. The rate counter is allowed to wrap normally.

The pseudo-code for the rate control DataGen3 (or Wait3) state is givenby: // decrement the rate count rate_cnt −−        // happens inDataGen2, or Wait2 // determine if data should be read // firstdetermine if data is available in buffer if (rd_adr != wr_adr ) then  if(print_head_rate[rate_cnt] == 1 ) then   dot_active = 1   gate_srclk = 1  count −−   next_state = DataGen1  else   dot_active = 0   gate_srclk =0   next_state = Wait1 else  dot_active = 0  gate_srclk = 0  next_state= Wait1

When the dot counter reaches zero the state machine will jump to theMarginGen1 state if the configured margin value is non-zero, otherwiseit will jump directly to the SrclkPost state. On transition toMarginGen1 state it loads the cycle counter with the dot_margin value,and begins to count down. While in the MarginGen1, MarginGen2 andMarginGen3 state machine loop the data generator logic block writes dotdata to the printhead but does not read from the dot buffers. It createszero dot data words for the margin duration. As with normal dot data, itcreates one dot in MarginGen1 and MarginGen2 states, then wait a clockcycle to allow the transfer to the data serializer to complete.

When the counter reaches zero the machine jumps to the SrclkPost state,loads the clock counter with the SrclkPost value and decrements. Whenthe count is finished the state machine returns to the Reset and awaitsthe next start pulse. Should a line sync arrive before the datagenerators have completed (data_fin signal) the PHI controller willdetect a print error and stall the PHI interface.

As a consequence of the data transfer mechanism of dot pair cyclesfollowed by a wait state, the printhead size (print_head_size) and dotmargin (dot_margin) must always be even dot values.

32.9.10.3 Data Serializer

The data serializer block converts 12-bit dot data at pclk rates(nominally 160 MHz) to 2-bit data at doclk rates (nominally 320 MHz).

The srclk is only active when data is available for transfer to theprinthead, as enabled by the gate_srclk signal. The data rate mechanismin the data generator block will mean that data is not transferred tothe printhead on every set of 3 pclk cycles. Both the dot_data andgate_srclk signals are controlled by the data generator block and canonly change on a fixed 3 pclk cycle boundary. Data is transferred to theprinthead on both edges of srclk (i.e double data rate DDR). Directlyafter a line sync pulse the mux control logic and the srclk generationlogic are reset to a known state (the srclk is set high). Before datacan begin transfer to the printhead it must generate a line setup edgeon srclk, causing srclk to go low. The line setup edge happens SrclkPrenumber of pclk cycles after the line sync falling edge (indicated by thesr_init signal from the data generator block).

All data transfers to the printhead will be in groups of 6 2-bit datawords, each word clocked on an edge of srclk. For each group srclk willstart low and end low.

At the end of a full line of data transfer the srclk must generate aline complete edge to return the srclk to a high state before the nextline sync pulse. The data generator block generates a sr_corn signal toindicate that the data transfer to the printhead has completed and thatthe line complete edge can be inserted. The sr_com signal is generatedbefore the SrClkPost period.

The data serializer block allows easy separation of clock gating andclock to logic structures from the rest of the PHI interface.

The mux logic determines which data bits from the dot_data bus should beselected for output on the ph_data bus to the printhead. The muxselector is initialized by an edge detect on the sr_init signal from thedata generator. // determine wrap and init points if (phi_serial_order== 1) then  mux_wrap = 5  mux_init = 0 else  mux_wrap = 0  mux_init = 5// the mux selector logic if ((sr_init_edge == 1)OR( mux_sel == mux_wrap)) then  mux_sel = mux_init elsif ( phi_serial_order == 1 ) then mux_sel−−          // decrement order else  mux_sel++          //increment order

The dot data serialization order can be configured by PhiSerialOrderregister. If the PhiSerialOrder is zero the order is dot[1:0], thendot[3:2] then dot[5:4]. If the register is one then the order isdot[5:4], dot[3:2], dot[1:0].

The srclk control logic is initialized to 1 when a line_st positive edgeis detected. If either sr_com_edge, sr_init_edge or gate_srclk are equalto one srclk is transitioned. srclk is always clocked out to the outputpins on the negative edge of doclk to place the clock edge in the centreof the data.

The pseudo code for the control logic is: if (line_st_edge ==1 ) then srclk_gen = 1 elsif  ((gate_srclk  ==1)  OR  (sr_init_edge==1)  OR(sr_com_edge==1)) then  srclk_gen = ˜srclk_gen else  // hold33 Package and TestTest Units33.1 JTAG Interface

A standard JTAG (Joint Test Action Group) Interface is included in SoPECfor Bonding and 10 testing purposes. The JTAG port will provide accessto all internal BIST (Built In Self Test) structures.

33.2 Scan Test I/O

The SoPEC device will require several test IO's for running scan tests.In general scan in and scan out pins will be multiplexed with functionalpins.

33.3 Analog Test Units

33.3.1 USB PHY Testing

The USB phy analog macro, will contain built-in in test structure, whichcan be access by either the CPU or through the JTAG port.

33.3.2 Embedded PLL Testing

The embedded clock generator PLL will require test access from JTAGport.

34 SoPEC Pinning and Package

34.1 Overview

It is intended that the SoPEC package be a 100 pin LQFP. Any spare pinsin the package may be used by increasing the number of available GPIOpins or adding extra power and ground pin. The pin list shows theminimum pin requirement for the SoPEC device. TABLE 217 SoPEC Pin List(100 LQFP) I/O Test Rate Freq Test Macro Group Pin Name #pin s Dir TypeVolt (S/D) (Mhz) Description IO Cell Type Function Function Clocks andresets Group 1 Xtalin 1 I N/A N/A 32 Crystal AINSA_PM_A None Input pinXtalout 1 O N/A N/A 32 Crystal ABNST_PM_A None output pin Group 2reset_n 1 I LVTTL 3.3 v s 10 Asynchronous IT33LTPUT_PM_A LT (leakageactive test) low reset PrintHead Interface Group 3 phead_data 8 O LVDS1.5 v d 160 Print head OLVDS15_PM_A None data Srclk 4 O LVDS 1.5 v d 160Print head OLVDS15_PM_A None clock Group 4 Readl 1 O LVTTL 3.3 v s 160Common BT3365T_PM_A A_Clock Print head mode control Frclk 1 I/O LVTTL3.3 v s 160 Common BT3365T_PM_A B_Clock Fire pattern shift clock, needsto toggle once per fire cycle phi_spare 1 I/O LVTTL 3.3 v s 160 PHIspare BT3365T_PM_A C_Clock1 pin (old profile pin) Lsyncl 1 I/O LVTTL 3.3v s 160 Line Sync BT3365T_PM_A C_Clock2 output from Master to Slaves USBConnections Group 5 Usb_hostd 2 I/O Differ- 3.3 v s 12 USB BUSB2_PM_ANone ential differential data for host Usb_devd 2 I/O Differ- 3.3 v s 12USB BUSB2_PM_A None ential differential data for device Group 6usbd_vbus_sense 1 I LVTTL 3.3 v s 10 USB device BT3365T_PM_C 1 scan outVBUS power sense usbd_pull_up_en 1 O LVTTL 3.3 v s 10 USB deviceBT3365T_PM_C 1 scan out termination enable JTAG Group 7 Tdo 1 O LVTTL3.3 v s 10 JTAG Test BT3365T_PM_A C_Clock3 data out port Tms 1 I LVTTL3.3 v s 10 JTAG Test IT33RIT_PM_A RI mode select Tdi 1 I LVTTL 3.3 v s10 JTAG Test IT33D1PUT_PM_A DI1 data in port Tck 1 I LVTTL 3.3 v s 10JTAG Test IT33D2PUT_PM_A DI2 access port clock General Purpose IO Group8 Gpio[3:0] 4 I/O LVTTL 3.3 v s 32 ISI BT3335PUT_PM_B 4 Scanin interfacepins/GPIO Group 9 Gpio[7:4] 4 I/O High 3.3 v s 32 LED driverBT3365T_PM_C 4 Scanin PCNT Drive pins/ PROGSROM LVTTL general OSCpurpose Input/Output Group Gpio[19:8] 12 I/O LVTTL 3.3 v s 32 GeneralBT3365PUT_PM_B 2 Scanin 10 DIAGOUT 10 purpose Scanout (aka Input/OutputMRSTR0) Group Gpio[22:20] 3 I/O LVTTL 3.3 v s 32 General BT3365PUT_PM_BCE0_Scan 11 purpose TESTM3 Input/Output TSTN1 Group Gpio[31:23] 10 I/OLVTTL 3.3 v s 32 Functional BT3365T_PM_C 6 Scanin 4 12 Spare IOs scanoutrequired for scan test Analog Power IO Group agnd 1 I Power N/A N/A N/APLL analog AINSD3_PM_A None 13 gnd avdd 1 I Power N/A N/A N/A PLL analogAINSD3_PM_A None vdd agnd 1 I Power N/A N/A N/A Oscillator AINSD_PM_ANone analog gnd avdd 1 I Power N/A N/A N/A Oscillator AINSD_PM_A Noneanalog vdd Test Only Pin Group TE 1 I CMOS 1.5 v N/A N/A Test EnableIC15TEPDT_PM_A Test only 14 VPP 1 I CMOS 1.5 v N/A N/A Fat WireDRAMVPP_PM Test only Analog Receiver/ Driver for Embedded DRAM AnalogInputs VWP 1 I CMOS 1.5 v N/A N/A Fat Wire DRAMVWP_PM Test only AnalogReceiver/ Driver for Embedded DRAM Analog Inputs VREFX 1 I CMOS 1.5 vN/A N/A Fat Wire DRAMVREFX_PM Test only Analog Receiver/ Driver forEmbedded DRAM Analog Inputs DLT 1 I CMOS 1.5 v N/A N/A DRAMIC15DLTPUT_PM Test only Iddq Test MC 1 I CMOS 1.5 v N/A N/A IO ModeIC15MCT_PM_A Test only Control DRAM_EN 1 I CMOS 1.5 v N/A N/A DRAMIC15LTPUT_PM_A Test only Enable(EN) Total Signal Pins 73 Functional pincount is 62 Test IO count 51 Power Only Pins Group Gnd 8 I Power N/A N/AN/A gnd GND_PM_A None 15 Vdd 4 I Power N/A N/A N/A vdd 1.5 v,VDD150_PM_A None core voltage vdd330 4 I Power N/A N/A N/A vdd 3.3 v,VDD330_PM_A None IO voltage Group vdd/gnd 11 I Power N/A N/A N/A Powerpin GND_PM_A/ None 15 fill, VDD150_PM_A/ GND.Vdd1.5, VDD330_PM_A Vdd3.3as required Total Pins 100Bilithic Printheads1 Background

Silverbrook's bilithic Memjet™ printheads are the target printheads forprinting systems which will be controlled by SoPEC and MoPEC devices.

This document presents the format and structure of these printheads, anddescribes the their possible arrangements in the target systems. It alsodefines a set of terms used to differentiate between the types ofprintheads and the systems which use them.

Bilithic Printhead Configurations

2 Definitions

This document presents terminology and definitions used to describe thebilithic printhead systems. These terms and definitions are as follows:

-   -   Printhead Type—There are 3 parameters which define the type of        printhead used in a system:    -   Direction of the data flow through the printhead (clockwise or        anti-clockwise, with the printhead shooting ink down onto the        page).    -   Location of the left-most dot (upper row or lower row, with        respect to V₊,).    -   Printhead footprint (type A or type B, characterized by the data        pin being on the left or the right of V₊, where V₊ is at the top        of the printhead).    -   Printhead Arrangement—Even though there are 8 printhead types,        each arrangement has to use a specific pairing of printheads, as        discussed in Section 3. This gives 4 pairs of printheads.        However, because the paper can flow in either direction with        respect to the printheads, there are a total of eight possible        arrangements, e.g. Arrangement 1 has a Type 0 printhead on the        left with respect to the paper flow, and a Type 1 printhead on        the right. Arrangement 2 uses the same printhead pair as        Arrangement 1, but the paper flows in the opposite direction.    -   Color 0 is always the first color plane encountered by the        paper.    -   Dot 0 is defined as the nozzle which can print a dot in the        left-most side of the page.    -   The Even Plane of a color corresponds to the row of nozzles that        prints dot 0.

Note that in all of the relevant drawings, printheads should beinterpreted as shooting ink down onto the page.

FIG. 295 shows the 8 different possible printhead types. Type 0 isidentical to the Right Printhead presented in FIG. 297 in [1], and Type1 is the same as the Left Printhead as defined in [1].

While the printheads shown in FIG. 295 look to be of equal width (havingthe same number of nozzles) it is important to remember that in atypical system, a pair of unequal sized printheads may be used.

2.1 Combining Bilithic Printheads

Although the printheads can be physically joined in the manner shown inFIG. 296, it is preferable to provide an arrangment that allows greaterspacing between the 2 printheads will be required for two main reasons:

-   -   inaccuracies in the backetch    -   cheaper manufacturing cost due to decreasing the tolerance        requirements in sealing the ink reservoirs behind the printhead

Failing to account for these inaccuracies and tolerances can lead tomisalignment of the nozzle rows both vertically and horizontally, asshown in FIG. 297.

An even row of color n on printhead A may be vertically misaligned fromthe even row of color n on printhead B by some number of dots e.g. inFIG. 297 this is shown to be 5 dots. And there can also be horizontalmisalignment, in that the even row of color n printhead A is notnecessarily aligned with the even row of color n+1 on printhead A, e.g.in FIG. 297 this horizontal misalignment is 6 dots.

The resultant conceptual printhead definition, shown in FIG. 297 hasproperties that are appropriately parameterized in SoPEC and MoPEC tocater for this class of printheads.

The preferred printheads can be characterized by the following features:

-   -   All nozzle rows are the same length (although may be        horizontally displaced some number of dots even within a color        on a single printhead)    -   The nozzles for color n printhead A may not be printing on the        same line of the page as the nozzles for color n printhead B. In        the example shown in FIG. 297, there is a 5 dot displacement        between adjacent rows of the printheads.    -   The exact shape of the join is an arbitrary shape although is        most likely to be sloping (if sloping, it could be sloping        either direction)    -   The maximum slope is 2 dots per row of nozzles    -   Although shift registers are provided in the printhead at the 2        sides of the joined printhead, they do not drive nozzles—this        means the printable area is less than the actual shift        registers, as highlighted by FIG. 298.        2.2 Printhead Arrangements

Table 218 defines the printhead pairing and location of the eachprinthead type, with respect to the flow of paper, for the 8 possiblearrangements Printhead Printhead on left side, on right side, Printheadwith respect to with respect to Arrangement the flow of paper the flowof paper Arrangement 1 Type 0 Type 1 Arrangement 2 Type 1 Type 0Arrangement 3 Type 2 Type 3 Arrangement 4 Type 3 Type 2 Arrangement 5Type 4 Type 5 Arrangement 6 Type 5 Type 4 Arrangement 7 Type 6 Type 7Arrangement 8 Type 7 Type 63 Bilithic Printhead Systems

When using the bilithic printheads, the position of the power/gnd barscoupled with the physical footprint of the printheads mean that we mustuse a specific pairing of printheads together for printing on the sameside of an A4 (or wider) page, e.g. we must always use a Type 0printhead with a Type 1 printhead etc.

While a given printing system can use any one of the eight possiblearrangements of printheads, this document only presents two of them,Arrangement 1 and Arrangement 2, for purposes of illustration. These twoarrangements are discussed in subsequent sections of this document.However, the other 6 possibilities also need to be considered.

The main difference between the two printhead arrangements discussed inthis document is the direction of the paper flow. Because of this, thedot data has to be loaded differently in Arrangement 1 compared toArrangement 2, in order to render the page correctly.

3.1 EXAMPLE 1

Printhead Arrangement 1

FIG. 299 shows an Arrangement 1 printing setup, where the bilithicprintheads are arranged as follows:

-   -   The Type 0 printhead is on the left with respect to the        direction of the paper flow.    -   The Type 1 printhead is on the right.

Table 219 lists the order in which the dot data needs to be loaded intothe above printhead system, to ensure color 0-dot 0 appears on the leftside of the printed page. TABLE 219 Order in which the even and odd dotsare loaded for printhead Arrangement 1 Type 0 printhead Type 1 printheadDot Sense when on the left when on the right Odd Loaded second in Loadedfirst in descending order. descending order. Even Loaded first in Loadedsecond in ascending order. ascending order.

FIG. 300 shows how the dot data is demultiplexed within the printheads.

FIG. 301 and FIG. 302 show the way in which the dot data needs to beloaded into the printheads in Arrangement 1, to ensure that color 0-dot0 appears on the left side of the printed page. Note that no data istransferred to the printheads on the first and last edges of SrClk.

3.2 EXAMPLE 2

Printhead Arrangement 2

FIG. 303 shows an Arrangement 2 printing setup, where the bilithicprintheads are arranged as follows:

-   -   The Type 1 printhead is on the left with respect to the        direction of the paper flow.    -   The Type 0 printhead is on the right.

Table 220 lists the order in which the dot data needs to be loaded intothe above printhead system, to ensure color 0-dot 0 appears on the leftside of the printed page. TABLE 220 Order in which the even and odd dotsare loaded for printhead Arrangement 2 Type 0 printhead Type 1 printheadDot Sense when on the right when on the left Odd Loaded first in Loadedsecond in descending order. descending order. Even Loaded second inLoaded first in ascending order. ascending order.

FIG. 304 shows how the dot data is demultiplexed within the printheads.

FIG. 305 and FIG. 306 show the way in which the dot data needs to beloaded into the printheads in Arrangement 2, to ensure that color 0-dot0 appears on the left side of the printed page.

Note that no data is transferred to the printheads on the first and lastedges of SrClk.

4 Conclusions

Comparing the signalling diagrams for Arrangement 1 with those shown forArrangement 2, it can be seen that the color/dot sequence output for aprinthead type in Arrangement 1 is the reverse of the sequence for sameprinthead in Arrangement 2 in terms of the order in which the colorplane data is output, as well as whether even or odd data is outputfirst. However, the order within a color plane remains the same, i.e.odd descending, even ascending.

From FIG. 307 and Table 221, it can be seen that the plane which has tobe loaded first (i.e. even or odd) depends on the arrangement. Also, theorder in which the dots have to be loaded (e.g. even ascending ordescending etc.) is dependent on the arrangement.

As well as having a mechanism to cope with the shape of the join betweenthe printheads, as discussed in Section 2.1, if the device controllingthe printheads can re-order the bits according to the followingcriteria, then it should be able to operate in all the possibleprinthead arrangements:

-   -   Be able to output the even or odd plane first.    -   Be able to output even and odd planes in either ascending or        descending order, independently.

Be able to reverse the sequence in which the color planes of a singledot are output to the printhead. TABLE 221 Order in which even and odddots and planes are loaded into the various printhead arrangementsPrinthead Arrangement Left side of printed page Right side of printedpage Arrangement 1 Even ascending loaded first Odd descending loadedfirst Odd descending loaded Even ascending loaded second secondArrangement 2 Odd descending loaded first Even ascending loaded firstEven ascending loaded Odd descending loaded second second Arrangement 3Odd ascending loaded first Even descending loaded Even descending loadedfirst second Odd ascending loaded second Arrangement 4 Even descendingloaded Odd ascending loaded first first Even descending loaded Oddascending loaded second second Arrangement 5 Odd ascending loaded firstEven descending loaded Even descending loaded first second Odd ascendingloaded second Arrangement 6 Even descending loaded Odd ascending loadedfirst first Even descending loaded Odd ascending loaded second secondArrangement 7 Even ascending loaded first Odd descending loaded firstOdd descending loaded Even ascending loaded second second Arrangement 8Odd descending loaded first Even ascending loaded first Even ascendingloaded Odd descending loaded second secondCMOS Support on Bilithic Printhead1 Basic Requirements

To create a two part printhead, of A4/Letter portrait width to print apage in 2 seconds. Matching Left/Right chips can be of different lengthsto make up this length facilitating increased wafer usage. the left andright chips are to be imaged on an 8 inch wafer by “Stitching” reticleimages.

The memjet nozzles have a horizontal pitch of 32 um, two rows of nozzlesare used for a single colour. These rows have a horizontal offset of 16um. This gives an effective dot pitch of 16 um, or 62.5 dots per mm, or1587.5 dots per inch, close enough to market as 1600 dpi.

The first nozzle of the right chip should have a 32 um horizontal offsetfrom the final nozzle of the left chip for the same color row. There isno ink nozzle overlap (of the same colour) scheme employed.

1.1 Power Supply

Vdd/Vpos and Ground supply is made through 30 um wide pads along thelength of the chip using conductive adhesive to bus bar beside thechips. Vdd/Vpos is 3.3 Volts. (12V was considered for Vpos but routingof CMOS Vdd at 3.3V would be a problem over the length of the chips, butthis will be revisited).

1.2 MEMS Cells

The preferred memjet device requires 180 nJ of energy to fire, with apulse of current for 1 usec. Assuming 95% efficiency, this requires a 55ohm actuator drawing 57.4 mA during this pulse.

1.2.1 Issue!!!

For 1 pages per 2 second, or ˜300 mm*62.5 (dots/mm)/2 sec˜=10 kHz or 100usec per line. With 1 usec fire pulse cycle, every 100th nozzle needs tofire at the same time. We have 13824 nozzles across the page, so we fire138 nozzles at a time.

1.2.2 64 um Unit Cell Height

This cell would have 4 line spacing between the odd and even dots, and 8line spacing between adjacent colours.

1.2.3 80 um Unit Cell Height

This cell would have 5 line spacing between the odd and even dots, and10 line spacing between adjacent colours.

1.3 Versions

1.3.1 6 Colour 1600 dpi with 64 um Unit Cell

Left and Right ChIP.

1.3.2 6 Colour 1600 dpi with 80 um Unit Cell

Left and Right ChIP.

1.3.3 4 Colour 800 dpi with 80 um Unit Cell

For camera application. Single nozzle row per colour.

1.4 Air Supply

Air must be supplied to the MEMS region through holes in the chIP.

2 Head Sizes

The combined heads have 13824 nozzles per colour totalling 221.184 mm ofprint area. Enough to provide full breadth for A4 (210 mm) and Letter(8.5 inch or 215.9 mm). TABLE 1 Head Combinations Left Head Right HeadStitch Parts Nozzles per Colour Stitch Parts Nozzles per Colour 8 111602 2664 7 9744 3 4080 6 8328 4 5496 5 6912 5 6912 4 5496 6 8328 3 4080 79744 2 2664 8 11160

Nozzles per Colour is calculated as ((“Stitch Parts” −1)*118+104)*12.Nozzles per row is half this value. Most likely the 8:2 head set willnot be manufactured. The preferred wafer layout, manages to avoid thisset, without any loses.

3 Interface

Each print head has the same I/O signals (but the Left and Rightversions might have a different pin out). TABLE 2 I/O pins Max SpeedName I/O Function Common (MHz) Data[0-1] I Dot data for colours 0-5,using Differential No 320 Signalling (DataL the complementary signal),colours[0-2] on Data[0], colour[3-5] on Data[1] DataL[0-1] Icomplementary signal of Data[0-1] SrClk I Dot data shift clock usingDifferential Signalling No¹ 320 (SrClkL the complementary signal) SrClkLI complementary signal of SrClk ReadL I FrClk, Pr, LSyncL output mode ifsignal mode Yes  1 bit is set FrClk I Fire pattern shift clock Yes  1 Onozzle test result (mode = 0b001), LsyncL = 0 Yes² CMOS testing (mode =0b111), LsyncL = 1 Pr I Pulse Profile for all colours Yes  1³ OTemperature Output (mode = 0b010), LsyncL = 0 Yes^(b) CMOS testing (mode= 0b111), LsyncL = 1 LsyncL I 0 - Capture dot data for next print lineYes  0.1⁴ O CMOS testing (mode = 0b111), LsyncL = 1 Yes^(b)¹Functionally could be common, but for timing/electrical reasons shouldrun point to point.²Can be shared if one side has mode = 0b000³1 MHz cycle, but the resolution of the mark/space ratio may require 50ns.⁴10 kHz cycle, with minimum low pulse of 10 ns (no maximum).

Pins marked as common can be controlled by the same signal from thecontroller (SOPEC).

3.1 Dot Firing

To fire a nozzle, three signals are needed. A dot data, a fire signal,and a profile signal. When all signals are high, the nozzle will fire.

The dot data is provide to the chip through a dot shift register withinput Data[x], and clocked into the chip with SrClk. The dot data ismultiplex on to the Data signals, as Dot[0-2] on Data[0], and Dot[3-51on Data[2]. After the dots are shifted into the dot shift register, thisdata is transfer into the dot latch, with a low pulse in LsyncL. Thevalue in the dot latch forms the dot data used to fire the nozzle. Theuse of the dot latch allows the next line of data to be loaded into thedot shift register, at the same time the dot pattern in the dot latch isbeen fired.

Across the top of a column of nozzles, containing 12 nozzles, 2 of eachcolour (odd and even dots, 4 or 5 lines apart), is two fire registerbits and a select register bit. The fire registers forms the fire shiftregister that runs length of the chip and back again with one registerbit in each direction flow. The select register forms the Select ShiftRegister that runs the length of the chIP. The select register, selectswhich of the two fire registers is used to enables this column. A ‘0’ inthis register selects the forward direction fire register, and a ‘1’selects the reverse direction fire register. This output of this blockprovides the fire signal for the column.

The third signal needed, the profile, is provide for all colours withinput Pr across the whole colour row at the same time (with a slightpropagation delay per column).

3.2 Dot Shift Register Orientation

The left side print head (chIP) and the right side print head that formcomplete bi-lithic print head, have different nozzle arrangement withrespect to the dot order mapping of the dot shift register to the dotposition on the page.

With this mapping, the following data streams will need to provided.Left Head Right Head Size n-m dot order m 7:3 97 44 [13822, 13820,13818, . . . , 4084, 4082, 4080,] line y + 5 40 80 [1, 3, 5, . . . ,4075, 4077, 4079,] line y [4081, 4083, 4085, . . . , 13819, 13821,13823] line y [4078, 4076, 4074, . . . , 4, 2, 0] line y + 5 6:4 83 28[13822, 13820, 13818, . . . , 5500, 5498, 5496,] line y + 5 54 96 [1, 3,5, . . . , 5491, 5493, 5495,] line y [5497, 5499, 5501, . . . , 13819,13821, 13823] line y [5494, 5492, 5490, . . . , 4, 2, 0] line y + 5 5:569 12 [13822, 13820, 13818, . . . , 6916, 6914, 6912,] line y + 5 69 12[1, 3, 5, . . . , 6907, 6909, 6911,] line y [6913, 6915, 6917, . . . ,13819, 13821, 13823] line y [6910, 6908, 6906, . . . , 4, 2, 0] line y +5 4:6 54 96 [13822, 13820, 13818, . . . , 8332, 8330, 8328,] line y + 583 28 [1, 3, 5, . . . , 8323, 8325, 8327,] line y [8329, 8331, 8333, . .. , 13819, 13821, 13823] line y [8326, 8324, 8322, . . . , 4, 2, 0] liney + 5 3:7 40 80 [13822, 13820, 13818, . . . , 9748, 9746, 9744,] liney + 5 97 44 [1, 3, 5, . . . , 9739, 9741, 9743,] line y [9745, 97447,9749, . . . , 13819, 13821, 13823] line y 9742, 9740, 9738, . . . , 4,2, 0] line y + 5

The data needs to be multiplexed onto the data pins, such that Data[0]has {(C0, C1, C2), (C0, C1, C2) . . . } in the above order, and Data[1]has {(C3, C4, C5), (C3, C4, C5) . . . }.

FIG. 311 shows the timing of data transfer during normal printing mode.Note SrClk has a default state of high and data is transferred on bothedges of SrClk. If there are L nozzles per colour, SrClk would have L+2edges, where the first and last edges do not transfer data.

Data requires a setup and hold about the both edges of SrClk. Datatransfers starts on the first rising after LSyncL rising. SrClk defaultstate is high and needs to return to high after the last data of theline. This means the first edge of SrClk (falling) after LSyncL rising,and the last edge of SrClk as it returns to the default state, no datais transferred to the print head. LSyncL rising requires setup to thefirst falling SrClk, and must stay high during the entire line datatransfer until after last rising SrClk.

3.3 Fire Shift Register

The fire shift register controls the rate of nozzle fire. If theregister is full of ‘1’s then the you could print the entire print headin a single FrClk cycle, although electrical current limitations willprevent this happening in any reasonable implementation.

Ideally, a ‘1’ is shifted in to the fire shift register, in every n^(th)position, and a ‘0’ in all other position. In this manner, after ncycles of FrClk, the entire print head will be printed.

The fire shift register and select shift registers allow the generationof a horizontal print line that on close inspection would not have adiscontinuity of a “saw tooth” pattern, FIGS. 312 a) & b) but a “sharkstooth” pattern of c).

This is done by firing 2 nozzles in every 2n group of nozzle at the sametime starting from the outer 2 nozzles working towards the centre two(or the starting from the centre, and working towards the outer two) atthe fire rate controlled by FrClk.

To achieve this fire pattern the fire shift register and select shiftregister need to be set up as show in FIG. 313.

The pattern has shifted a ‘1’ into the fire shift register every n^(th)positions (where n is usually is a minimum of about 100) and n ‘1’s,followed n ‘0’s in the select shift register. At a start of a printcycle, these patterns need to be aligned as above, with the 1000 . . . ”of a forward half of fire shift register, matching an n grouping of ‘1’or ‘0’s in the select shift register. As well, with the “1000 . . . ” ofa reverse half of the fire shift register, matching an n grouping of ‘1’or ‘0’s in the select shift register. And to continue this print patternacross the butt ends of the chips, the select shift register in eachshould end with a complete block of n ‘1’s (or ‘0’s).

Since the two chips can be of different lengths, initialisation of thesepatterns is an issue. This is solved by building initialisationcircuitry into chips. This circuit is controlled by two registers,nlen(14) and count(14) and b(1). These registers are loaded seriallythrough Data[0], while LSyncL is low, and ReadL is high with FrClk.

The scan order from input is b, n[13-0],c[0-13],color[5-0], mode[2-0]therefore b is shifted in last. The system color and mode registers areunrelated to the Fire Shift Register, but are loaded at the same time asthis block. There function is described later. TABLE 4 Head CombinationsInitialisation for n = 100 Nozzle s Nozzle s count_(A) = (L_(A)/ rem =(L_(B)/ count_(B) = (L_(A) − L_(B) + rem) L_(B) L_(A) nlen_((A&B)) = n −1 2) mod n − 1 b_(A) b_(B) 2) mod n mod n − 1 4080 9744 99 71 0 0 40 35496 8328 99 63 0 0 48 79 6912 6912 99 55 0 0 56 55

The following table shows the values to programme the bi-lithic headpairs using a fire pattern length of 100. The calculation assumes head‘A’ is the longest head of the pair and once the registers areinitialised with LA FrClk cycles (ReadL=‘0’, LSyncL=‘1’). rem would bethe correct value for count_(B) if chip B was only clocked (FrClk) L_(B)times. But this chip will be over clocked L_(A)−L_(B) cycles. The valuesof b_(A) and b_(B) are either the same or inverse of each other. Theactually value does not matter. They need to be different from eachother if the select shift registers would end up with different valuesat the butt ends. If (L_(A)/2n) is even (and count_(A) is non zero),then the final run in ‘A’s select shift register will be !b_(A). If(L_(A)−L_(B)/2) mod n is even (and count_(b) is non zero) then the finalrun in ‘B’s select shift register will be !b_(B).

3.4 System Registers

As describe above, the Fire Shift Register generation block, alsocontains some system registers. TABLE 5 System Registers Name SizeFunction Color 6 Each bit is an enable for the corresponding colour. Ifcolor[X]=0, then Pr_(X) is 0 and SrClk_(X) is 0. If color[X]=1, thenPr_(X) follows the Pr signal and SrClk_(x) is deserialised SrClk. Mode 3Mode[0] = 1, then FrClk pin is used as an output, internally the FrClksignal is set to 0 Mode[1] = 1, then Pr pin is used as an output,internally the Pr signal is set to 0 Mode[2] = 1, then LsyncL pin isused as an output, internally the LsyncL signal is set to 13.5 Profile Pattern

A profile pattern is repeated at FrClk rate. It is expected to be asingle pulse about 1 us long. But it could be a more complicated seriesof pulse. The actual pattern depends on the ink type.

The following figure show the external timing to print a line of data.In this example the line is printed in 8 cycles of FrClk.

3.6 Interface Modes

The print head has eight different modes controlled by signals ReadL andLSyncL and system mode register. As seen in FIG. 318 with both LSyncLand ReadL high, the chip in normal printing mode. Some of these modescan operate at the same time, but may interfere with the result of theother modes. TABLE 6 Print Head Modes Mode ReadL LSyncL FunctionRegister Internal Mapping 1 1 Normal Print Mode 000 (XXX) SrClk=SrClk/3frclk=FrClk SelClk=0 FsClk=FrClk Scan=0 CoreScan=0 X 0 Dot Load Mode 000(XXX) Dot latches are open, loaded with Dot shift registers, latch onceLSyncL returns to 1 (this happens regardless of ReadL) Enables Dot Shiftregister to capture fire result. 1 0 Fire Load Mode 000 (XXX) SrClk=XData[0] will shift through mode, color, nlen, frclk=X count and b withFrClk SelClk=X FsClk=FrClk Scan=1 CoreScan=X 0 1 Reset Nozzle Test 001SrClk=SrClk Resets the state of nozzle test circuit FrClk=FrClkSelClk=FrClk FsClk=FrClk Scan=0 CoreScan=1 0 1 CMOS testing mode 111 Thecontents of the dot shift registers are serial shifted out on LsyncL(colour0-1), FrClk (colour2-3), Pr (colour4-5) with SrClk 0 1 FireInitialise mode 000 (XX0) The contents of the fire shift register andselect shift register is generated with FrClk 0 0 Temperature Output 010SrClk=X The series of Sigma Delta output are frclk=0 clocked out on Prwith FrClk. The sum of SelClk=0 these bits represent the temperature ofthe FsClk=0 chip. Scan=0 CoreScan=X 0 0 Nozzle Test Output 001 Theresult of a nozzle test is output on FrClk.3.6.1 Printing

FIG. 318 shows show timing for normal printing. During this action, wedrop out of Normal Print Mode, to Dot Load Mode between line transfers.For printing to perform correctly, all other signals should be stable.

3.6.2 Initialising for Printing

To initialise for printing the fire shift registers and select shiftregisters need to be setup into a state as shown in FIG. 318. To do thisthe chips are put into Fire Load Mode and the values for nlen, count andb are serially shifted from Data[0] clocked by FrClk. As the two chiphave separate Data line, and common FrClk, this happens at the sametime. Once this is done, mode is changed to Fire Initialise Mode, andfurther LA FrClk cycles are provided to both chips. During all theseoperation Pr should be low, to prevent unintentional firing for nozzles.

3.6.3 Nozzle Testing

Nozzle testing is done by firing a single nozzle at a time andmonitoring the FrClk pin in the Nozzle Test Output mode.

Each nozzle has a test switch which closes when the nozzle is fired withan energy level greater than required for normal ink ejection. All 12switches in a nozzle column are connect in parallel to the followingcircuit.

This circuit is initialised when ever LSyncL is high and ReadL is low(Reset Nozzle Test mode). This forces all “switch nodes” to low, and thefeedback through lower NOR gate will latches this value. With LSyncL lowand ReadL still low (Nozzle Test Output mode) the Testout of the firstnozzle column is output on FrClk. If any switch is closed, the switchnode of this column will be pulled up, and will ripple through to theoutput as transition from high to low.

Nozzle testing requires a setup phase in order to fire only one nozzle.There are many ways to achieve this. Simplest might be to load a singlecolour with 101010 through the even nozzles, and 010101 . . . for theodd nozzles (0's for all other colours), and set up a fire pattern withn=L_(A)/2. With this fire pattern only one nozzle will fire in each Prpulse. After firing in Nozzle Test Output mode, a single FrClk willadvance to next nozzle, then Reset and Test. After L_(A)/2 cycles ofthis testing, a single SrClk will advance the dot shift registers tosetup the untested nozzles of this colour, and another L_(A)/2 cycles ofFrClk, Reset and Test will finished testing this colour. Then repeattest procedure for other colours.

3.6.4 Temperature Output

This mode is not well defined yet. In this mode, Pr will output a seriesof ones and zeros clocked by FrClk. After a (currently unknown) numberof FrClk cycles the sum of this series will represent the temperature ofthe chIP. Clocking frequency in this mode it expected to be in the range10 kHz-1 MHz.

The Frequency of FrClk and the number of cycles need to be programmable.Since this mode cycles FrClk, the result of fire shift register andselect shift register would be changed, but in this mode FrClk isdisabled to these circuit. So printing can resume withoutreinitialising.

3.6.5 CMOS Testing

CMOS testing is a mode meant for chip testing before MEMS as added tothe chIP. This mode allows the dot shift register to be shifted out onthe LsyncL, FrClk and Pr pins. Much like the nozzle test mode, thenozzles are fired while LSyncL is low, but during the firing SrClk willbe pulsed, loading the dot shift register with the signal that wouldfire the nozzle. Once captured, the result can be shifted out.

The Dot Load Mode above violates normal printing procedure by firing thenozzles (Pr) and modify the dot shift register (SrClk).

4 Reticle Layout

To make long chips we need to stitch the CMOS (and MEMS) together byoverlapping the reticle stepping field. The reticle will contain twoareas:

The top edge of Area 2, PAD END contains the pads that stitch on bottomedge of Area 1, CORE. Area 1 contains the core array of nozzle logic.The top edge of Area 1 will stitch to the bottom edge of itself. Finallythe bottom edge of Area 2, BUTT END will stitch to the top edge ofArea 1. The BUTT END to used to complete a feedback wiring and seal thechIP.

The above region will then be exposed across a wafer bottom to top. Area2, Area 1, Area 1 . . . , Area 2. Only the PAD END of Area 2 needs tofit on the wafer. The final exposure of Area 2 only requires the BUTTEND on the wafer.

4.1 TSMC U-Frame Requirements.

TSMC will be building us frames 10 mm×0.23 mm which will be placedeither side of both Area 1 and Area 2.

TSMC requires 6 mm area for blading between the two exposure area. Thistranslates to 3 mm on the reticle, as some reticules are 2× size, whilemost are 5×, the worst case must be used.

Security Overview

1 Introduction

A number of hardware, software and protocol solutions to security issueshave been developed. These range from authorization and encryptionprotocols for enabling secure communication between hardware andsoftware modules, to physical and electrical systems that protect theintegrity of integrated circuits and other hardware.

It should be understood that in many cases, principles described withreference to hardware such as integrated circuits (ie, chips) can beimplemented wholly or partly in software running on, for example, acomputer. Mixed systems in which software and hardware (andcombinations) embody various entities, modules and units can also beconstructed using may of these principles, particularly in relation toauthorization and authentication protocols. The particular extent towhich the principles described below can be translated to or fromhardware or software will be apparent to one skilled in the art, and sowill not always explicitly be explained.

It should also be understood that many of the techniques disclosed belowhave application to many fields other than printing. Some specificexamples are described towards the end of this description.

A “QA Chip” is a quality assurance chip can allows certain securityfunctions and protocols to be implemented. The preferred QA Chip isdescribed in some detail later in this specification.

1.5 QA Chip Terminology

The Authentication Protocols documents [5] and [6] refer to QA Chips bytheir function in particular protocols:

-   -   For authenticated reads in [5], ChipR is the QA Chip being read        from, and ChipT is the QA Chip that identifies whether the data        read from ChipR can be trusted. ChipR and ChipT are referred to        as Untrusted QA Device and Trusted QA Device respectively in        [6].    -   For replacement of keys in [5], ChipP is the QA Chip being        programmed with the new key, and ChipF is the factory QA Chip        that generates the message to program the new key. ChipF is        referred to as the Key Programmer QA Device in [6].    -   For upgrades of data in memory vectors in [5], ChipU is the QA        Chip being upgraded, and ChipS is the QA Chip that signs the        upgrade value. ChipS is referred to as the Value Upgrader QA        Device and Parameter Upgrader QA Device in [6].

Any given physical QA Chip will contain functionality that allows it tooperate as an entity in some number of these protocols.

Therefore, wherever the terms ChipR, ChipT, ChipP, ChipF, ChipU andChipS are used in this document, they are referring to logical entitiesinvolved in an authentication protocol as defined in [5] and [6].

Physical QA Chips are referred to by their location. For example, eachink cartridge may contain a QA Chip referred to as an INK_QA, with allINK_QA chips being on the same physical bus. In the same way, the QAChip inside the printer is referred to as PRINTER_QA, and will be on aseparate bus to the INK_QA chips.

2 Requirements

2.1 Security

When applied to a printing environment, the functional securityrequirements for the preferred embodiment are:

-   -   Code of QA chip owner or licensee co-existing safely with code        of authorized OEMs    -   Chip owner/licensee operating parameters authentication    -   Parameters authentication for authorized OEMs    -   Ink usage authentication

Each of these is outlined in subsequent sections.

The authentication requirements imply that:

-   -   OEMs and end-users must not be able to replace or tamper with QA        chip manufacturer/owner's program code or data    -   OEMs and end-users must not be able to perform unauthorized        activities for example by calling chip manufacturer/owner's code    -   End-users must not be able to replace or tamper with OEM program        code or data    -   End-users must not be able to call unauthorized functions within        OEM program code    -   Manufacturer/owner's development program code must not be        capable of running on all SoPECs.    -   OEMs must be able to test products at their highest upgradable        status, yet not be able to ship them outside the terms of their        license    -   OEMs and end-users must not be able to directly access the print        engine pipeline (PEP) hardware, the LSS Master (for QA Chip        access) or any other peripheral block with the exception of        operating system permitted GPIO pins and timers.        2.1.1 QA Manufacturer/Owner Code and OEM Program Code        Co-Existing Safely

SoPEC includes a CPU that must run both manufacturer/owner program codeand OEM program code. The execution model envisaged for SoPEC is onewhere Manufacturer/owner program code forms an operating system (O/S),providing services such as controlling the print engine pipeline,interfaces to communications channels etc. The OEM program code must runin a form of user mode, protected from harming the Manufacturer/ownerprogram code. The OEM program code is permitted to obtain services bycalling functions in the O/S, and the O/S may also call OEM code atspecific times. For example, the OEM program code may request that theO/S call an OEM interrupt service routine when a particular GPIO pin isactivated.

In addition, we may wish to permit the OEM code to directly callfunctions in Manufacturer/owner code with the same permissions as theOEM code. For example, the Manufacturer/owner code may provide SHA1 as aservice, and the OEM could call the SHA1 function, but execute thatfunction with OEM permissions and not Silverbook permissions.

A basic requirement then, for SoPEC, is a form of protection management,whereby Manufacturer/owner and OEM program code can co-exist without theOEM program code damaging operations or services provided by theManufacturer/owner O/S. Since services rely on SoPEC peripherals (suchas USB2 Host, LSS Master, Timers etc) access to these peripherals shouldalso be restricted to Manufacturer/owner program code only.

2.1.2 Manufacturer/Owner Operating Parameters Authentication

A particular OEM will be licensed to run a Print Engine with aparticular set of operating parameters (such as print speed or quality).The OEM and/or end-user can upgrade the operating license for a fee andthereby obtain an upgraded set of operating parameters.

Neither the OEM nor end-user should be able to upgrade the operatingparameters without paying the appropriate fee to upgrade the license.Similarly, neither the OEM nor end-user should be able to bypass theauthentication mechanism via any program code on SoPEC. This impliesthat OEMs and end-users must not be able to tamper with or replaceManufacturer/owner program code or data, nor be able to callunauthorized functions within Manufacturer/owner program code.

However, the OEM must be capable of assembly-line testing the PrintEngine at the upgraded status before selling the Print Engine to theend-user.

2.1.3 OEM Operating Parameters Authentication

The OEM may provide operating parameters to the end-user independent ofthe Manufacturer/owner operating parameters. For example, the OEM maywant to sell a franking machine¹.¹a franking machine print stamps

The end-user should not be able to upgrade the operating parameterswithout paying the appropriate fee to the OEM. Similarly, the end-usershould not be able to bypass the authentication mechanism via anyprogram code on SoPEC. This implies that end-users must not be able totamper with or replace OEM program code or data, as well as not be ableto tamper with the PEP blocks or service-related peripherals.

2.2 Acceptable Compromises

If an end user takes the time and energy to hack the print engine andthereby succeeds in upgrading the single print engine only, yet not beable to use the same keys etc on another print engine, that is anacceptable security compromise. However it doesn't mean we have to makeit totally simple or cheap for the end-user to accomplish this.

Software-only attacks are the most dangerous, since they can betransmitted via the internet and have no perceived cost. Physicalmodification attacks are far less problematic, since most printer usersare not likely to want their print engine to be physically modified.This is even more true if the cost of the physical modification islikely to exceed the price of a legitimate upgrade.

2.3 Implementation Constraints

Any solution to the requirements detailed in Section 2.1 should alsomeet certain preferred implementation constraints. These are:

-   -   No flash memory inside SoPEC    -   SoPEC must be simple to verify    -   Manufacturer/owner program code must be updateable    -   OEM program code must be updateable    -   Must be bootable from activity on USB2    -   Must be bootable from an external ROM to allow stand-alone        printer operation    -   No extra pins for assigning IDs to slave SoPECs    -   Cannot trust the comms channel to the QA Chip in the printer        (PRINTER QA)    -   Cannot trust the comms channel to the QA Chip in the ink        cartridges (INK_QA)    -   Cannot trust the USB comms channel

These constraints are detailed below.

2.3.1 No Flash Memory Inside SoPEC

The preferred embodiment of SoPEC is intended to be implemented in 0.13micron or smaller. Flash memory will not be available in any of thetarget processes being considered.

2.3.2 SoPEC Must be Simple to Verify

All combinatorial logic and embedded program code within SoPEC must beverified before manufacture. Every increase in complexity in either ofthese increases verification effort and increases risk.

2.3.3 Manufacturer/Owner Program Code Must be Updateable

It is neither possible nor desirable to write a single completeoperating system that is:

-   -   verified completely (see Section 2.3.1)    -   correct for all possible future uses of SoPEC systems    -   finished in time for SoPEC manufacture

Therefore the complete Manufacturer/owner program code must notpermanently reside on SoPEC. It must be possible to update theManufacturer/owner program code as enhancements to functionality aremade and bug fixes are applied.

In the worst case, only new printers would receive the new functionalityor bug fixes. In the best case, existing SoPEC users can download newembedded code to enable functionality or bug fixes. Ideally, these sameusers would be obtaining these updates from the OEM website orequivalent, and not require any interaction with Manufacturer/owner.

2.3.4 OEM Program Code Must be Updateable

Given that each OEM will be writing specific program code for printersthat have not yet been conceived, it is impossible for all OEM programcode to be embedded in SoPEC at the ASIC manufacture stage.

Since flash memory is not available (see Section 2.3.1), OEMs cannotstore their program code in on-chip flash. While it is theoreticallypossible to store OEM program code in ROM on SoPEC, this would entailOEM-specific ASICs which would be prohibitively expensive. Therefore OEMprogram code cannot permanently reside on SoPEC.

Since OEM program code must be downloadable for SoPEC to execute, itshould therefore be possible to update the OEM program code asenhancements to functionality are made and bug fixes are applied.

In the worst case, only new printers would receive the new functionalityor bug fixes. In the best case, existing SoPEC users can download newembedded code to enable functionality or bug fixes. Ideally, these sameusers would be obtaining these updates from the OEM website orequivalent, and not require any interaction with Manufacturer/owner.

2.3.5 Must be Bootable From Activity on USB2

SoPEC can be placed in sleep mode to save power when printing is notrequired. RAM is not preserved in sleep mode. Therefore any program codeand data in RAM will be lost. However, SoPEC must be capable of beingwoken up by the host when it is time to print again.

In the case of a single SoPEC system, the host communicates with SoPECvia USB2. From SoPEC's point of view, it is activity on the USB2 deviceport that signals the time to wake up.

In the case of a multi-SoPEC system, the host typically communicateswith the Master SoPEC chip (as above), and then the Master relaysmessages to other Slave SoPECs by sending data out USB2 host port(s) andinto the Slave SoPEC's device port. The net result is that the SlaveSoPECs and the Master SoPEC all boot as a result of activity on the USB2device port.

Therefore SoPEC must be capable of being woken up by activity on theUSB2 device port.

2.3.6 Must be Bootable From an External ROM to Allow Stand-Alone PrinterOperation

SoPEC must also support the case where the printer is not connected to aPC (or the PC is currently turned off), and a digital camera orequivalent is plugged into the SoPEC-based printer. In this case, theentire printing application needs to be present within the hardware ofthe printer. Since the Manufacturer/owner program code and OEM programcode will vary depending on the application (see Section 2.3.3 andSection 2.3.4), it is not possible to store the program in SoPEC's ROM.

Therefore SoPEC requires a means of booting from a non-PC host. It ispossible that this could be accomplished by the OEM adding a USB2-hostchip to the printer and simulating the effect of a PC, and therebydownload the program code. This solution requires the boot operation tobe based on USB2 activity (see Section 2.3.5). However this is anunattractive solution since it adds microprocessor complexity andcomponent cost when only a ROM-equivalent was desired.

As a result SoPEC should ideally be able to boot from an external ROM ofsome kind. Note that booting from an external ROM means first bootingfrom the internal ROM, and then downloading and authenticating thestartup section of the program from the external ROM. This is not thesame as simply running program code in-situ within an external ROM,since one of the security requirements was that OEMs and end-users mustnot be able to replace or tamper with Manufacturer/owner program code ordata, i.e. we never want to blindly run code from an external ROM.

As an additional point, if SoPEC is in sleep mode, SoPEC must be capableof instigating the boot process due to activity on a programmable GPIO.e.g. a wake-up button. This would begin addition to the standardpower-on booting.

2.3.7 No Extra Pins to Assign IDs to Slave SoPECs

In a single SoPEC system the host only sends data to the single SoPEC.However in a multi-SoPEC system, each of the slaves needs to be uniquelyidentifiable in order to be able for the host to send data to thecorrect slave.

Since there is no flash on board SoPEC (Section 2.3.1) we are unable tostore a slave ID in each SoPEC. Moreover, any ROM in each SoPEC will beidentical.

It is possible to assign n pins to allow 2^(n) combinations of IDs forslave SoPECs. However a design goal of SoPEC is to minimize pins forcost reasons, and this is particularly true of features only used inmulti-SoPEC systems.

The design constraint requirement is therefore to allow slaves to beIDed via a method that does not require any extra pins. This impliesthat whatever boot mechanism that satisfies the security requirements ofSection 2.1 must also be able to assign IDs to slave SoPECs.

2.3.8 Cannot Trust the Comms Channel to the QA Chip in the Printer(PRINTER_QA)

If the printer operating parameters are stored in the non-volatilememory of the Print Engine's on-board PRINTER_QA chip, bothManufacturer/owner and OEM program code cannot rely on the communicationchannel being secure. It is possible for an attacker to eavesdrop oncommunications to the PRINTER_QA chip, replace the PRINTER_QA chipand/or subvert the communications channel. It is also possible for thisto be true during manufacture of the circuit board containing the SoPECand the PRINTER_QA chIP.

2.3.9 Cannot Trust the Comms Channel to the QA Chip in the InkCartridges (INK_QA)

The amount of ink remaining for a given ink cartridge is stored in thenon-volatile memory of that ink cartridge's INK_QA chIP. BothManufacturer/owner and OEM program code cannot rely on the communicationchannel to the INK_QA being secure. It is possible for an attacker toeavesdrop on communications to the INK_QA chip, to replace the INK_QAchip and/or to subvert the communications channel. It is also possiblefor this to be true during manufacture of the consumable containing theINK_QA chIP.

2.3.10 Cannot Trust the Inter-SoPEC Comms Channel (USB2)

In a multi-SoPEC system, or in a single-SoPEC system that has a non-USB2connection to the host, a given SoPEC will receive its data over a USB2host port. It is quite possible for an end-user to insert a chip thateavesdrops on and/or subverts the communications channel (for exampleperforms man-in-the-middle attacks).

3 Proposed Solution

A proposed solution to the requirements of Section 2, can be summarisedas:

-   -   Each SoPEC has a unique id    -   CPU with user/supervisor mode    -   Memory Management Unit    -   The unique id is not cached    -   Specific entry points in O/S    -   Boot procedure, including authentication of program code and        operating parameters    -   SoPEC physical identification        3.1 Each SoPEC Has a Unique ID

Each SoPEC needs to contains a unique SoPEC_id of minimum size 64-bits.This SoPEC_id is used to form a symmetric key unique to each SoPEC:SoPEC_id_key. On SoPEC we make use of an additional 112-bit ECID² macrothat has been programmed with a random number on a per-chip basis. ThusSoPEC_id is the 112-bit macro, and the SoPEC_id_key is a 160-bit resultobtained by SHA1(SoPEC_ID).²Electronic Chip Id

The verification of operating parameters and ink usage depends onSoPEC_id being difficult to determine. Difficult to determine means thatsomeone should not be able to determine the id via software, or byviewing the communications between chips on the board. If the SoPEC_idis available through running a test procedure on specific test pins onthe chip, then depending on the ease by which this can be done, it islikely to be acceptable.

It is important to note that in the proposed solution, compromise of theSoPEC_id leads only to compromise of the operating parameters and inkusage on this particular SoPEC. It does not compromise any other SoPECor all inks or operating parameters in general.

It is ideal that the SoPEC_id be random, although this is unlikely tooccur on standard manufacture processes for ASICs. If the id is within asmall range however, it will be able to be broken by brute force. Thisis why 32-bits is not sufficient protection.

3.2 CPU with User/Supervisor Mode

SoPEC contains a CPU with direct hardware support for user andsupervisor modes. At present, the intended CPU is the LEON (a 32-bitprocessor with an instruction set according to the IEEE-1754 standard.The IEEE1754 standard is compatible with the SPARC V8 instruction set).

Manufacturer/owner (operating system) program code will run insupervisor mode, and all OEM program code will run in user mode.

3.3 Memory Management Unit

SoPEC contains a Memory Management Unit (MMU) that limits access toregions of DRAM by defining read, write and execute access permissionsfor supervisor and user mode. Program code running in user mode issubject to user mode permission settings, and program code running insupervisor mode is subject to supervisor mode settings.

A setting of 1 for a permission bit means that type of access (e.g.read, write, execute) is permitted. A setting of 0 for a read permissionbit means that that type of access is not permitted.

At reset and whenever SoPEC wakes up, the settings for all thepermission bits are 1 for all supervisor mode accesses, and 0 for alluser mode accesses. This means that supervisor mode program code mustexplicitly set user mode access to be permitted on a section of DRAM.

Access permission to all the non-valid address space should be trapped,regardless of user or supervisor mode, and regardless of the accessbeing read, execute, or write.

Access permission to all of the valid non-DRAM address space (forexample the PEP blocks) is supervisor read/write access only (nosupervisor execute access, and user mode has no acccess at all) with theexception that certain GPIO and Timer registers can also be accessed byuser code. These registers will require bitwise access permissions. Eachperipheral block will determine how the access is restricted.

With respect to the DRAM and PEP subsystems of SoPEC, typically we wouldset user read/write/execute mode permissions to be 1/1/0 only in theregion of memory that is used for OEM program data, 1/0/1 for regions ofOEM program code, and 0/0/0 elsewhere (including the trap table). Bycontrast we would typically set supervisor mode read/write/executepermissions for this memory to be 1/1/0 (to avoid accidentally executinguser code in supervisor mode).

The SoPEC_id parameter (see Section 3.1) should only be accessible insupervisor mode, and should only be stored and manipulated in a regionof memory that has no user mode access. μ3.4 Unique ID IS Not Cached

The unique SoPEC_id needs to be available to supervisor code and notavailable to user code. This is taken care of by the MMU (Section 3.3).

However the SoPEC_id must also not be accessable via the CPU's datacache or register windows. For example, if the user were to cause aninterrupt to occur at a particular point in the program execution whenthe SoPEC_id was being manipulated, it must not be possible for the userprogram code to turn caching off and then access the SoPEC_id inside thedata cache. This would bypass any MMU security.

The same must be true of register windows. It must not be possible foruser mode program code to read or modify register settings in asupervisor program's register windows.

This means that at the least, the SoPEC_id itself must not be cacheable.Likewise, any processed form of the SoPEC_id such as the SoPEC_id key(e.g. read into registers or calculated expected results from a QA_ChIP)should not be accessable by user program code.

3.5 Specific Entry Points in O/S

Given that user mode program code cannot even call functions insupervisor code space, the question arises as how OEM programs canaccess functions, or request services. The implementation for thisdepends on the CPU.

On the LEON processor, the TRAP instruction allows programs to switchbetween user and supervisor mode in a controlled way. The TRAP switchesbetween user and supervisor register sets, and calls a specific entrypoint in the supervisor code space in supervisor mode. The TRAP handlerdispatches the service request, and then returns to the caller in usermode.

Use of a command dispatcher allows the O/S to provide services thatfilter access—e.g. a generalised print function will set PEP registersappropriately and ensure QA Chip ink updates occur.

The LEON also allows supervisor mode code to call user mode code in usermode. There are a number of ways that this functionality can beimplemented. It is possible to call the user code without a trap, but toreturn to supervisor mode requires a trap (and associated latency).

3.6 Boot Procedure

3.6.1 Basic Premise

The intention is to load the Manufacturer/owner and OEM program codeinto SoPEC's RAM, where it can be subsequently executed. The basic SoPECtherefore, must be capable of downloading program code. However SoPECmust be able to guarantee that only authorized Manufacturer/owner bootprograms can be loaded, otherwise anyone could modify the O/S to doanything, and then load that—thereby bypassing the licensed operatingparameters.

We perform authentication of program code and data using asymmetric(public-key) digital signatures and without using a QA ChIP.

Assuming we have already downloaded some data and a 160-bit signatureinto eDRAM, the boot loader needs to perform the following tasks:

-   -   perform SHA-1 on the downloaded data to calculate a digest        localDigest    -   perform asymmetric decryption on the downloaded signature        (160-bits) using an asymmetric public key to obtain        authorizedDigest    -   If authorizedDigest is the PKCS#1 (patent free) form of        localDigest, then the downloaded data is authorized (the        signature must have been signed with the asymmetric private key)        and control can then be passed to the downloaded data

Asymmetric decryption is used instead of symmetric decryption becausethe decrypting key must be held in SoPEC's ROM. If symmetric privatekeys are used, the ROM can be probed and the security is compromised.

The procedure requires the following data item:

-   -   boot0key=an n-bit asymmetric public key

The procedure also requires the following two functions:

-   -   SHA-1=a function that performs SHA-1 on a range of memory and        returns a 160-bit digest    -   decrypt=a function that performs asymmetric decryption of a        message using the passed-in key        -   PKCS#1 form of localDigest is 2048-bits formatted as            follows: bits 2047-2040=0x00, bits 2039-2032=0x01, bits            2031-288=0xFF..0xFF, bits            287-160=0x003021300906052B0E03021A05000414, bits            159-0=localDigest. For more information, see PKCS#1 v2.1            section 9.2

Assuming that all of these are available (e.g. in the boot ROM), bootloader 0 can be defined as in the following pseudocode:  bootloader0(data, sig)    localDigest

SHA-1(data)    authorizedDigest

decrypt(sig, boot0key)    expectedDigest    =    0x00|0x01|0xFF..0xFF|     0x003021300906052B0E03021A05000414  |localDigest)  // “|” = concat   If (authorizedDigest == expectedDigest)     jump to program code atdata-start address// will never return    Else     // program code isunauthorized    EndIf

The length of the key will depend on the asymmetric algorithm chosen.The key must provide the equivalent protection of the entire QA Chipsystem—if the Manufacturer/owner O/S program code can be bypassed, thenit is equivalent to the QA Chip keys being compromised. In fact it isworse because it would compromise Manufacturer/owner operatingparameters, OEM operating parameters, and ink authentication by softwaredownloaded off the net (e.g. from some hacker).

In the case of RSA, a 2048-bit key is required to match the 160-bitsymmetric-key security of the QA ChIP. In the case of ECDSA, a keylength of 132 bits is likely to suffice. RSA is convenient because thepatent (U.S. Pat. No. 4,405,829) expired in September 2000.

There is no advantage to storing multiple keys in SoPEC and having theexternal message choose which key to validate against, because acompromise of any key allows the external user to always select thatkey.

There is also no particular advantage to having the boot mechanismselect the key (e.g. one for USB-based booting and one for external ROMbooting) a compromise of the external ROM booting key is enough tocompromise all the SoPEC systems.

However, there are advantages in having multiple keys present in theboot ROM and having a wire-bonding option on the pads select which ofthe keys is to be used. Ideally, the pads would be connected within thepackage, and the selection is not available via external means once thedie has ben packaged. This means we can have different keys fordifferent application areas (e.g. different uses of the chIP), and ifany particular SoPEC key is compromised, the die could be kept constantand only the bonding changed. Note that in the worst case of all keysbeing compromised, it may be economically feasible to change theboot0key value in SoPEC's ROM, since this is only a single mask change,and would be easy to verify and characterize.

Therefore the entire security of SoPEC is based on keeping theasymmetric private key paired to boot0key secure. The entire security ofSoPEC is also based on keeping the program that signs (i.e. authorizes)datasets using the asymmetric private key paired to boot0key secure.

It may therefore be reasonable to have multiple signatures (and hencemultiple signature programs) to reduce the chance of a single point ofweakness by a rogue employee. Note that the authentication timeincreases linearly with the number of signatures, and requires a2048-bit public key in ROM for each signature.

3.6.2 Hierarchies of Authentication

Given that test programs, evaluation programs, and Manufacturer/ownerO/S code needs to be written and tested, and OEM program code etc. alsoneeds to be tested, it is not secure to have a single authentication ofa monolithic dataset combining Manufacturer/owner O/S, non-O/S, and OEMprogram code—we certainly don't want OEMs signing Manufacturer/ownerprogram code, and Manufacturer/owner shouldn't have to be involved withthe signing of OEM program code.

Therefore we require differing levels of authentication and therefore anumber of keys, although the procedure for authentication is identicalto the first—a section of program code contains the key and procedurefor authenticating the next.

This method allows for any hierarchy of authentication, based on a rootkey of boot0key. For example, assume that we have the followingentities:

-   -   QACo, Manufacturer/owner's QA/key company. Knows private version        of boot0key, and owner of security concerns.    -   SoPECCo, Manufacturer/owner's SoPEC hardware/software company.        Supplies SoPEC ASICs and SoPEC O/S printing software to a ComCo.    -   ComCo, a company that assembles Print Engines from SoPECs,        Memjet printheads etc, customizing the Print Engine for a given        OEM according to a license    -   OEM, a company that uses a Print Engine to create a printer        product to sell to the end-users. The OEM would supply the motor        control logic, user interface, and casing.

The levels of authentication hierarchy are as follows:

-   -   QACo writes the boot ROM, agenerates dataset1, consisting of a        boot loader program that loads and validates dataset2 and QACo's        asymmetric public boot1key. QACo signs dataset0 with the        asymmetric private boot0key.    -   SoPECCo generates dataset1, consisting of the print engine        security kernel O/S (which incorporates the security-based        features of the print engine functionality) and the ComCo's        asymmetric public key. Upon a special “formal release” request        from SoPECCo, QACo signs dataset0 with QACo's asymmetric private        boot0key key. The print engine program code expects to see an        operating parameter block signed by the ComCo's asymmetric        private key. Note that this is a special “formal release”        request to by SoPECCo; the procedure for development versions of        the program are described in Section 3.6.3.    -   The ComCo generates dataSet3, consisting of dataset1 plus        dataset2, where dataset2 is an operating parameter block for a        given OEM's print engine licence (according to the print engine        license arrangement) signed with the ComCo's asymmetric private        key. The operating parameter block (dataset2) would contain        valid print speed ranges, a PrintEngineLicenseID, and the OEM's        asymmetric public key. The ComCo can generate as many of these        operating parameter blocks for any number of Print Engine        Licenses, but cannot write or sign any supervisor O/S program        code.    -   The OEM would generate dataset5, consisting of dataset3 plus        dataset4, where dataset4 is the OEM program code signed with the        OEM's asymmetric private key. The OEM can produce as many        versions of dataset5 as it likes (e.g. for testing purposes or        for updates to drivers etc) and need not involve        Manufacturer/owner, QACo, or ComCo in any way.

The relationship is shown below in FIG. 325.

When the end-user uses dataset5, SoPEC itself validates dataset1 via theboot0key mechanism described in Section 3.6.1. Once dataset1 isexecuting, it validates dataset2, and uses dataset2 data to validatedataset4. The validation hierarchy is shown in FIG. 326.

If a key is compromised, it compromises all subsequent authorizationsdown the hierarchy. In the example from above (and as illustrated inFIG. 326) if the OEM's asymmetric private key is compromised, then O/Sprogram code is not compromised since it is above OEM program code inthe authentication hierarchy. However if the ComCo's asymmetric privatekey is compromised, then the OEM program code is also compromised. Acompromise of boot0key compromises everything up to SoPEC itself, andwould require a mask ROM change in SoPEC to fix.

It is worthwhile repeating that in any hierarchy the security of theentire hierarchy is based on keeping the asymmetric private key pairedto boot0key secure. It is also a requirement that the program that signs(i.e. authorizes) datasets using the asymmetric private key paired toboot0key secure.

3.6.3 Developing Program Code at Manufacturer/Owner

The hierarchical boot procedure described in Section 3.6.1 and Section3.6.2 gives a hierarchy of protection in a final shipped product.

It is also desirable to use a hierarchy of protection during softwaredevelopment within Manufacturer/owner.

For a program to be downloaded and run on SoPEC during development, itwill need to be signed. In addition, we don't want to have to sign eachand every Manufacturer/owner development code with the boot0key, as itcreates the possibility of any developmental (including buggy or rogue)application being run on any SoPEC.

Therefore QACo needs to generate/create a special intermediate bootloader, signed with boot0key, that performs the exact same tasks as thenormal boot loader, except that it checks the SoPECid to see if it is aspecific SoPECid (or set of SoPECids). If the SoPEC_id is in the validset, then the developmental boot loader validates dataset2 by means ofits length and a SHA-1 digest of the developmental code³, and not by afurther digital signature. The QACo can give this boot loader to thesoftware development team within Manufacturer/owner. The software teamcan now write and run any program code, and load the program code usingthe development boot loader. There is no requirement for the subsequentsoftware program (i.e. the developmental program code) to be signed withany key since the programs can only be run on the particular SoPECs.³The SHA-1 digest is to allow the total program load time to simulatethe running time of the normal boot loader running on anon-developmental version of the program.

If the developmental boot loader (and/or signature generator) werecompromised, or any of the developmental programs were compromised, theworst situation is that an attacker could run programs on thatparticular set of SoPECs, and on no others.

This should greatly reduce the possibility of erroneous programs signedwith boot0key being available to an attacker (only official releases aresigned by boot0key), and therefore reduces the possibility of aManufacturer/owner employee intentionally or inadvertently creating aback door for attackers.

The relationship is shown below in FIG. 327.

Theoretically the same kind of hierarchy could also be used to allowOEMs to be assured that their program code will only work on specificSoPECs, but this is unlikely to be necessary, and is probablyundesirable.

3.6.4 Date-Limited Loaders

It is possible that errors in supervisor program code (e.g. theoperating system) could allow attackers to subvert the program in SoPECand gain supervisor control.

To reduce the impact of this kind of attack, it is possible to allocatesome bits of the SoPEC_id to form some kind of date. The granularity ofthe date could be as simple as a single bit that says the date isobtained from the regular IBM ECID, or it could be 6 bits that give 10years worth of 3-month units.

The first step of the program loaded by boot loader 0 could check theSoPEC_id date, and run or refuse to run appropriately. TheManufacturer/owner driver or OS could therefore be limited to run onSoPECs that are manufactured up until a particular date.

This means that the OEM would require a new version of the OS for SoPECsafter a particular date, but the new driver could be made to work on allprevious versions of SoPEC.

The function simply requires a form of date, whose granularity forworking can be determined by agreement with the OEM.

For example, suppose that SoPECs are supplied with 3-month granularityin their date components. Manufacturer/owner could ship a version of theOS that works for any SoPEC of the date (i.e. on any chIP), or for allSoPECs manufactured during the year etc. The driver issued the next yearcould work with all SoPECs up until that years etc. In this way thedrivers for a chip will be backwards compatible, but will bedeliberately not forwards-compatible. It allows the downloading of a newdriver with no problems, but it protects against bugs in one years'sdriver OS from being used against future SoPECs.

Note that the phasing in of a new OS doesn't have to be at the same timeas the hardware. For example, the new OS can come in 3 months before thehardware that it supports. However once the new SoPECs are beingdelivered, the OEM must not ship the older driver with the newer SoPECs,for the old driver will not work on the newer SoPECs. Basically once theOEM has received the new driver, they should use that driver for allSoPEC systems from that point on (old SoPECs will work with the newdriver).

This date-limiting feature would most likely be using a field in theComCo specified operating parameters, so it allows the SoPEC to usedate-checking in addition to additional QA Chip related parameterchecking (such as the OEM's PrintEngineLicenseId etc).

A variant on this theme is a date-window, where a start-date andend-date are specified (as relating to SoPEC manufacture, not date ofuse).

3.6.5 Authenticating Operating Parameters

Operating parameters need to be considered in terms ofManufacturer/owner operating parameters and OEM operating parameters.Both sets of operating parameters are stored on the PRINTER_QA chip(physically located inside the printer). This allows the printer tomaintain parameters regardless of being moved to different computers, ora loss/replacement of host O/S drivers etc.

On PRINTER_QA, memory vector M₀ contains the upgradable operatingparameters, and memory vectors M₁₊ contains any constant(non-upgradable) operating parameters.

Considering only Manufacturer/owner operating parameters for the moment,there are actually two problems:

-   a. setting and storing the Manufacturer/owner operating parameters,    which should be authorized only by Manufacturer/owner-   b. reading the parameters into SoPEC, which is an issue of SoPEC    authenticating the data on the PRINTER_QA chip since we don't trust    PRINTER_QA.

The PRINTER_QA chip therefore contains the following symmetric keys:

-   -   K₀=PrintEngineLicense_key. This key is constant for all SoPECs        supplied for a given print engine license agreement between an        OEM and a Manufacturer/owner ComCo. K₀ has write permissions to        the Manufacturer/owner upgradeable region of M₀ on PRINTER_QA.    -   K₁=SoPEC_id_key. This key is unique for each SoPEC (see Section        3.1), and is known only to the SoPEC and PRINTER_QA. K, does not        have write permissions for anything.

K₀ is used to solve problem (a). It is only used to authenticate theactual upgrades of the operating parameters. Upgrades are performedusing the standard upgrade protocol described in [5], with PRINTER_QAacting as the ChipU, and the external upgrader acting as the ChipS.

K₁ is used by SoPEC to solve problem (b). It is used to authenticatereads of data (i.e. the operating parameters) from PRINTER_QA. Theprocedure follows the standard authenticated read protocol described in[5], with PRINTER_QA acting as ChipR, and the embedded supervisorsoftware on SoPEC acting as ChipT. The authenticated read protocol [5]requires the use of a 160-bit nonce, which is a pseudo-random number.This creates the problem of introducing pseudo-randomness into SoPECthat is not readily determinable by OEM programs, especially given thatSoPEC boots into a known state. One possibility is to use the samerandom number generator as in the QA Chip (a 160-bit maximal-lengthedlinear feedback shift register) with the seed taken from the value inthe WatchDogTimer register in SoPEC's timer unit when the first pagearrives.

Note that the procedure for verifying reads of data from PRINTER_QA doesnot rely on Manufacturer/owner's key K₀. This means that precisely thesame mechanism can be used to read and authenticate the OEM data alsostored in PRINTER_QA. Of course this must be done by Manufacturer/ownersupervisor code so that SoPEC_id key is not revealed.

If the OEM also requires upgradable parameters, we can add an extra keyto PRINTER_QA, where that key is an OEM_key and has write permissions tothe OEM part of M₀.

In this way, K₁ never needs to be known by anyone except the SoPEC andPRINTER_QA.

Each printing SoPEC in a multi-SoPEC system need access to a PRINTER_QAchip that contains the appropriate SoPEC_id_key to validate ink useageand operating parameters. This can be accomplished by a separatePRINTER_QA for each SoPEC, or by adding extra keys (multipleSoPEC_id_keys) to a single PRINTER_QA.

However, if ink usage is not being validated (e.g. if print speed werethe only Manufacturer/owner upgradable parameter) then not all SoPECsrequire access to a PRINTER_QA chip that contains the appropriateSoPEC_id_key. Assuming that OEM program code controls the physical motorspeed (different motors per OEM), then the PHI within the first (oronly) front-page SoPEC can be programmed to accept (or generate) linesync pulses no faster than a particular rate. If line syncs arrivedfaster than the particular rate, the PHI would simply print at theslower rate. If the motor speed was hacked to be fast, the print imagewill appear stretched.

3.6.5.1 Floating Operating Parameters and Dongles

As described in Section 2.1.2, Manufacturer/owner operating parametersinclude such items as print speed, print quality etc. and are tied to alicense provided to an OEM. These parameters are underManufacturer/owner control. The licensed Manufacturer/owner operatingparameters are typically stored in the PRINTER_QA as described inSection 3.6.5.

However there are situations when it is desirable to have a floatingupgrade to a license, for use on a printer of the user's choice. Forexample, OEMs may sell a speed-increase license upgrade that can beplugged into the printer of the user's choice. This form of upgrade canbe considered a floating upgrade in that it upgrades whichever printerit is currently plugged into. This dongle is referred to asADDITIONAL_PRINTER_QA. The software checks for the existence of anADDITIONAL_PRINTER_QA, and if present the operating parameters arechosen from the values stored on both QA chips.

The basic problem of authenticating the additional operating parametersboils down to the problem that we don't trust ADDITIONAL_PRINTER_QA.Therefore we need a system whereby a given SoPEC can perform anauthenticated read of the data in ADDITIONAL_PRINTER_QA.

We should not write the SoPEC_id_key to a key in theADDITIONAL_PRINTER_QA because:

-   -   then it will be tied specifically to that SoPEC, and the primary        intention of the ADDITIONAL_PRINTER_QA is that it be floatable;    -   the ink cartridge would then not work in another printer since        the other printer would not know the old SoPEC_id_key (knowledge        of the old key is required in order to change the old key to a        new one).    -   updating keys is not power-safe (i.e. if at the user's site,        power is removed mid-update, the ADDITIONAL_PRINTER_QA could be        rendered useless)

The proposed solution is to let ADDITIONAL_PRINTER_QA have two keys:

-   -   K₀=FloatingPrintEngineLicense_key. This key has the same        function as the PrintEngineLicense_key in the PRINTER_QA⁴ in        that K₀ has write permissions to the Manufacturer/owner        upgradeable region of M₀ on ADDITIONAL_PRINTER_QA.        ⁴This can be identical to PrintEngineLicense_key in the        PRINTER_QA if it is desireable (unlikely) that upgraders can        function on PRINTER_QAs as well as ADDITIONAL_PRINTER_QAs    -   K₁=UseExtParmsLicense_key. This key is constant for all of the        ADDITIONAL_PRINTER_QAs for a given license agreement between an        OEM and a Manufacturer/owner ComCo (this is not the same key as        PrintEngineLicense_key which is stored as K₀ in PRINTER_QA). K₁        has no write permissions to anything.

K₀ is used to allow writes to the various fields containing operatingparameters in the ADDITIONAL_PRINTER_QA. These writes/upgrades areperformed using the standard upgrade protocol described in [5], withADDITIONAL_PRINTER_QA acting as the ChipU, and the external upgraderacting as the ChipS. The upgrader (ChipS) also needs to check theappropriate licensing parameters such as OEM_Id for validity.

K₁ is used to allow SoPEC to authenticate reads of the ink remaining andany other ink data. This is accomplished by having the sameUseExtParmsLicense_key within PRINTER_QA (e.g. in K₂), also with nowrite permissions. i.e:

-   -   PRINTER_QA.K₂=UseExtParmsLicense_key. This key is constant for        all of the PRINTER_QAs for a given license agreement between an        OEM and a Manufacturer/owner ComCo. K₂ has no write permissions        to anything.

This means there are two shared keys, with PRINTER_QA sharing both, andthereby acting as a bridge between INK_CA and SoPEC.

-   -   UseExtParmsLicense_key is shared between PRINTER_QA and        ADDITIONAL_PRINTER_QA    -   SoPEC_id_key is shared between SoPEC and PRINTER_QA

All SoPEC has to do is do an authenticated read [6] fromADDITIONAL_PRINTER_QA, pass the data/signature to PRINTER_QA, letPRINTER_QA validate the data/signature, and get PRINTER_QA to produce asimilar signature based on the shared SoPEC_id_key. It can do so usingthe Translate function [6]. SoPEC can then compare PRINTER_QA'ssignature with its own calculated signature (i.e. implement a Testfunction [6] in software on SoPEC), and if the signatures match, thedata from ADDITIONAL_PRINTER_QA must be valID, and can therefore betrusted.

Once the data from ADDITIONAL_PRINTER_QA is known to be trusted, thevarious operating parameters such as OEM_Id can be checked for validity.

The actual steps of read authentication as performed by SoPEC are:R_(PRINTER)

PRINTER_QA.random( ) R_(DONGLE),M_(DONGLE),SIG_(DONGLE)

DONGLE_QA.read(K1, R_(PRINTER)) R_(SOPEC)

random( ) R_(PRINTER), SIG_(PRINTER)

PRINTER_QA.translate(K2, R_(DONGLE), M_(DONGLE), SIG_(DONGLE), K1,R_(SOPEC)) SIG_(SOPEC)

HMAC_SHA_1(SoPEC_id_key, M_(DONGLE) | R_(PRINTER) | R_(SOPEC)) If(SIG_(PRINTER) = SIG_(SOPEC))  //  various parms inside M_(DONGLE) (dataread from ADDITIONAL_PRINTER_QA) is valid Else  // the data read fromADDITIONAL_PRINTER_QA is not valid and cannot be trusted EndIf3.6.5.2 Dongles Tied to a Given SoPEC

Section 3.6.5.1 describes floating dongles i.e. dongles that can be usedon any SoPEC. Sometimes it is desirable to tie a dongle to a specificSoPEC.

Tying a QA_CHIP to be used only on a specific SoPEC can be easilyaccomplished by writing the PRINTER_QA's chipId (unique serial number)into an appropriate M₀ field on the ADDITIONAL_PRINTER_QA. The systemsoftware can detect the match and function appropriately. If there is nomatch, the software can ignore the data read from theADDITIONAL_PRINTER_QA.

Although it is also possible to store the SoPEC_id_key in one of thekeys within the dongle, this must be done in an environment where powerwill not be removed partway through the key update process (if power isremoved during the key update there is a possibility that the dongle QAChip may be rendered unusable, although this can be checked for afterthe power failure).

3.6.5.3 OEM Assembly-Line Test

Although an OEM should only be able sell the licensed operatingparameters for a given Print Engine, they must be able to assembly-linetest⁵ or service/test the Print Engine with a different set of operatingparameters e.g. a maximally upgraded Print Engine.⁵This section is referring to assembly-line testing rather thandevelopment testing. An OEM can maximally upgrade a given Print Engineto allow developmental testing of their own OEM program code &mechanics.

Several different mechanisms can be employed to allow OEMs to test theupgraded capabilities of the Print Engine. At present it is unclearexactly what kind of assembly-line tests would be performed.

The simplest solution is to use an ADDITIONAL_PRINTER_QA (i.e. specialdongle PRINTER_QA as described in Section 3.6.5.1). TheADDITIONAL_PRINTER_QA would contain the operating parameters thatmaximally upgrade the printer as long as the dongle is connected to theSoPEC. The exact connection may be directly electrical (e.g. via thestandard QA Chip connections) or may be over the USB connection to theprinter test host depending on the nature of the test. The exactpreferred connection is yet to be determined.

In the testing environment, the ADDITIONAL_PRINTER_QA also requires anumberOfImpressions field inside M₀, which is writeable by K₀. Beforethe SoPEC prints a page at the higher speed, it decrements thenumberOfImpressions counter, performs an authenticated read to ensurethe count was decremented, and then prints the page. In this way, thetotal number of pages that can be printed at high speed is reduced inthe event of someone stealing the ADDITIONAL_PRINTER_QA device. It alsomeans that multiple test machines can make use of the sameADDITIONAL_PRINTER_QA.

3.6.6 Use of a PrintEngineLicense id

Manufacturer/owner O/S program code contains the OEM's asymmetric publickey to ensure that the subsequent OEM program code is authentic—i.e.from the OEM. However given that SoPEC only contains a single root key,it is theoretically possible for different OEM's applications to be runidentically physical Print Engines i.e. printer driver for OEM, run onan identically physical Print Engine from OEM₂.

To guard against this, the Manufacturer/owner O/S program code containsa PrintEngineLicense_id code (e.g. 16 bits) that matches the same namedvalue stored as a fixed operating parameter in the PRINTER_QA (i.e. inM₁₊). As with all other operating parameters, the value ofPrintEngineLicense_id is stored in PRINTER_QA (and anyADDITIONAL_PRINTER_QA devices) at the same time as the other variousPRINTER_QA customizations are being applied, before being shipped to theOEM site.

In this way, the OEMs can be sure of differentiating themselves throughsoftware functionality.

3.6.7 Authentication of Ink

The Manufacturer/owner O/S must perform ink authentication [6] duringprints. Ink usage authentication makes use of counters in SoPEC thatkeep an accurate record of the exact number of dots printed for eachink.

The ink amount remaining in a given cartridge is stored in thatcartridge's INK QA chIP. Other data stored on the INK_QA chip includesink color, viscosity, Memjet firing pulse profile information, as wellas licensing parameters such as OEM_ID, inkType, InkUsageLicense_ID,etc. This information is typically constant, and is therefore likely tobe stored in M₁₊ within INK_QA.

Just as the Print Engine operating parameters are validated by means ofPRINTER_QA, a given Print Engine license may only be permitted tofunction with specifically licensed ink. Therefore the software on SoPECcould contain a valid set of ink types, colors, OEM_Ids,InkUsageLicense_Ids etc. for subsequent matching against the data in theINK_QA.

SoPEC must be able to authenticate reads from the INK_QA, both in termsof ink parameters as well as ink remaining.

To authenticate ink a number of steps must be taken:

-   -   restrict access to dot counts    -   authenticate ink usage and ink parameters via INK_QA and        PRINTER_QA    -   broadcast ink dot usage to all SoPECs in a multi-SoPEC system        3.6.7.1 Restrict Access to Dot Counts

Since the dot counts are accessed via the PHI in the PEP section ofSoPEC, access to these registers (and more generally all PEP registers)must be only available from supervisor mode, and not by OEM code(running in user mode). Otherwise it might be possible for OEM programcode to clear dot counts before authentication has occurred.

3.6.7.2 Authenticate Ink Usage and Ink Parameters via INK_QA andPRINTER_QA

The basic problem of authentication of ink remaining and other ink databoils down to the problem that we don't trust INK_QA. Therefore how cana SoPEC know the initial value of ink (or the ink parameters), and howcan a SoPEC know that after a write to the INK_QA, the count has beencorrectly decremented.

Taking the first issue, which is determining the initial ink count orthe ink parameters, we need a system whereby a given SoPEC can performan authenticated read of the data in INK_QA.

We cannot write the SoPEC_id_key to the INK_QA for two reasons:

-   -   updating keys is not power-safe (i.e. if power is removed        mid-update, the INK_QA could be rendered useless)    -   the ink cartridge would then not work in another printer since        the other printer would not know the old SoPEC_id_key (knowledge        of the old key is required in order to change the old key to a        new one).

The proposed solution is to let INK_QA have two keys:

-   -   K₀=SupplyInkLicense_key. This key is constant for all ink        cartridges for a given ink supply agreement between an OEM and a        Manufacturer/owner ComCo (this is not the same key as        PrintEngineLicense_key which is stored as K₀ in PRINTER_QA). K₀        has write permissions to the ink remaining regions of M₀ on        INK_QA.    -   K₁=UseInkLicense_key. This key is constant for all ink        cartridges for a given ink usage agreement between an OEM and a        Manufacturer/owner ComCo (this is not the same key as        PrintEngineLicense_key which is stored as K₀ in PRINTER_QA). K₁        has no write permissions to anything.

K₀ is used to authenticate the actual upgrades of the amount of inkremaining (e.g. to fill and refill the amount of ink). Upgrades areperformed using the standard upgrade protocol described in [5], withINK_QA acting as the ChipU, and the external upgrader acting as theChipS. The fill and refill upgrader (ChipS) also needs to check theappropriate ink licensing parameters such as OEM_ID, InkType andInkUsageLicense_Id for validity.

K₁ is used to allow SoPEC to authenticate reads of the ink remaining andany other ink data. This is accomplished by having the sameUseInkLicense_key within PRINTER_QA (e.g. in K₂ or K₃), also with nowrite permissions.

This means there are two shared keys, with PRINTER_QA sharing both, andthereby acting as a bridge between INK_QA and SoPEC.

-   -   UseInkLicense_key is shared between INK_QA and PRINTER_QA    -   SoPEC_id_key is shared between SoPEC and PRINTER_QA

All SoPEC has to do is do an authenticated read [6] from INK_QA, passthe data/signature to PRINTER_QA, let PRINTER_QA validate thedata/signature and get PRINTER_QA to produce a similar signature basedon the shared SoPEC id key (i.e. the Translate function [6]). SoPEC canthen compare PRINTER_QA's signature with its own calculated signature(i.e. implement a Test function [6] in software on the SoPEC), and ifthe signatures match, the data from INK_QA must be valID, and cantherefore be trusted.

Once the data from INK_QA is known to be trusted, the amount of inkremaining can be checked, and the other ink licensing parameters such asOEM_ID, InkType, InkUsageLicense_Id can be checked for validity.

The actual steps of read authentication as performed by SoPEC are:R_(PRINTER)

PRINTER_QA.random( ) R_(INK), M_(INK), SIG_(INK)

INK_QA.read(K1, R_(PRINTER))  //  read with key1: UseInkLicense_keyR_(SOPEC)

random( ) R_(PRINTER), SIG_(PRINTER)

PRINTER_QA.translate(K2, R_(INK), M_(INK), SIG_(INK), K1, R_(SOPEC))SIG_(SOPEC)

HMAC_SHA_1(SoPEC_id_key, M_(INK) | R_(PRINTER) | R_(SOPEC)) If(SIG_(PRINTER) = SIG_(SOPEC))  // M_(INK) (data read from INK_QA) isvalid  // M_(INK) could be ink parameters, such as InkUsageLicense_Id,or ink remaining  If (M_(INK).inkRemaining = expectedInkRemaining)   //all is ok  Else   // the ink value is not what we wrote, so don't printanything anymore  EndIf Else  // the data read from INK_QA is not validand cannot be trusted EndIf

Strictly speaking, we don't need a nonce (R_(SOPEC)) all the timebecause M_(A) (containing the ink remaining) should be decrementingbetween authentications. However we do need one to retrieve the initialamount of ink and the other ink parameters (at power up). This is whytaking a random number from the WatchDogTimer at the receipt of thefirst page is acceptable.

In summary, the SoPEC performs the non-authenticated write [6] of inkremaining to the INK_QA chip, and then performs an authenticated read ofthe data via the PRINTER_QA as per the pseudocode above. If the value isauthenticated, and the INK_QA ink-remaining value matches the expectedvalue, the count was correctly decremented and the printing cancontinue.

3.6.7.3 Broadcast Ink Dot Usage to all SoPECs in a Multi-SoPEC System

In a multi-SoPEC system, each SoPEC attached to a printhead mustbroadcast its ink usage to all the SoPECs. In this way, each SoPEC willhave its own version of the expected ink usage.

In the case of a man-in-the-middle attack, at worst the count in a givenSoPEC is only its own count (i.e. all broadcasts are turned into 0 inkusage by the man-in-the-middle). We would also require the broadcastamount to be treated as an unsigned integer to prevent negative amountsfrom being substituted.

A single SoPEC performs the update of ink remaining to the INK_QA chip,and then all SoPECs perform an authenticated read of the data via theappropriate PRINTER_QA (the PRINTER_QA that contains their matchingSoPEC_id_key—remember that multiple SoPEC id keys can be stored in asingle PRINTER_QA). If the value is authenticated, and the INK_QA valuematches the expected value, the count was correctly decremented and theprinting can continue.

If any of the broadcasts are not received, or have been tampered with,the updated ink counts will not match. The only case this does not caterfor is if each SoPEC is tricked (via a USB2 inter-SoPEC-commsman-in-the-middle attack) into a total that is the same, yet not thetrue total. Apart from the fact that this is not viable for generalpages, at worst this is the maximum amount of ink printed by a singleSoPEC. We don't care about protecting against this case.

Since a typical maximum is 4 printing SoPECs, it requires at most 4authenticated reads. This should be completed within 0.5 seconds, wellwithin the 1-2 seconds/page print time.

3.6.8 Example Hierarchy

Adding an extra bootloader step to the example from Section 3.6.2, wecan break up the contents of program space into logical sections, asshown in Table 227. Note that the ComCo does not provide any programcode, merely operating parameters that is used by the O/S. TABLE 227Sections of Program Space section contents verifies 0 boot loader 0section 1 via boot0key (ROM) SHA-1 function asymmetric decrypt functionboot0key 1 boot loader 1 section 2 via SoPEC_OS_public_keySoPEC_OS_public_key 2 Manufacturer/owner O/S program section 3 viaComCo_public_key code section 4 via OEM_public_key (supplied function togenerate in section 3) SoPEC_id_key from SoPEC_id PRINTER_QA data, whichincludes the Basic Print Engine PrintEngineLicense_id, ComCo_public_keyManufacturer/owner operating parameters, and OEM operating parameters(all authenticated via SoPEC_id_key) 3 ComCo license agreement operatingIs used by section 2 to verify section 4 parameter ranges, including andrange of parameters as found in PrintEngineLicense_id (gets PRINTER_QAloaded into supervisor mode section of memory) OEM_public_key (getsloaded into supervisor mode section of memory) Any ComCo writtenuser-mode program code (gets loaded into mode mode section of memory) 4OEM specific program code OEM operating parameters via calls toManufacturer/owner O/S code

The verification procedures will be required each time the CPU is wokenup, since the RAM is not preserved.

3.6.9 What if the CPU is Not Fast Enough?

In the example of Section 3.6.8, every time the CPU is woken up to printa document it needs to perform:

-   -   SHA-1 on all program code and program data    -   4 sets of asymmetric decryption to load the program code and        data    -   1 HMAC-SHA1 generation per 512-bits of Manufacturer/owner and        OEM printer and ink operating parameters

Although the SHA-1 and HMAC process will be fast enough on the embeddedCPU (the program code will be executing from ROM), it may be that theasymmetric decryption will be slow. And this becomes more likely witheach extra level of authentication. If this is the case (as is likely),hardware acceleration is required.

A cheap form of hardware acceleration takes advantage of the fact thatin most cases the same program is loaded each time, with the first timelikely to be at power-up. The hardware acceleration is simply datastorage for the authorizedDigest which means that the boot procedure nowis:  slowCPU_bootloader0(data, sig)   localDigest

SHA-1(data)   If (localDigest = previouslyStoredAuthorizedDigest)   jump to program code at data-start address// will never return   Else   authorizedDigest

decrypt(sig, boot0key)    expectedDigest    =    0x00|0x01|0xFF..0xFF|     0x003021300906052B0E03021A05000414 |localDigest)    If(authorizedDigest == expectedDigest)    previouslyStoredAuthorizedDigest

localDigest     jump to program code at data-start address// will neverreturn    Else    // program code is unauthorized   EndIf

This procedure means that a reboot of the same authorized program codewill only require SHA-1 processing. At power-up, or if new program codeis loaded (e.g. an upgrade of a driver over the internet), then the fullauthorization via asymmetric decryption takes place. This is because thestored digest will not match at power-up and whenever a new program isloaded.

The question is how much preserved space is required.

Each digest requires 160 bits (20 bytes), and this is constantregardless of the asymmetric encryption scheme or the key length. Whileit is possible to reduce this number of bits, thereby sacrificingsecurity, the cost is small enough to warrant keeping the full digest.

However each level of boot loader requires its own digest to bepreserved. This gives a maximum of 20 bytes per loader. Digests foroperating parameters and ink levels may also be preserved in the sameway, although these authentications should be fast enough not to requirecached storage.

Assuming SoPEC provides for 12 digests (to be generous), this is a totalof 240 bytes. These 240 bytes could easily be stored as 60×32-bitregisters, or probably more conveniently as a small amount of RAM (eg0.25-1 Kbyte). Providing something like 1 Kbyte of RAM has the advantageof allowing the CPU to store other useful data, although this is not arequirement.

In general, it is useful for the boot ROM to know whether it is beingstarted up due to power-on reset, GPIO activity, or activity on theUSB2. In the former case, it can ignore the previously stored values(either 0 for registers or garbage for RAM). In the latter cases, it canuse the previously stored values. Even without this, a startup value of0 (or garbage) means the digest won't match and therefore theauthentication will occur implictly.

3.7 SoPEC Phsyical Identification

There must be a mapping of logical to physical since specific SoPECs areresponsible for printing on particular physical parts of the page,and/or have particular devices attached to specific pins.

The identification process is mostly solved by general USB2 enumeration.

Each slave SoPEC will need to verify the boot broadcast messagesreceived over USB2, and only execute the code if the signatures arevalid. Several levels of authorization may occur. However, at somestage, this common program code (broadcast to all of the slave SoPECsand signed by the appropriate asymmetric private key) can, among otherthings, set the slave SoPEC's id relating to the physical location. Ifthere is only 1 slave, the id is easy to determine, but if there is morethan 1 slave, the id must be determined in some fashion. For example,physical location/id determination may be:

-   -   given by the physical USB2 port on the master    -   related to the physical wiring up of the USB2 interconnects    -   based on GPIO wiring. On other systems, a particular physical        arrangement of SoPECs may exist such that each slave SoPEC will        have a different set of connections on GPIOs. For example, one        SoPEC maybe in charge of motor control, while another may be        driving the LEDs etc. The unused GPIO pins (not necessarily the        same on each SoPEC) can be set as inputs and then tied to 0        or 1. As long as the connection settings are mutually exclusive,        program code can determine which is which, and the id        appropriately set.

This scheme of slave SoPEC identification does not introduce a securitybreach. If an attacker rewires the pinouts to confuse identification, atbest it will simply cause strange printouts (e.g. swapping of printoutdata) to occur, while at worst the Print Engine will simply notfunction.

3.8 Setting Up QA Chip Keys

In use, each INK_QA chip needs the following keys:

-   -   K₀=SupplyInkLicense_key    -   K₁=UseInkLicense_key

Each PRINTER_QA chip tied to a specific SoPEC requires the followingkeys:

-   -   K₀=PrintEngineLicense_key    -   K₁=SoPEC_id_key    -   K₂=UseExtParmsLicense_key    -   K₃=UseInkLicense_key

Note that there may be more than one K₁ depending on the number ofPRINTER_QA chips and SoPECs in a system. These keys need to beappropriately set up in the QA Chips before they will function correctlytogether.

3.8.1 Original QA Chips as Received by a ComCo

When original QA Chips are shipped from QACo to a specific ComCo theirkeys are as follows:

-   -   K₀=QACo_ComCo_Key0    -   K₁=QACo_ComCo_Key1    -   K₂=QACo_ComCo_Key2    -   K₃=QACo_ComCo_Key3

All 4 keys are only known to QACo. Note that these keys are differentfor each QA ChIP.

3.8.2 Steps at the ComCo

The ComCo is responsible for making Print Engines out of Memjetprintheads, QA Chips, PECs or SoPECs, PCBs etc.

In addition, the ComCo must customize the INK_QA chips and PRINTER_QAchip on-board the print engine before shipping to the OEM.

There are two stages:

-   -   replacing the keys in QA Chips with specific keys for the        application (i.e. INK_QA and PRINTER_QA)    -   setting operating parameters as per the license with the OEM        3.8.2.1 Replacing Keys

The ComCo is issued QID hardware [4] by QACo that allows programming ofthe various keys (except for K₁) in a given QA Chip to the final values,following the standard ChipF/ChipP replace key (indirect version)protocol [6]. The indirect version of the protocol allows eachQACo_ComCo_Key to be different for each SoPEC.

In the case of programming of PRINTER_QA's K₁ to be SoPEC_id_key, thereis the additional step of transferring an asymmetrically encryptedSoPEC_id_key (by the public-key) along with the nonce (R_(P)) used inthe replace key protocol to the device that is functioning as a ChipF.The ChipF must decrypt the SoPEC_id_key so it can generate the standardreplace key message for PRINTER_QA (functioning as a ChipP in theChipF/ChipP protocol). The asymmetric key pair held in the ChipFequivalent should be unique to a ComCo (but still known only by QACo) toprevent damage in the case of a compromise.

Note that the various keys installed in the QA Chips (both INK_QA andPRINTER_QA) are only known to the QACo. The OEM only uses QIDs and QACosupplied ChipFs. The replace key protocol [6] allows the programming tooccur without compromising the old or new key.

3.8.2.2 Setting Operating Parameters

There are two sets of operating parameters stored in PRINTER_QA andINK_QA:

-   -   fixed    -   upgradable

The fixed operating parameters can be written to by means of anon-authenticated writes [6] to M₁₊ via a QID [4], and permission bitsset such that they are ReadOnly.

The upgradable operating parameters can only be written to after the QAChips have been programmed with the correct keys as per Section 3.8.2.1.Once they contain the correct keys they can be programmed withappropriate operating parameters by means of a QID and an appropriateChipS (containing matching keys).

Authentication Protocols

1 Introduction

The following describes authentication protocols for generalauthentication applications, but with specific reference to the QA ChIP.

The intention is to show the broad form of possible protocols for use indifferent authentication situations, and can be used as a reference whensubsequently defining an implementation specification for a particularapplication. As mentioned earlier, although the protocols are describedin relation to a printing environment, many of them have widerapplication such as, but not limited to, those described at the end ofthis specification.

2 Nomenclature

The following symbolic nomenclature is used throughout this document:TABLE 228 Summary of symbolic nomenclature Symbol Description F[X]Function F, taking a single parameter X F[X, Y] Function F, taking twoparameters, X and Y X|Y X concatenated with Y X

Y Bitwise X AND Y X

Y Bitwise X OR Y (inclusive-OR) X ⊕ Y Bitwise X XOR Y (exclusive-OR)

X Bitwise NOT X (complement) X

Y X is assigned the value Y X

{Y, Z} The domain of assignment inputs to X is Y and Z X = Y X is equalto Y X ≠ Y X is not equal to Y

X Decrement X by 1 (floor 0)

X Increment X by 1 (modulo register length) Erase X Erase Flash memoryregister X SetBits[X, Y] Set the bits of the Flash memory register Xbased on Y Z

ShiftRight[X, Y] Shift register X right one bit position, taking inputbit from Y and placing the output bit in Z3 Pseudocode3.1 Asynchronous

The following pseudocode:

-   -   var=expression        -   means the var signal or output is equal to the evaluation of            the expression.            3.2 Synchronous

The following pseudocode:

-   -   var←expression        -   means the var register is assigned the result of evaluating            the expression during this cycle.            3.3 Expression

Expressions are defined using the nomenclature in Table 228 above.Therefore:

-   -   var=(a=b)        is interpreted as the var signal is 1 if a is equal to b, and 0        otherwise.        4. Intentionally Blank        5 Basic Protocols        5.1 Protocol Background

This protocol set is a restricted form of a more general case of amultiple key single memory vector protocol. It is a restricted form inthat the memory vector M has been optimized for Flash memoryutilization:

-   -   M is broken into multiple memory vectors (semi-fixed and        variable components) for the purposes of optimizing flash memory        utilization. Typically M contains some parts that are fixed at        some stage of the manufacturing process (eg a batch number,        serial number etc.), and once set, are not ever updated. This        information does not contain the amount of consumable remaining,        and therefore is not read or written to with any great        frequency.    -   We therefore define M₀ to be the M that contains the frequently        updated sections, and the remaining Ms to be rarely written to.        Authenticated writes only write to M₀, and non-authenticated        writes can be directed to a specific M_(n). This reduces the        size of permissions that are stored in the QA Chip (since        key-based writes are not required for Ms other than M₀). It also        means that M₀ and the remaining Ms can be manipulated in        different ways, thereby increasing flash memory longevity.        5.2 Requirements of Protocol

Each QA Chip contains the following values:

-   N The maximum number of keys known to the chIP.-   T The number of vectors M is broken into.-   K_(N) Array of N secret keys used for calculating F_(Kn)[X] where    K_(n) is the nth element of the array.-   R Current random number used to ensure time varying messages. Each    chip instance must be seeded with a different initial value. Changes    for each signature generation.-   M_(T) Array of T memory vectors. Only M₀ can be written to with an    authorized write, while all Ms can be written to in an unauthorized    write. Writes to M₀ are optimized for Flash usage, while updates to    any other M₁₊ are expensive with regards to Flash utilization, and    are expected to be only performed once per section of M_(n). M₁    contains T, N and f in ReadOnly form so users of the chip can know    these two values.-   P_(T+N) T+N element array of access permissions for each part of M.    Entries n={0 . . . T−1} hold access permissions for    non-authenticated writes to M_(n) (no key required). Entries n={T to    T+N−1}hold access permissions for authenticated writes to M₀ for    K_(n). Permission choices for each part of M are Read Only,    Read/Write, and Decrement Only.-   C 3 constants used for generating signatures. C₁, C₂, and C₃ are    constants that pad out a sub-message to a hashing boundary, and all    3 must be different.

Each QA Chip contains the following private function:

-   S_(Kn)[N,X] Internal function only. Returns S_(Kn)[X], the result of    applying a digital signature function S to X based upon the    appropriate key K_(n). The digital signature must be long enough to    counter the chances of someone generating a random signature. The    length depends on the signature scheme chosen, although the scheme    chosen for the QA Chip is HMAC-SHA1, and therefore the length of the    signature is 160 bits.

Additional functions are required in certain QA Chips, but these aredescribed as required.

5.3 Read protocols

The set of read protocols describe the means by which a System reads aspecific data vector M_(t) from a QA Chip referred to as ChipR.

We assume that the communications link to ChipR (and therefore ChipRitself) is not trusted. If it were trusted, the System could simply readthe data and there is no issue. Since the communications link to ChipRis not trusted and ChipR cannot be trusted, the System needs a way ofauthenticating the data as actually being from a real ChipR.

Since the read protocol must be capable of being implemented in physicalQA Chips, we cannot use asymmetric cryptography (for example the ChipRsigns the data with a private key, and System validates the signatureusing a public key).

This document describes two read protocols:

-   -   direct validation of reads    -   indirect validation of reads.        5.3.1 Direct Validation of Reads

In a direct validation read protocol we require two QA Chips: ChipR isthe QA Chip being read, and ChipT is the QA Chip we entrust to tell uswhether or not the data read from ChipR is trustworthy. The basic ideais that system asks ChipR for data, and ChipR responds with the data anda signature based on a secret key. System then asks ChipT whether thesignature supplied by ChipR is correct. If ChipT responds that it is,then System can trust that data just read from ChipR. Every time data isread from ChipR, the validation procedure must be carried out.

Direct validation requires the System to trust the communication line toChipT. This could be because ChipT is in physical proximity to theSystem, and both System and ChipT are in a trusted (e.g. Silverbrooksecure) environment. However, since we need to validate the read, ChipRby definition must be in a non-trusted environment.

Each QA Chip protects its signature generation or verification mechanismby the use of a nonce.

The protocol requires the following publicly available functions inChipT:

-   Random    Returns R (does not advance R).-   Test[n,X, Y, Z] Advances R and returns 1 if S_(Kn)[R|X|C₁|Y]=Z.    Otherwise returns 0. The time taken to calculate and compare    signatures must be independent of data content.

The protocol requires the following publicly available functions inChipR:

-   Read[n, t, X] Advances R, and returns R, M_(t),    S_(Kn)[X|R|C₁|M_(t)]. The time taken to calculate the signature must    not be based on the contents of X, R, M_(t), or K. If t is invalID,    the function assumes t=0.

To read ChipR's memory M_(t) in a validated way, System performs thefollowing tasks:

-   a. System calls ChipT's Random function;-   b. ChipT returns R_(T) to System;-   c. System calls ChipR's Read function, passing in some key number    n1, the desired data vector number t, and R_(T) (from b);-   d. ChipR updates R_(R), then calculates and returns R_(R), M_(Rt),    S_(Kn1)[R_(T)|R_(R)|C₁|M_(Rt)];-   e. System calls ChipT's Test function, passing in the key to use for    signature verification n2, and the results from d (i.e. R_(R),    M_(Rt), S_(Kn1)[R_(T)|R_(R)|C₁|M_(Rt)]);-   f. System checks response from ChipT. If the response is 1, then the    M_(t) read from ChipR is considered to be valid. If 0, then the    M_(t) read from ChipR is considered to be invalid.

The choice of n1 and n2 must be such that ChipR's K_(n1)=ChipT's K_(n2).

The data flow for this read protocol is shown in FIG. 328.

From the System's perspective, the protocol would take on a form likethe following pseudocode: R_(T)

ChipT.Random( ) R_(R), M_(R), SIG_(R)

ChipR.Read(keyNumOnChipR,desiredM, R_(T)) ok

ChipT.Test(keyNumOnChipT, R_(R), M_(R), SIG_(R)) If (ok = 1) // M_(R) isto be trusted Else // M_(R) is not to be trusted EndIf

With regards to security, if an attacker finds out ChipR's K_(n1), theycan replace the ChipR by a fake ChipR because they can createsignatures. Likewise, if an attacker finds out ChipT's K_(n2), they canreplace the ChipR by a fake ChipR because ChipR's K_(n1)=ChipT's K_(n2).Moreover, they can use the ChipRs on any system that shares the samekey.

The only way of restricting exposure due to key reveals is to restrictthe number of systems that match ChipR and ChipT. i.e. vary the key asmuch as possible. The degree to which this can be done will depend onthe application. In the case of a PRINTER_QA acting as a ChipT, and anINK_QA acting as a ChipR, the same key must be used on all systems wherethe particular INK_QA data must be validated.

In all cases, ChipR must contain sufficient information to produce asignature. Knowing (or finding out) this information, whatever form itis in, allows clone ChipRs to be built.

5.3.2 Indirect Validation of Reads

In a direct validation protocol (see Section 5.3.1), the Systemvalidates the correctness of data read from ChipR by means of a trustedchip ChipT. This is possible because ChipR and ChipT share some secretinformation.

However, it is possible to extend trust via indirect validation. This isrequired when we trust ChipT, but ChipT doesn't know how to validatedata from ChipR. Instead, ChipT knows how to validate data from ChipI(some intermediate chIP) which in turn knows how to validate data fromeither another ChipI (and so on up a chain) or ChipR. Thus we have achain of validation.

The means of validation chains is translation of signatures. ChipI_(n)translates signatures from higher up the chain (either ChipI_(n−1) orfrom ChipR at the start of the chain) into signatures capable of beingpassed to the next stage in the chain (either ChipI_(n+1) or to ChipT atthe end of the chain). A given ChipI can only translate signatures if itknows the key of the previous stage in the chain as well as the key ofthe next stage in the chain.

The protocol requires the following publicly available functions inChipI:

-   Random    Returns R (does not advance R).-   Translate[n1,X, Y, Z,n2,A] Returns 1, S_(Kn2)[A|R|C₁|Y] and advances    R if Z=S_(Kn1)[R|X|C₁|Y]. Otherwise returns 0, 0. The time taken to    calculate and compare signatures must be independent of data    content.

The data flow for this signature translation protocol is shown in FIG.329:

Note that R_(prev) is eventually R_(R), and R_(next) is eventuallyR_(T). In the multiple ChipI case, R_(prev) is the R_(I) of ChipI_(n−1)and R_(next) is R_(I) of ChipI_(n+1). The R_(prev) of the first ChipI inthe chain is R_(R), and the R_(next) of the last ChipI in the chain isR_(T).

Assuming at least 1 ChipT, the System would need to perform thefollowing tasks in order to read ChipR's memory M_(t) in an indirectlyvalidated way:

-   a. System calls ChipI_(n)'s Random function;-   b. ChipI₀ returns R_(I0) to System;-   c. System calls ChipR's Read function, passing in some key number    n0, the desired data vector number t, and R_(I0) (from b);-   d. ChipR updates R_(R), then calculates and returns R_(R), M_(Rt),    S_(Kn0)[R_(In)|R_(R)|C₁|M_(Rt)];-   e. System assigns R_(R) to R_(prev) and    S_(Kn0)[R_(In)|R_(R)|C₁|M_(Rt)] to SIG_(prev)-   f. System calls the next-chip-in-the-chain's Random function (either    ChipI_(n+), or ChipT)-   g. The next-chip-in-the-chain will return R_(next) to System-   h. System calls ChipI_(n)'s Translate function, passing in n1_(n)    (translation input key number), R_(prev), M_(Rt), SIG_(prev)),    n2_(n), (translation output key number) and the results from g    (R_(next));-   i. ChipI returns testResult and SIG₁ to System-   j. If testResult=0, then the validation has failed, and the M_(t)    read from ChipR is considered to be invalid. Exit with failure.-   k. If the next chip in the chain is a ChipI, assign SIG₁ to    SIG_(prev) and go to step f-   l. System calls ChipT's Test function, passing in n_(t), R_(prev),    M_(Rt), and SIG_(prev);-   m. System calls System checks response from ChipT. If the response    is 1, then the M_(t) read from ChipR is considered to be valid. If    0, then the M_(t) read from ChipR is considered to be invalid.

For the Translate function to work, ChipI_(n) and ChipI_(n+1), mustshare a key. The choice of n1 and n2 in the protocol described must besuch that ChipI_(n)'s K_(n2)=ChipI_(n+1)'s K_(n1).

Note that Translate is essentially a “Test plus resign” function. Froman implementation point of view the first part of Translate is identicalto Test.

Note that the use of ChipIs and the translate function merely allowssignatures to be transformed. At the end of the translation chain (ifpresent) will be a ChipT requiring the use of a Test function.

There can be any number of ChipIs in the chain to ChipT as long as theTranslate function is used to map signatures between ChipI_(n) andChipI_(n+1) and so on until arrival at the final destination (ChipT).

From the System's perspective, a read protocol using at least 1 ChipIwould take on a form like the following pseudocode: R_(next)

ChipI[0].Random( ) R_(prev), M_(R), SIG_(prev)

ChipR.Read(keyNumOnChipR,desiredM, R_(next)) ok = 1 i = 0 while ((i <iMax) AND ok) For i

0 to iMax If (i = iMax)  R_(next)

ChipT.Random( ) Else  R_(next)

ChipI[i+1].Random( ) EndIf ok, SIG_(prev)

ChipI[i].Translate(iKey[i], R_(prev), M_(R), SIG_(prev), oKey[i],R_(next)) R_(prev) = R_(next) If (ok = 0)  // M_(R) is not to be trustedEndIf EndFor ok

ChipT.Test(keyNumOnChipT, R_(prev), M_(R), SIG_(prev)) If (ok = 1) //M_(R) is to be trusted Else // M_(R) is not to be trusted EndIf5.3.3 Additional Comments on Reads

In the Memjet printing environment, certain implementations will existwhere the operating parameters are stored in QA Chips. In this case, thesystem must read the data from the QA Chip using an appropriate readprotocol.

If the connection is trusted (e.g. to a virtual QA Chip in software), ageneric Read is sufficient. If the connection is not trusted, it isideal that the System have a trusted ChipT in the form of software (ifpossible) or hardware (e.g. a QA Chip on board the same silicon packageas the microcontroller and firmware). Whether implemented in software orhardware, the QA Chip should contain an appropriate key that is uniqueper print engine. Such a key setup would allow reads of print engineparameters and also allow indirect reads of consumables (from aconsumable QA ChIP).

If the ChipT is physically separate from System (e.g. ChipT is on aboard connected to System) System must also occasionally (based onsystem clock for example) call ChipT's Test function with bad data,expecting a 0 response. This is to reduce the possibility of someoneinserting a fake ChipT into the system that always returns 1 for theTest function.

5.4 Upgrade Protocols

This set of protocols describe the means by which a System upgrades aspecific data vector M_(t) within a QA Chip (ChipU). The data vector maycontain information about the functioning of the device (e.g. thecurrent maximum operating speed) or the amount of a consumableremaining.

The updating of M_(t) in ChipU falls into two categories:

-   -   non-authenticated writes, where anyone is able to update the        data vector    -   authenticated writes, where only authorized entities are able to        upgrades data vectors        5.4.1 Non-Authenticated Writes

This is the most frequent type of write, and takes place between theSystem/consumable during normal everyday operation for M₀, and duringthe manufacturing process for M₁₊.

In this kind of write, the System wants to change M_(t) within ChipUsubject to P. For example, the System could be decrementing the amountof consumable remaining. Although System does not need to know and ofthe K_(S) or even have access to a trusted chip to perform the write,the System must follow a non-authenticated write by an authenticatedread if it needs to know that the write was successful.

The protocol requires ChipU to contain the following publicly availablefunction:

-   Write[t, X] Writes X over those parts of M_(t) subject to P_(t) and    the existing value for M.    -   To authenticate a write of M_(new) to ChipA's memory M_(new):-   a. System calls ChipU's Write function, passing in M_(new);-   b. The authentication procedure for a Read is carried out (see    Section 5.3 on page 604);-   c. If the read succeeds in such a way that M_(new)=M returned in b,    the write succeeded. If not, it failed.

Note that if these parameters are transmitted over an error-pronecommunications line (as opposed to internally or using an additionalerror-free transport layer), then an additional checksum would berequired to prevent the wrong M from being updated or to prevent thecorrect M from being updated to the wrong value. For example, SHA-1[t,X] should be additionally transferred across the communications lineand checked (either by a wrapper function around Write or in a variantof Write that takes a hash as an extra parameter).

This is the most frequent type of write, and takes place between theSystem/consumable during normal everyday operation for M₀, and duringthe manufacturing process for M₁₊.

5.4.2 Authenticated Writes

In the QA Chip protocols, M₀ is defined to be the only data vector thatcan be upgraded in an authenticated way. This decision was madeprimarily to simplify flash management, although it also helps to reducethe permissions storage requirements.

In this kind of write, System wants to change Chip U's M₀ in anauthorized way, without being subject to the permissions that applyduring normal operation. For example, a consumable may be at a refillingstation and the normally Decrement Only section of M₀ should be updatedto include the new valid consumable. In this case, the chip whose M₀ isbeing updated must authenticate the writes being generated by theexternal System and in addition, apply the appropriate permission forthe key to ensure that only the correct parts of M₀ are updated. Havinga different permission for each key is required as when multiple keysare involved, all keys should not necessarily be given open access toM₀. For example, suppose M₀ contains printer speed and a counter ofmoney available for franking. A ChipS that updates printer speed shouldnot be capable of updating the amount of money. Since P_(0 . . . T−1) isused for non-authenticated writes, each K_(n) has a correspondingpermission P_(T+n) that determines what can be updated in anauthenticated write.

The basic principle of the authenticated write (or upgrade) protocol isthat the new value for the M_(t) must be signed before ChipU accepts it.The QA Chip responsible for generating the signature (ChipS) must firstvalidate that the ChipU is valid by reading the old value for M_(t).Once the old value is seen as valID, a new value can be signed by ChipSand the resultant data plus signature passed to ChipU. Note that bothchips distrust each other.

There are two forms of authenticated writes. The first form is when bothChipU and ChipS directly store the same key. The second is when bothChipU and ChipS store different versions of the key and a transformingprocedure is used on the stored key to generate the required key—i.e.the key is indirectly stored. The second form is slightly morecomplicated, and only has value when the ChipS is not readily availableto an attacker.

5.4.2.1 Direct Authenticated Writes

The direct form of the authenticated write protocol is used when theChipS and ChipU are equally available to an attacker. For example,suppose that ChipU contains a printer's operating speed. Suppose thatthe speed can be increased by purchasing a ChipS and inserting it intothe printer system. In this case, the ChipS and ChipU are equallyavailable to an attacker. This is different from upgrading the printerover the internet where the effective ChipS is in a remote location, andthereby not as readily available to an attacker.

The direct authenticated write protocol requires ChipU to contain thefollowing publicly available functions: Read[n, t, X] Advances R, andreturns R, M_(t), S_(Kn)[X|R|C₁|M_(t)]. The time taken to calculate thesignature must not be based on the contents of X, R, M_(t), or K.WriteA[n, X, Y, Z] Advances R, replaces M₀ by Y subject to P_(T+n), andreturns 1 only if S_(Kn)[R|X|C₁|Y] = Z. Otherwise returns 0. The timetaken to calculate and compare signatures must be independent of datacontent. This function is identical to ChipT's Test function except thatit additionally writes Y subject to P_(T+n) to its M when the signaturematches.

Authenticated writes require that the System has access to a ChipS thatis capable of generating appropriate signatures.

In its basic form, ChipS requires the following variables and function:

-   SignM[n,V,W,X,Y,Z] Advances R, and returns R, S_(Kn)[W|R|C₁|Z] only    if Y=S_(Kn)[V|W|C₁|X]. Otherwise returns all 0s. The time taken to    calculate and compare signatures must be independent of data    content.

To update ChipU's M vector:

-   a. System calls ChipU's Read function, passing in n1, 0 (desired    vector number) and 0 (the random value, but is a don't-care value)    as the input parameters;-   b. ChipU produces R_(U), M_(U0), S_(Kn1)[0|R_(U)|C₁|M_(U0)] and    returns these to System;-   c. System calls ChipS's SignM function, passing in n2 (the key to be    used in ChipS), 0 (the random value as used in a), R_(U), M_(U0),    S_(Kn1)[0|R_(U)|C₁|M_(U0)], and M_(D) (the desired vector to be    written to ChipU);-   d. ChipS produces R_(S) and S_(Kn2)[R_(U)|R_(S)|C₁|M_(D)] if the    inputs were valID, and 0 for all outputs if the inputs were not    valid.-   e. If values returned in d are non zero, then ChipU is considered    authentic. System can then call ChipU's WriteA function with these    values from d.-   f. ChipU should return a 1 to indicate success. A 0 should only be    returned if the data generated by ChipS is incorrect (e.g. a    transmission error).

The choice of n1 and n2 must be such that ChipU's K_(n1)=ChipS's K_(n2).

The data flow for authenticated writes is shown in FIG. 330.

Note that this protocol allows ChipS to generate a signature for anydesired memory vector M_(D), and therefore a stolen ChipS has theability to effectively render the particular keys for those parts of M₀in ChipU irrelevant.

It is therefore not recommended that the basic form of ChipS be everimplemented except in specifically controlled circumstances.

It is much more secure to limit the powers of ChipS. The following listcovers some of the variants of limiting the power of ChipS:

-   a. the ability to upgrade a limited number of times-   b. the ability to upgrade based on a credit value—i.e. the upgrade    amount is decremented from the local value, and effectively    transferred to the upgraded device-   c. the ability to upgrade to a fixed value or from a limited list-   d. the ability to upgrade to any value-   e. the ability to only upgrade certain data fields within M

In many of these variants, the ability to refresh the ChipS in some way(e.g. with a new count or credit value) would be a useful feature.

In certain cases, the variant is in ChipS, while ChipU remains the same.It may also be desirable to create a ChipU variant, for example onlyallowing ChipU to only be upgraded a specific number of times.

5.4.2.1.1 Variant Example

This section details the variant for the ability to upgrade a memoryvector to any value a specific number of times, but the upgrade is onlyallowed to affect certain fields within the memory vector i.e. acombination of (a), (d), and (e) above.

In this example, ChipS requires the following variables and function:CountRemaining Part of ChipS's M₀ that contains the number of signaturesthat ChipS is allowed to generate. Decrements with each successful callto SignM and SignP. Permissions in ChipS's P_(0..T−1) for this part ofM₀ needs to be ReadOnly once ChipS has been setup. ThereforeCountRemaining can only be updated by another ChipS that will performupdates to that part of M₀ (assuming ChipS's Ps allows that part of M₀to be updated). Q Part of M that contains the write permissions forupdating ChipU's M. By adding Q to ChipS we allow different ChipSs thatcan update different parts of M_(U). Permissions in ChipS's P_(0..T−1)for this part of M needs to be ReadOnly once ChipS has been setup.Therefore Q can only be updated by another ChipS that will performupdates to that part of M. SignM[n,V,W,X,Y,Z] Advances R, decrementsCountRemaining and returns R, Z_(QX) (Z applied to X with permissionsQ), S_(Kn)[W|R|C₁|Z_(QX)] only if Y = S_(Kn)[V|W|C₁|X] andCountRemaining > 0. Otherwise returns all 0s. The time taken tocalculate and compare signatures must be independent of data content.

To update ChipU's M vector:

-   a. System calls ChipU's Read function, passing in n1, 0 (desired    vector number) and 0 (the random value, but is a don't-care value)    as the input parameters;-   b. ChipU produces R_(U), M_(U0), S_(Kn1)[0|R_(U)|C₁|M_(U0)] and    returns these to System;-   c. System calls ChipS's SignM function, passing in n2 (the key to be    used in ChipS), 0 (as used in a), R_(U), M_(U0),    S_(Kn1)[0|R_(U)|C₁|M_(U0)], and M_(D) (the desired vector to be    written to ChipU);-   d. ChipS produces R_(S), M_(QD) (processed by running M_(D) against    M_(U0) using Q) and S_(Kn2)[R_(U)|R_(S)|C₁|M_(QD)] if the inputs    were valID, and 0 for all outputs if the inputs were not valid.    -   e. If values returned in d are non zero, then ChipU is        considered authentic. System can then call ChipU's WriteA        function with these values from d.-   f. ChipU should return a 1 to indicate success. A 0 should only be    returned if the data generated by ChipS is incorrect (e.g. a    transmission error).

The choice of n1 and n2 must be such that ChipU's K_(n1)=ChipS's K_(n2).

The data flow for this variant of authenticated writes is shown in FIG.331.

Note that Q in ChipS is part of ChipS's M. This allows a user to set upChipS with a permission set for upgrades. This should be done to ChipSand that part of M designated by P_(0..T−1) set to ReadOnly before ChipSis programmed with K_(U). If K_(S) is programmed with K_(U) first, thereis a risk of someone obtaining a half-setup ChipS and changing all ofM_(U) instead of only the sections specified by Q.

In addition, CountRemaining in ChipS needs to be setup (including makingit ReadOnly in P_(S)) before ChipS is programmed with K_(U). ChipSshould therefore be programmed to only perform a limited number of SignMoperations (thereby limiting compromise exposure if a ChipS is stolen).Thus ChipS would itself need to be upgraded with a new CountRemainingevery so often.

5.4.2.2 Indirect Authenticated Writes

This section describes an alternative authenticated write protocol whenChipU is more readily available to an attacker and ChipS is lessavailable to an attacker. We can store different keys on ChipU andChipS, and implement a mapping between them in such a way that if theattacker is able to obtain a key from a given ChipU, they cannot upgradeall ChipUs.

In the general case, this is accomplished by storing key K_(S) on ChipS,and K_(U) and f on ChipU. The relationship is f(K_(S))=K_(U) such thatknowledge of K_(U) and f does not make it easy to determine K_(S). Thisimplies that a one-way function is desirable for f.

In the QA Chip domain, we define f as a number (e.g. 32-bits) such thatSHA1(K_(S)|f)=K_(U). The value of f (random between chips) can be storedin a known location within M₁ as a constant for the life of the QA ChIP.It is possible to use the same f for multiple relationships if desired,since f is public and the protection lies in the fact that f variesbetween QA Chips (preferably in a non-predictable way).

The indirect protocol is the same as the direct protocol with theexception that f is additionally passed in to the SignM function so thatChipS is able to generate the correct key. The System obtains f byperforming a Read of M₁. Note that all other functions, including theWriteA function in ChipU, are identical to their direct authenticationcounterparts.

-   SignM[f,n,V,W,X,Y,Z] Advances R, and returns R, S_(f(Kn))[W|R|C₁|Z]    only if Y=S_(f(Kn))[V|W|C₁|X] and CountRemaining>0. Otherwise    returns all 0s. The time taken to calculate and compare signatures    must be independent of data content.

Before reading ChipU's memory M₀ (the pre-upgrade value), the Systemmust extract f from ChipU by performing the following tasks:

-   a. System calls ChipU's Read function, passing in (dontCare, 1,    dontCare)-   b. ChipU returns M₁, from which System can extract f_(U)-   c. System stores f_(U) for future use

To update ChipU's M vector, the protocol is identical to that describedin the basic authenticated write protocol with the exception of steps cand d:

-   c. System calls ChipS's SignM function, passing in f_(U), n2 (the    key to be used in ChipS), 0 (as used in a), R_(U), M_(U0),    S_(Kn1)[0|R_(U)|C₁|M_(U0)], and M_(D) (the desired vector to be    written to ChipU);-   d. ChipS produces R_(S) and S_(fU(Kn2))[R_(U)|R_(S)|C₁|M_(D)] if the    inputs were valID, and 0 for all outputs if the inputs were not    valid.

In addition, the choice of n1 and n2 must be such that ChipU'sK_(n1)=ChipS's f_(U)(K_(n2)).

Note that f_(U) is obtained from M₁ without validation. This is becausethere is nothing to be gained by subverting the value of f_(U), (becausethen the signatures won't match).

From the System's perspective, the protocol would take on a form likethe following pseudocode: dontCare, M_(R), dontCare

ChipR.Read(dontCare,1, dontCare) f_(R) = extract from M_(R) ... R_(U),M_(U), SIG_(U)

ChipU.Read(keyNumOnChipU,0, 0) R_(S), SIG_(S) = ChipS.SignM2(f_(R),keyNumOnChipS, 0, R_(U), M_(U), SIG_(U), M_(D)) If (R_(S) = SIG_(S) = 0) // ChipU and therefore M_(U) is not to be trusted Else  // ChipU andtherefore M_(U) can be trusted  ok = ChipU.WriteA(keyNumOnChipU, R_(S),M_(D), SIG_(S))  If (ok)   // updating of data in ChipU was successful Else   // transmission error during WriteA  EndIf EndIf5.4.2.2.1 Variant Example

The indirect form of the example from Section 5.4.2.1.1 is shown here.

-   SignM[f,n,V,W,X,Y,Z] Advances R, decrements CountRemaining and    returns R, Z_(QX) (Z applied to X with permissions Q),    S_(f(Kn))[W|R|C₁|Z_(QX)] only if Y=S_(f(Kn))[V|W|C₁X] and    CountRemaining>0. Otherwise returns all 0s. The time taken to    calculate and compare signatures must be independent of data    content.

Before reading ChipU's memory M₀ (the pre-upgrade value), the Systemmust extract f from ChipU by performing the following tasks:

-   a. System calls ChipU's Read function, passing in (dontCare, 1,    dontCare)-   b. ChipU returns M₁, from which System can extract f_(U)-   c. System stores f_(U) for future use

To update ChipU's M vector, the protocol is identical to that describedin the basic authenticated write protocol with the exception of steps cand d:

-   c. System calls ChipS's SignM function, passing in f_(U), n2 (the    key to be used in ChipS), 0 (as used in a), R_(U), M_(U0),    S_(Kn1)[0|R_(U)|C₁|M_(U0)], and M_(D) (the desired vector to be    written to ChipU);-   d. ChipS produces R_(S), M_(QD) (processed by running M_(D) against    M_(U0) using Q) and S_(fU(Kn2))[R_(U)|R_(S)|C₁|M_(QD)] if the inputs    were valID, and 0 for all outputs if the inputs were not valid.

In addition, the choice of n1 and n2 must be such that ChipU'sK_(n1)=ChipS's f_(U)(K_(n2)).

Note that f_(U) is obtained from M₁ without validation. This is becausethere is nothing to be gained by subverting the value of f_(U), (becausethen the signatures won't match).

From the System's perspective, the protocol would take on a form likethe following pseudocode: dontCare, M_(R), dontCare

ChipR.Read(dontCare,1, dontCare) f_(R) = extract from M_(R) ... R_(U),M_(U), SIG_(U)

ChipU.Read(keyNumOnChipU,0, 0) R_(S), M_(QD), SIG_(S) =ChipS.SignM2(f_(R), keyNumOnChipS, 0, R_(U), M_(U), SIG_(U), M_(D)) If(R_(S) = M_(QD) = SIG_(S) = 0)  // ChipU and therefore M_(U) is not tobe trusted Else  // ChipU and therefore M_(U) can be trusted  ok =ChipU.WriteA(keyNumOnChipU, R_(S), M_(QD), SIG_(S))  If (ok)   //updating of data in ChipU was successful  Else   // transmission errorduring WriteA  EndIf EndIf5.4.3 Updating Permissions for Future Writes

In order to reduce exposure to accidental and malicious attacks on P(and certain parts of M), only authorized users are allowed to update P.Writes to P are the same as authorized writes to M, except that theyupdate P_(n) instead of M. Initially (at manufacture), P is set to beRead/Write for all M. As different processes fill up different parts ofM, they can be sealed against future change by updating the permissions.Updating a chip's P_(0..T−1) changes permissions for unauthorized writesto M_(n), and updating P_(T..T+N−1) changes permissions for authorizedwrites with key K_(n).

P_(n) is only allowed to change to be a more restrictive form of itself.For example, initially all parts of M have permissions of Read/Write. Apermission of Read/Write can be updated to Decrement Only or Read Only.A permission of Decrement Only can be updated to become Read Only. ARead Only permission cannot be further restricted.

In this transaction protocol, the System's chip is referred to as ChipS,and the chip being updated is referred to as ChipU. Each chip distruststhe other.

The protocol requires the following publicly available functions inChipU:

-   Random    Returns R (does not advance R).-   SetPermission[n,p,X,Y,Z] Advances R, and updates P_(p) according to    Y and returns 1 followed by the resultant P_(p) only if    S_(Kn)[R|X|Y|C₂]=Z. Otherwise returns 0. P_(p) can only become more    restricted. Passing in 0 for any permission leaves it unchanged    (passing in Y=0 returns the current P_(p)).

Authenticated writes of permissions require that the System has accessto a ChipS that is capable of generating appropriate signatures. ChipSrequires the following variable: CountRemaining Part of ChipS's M₀ thatcontains the number of signatures that ChipS is allowed to generate.Decrements with each successful call to SignM and SignP. Permissions inChipS's P_(0..T−1) for this part of M₀ needs to be ReadOnly once ChipShas been setup. Therefore CountRemaining can only be updated by anotherChipS that will perform updates to that part of M₀ (assuming ChipS'sP_(n) allows that part of M₀ to be updated).

In addition, ChipS requires either of the following two SignP functionsdepending on whether direct or indirect key storage is used (see directvs indirect authenticated write protocols in Section 5.4.2):

-   SignP[n,X,Y] Used when the same key is directly stored in both ChipS    and ChipU. Advances R, decrements CountRemaining and returns R and    S_(Kn)[X|R|Y|C₂] only if CountRemaining>0. Otherwise returns all 0s.    The time taken to calculate and compare signatures must be    independent of data content.-   SignP[f,n,X,Y] Used when the same key is not directly stored in both    ChipS and ChipU. In this case ChipU's K_(n1)=ChipS's f(K_(n2)). The    function is identical to the direct form of SignP, except that it    additionally accepts f and returns S_(f(Kn))[X|R|Y|C₂] instead of    S_(Kn)[X|R|Y|C₂].    5.4.3.1 Direct Form of SignP

When the direct form of SignP is used, ChipU's P_(n) is updated asfollows:

-   a. System calls ChipU's Random function;-   b. ChipU returns R_(U) to System;-   c. System calls ChipS's SignP function, passing in n2, R_(U) and    P_(D) (the desired P to be written to ChipU);-   d. ChipS produces R_(S) and S_(Kn2)[R_(U)|R_(S)|P_(D)|C₂] if it is    still permitted to produce signatures.-   e. If values returned in d are non zero, then System can then call    ChipU's SetPermission function with n1, the desired permission entry    p, R_(S), P_(D) and S_(Kn2)[R_(U)|R_(S)|P_(D)|C₂].-   f. ChipU verifies the received signature against its own generated    signature S_(Kn1)[R_(U)|R_(S)|P_(D)|C₂] and applies P_(D) to P_(n)    if the signature matches-   g. System checks 1 st output parameter. 1=success, 0=failure.

The choice of n1 and n2 must be such that ChipU's K_(n1)=ChipS's K_(n2).

The data flow for basic authenticated writes to permissions is shown inFIG. 332.

5.4.3.2 Indirect Form of SignP

When the indirect form of SignP is used in ChipS, the System mustextract f from ChipU (so it knows how to generate the correct key) byperforming the following tasks:

-   a. System calls ChipU's Read function, passing in (dontCare, 1,    dontCare)-   b. ChipU returns M₁, from which System can extract f_(U)-   c. System stores f_(U) for future use

ChipU's P_(n) is updated as follows:

-   a. System calls ChipU's Random function;-   b. ChipU returns R_(U) to System;-   c. System calls ChipS's SignP function, passing in f_(U), n2, R_(U)    and P_(D) (the desired P to be written to ChipU);-   d. ChipS produces R_(S) and S_(fU(K) _(n2))[R_(U)|R_(S)|P_(D)|C₂] if    it is still permitted to produce signatures.-   e. If values returned in d are non zero, then System can then call    ChipU's SetPermission function with n1, the desired permission entry    p, R_(S), P_(D) and S_(fU(Kn2))[R_(U)|R_(S)|P_(D)|C₂].-   f. ChipU verifies the received signature against    S_(Kn1)[R_(U)|R_(S)|P_(D)|C₂] and applies P_(D) to P_(n) if the    signature matches-   g. System checks 1 st output parameter. 1=success, 0=failure.

In addition, the choice of n1 and n2 must be such that ChipU'sK_(n1)=ChipS's f_(U)(K_(n2)).

5.4.4 Protecting Memory Vectors

To protect the appropriate part of M_(n) against unauthorized writes,call SetPermissions[n] for n=0 to T−1. To protect the appropriate partof M₀ against authorized writes with key n, call SetPermissions[T+n] forn=0 to N−1.

Note that only M₀ can be written in an authenticated fashion.

Note that the SetPermission function must be called after the part of Mhas been set to the desired value.

For example, if adding a serial number to an area of M₁ that iscurrently ReadWrite so that noone is permitted to update the numberagain:

-   -   the Write function is called to write the serial number to M₁    -   SetPermission(1) is called for to set that part of M to be        ReadOnly for non-authorized writes.

If adding a consumable value to M₀ such that only keys 1-2 can updateit, and keys 0, and 3-N cannot:

-   -   the Write function is called to write the amount of consumable        to M    -   SetPermission is called for 0 to set that part of M₀ to be        DecrementOnly for non-authorized writes. This allows the amount        of consumable to decrement.    -   SetPermission is called for n={T, T+3, T+4 . . . , T+N−1} to set        that part of M₀ to be ReadOnly for authorized writes using all        but keys 1 and 2. This leaves keys 1 and 2 with ReadWrite        permissions to M₀.

It is possible for someone who knows a key to further restrict otherkeys, but it is not in anyone's interest to do so.

5.5 Programming K

In this case, we have a factory chip (ChipF) connected to a System. TheSystem wants to program the key in another chip (ChipP). System wants toavoid passing the new key to ChipP in the clear, and also wants to avoidthe possibility of the key-upgrade message being replayed on anotherChipP (even if the user doesn't know the key).

The protocol assumes that ChipF and ChipP already share (directly orindirectly) a secret key K_(old). This key is used to ensure that only achip that knows K_(old) can set K_(new).

Although the example shows a ChipF that is only allowed to program aspecific number of ChipPs, the key-upgrade protocol can be easilyaltered (similar to the way the write protocols have variants) toprovide other means of limiting the ability to update ChipPs.

The protocol requires the following publicly available functions inChipP:

-   Random    Returns R (does not advance R).    -   ReplaceKey[n, X, Y, Z] Replaces K_(n) by S_(Kn)[R|X|C₃]⊕Y,        advances R, and returns 1 only if S_(Kn)[X|Y|C₃]=Z. Otherwise        returns 0. The time taken to calculate signatures and compare        values must be identical for all inputs.

And the following data and functions in ChipF:

-   CountRemaining Part of M₀ with contains the number of signatures    that ChipF is allowed to generate. Decrements with each successful    call to GetProgramKey. Permissions in P for this part of M₀ needs to    be ReadOnly once ChipF has been setup. Therefore can only be updated    by a ChipS that has authority to perform updates to that part of M₀.-   K_(new) The new key to be transferred from ChipF to ChipP. Must not    be visible. After manufacture, K_(new) is 0.

SetPartialKey[X] Updates K_(new) to be K_(new)⊕X. This function allowsK_(new) to be programmed in any number of steps, thereby allowingdifferent people or systems to know different parts of the key (but notthe whole K_(new)). K_(new) is stored in ChipF's flash memory.

In addition, ChipF requires either of the following GetProgramKeyfunctions depending on whether direct or indirect key storage is used onthe input key and/or output key (see direct vs indirect authenticatedwrite protocols in Section 5.4.2):

-   GetProgramKey1[n, X] Direct to direct. Used when the same key    (K_(n)) is directly stored in both ChipF and ChipP and we want to    store K_(new) in ChipP. Advances R_(F), decrements CountRemaining,    outputs R_(F), the encrypted key S_(Kn)[X|R_(F)|C₃]⊕K_(new) and a    signature of the first two outputs plus C₃ if CountRemaining>0.    Otherwise outputs 0. The time to calculate the encrypted key &    signature must be identical for all inputs.-   GetProgramKey2[f, n, X] Direct to indirect. Used when the same key    (K_(n)) is directly stored in both ChipF and ChipP but we want to    store f_(P)(K_(new)) in ChipP instead of simply K_(new) (i.e. we    want to keep the key in ChipP to be different in all ChipPs). In    this case ChipP's K_(n1)=ChipF's f_(P)(K_(n2)). The function is    identical to GetProgramKey1, except that it additionally accepts    f_(P), and returns S_(Kn)[X|R_(F)|C₃]⊕f_(P)(K_(new)) instead of    S_(Kn)[X|R_(F)|C₃]⊕K_(new). Note that the produced signature is    produced using K_(n) since that is what is already stored in ChipP.-   GetProgramKey3[f, n, X] Indirect to direct. Used when the same key    is not directly stored in both ChipF and ChipP but we want to store    K_(new) in ChipP. In this case ChipP's K_(n1)=ChipF's f_(P)(K_(n2)).    The function is identical to GetProgramKey1, except that it    additionally accepts f_(P), and returns    S_(fP(Kn))[X|R_(F)|C₃]⊕K_(new) instead of    S_(Kn)[X|R_(F)|C₃]⊕K_(new). The produced signature is produced using    f_(P)(Kn) instead of K_(n) since that is what is already stored in    ChipP.-   GetProgramKey4[f, n, X] Indirect to indirect. Used when the same key    is not directly stored in both ChipF and ChipP but we want to store    f_(P)(K_(new)) in ChipP instead of simply K_(new) (i.e. we want to    keep the key in ChipP to be different in all ChipPs). In this case    ChipP's K_(n1)=ChipF's f_(P)(K_(n2)). The function is identical to    GetProgramKey3, except that it returns    S_(fP(Kn))[X|R_(F)|C₃]⊕f_(P)(K_(new)) instead of    S_(fP(Kn))[X|R_(F)|C₃]⊕K_(new). The produced signature is produced    using f_(P)(K_(n)) since that is what is already stored in ChipP.

Since there are likely to be few ChipFs, and many ChipPs, the indirectforms of GetProgramKey can be usefully employed.

5.5.1 GetProgramKey1—direct to direct

With the “old key=direct, new key=direct” form of GetProgramKey, toupdate P's key:

-   a. System calls ChipP's Random function;-   b. ChipP returns R_(P) to System;-   c. System calls ChipF's GetProgramKey function, passing in n2 (the    desired key to use) and the result from b;-   d. ChipF updates R_(F), then calculates and returns R_(F),    S_(Kn2)[R_(P)|R_(F)|C₃]⊕K_(new), and    S_(Kn2)[R_(F)|S_(Kn2)[R_(P)|R_(F)|C₃|⊕K_(new)⊕C₃];-   e. If the response from d is not 0, System calls ChipP's ReplaceKey    function, passing in n1 (the key to use in ChipP) and the response    from d;-   f. System checks response from ChipP. If the response is 1, then    ChipP's K_(n1) has been correctly updated to K_(new). If the    response is 0, ChipP's K_(n1) has not been updated.

The choice of n1 and n2 must be such that ChipP's K_(n1)=ChipF's K_(n2).

The data flow for key updates is shown in FIG. 333:

Note that K_(new) is never passed in the open. An attacker could sendits own R_(P), but cannot produce S_(Kn2)[R_(P)|R_(F)|C₃] withoutK_(n2). The signature based on K_(new) is sent to ensure that ChipP willbe able to determine if either of the first two parameters have beenchanged en route.

CountRemaining needs to be setup in M_(F0) (including making it ReadOnlyin P) before ChipF is programmed with K_(P). ChipF should therefore beprogrammed to only perform a limited number of GetProgramKey operations(thereby limiting compromise exposure if a ChipF is stolen). Anauthorized ChipS can be used to update this counter if necessary (seeSection 5.4.2 on page 610).

5.5.2 GetProgramKey2—Direct to Indirect

With the “old key=direct, new key=indirect” form of GetProgramKey, toupdate P's key, the System must extract f from ChipP (so it can tellChipF how to generate the correct key) by performing the followingtasks:

-   a. System calls ChipP's Read function, passing in (dontCare, 1,    dontCare)-   b. ChipP returns M₁, from which System can extract f_(P)-   c. System stores f_(P) for future use

ChipP's key is updated as follows:

-   a. System calls ChipP's Random function;-   b. ChipP returns R_(P) to System;-   c. System calls ChipF's GetProgramKey function, passing in f_(P), n2    (the desired key to use) and the result from b;-   d. ChipF updates R_(F), then calculates and returns R_(F),    S_(Kn2)[R_(P)|R_(F)|C₃]⊕f_(P)(K_(new)), and    S_(Kn2)[R_(F)|S_(Kn2)[R_(P)|R_(F)|C₃]⊕f_(P)(K_(new))|C₃];-   e. If the response from d is not 0, System calls ChipP's ReplaceKey    function, passing in n1 (the key to use in ChipP) and the response    from d;-   f. System checks response from ChipP. If the response is 1, then    ChipP's K_(n1) has been correctly updated to f_(P)(K_(new)). If the    response is 0, ChipP's K_(n1) has not been updated.

The choice of n1 and n2 must be such that ChipP's K_(n1)=ChipF's K_(n2).

5.5.3 GetProgramKey3—Indirect to Direct

With the “old key=indirect, new key=direct” form of GetProgramKey, toupdate P's key, the System must extract f from ChipP (so it can tellChipF how to generate the correct key) by performing the followingtasks:

-   a. System calls ChipP's Read function, passing in (dontCare, 1,    dontCare)-   b. ChipP returns M₁, from which System can extract f_(P)-   c. System stores f_(P) for future use

ChipP's key is updated as follows:

-   a. System calls ChipP's Random function;-   b. ChipP returns R_(P) to System;-   c. System calls ChipF's GetProgramKey function, passing in f_(P), n2    (the desired key to use) and the result from b;-   d. ChipF updates R_(F), then calculates and returns R_(F),    S_(fP(Kn2))[R_(P)|R_(F)|C₃]⊕K_(new), and    S_(fP(Kn2))[R_(F)|S_(fP(Kn2))[R_(P)|R_(F)|C₃]⊕K_(new)|C₃];-   e. If the response from d is not 0, System calls ChipP's ReplaceKey    function, passing in n1 (the key to use in ChipP) and the response    from d;-   f. System checks response from ChipP. If the response is 1, then    ChipP's K_(n1) has been correctly updated to K_(new). If the    response is 0, ChipP's K_(n1) has not been updated.

The choice of n1 and n2 must be such that ChipP's K_(n1)=ChipF'sf_(P)(K_(n2)).

5.5.4 GetProgramKey4—Indirect to Indirect

With the “old key=indirect, new key=indirect” form of GetProgramKey, toupdate P's key, the System must extract f from ChipP (so it can tellChipF how to generate the correct key) by performing the followingtasks:

-   a. System calls ChipP's Read function, passing in (dontCare, 1,    dontCare)-   b. ChipP returns M₁, from which System can extract f_(P)-   c. System stores f_(P) for future use

ChipP's key is updated as follows:

-   a. System calls ChipP's Random function;-   b. ChipP returns R_(P) to System;-   c. System calls ChipF's GetProgramKey function, passing in f_(P), n2    (the desired key to use) and the result from b;-   d. ChipF updates R_(F), then calculates and returns R_(F),    S_(fP(Kn2))[R_(P)|R_(F)|C₃]⊕f_(P)(K_(new)), and    S_(fP(Kn2))[R_(F)|S_(fP(Kn2))[R_(P)|R_(F)|C₃]⊕f_(P)(K_(new))|C₃];-   e. If the response from d is not 0, System calls ChipP's ReplaceKey    function, passing in n1 (the key to use in ChipP) and the response    from d;-   f. System checks response from ChipP. If the response is 1, then    ChipP's K_(n1) has been correctly updated to f_(P)(K_(new)). If the    response is 0, ChipP's K_(n1) has not been updated.

The choice of n1 and n2 must be such that ChipP's K_(n1)=ChipF'sf_(P)(K_(n2)).

5.5.5 Chicken and Egg

The Program Key protocol requires both ChipF and ChipP to know K_(old)(either directly or indirectly). Obviously both chips had to beprogrammed in some way with K_(old), and thus K_(old) can be thought ofas an older K_(new):K_(old) can be placed in chips if another ChipFknows K_(older), and so on.

Although this process allows a chain of reprogramming of keys, with eachstage secure, at some stage the very first key (K_(first)) must beplaced in the chips. K_(first) is in fact programmed with the chip'smicrocode at the manufacturing test station as the last step inmanufacturing test. K_(first) can be a manufacturing batch key, changedfor each batch or for each customer etc., and can have as short a lifeas desired. Compromising K_(first) need not result in a completecompromise of the chain of Ks. This is especially true if K_(first) isindirectly stored in ChipPs (i.e. each ChipP holds an f and f(K_(first))instead of K_(first) directly). One example is where K_(first) (the keystored in each chip after manufacture/test) is a batch key, and can bedifferent per chIP. K_(first) may advance to a ComCo specific K_(seond)etc. but still remain indirect. A direct form (e.g. K_(fianal)) onlyneeds to go in if it is actually required at the end of the programmingchain.

Depending on reprogramming requirements, K_(first) can be the same ordifferent for all K_(n).

6 Memjet Forms of Protocols

Physical QA Chips are used in Memjet printer systems to store printeroperating parameters as well as consumable parameters.

6.1 PRINTER_QA

A PRINTER_QA is stored within each print engine to perform two primarytasks:

-   -   storage and protection of operating parameters    -   a means of indirect read validation of other QA Chip data        vectors

Each PRINTER_QA contains the following keys: TABLE 229 Keys in PrinterAKey Contents Comments 0 Upgrade Key Used to upgrade the operatingparameters. Should be indirect form of key (i.e. a different key foreach PRINTER_QA) so that an indirect form of the write is required. 1Consumable Read Used to indirectly read the data from Validation Key anCONSUMABLE_QA chip using indirect authenticated read protocol (Section5.3.2 on page 606). 2 PrintEngineController When reading data from theReadValidation Key PRINTER_QA, the system can either trust the data, ormust use this key to perform the authenticated read protocol (seeSection 5.3 on page 604). 3-n (reserved) Currently unused. Could be usedto provide a means to indirectly read additional print engine operatingparameters ala K1, or provide additional Print Engine validation ala K2.

Note that if multiple Print Engine Controllers are used (e.g. a multipleSoPEC system), then multiple PrintEngineController Read Validation Keysare required. These keys can be stored within a single PRINTER_QA (e.g.in K₃ and beyond), or can be stored in separate PRINTER_QAs (for exampleeach SoPEC (or group of SoPECs) has an individual PRINTER_QA).

The functions required in the PRINTER_QA are:

-   -   Random, ReplaceKey, to allow key programming & substitution    -   Read, to allow reads of data    -   Write, to allow updates of M₁₊ during manufacture    -   WriteAuth, to provide a means of updating the M₀ data (operating        parameters)    -   SetPermissions, to provide a means of updating write permissions    -   Test, to provide a means of checking if consumable reads are        valid    -   Translate, to provide a means of indirect reading of consumable        data        6.2 CONSUMABLE_QA

A CONSUMABLE_QA is stored with each consumable (e.g. ink cartridge) toperform two primary tasks:

-   -   storage of consumable related data    -   protection of consumable amount remaining

Each CONSUMABLE_QA contains the following keys: TABLE 230 Keys inCONSUMABLE_QA Key Contents Comments 0 Upgrade Key Used to upgrade theconsumable parameters. Should be stored as the indirect form of the key(i.e. a different key for each CONSUMABLE_QA) so that an indirect formof the write is required. 1 Consumable Read When reading data from theValidation Key CONSUMABLE_QA, the system can either trust the data, ormust use this key to perform either the direct or indirect authenticatedread protocol (see Section 5.3 on page 604). 2 (reserved) Currentlyunused. 3-n (reserved) Currently unused.

The functions required in the CONSUMABLE_QA are:

-   -   Random, ReplaceKey, to allow key programming & substitution    -   Read, to allow reads of data.    -   Write, to allow updates of M₁₊ during manufacture    -   WriteAuth, to provide a means of updating the M₀ data        (consumable remaining)    -   SetPermissions, to provide a means of updating write permissions        Authentication of Consumables        1 Introduction

Manufacturers of systems that require consumables (such as a laserprinter that requires toner cartridges) have struggled with the problemof authenticating consumables, to varying levels of success. Most haveresorted to specialized packaging that involves a patent. However thisdoes not stop home refill operations or clone manufacture in countrieswith weak industrial property protection. The prevention of copying isimportant to prevent poorly manufactured substitute consumables fromdamaging the base system. For example, poorly filtered ink may clogprint nozzles in an ink jet printer, causing the consumer to blame thesystem manufacturer and not admit the use of non-authorized consumables.

To solve the authentication problem, this document describes an QA Chipthat contains authentication keys and circuitry specially designed toprevent copying. The chip is manufactured using the standard Flashmemory manufacturing process, and is low cost enough to be included inconsumables such as ink and toner cartridges. The implementation isapproximately 1 mm² in a 0.25 micron flash process, and has an expectedmanufacturing cost of approximately 10 cents in 2003.

2 NSA

Once programmed, the QA Chips as described here are compliant with theNSA export guidelines since they do not constitute a strong encryptiondevice. They can therefore be practically manufactured in the USA (andexported) or anywhere else in the world.

3 Nomenclature

The following symbolic nomenclature is used throughout this document:TABLE 231 Summary of symbolic nomenclature Symbol Description F[X]Function F, taking a single parameter X F[X, Y] Function F, taking twoparameters, X and Y X|Y X concatenated with Y X

Y Bitwise X AND Y X

Y Bitwise X OR Y (inclusive-OR) X ⊕ Y Bitwise X XOR Y (exclusive-OR)

X Bitwise NOT X (complement) X

Y X is assigned the value Y X

{Y, Z} The domain of assignment inputs to X is Y and Z X = Y X is equalto Y X ≠ Y X is not equal to Y

X Decrement X by 1 (floor 0)

X Increment X by 1 (modulo register length) Erase X Erase Flash memoryregister X SetBits[X, Y] Set the bits of the Flash memory register Xbased on Y Z

ShiftRight[X, Y] Shift register X right one bit position, taking inputbit from Y and placing the output bit in Z4 Pseudocode4.1.1 Asynchronous

The following pseudocode:

-   -   var=expression        means the var signal or output is equal to the evaluation of the        expression.        4.1.2 Synchronous

The following pseudocode:

-   -   var←expression        means the var register is assigned the result of evaluating the        expression during this cycle.        4.1.3 Expression

Expressions are defined using the nomenclature in Table 231 above.Therefore:

-   -   var=(a=b)        is interpreted as the var signal is 1 if a is equal to b, and 0        otherwise.        4.2 Diagrams

Black is used to denote data, and red to denote 1-bit control-signallines.

4.3 QA Chip Terminology

This document refers to QA Chips by their function in particularprotocols:

-   -   For authenticated reads, ChipA is the QA Chip being        authenticated, and ChipT is the QA Chip that is trusted.    -   For replacement of keys, ChipP is the QA Chip being programmed        with the new key, and ChipF is the factory QA Chip that        generates the message to program the new key.    -   For upgrades of data in a QA Chip, ChipU is the QA Chip being        upgraded, and ChipS is the QA Chip that signs the upgrade value.

Any given physical QA Chip will contain functionality that allows it tooperate as an entity in some number of these protocols.

Therefore, wherever the terms ChipA, ChipT, ChipP, ChipF, ChipU andChipS are used in this document, they are referring to logical entitiesinvolved in an authentication protocol as defined in subsequentsections.

Physical QA Chips are referred to by their location. For example, eachink cartridge may contain a QA Chip referred to as an INK_QA, with allINK_QA chips being on the same physical bus. In the same way, the QAChip inside a printer is referred to as PRINTER_QA, and will be on aseparate bus to the INK_QA chips.

5 Concepts and Terms

This chapter provides a background to the problem of authenticatingconsumables. For more in-depth introductory texts, see [12], [78], and[56].

5.1 Basic Terms

A message, denoted by M, is plaintext. The process of transforming Minto ciphertext C, where the substance of M is hidden, is calledencryption. The process of transforming C back into M is calleddecryption. Referring to the encryption function as E, and thedecryption function as D, we have the following identities:E[M]=CD[C]=M

Therefore the following identity is true:D[E[M]]=M5.2 Symmetric Cryptography

A symmetric encryption algorithm is one where:

-   -   the encryption function E relies on key K₁,    -   the decryption function D relies on key K₂,    -   K₂ can be derived from K₁, and    -   K₁ can be derived from K₂.

In most symmetric algorithms, K₁ equals K₂. However, even if K₁ does notequal K₂, given that one key can be derived from the other, a single keyK can suffice for the mathematical definition. Thus:E_(K)[M]=CD_(K)[C]=M

The security of these algorithms rests very much in the key K. Knowledgeof K allows anyone to encrypt or decrypt. Consequently K must remain asecret for the duration of the value of M. For example, M may be awartime message “My current position is grid position 123-456”. Once thewar is over the value of M is greatly reduced, and if K is made public,the knowledge of the combat unit's position may be of no relevancewhatsoever. Of course if it is politically sensitive for the combatunit's position to be known even after the war, K may have to remainsecret for a very long time.

An enormous variety of symmetric algorithms exist, from the textbooks ofancient history through to sophisticated modern algorithms. Many ofthese are insecure, in that modern cryptanalysis techniques (see Section5.7 on page 646) can successfully attack the algorithm to the extentthat K can be derived.

The security of the particular symmetric algorithm is a function of twothings: the strength of the algorithm and the length of the key [78].

The strength of an algorithm is difficult to quantify, relying on itsresistance to cryptographic attacks (see Section 5.7 on page 646). Inaddition, the longer that an algorithm has remained in the public eye,and yet remained unbroken in the midst of intense scrutiny, the moresecure the algorithm is likely to be. By contrast, a secret algorithmthat has not been scrutinized by cryptographic experts is unlikely to besecure.

Even if the algorithm is “perfectly” strong (the only way to break it isto try every key—see Section 5.7.1.5 on page 647), eventually the rightkey will be found. However, the more keys there are, the more keys haveto be tried. If there are N keys, it will take a maximum of N tries. Ifthe key is N bits long, it will take a maximum of 2^(N) tries, with a50% chance of finding the key after only half the attempts (2^(N−1)).The longer N becomes, the longer it will take to find the key, and hencethe more secure it is. What makes a good key length depends on the valueof the secret and the time for which the secret must remain secret aswell as available computing resources.

In 1996, an ad hoc group of world-renowned cryptographers and computerscientists released a report [9] describing minimal key lengths forsymmetric ciphers to provide adequate commercial security. They suggestan absolute minimum key length of 90 bits in order to protect data for20 years, and stress that increasingly, as cryptosystems succumb tosmarter attacks than brute-force key search, even more bits may berequired to account for future surprises in cryptanalysis techniques.

We will ignore most historical symmetric algorithms on the grounds thatthey are insecure, especially given modern computing technology.Instead, we will discuss the following algorithms:

-   -   DES    -   Blowfish    -   RC5    -   IDEA        5.2.1 DES

DES (Data Encryption Standard) [26] is a US and international standard,where the same key is used to encrypt and decrypt. The key length is 56bits. It has been implemented in hardware and software, although theoriginal design was for hardware only. The original algorithm used inDES was patented in 1976 (U.S. Pat. No. 3,962,539) and has sinceexpired.

During the design of DES, the NSA (National Security Agency) providedsecret S-boxes to perform the key-dependent nonlinear transformations ofthe data block. After differential cryptanalysis was discovered outsidethe NSA, it was revealed that the DES S-boxes were specifically designedto be resistant to differential cryptanalysis.

As described in [95], using 1993 technology, a 56-bit DES key can berecovered by a custom-designed $1 million machine performing a bruteforce attack in only 35 minutes. For $10 million, the key can berecovered in only 3.5 minutes. DES is clearly not secure now, and willbecome less so in the future.

A variant of DES, called triple-DES is more secure, but requires 3 keys:K₁, K₂, and K₃. The keys are used in the following manner:E_(K3) [D_(K2)[E_(K1)[M]]]=CD_(K3)[E_(K2)[D_(K1[C]]]=M)

The main advantage of triple-DES is that existing DES implementationscan be used to give more security than single key DES. Specifically,triple-DES gives protection of equivalent key length of 112 bits [78].Triple-DES does not give the equivalent protection of a 168-bit key(3×56) as one might naively expect.

Equipment that performs triple-DES decoding and/or encoding cannot beexported from the United States.

5.2.2 Blowfish

Blowfish is a symmetric block cipher first presented by Schneier in 1994[76]. It takes a variable length key, from 32 bits to 448 bits, isunpatented, and is both license and royalty free. In addition, it ismuch faster than DES.

The Blowfish algorithm consists of two parts: a key-expansion part and adata-encryption part. Key expansion converts a key of at most 448 bitsinto several subkey arrays totaling 4168 bytes. Data encryption occursvia a 16-round Feistel network. All operations are XORs and additions on32-bit words, with four index array lookups per round.

It should be noted that decryption is the same as encryption except thatthe subkey arrays are used in the reverse order. Complexity ofimplementation is therefore reduced compared to other algorithms that donot have such symmetry.

[77] describes the published attacks which have been mounted onBlowfish, although the algorithm remains secure as of February 1998[79]. The major finding with these attacks has been the discovery ofcertain weak keys. These weak keys can be tested for during keygeneration. For more information, refer to [77] and [79].

5.2.3 RC5

Designed by Ron Rivest in 1995, RC5 [74] has a variable block size, keysize, and number of rounds. Typically, however, it uses a 64-bit blocksize and a 128-bit key.

The RC5 algorithm consists of two parts: a key-expansion part and adata-encryption part. Key expansion converts a key into 2r+2 subkeys(where r=the number of rounds), each subkey being w bits. For a 64-bitblocksize with 16 rounds (w=32, r=16), the subkey arrays total 136bytes. Data encryption uses addition mod 2^(W), XOR and bitwiserotation.

An initial examination by Kaliski and Yin [43] suggested that standardlinear and differential cryptanalysis appeared impractical for the64-bit blocksize version of the algorithm. Their differential attacks on9 and 12 round RC5 require 2⁴⁵ and 2⁶² chosen plaintexts respectively,while the linear attacks on 4, 5, and 6 round RC5 requires 2³⁷, 2⁴⁷ and2⁵⁷ known plaintexts). These two attacks are independent of key size.

More recently however, Knudsen and Meier [47] described a new type ofdifferential attack on RC5 that improved the earlier results by a factorof 128, showing that RC5 has certain weak keys.

RC5 is protected by multiple patents owned by RSA Laboratories. Alicense must be obtained to use it.

5.2.4 IDEA

Developed in 1990 by Lai and Massey [53], the first incarnation of theIDEA cipher was called PES. After differential cryptanalysis wasdiscovered by Biham and Shamir in 1991, the algorithm was strengthened,with the result being published in 1992 as IDEA [52].

IDEA uses 128-bit keys to operate on 64-bit plaintext blocks. The samealgorithm is used for encryption and decryption. It is generallyregarded as the most secure block algorithm available today [78][78].

The biggest drawback of IDEA is the fact that it is patented (U.S. Pat.No. 5,214,703, issued in 1993), and a license must be obtained fromAscom Tech AG (Bern) to use it.

5.3 Asymmetric Cryptography

An asymmetric encryption algorithm is one where:

-   -   the encryption function E relies on key K₁,    -   the decryption function D relies on key K₂,    -   K₂ cannot be derived from K₁ in a reasonable amount of time, and    -   K₁ cannot be derived from K₂ in a reasonable amount of time.

Thus:E_(K1)[M]=CD_(K2)[C]=M

These algorithms are also called public-key because one key K₁ can bemade public. Thus anyone can encrypt a message (using K₁) but only theperson with the corresponding decryption key (K₂) can decrypt and thusread the message.

In most cases, the following identity also holds:E_(K2)[M]=CD_(K1)[C]=M

This identity is very important because it implies that anyone with thepublic key K₁ can see M and know that it came from the owner of K₂.No-one else could have generated C because to do so would implyknowledge of K₂. This gives rise to a different application, unrelatedto encryption—digital signatures.

The property of not being able to derive K₁ from K₂ and vice versa in areasonable time is of course clouded by the concept of reasonable time.What has been demonstrated time after time, is that a calculation thatwas thought to require a long time has been made possible by theintroduction of faster computers, new algorithms etc. The security ofasymmetric algorithms is based on the difficulty of one of two problems:factoring large numbers (more specifically large numbers that are theproduct of two large primes), and the difficulty of calculating discretelogarithms in a finite field. Factoring large numbers is conjectured tobe a hard problem given today's understanding of mathematics. Theproblem however, is that factoring is getting easier much faster thananticipated. Ron Rivest in 1977 said that factoring a 125-digit numberwould take 40 quadrillion years [30]. In 1994 a 129-digit number wasfactored (3]. According to Schneier, you need a 1024-bit number to getthe level of security today that you got from a 512-bit number in the1980s [78]. If the key is to last for some years then 1024 bits may noteven be enough. Rivest revised his key length estimates in 1990: hesuggests 1628 bits for high security lasting until 2005, and 1884 bitsfor high security lasting until 2015 [69]. Schneier suggests 2048 bitsare required in order to protect against corporations and governmentsuntil 2015 [80].

Public key cryptography was invented in 1976 by Diffie and Hellman[15][15], and independently by Merkle [57]. Although Diffie, Hellman andMerkle patented the concepts (U.S. Pat. Nos. 4,200,770 and 4,218,582),these patents expired in 1997.

A number of public key cryptographic algorithms exist. Most areimpractical to implement, and many generate a very large C for a given Mor require enormous keys. Still others, while secure, are far too slowto be practical for several years. Because of this, many public keysystems are hybrid—a public key mechanism is used to transmit asymmetric session key, and then the session key is used for the actualmessages.

All of the algorithms have a problem in terms of key selection. A randomnumber is simply not secure enough. The two large primes p and q must bechosen carefully—there are certain weak combinations that can befactored more easily (some of the weak keys can be tested for). Butnonetheless, key selection is not a simple matter of randomly selecting1024 bits for example. Consequently the key selection process must alsobe secure.

Of the practical algorithms in use under public scrutiny, the followingare discussed:

-   -   RSA    -   DSA    -   EIGamal        5.3.1 RSA

The RSA cryptosystem [75], named after Rivest, Shamir, and Adleman, isthe most widely used public key cryptosystem, and is a de facto standardin much of the world [78].

The security of RSA depends on the conjectured difficulty of factoringlarge numbers that are the product of two primes (p and q). There are anumber of restrictions on the generation of p and q. They should both belarge, with a similar number of bits, yet not be close to one another(otherwise p≡q≡√pq). In addition, many authors have suggested that p andq should be strong primes [56]. The Hellman-Bach patent (U.S. Pat. No.4,633,036) covers a method for generating strong RSA primes p and q suchthat n=pq and factoring n is believed to be computationally infeasible.The RSA algorithm patent was issued in 1983 (U.S. Pat. No. 4,405,829).The patent expires on Sep. 20, 2000.

5.3.2 DSA

DSA (Digital Signature Algorithm) is an algorithm designed as part ofthe Digital Signature Standard (DSS) [29]. As defined, it cannot be usedfor generalized encryption. In addition, compared to RSA, DSA is 10 to40 times slower for signature verification [40]. DSA explicitly uses theSHA-1 hashing algorithm (see Section 5.5.3.3 on page 640).

DSA key generation relies on finding two primes p and q such that qdivides p−1. According to Schneier [78], a 1024-bit p value is requiredfor long term DSA security. However the DSA standard [29] does notpermit values of p larger than 1024 bits (p must also be a multiple of64 bits).

The US Government owns the DSA algorithm and has at least one relevantpatent (U.S. Pat. No. 5,231,688 granted in 1993). However, according toNIST [61]:

-   -   “The DSA patent and any foreign counterparts that may issue are        available for use without any written permission from or any        payment of royalties to the U.S. government.”

In a much stronger declaration, NIST states in the same document [61]that DSA does not infringe third party's rights:

-   -   “NIST reviewed all of the asserted patents and concluded that        none of them would be infringed by DSS. Extra protection will be        written into the PK1 pilot project that will prevent an        organization or individual from suing anyone except the        government for patent infringement during the course of the        project.”

It must however, be noted that the Schnorr authentication algorithm [81](U.S. Pat. No. 4,995,082) patent holder claims that DSA infringes hispatent. The Schnorr patent is not due to expire until 2008.

5.3.3 EIGamal

The EIGamal scheme [22][22] is used for both encryption and digitalsignatures. The security is based on the conjectured difficulty ofcalculating discrete logarithms in a finite field.

Key selection involves the selection of a prime p, and two randomnumbers g and x such that both g and x are less than p. Then calculatey=gx mod p. The public key is y, g, and p. The private key is x.

EIGamal is unpatented. Although it uses the patented Diffie-Hellmanpublic key algorithm [15][15], those patents expired in 1997. EIGamalpublic key encryption and digital signatures can now be safely usedwithout infringing third party patents.

5.4 Cryptographic Challenge-Response Protocols and Zero Knowledge Proofs

The general principle of a challenge-response protocol is to provideidentity authentication. The simplest form of challenge-response takesthe form of a secret password. A asks B for the secret password, and ifB responds with the correct password, A declares B authentic.

There are three main problems with this kind of simplistic protocol.Firstly, once B has responded with the password, any observer C willknow what the password is. Secondly, A must know the password in orderto verify it. Thirdly, if C impersonates A, then B will give thepassword to C (thinking C was A), thus compromising the password.

Using a copyright text (such as a haiku) as the password is notsufficient, because we are assuming that anyone is able to copy thepassword (for example in a country where intellectual property is notrespected).

The idea of cryptographic challenge-response protocols is that oneentity (the claimant) proves its identity to another (the verifier) bydemonstrating knowledge of a secret known to be associated with thatentity, without revealing the secret itself to the verifier during theprotocol [56]. In the generalized case of cryptographicchallenge-response protocols, with some schemes the verifier knows thesecret, while in others the secret is not even known by the verifier. Agood overview of these protocols can be found in [25], [78], and [56].

Since this documentation specifically concerns Authentication, theactual cryptographic challenge-response protocols used forauthentication are detailed in the appropriate sections. However theconcept of Zero Knowledge Proofs bears mentioning here.

The Zero Knowledge Proof protocol, first described by Feige, Fiat andShamir in [24] is extensively used in Smart Cards for the purpose ofauthentication [34][34][34]. The protocol's effectiveness is based onthe assumption that it is computationally infeasible to compute squareroots modulo a large composite integer with unknown factorization. Thisis provably equivalent to the assumption that factoring large integersis difficult.

It should be noted that there is no need for the claimant to havesignificant computing power. Smart cards implement this kind ofauthentication using only a few modulo multiplications [34][34].

Finally, it should be noted that the Zero Knowledge Proof protocol ispatented [82] (U.S. Pat. No. 4,748,668, issued May 31, 1988).

5.5 One-Way Functions

A one-way function F operates on an input X, and returns F[X] such thatX cannot be determined from F[X]. When there is no restriction on theformat of X, and F[X] contains fewer bits than X, then collisions mustexist. A collision is defined as two different X input values producingthe same F[X] value—i.e. X₁ and X₂ exist such that X₁≠X₂ yetF[X₁]=F[X₂].

When X contains more bits than F[X], the input must be compressed insome way to create the output. In many cases, X is broken into blocks ofa particular size, and compressed over a number of rounds, with theoutput of one round being the input to the next. The output of the hashfunction is the last output once X has been consumed. A pseudo-collisionof the compression function CF is defined as two different initialvalues V₁ and V₂ and two inputs X₁ and X₂ (possibly identical) are givensuch that CF(V₁, X₁)=CF(V₂, X₂). Note that the existence of apseudo-collision does not mean that it is easy to compute an X₂ for agiven X₁.

We are only interested in one-way functions that are fast to compute. Inaddition, we are only interested in deterministic one-way functions thatare repeatable in different implementations.

Consider an example F where F[X] is the time between calls to F. For agiven F(X] X cannot be determined because X is not even used by F.However the output from F will be different for differentimplementations. This kind of F is therefore not of interest.

In the scope of this document, we are interested in the following formsof one-way functions:

-   -   Encryption using an unknown key    -   Random number sequences    -   Hash Functions    -   Message Authentication Codes        5.5.1 Encryption Using an Unknown Key

When a message is encrypted using an unknown key K₁ the encryptionfunction E is effectively one-way. Without the key, it iscomputationally infeasible to obtain M from EK[M] without K. Anencryption function is only one-way for as long as the key remainshidden.

An encryption algorithm does not create collisions, since E createsEK[M] such that it is possible to reconstruct M using function D.Consequently F[X] contains at least as many bits as X (no information islost) if the one-way function F is E.

Symmetric encryption algorithms (see Section 5.2 on page 629) have theadvantage over asymmetric algorithms (see Section 5.3 on page 632) forproducing one-way functions based on encryption for the followingreasons:

-   -   The key for a given strength encryption algorithm is shorter for        a symmetric algorithm than an asymmetric algorithm    -   Symmetric algorithms are faster to compute and require less        software or silicon

Note however, that the selection of a good key depends on the encryptionalgorithm chosen. Certain keys are not strong for particular encryptionalgorithms, so any key needs to be tested for strength. The more teststhat need to be performed for key selection, the less likely the keywill remain hidden.

5.5.2 Random Number Sequences

Consider a random number sequence R₀, R₁, . . . , R_(i), R_(i+1). Wedefine the one-way function F such that F[X] returns the X^(th) randomnumber in the random sequence. However we must ensure that F[X] isrepeatable for a given X on different implementations. The random numbersequence therefore cannot be truly random. Instead, it must bepseudo-random, with the generator making use of a specific seed.

There are a large number of issues concerned with defining good randomnumber generators. Knuth, in [48] describes what makes a generator“good” (including statistical tests), and the general problemsassociated with constructing them. Moreau gives a high level survey ofthe current state of the field in [60].

The majority of random number generators produce the i^(th) randomnumber from the i−1 ^(th) state—the only way to determine the i^(th)number is to iterate from the 0^(th) number to the i^(th). If i islarge, it may not be practical to wait for i iterations.

However there is a type of random number generator that does allowrandom access. In [10], Blum, Blum and Shub define the ideal generatoras follows: “ . . . we would like a pseudo-random sequence generator toquickly produce, from short seeds, long sequences (of bits) that appearin every way to be generated by successive flips of a fair coin”. Theydefined the x² mod n generator [10], more commonly referred to as theBBS generator. They showed that given certain assumptions upon whichmodern cryptography relies, a BBS generator passes extremely stringentstatistical tests.

The BBS generator relies on selecting n which is a Blum integer (n=pqwhere p and q are large prime numbers, p≠q, p mod 4=3, and q mod 4=3).The initial state of the generator is given by x₀ where x₀=x² mod n, andx is a random integer relatively prime to n. The i^(th) pseudo-randombit is the least significant bit of x_(i) where:x _(i) =x _(i−1) ² mod n

As an extra property, knowledge of p and q allows a direct calculationof the i^(th) number in the sequence as follows:x _(i) =x ₀ ^(y) mod n where y=2^(i) mod((p−1)(q−1))

Without knowledge of p and q, the generator must iterate (the securityof calculation relies on the conjectured difficulty of factoring largenumbers).

When first defined, the primary problem with the BBS generator was theamount of work required for a single output bit. The algorithm wasconsidered too slow for most applications. However the advent ofMontgomery reduction arithmetic [58] has given rise to more practicalimplementations, such as [59]. In addition, Vazirani and Vazirani haveshown in [93] that depending on the size of n, more bits can safely betaken from x_(i) without compromising the security of the generator.

Assuming we only take 1 bit per x_(i), N bits (and hence N iterations ofthe bit generator function) are needed in order to generate an N-bitrandom number. To the outside observer, given a particular set of bits,there is no way to determine the next bit other than a 50/50probability. If the x, p and q are hidden, they act as a key, and it iscomputationally infeasible to take an output bit stream and compute x,p, and q. It is also computationally infeasible to determine the valueof i used to generate a given set of pseudo-random bits. This lastfeature makes the generator one-way.

Different values of i can produce identical bit sequences of a givenlength (e.g. 32 bits of random bits). Even if x, p and q are known, fora given F[i], i can only be derived as a set of possibilities, not as acertain value (of course if the domain of i is known, then the set ofpossibilities is reduced further).

However, there are problems in selecting a good p and q, and a good seedx. In particular, Ritter in [68] describes a problem in selecting x. Thenature of the problem is that a BBS generator does not create a singlecycle of known length. Instead, it creates cycles of various lengths,including degenerate (zero-length) cycles. Thus a BBS generator cannotbe initialized with a random state—it might be on a short cycle.Specific algorithms exist in section 9 of [10] to determine the lengthof the period for a given seed given certain strenuous conditions for n.

5.5.3 Hash Functions

Special one-way functions, known as Hash functions, map arbitrary lengthmessages to fixed-length hash values. Hash functions are referred to asH[M]. Since the input is of arbitrary length, a hash function has acompression component in order to produce a fixed length output. Hashfunctions also have an obfuscation component in order to make itdifficult to find collisions and to determine information about M fromH[M].

Because collisions do exist, most applications require that the hashalgorithm is preimage resistant, in that for a given X₁ it is difficultto find X₂ such that H[X₁]=H[X₂]. In addition, most applications alsorequire the hash algorithm to be collision resistant (i.e. it should behard to find two messages X₁ and X₂ such that H[X₁]=H[X₂]). However, asdescribed in [20], it is an open problem whether a collision-resistanthash function, in the ideal sense, can exist at all.

The primary application for hash functions is in the reduction of aninput message into a digital “fingerprint” before the application of adigital signature algorithm. One problem of collisions with digitalsignatures can be seen in the following example.

-   -   A has a long message M₁ that says “I owe B $10”. A signs H[M₁]        using his private key. B, being greedy, then searches for a        collision message M₂ where H[M₂]=H[M₁] but where M₂ is favorable        to B, for example “I owe B $1 million”. Clearly it is in A's        interest to ensure that it is difficult to find such an M₂.

Examples of collision resistant one-way hash functions are SHA-1 [28],MD5 [73] and RIPEMD-160 [66], all derived from MD4 [70][70].

5.5.3.1 MD4

Ron Rivest introduced MD4 [70][70] in 1990. It is only mentioned herebecause all other one-way hash functions are derived in some way fromMD4.

MD4 is now considered completely broken [18][18] in that collisions canbe calculated instead of searched for. In the example above, B couldtrivially generate a substitute message M₂ with the same hash value asthe original message M₁.

5.5.3.2 MD5

Ron Rivest introduced MD5 [73] in 1991 as a more secure MD4. Like MD4,MD5 produces a 128-bit hash value. MD5 is not patented [80].

Dobbertin describes the status of MD5 after recent attacks [20]. Hedescribes how pseudo-collisions have been found in MD5, indicating aweakness in the compression function, and more recently, collisions havebeen found. This means that MD5 should not be used for compression indigital signature schemes where the existence of collisions may havedire consequences. However MD5 can still be used as a one-way function.In addition, the HMAC-MD5 construct (see Section 5.5.4.1 on page 643) isnot affected by these recent attacks.

5.5.3.3 SHA-1

SHA-1 [28] is very similar to MD5, but has a 160-bit hash value (MD5only has 128 bits of hash value). SHA-1 was designed and introduced bythe NIST and NSA for use in the Digital Signature Standard (DSS). Theoriginal published description was called SHA [27], but very soonafterwards, was revised to become SHA-1 [28], supposedly to correct asecurity flaw in SHA (although the NSA has not released the mathematicalreasoning behind the change).

There are no known cryptographic attacks against SHA-1 [78]. It is alsomore resistant to brute force attacks than MD4 or MD5 simply because ofthe longer hash result.

The US Government owns the SHA-1 and DSA algorithms (a digital signatureauthentication algorithm defined as part of DSS [29]) and has at leastone relevant patent (U.S. Pat. No. 5,231,688 granted in 1993). However,according to NIST [61]:

-   -   “The DSA patent and any foreign counterparts that may issue are        available for use without any written permission from or any        payment of royalties to the U.S. government.”

In a much stronger declaration, NIST states in the same document [61]that DSA and SHA-1 do not infringe third party's rights:

-   -   “NIST reviewed all of the asserted patents and concluded that        none of them would be infringed by DSS. Extra protection will be        written into the PK1 pilot project that will prevent an        organization or individual from suing anyone except the        government for patent infringement during the course of the        project.”

It must however, be noted that the Schnorr authentication algorithm [81](U.S. Pat. No. 4,995,082) patent holder claims that DSA infringes hispatent. The Schnorr patent is not due to expire until 2008. Fortunatelythis does not affect SHA-1.

5.5.3.4 RIPEMD-160

RIPEMD-160 [66] is a hash function derived from its predecessor RIPEMD[11] (developed for the European Community's RIPE project in 1992). Asits name suggests, RIPEMD-160 produces a 160-bit hash result. Tuned forsoftware implementations on 32-bit architectures, RIPEMD-160 is intendedto provide a high level of security for 10 years or more.

Although there have been no successful attacks on RIPEMD-160, it iscomparatively new and has not been extensively cryptanalyzed. Theoriginal RIPEMD algorithm [11] was specifically designed to resist knowncryptographic attacks on MD4. The recent attacks on MD5 (detailed in[20]) showed similar weaknesses in the RIPEMD 128-bit hash function.Although the attacks showed only theoretical weaknesses, Dobbertin,Preneel and Bosselaers further strengthened RIPEMD into a new algorithmRIPEMD-160.

RIPEMD-160 is in the public domain, and requires no licensing or royaltypayments.

5.5.4 Message Authentication Codes

The problem of message authentication can be summed up as follows:

-   -   How can A be sure that a message supposedly from B is in fact        from B?

Message authentication is different from entity authentication(described in the section on cryptographic challenge-responseprotocols). With entity authentication, one entity (the claimant) provesits identity to another (the verifier). With message authentication, weare concerned with making sure that a given message is from who we thinkit is from i.e. it has not been tampered with en route from the sourceto its destination. While this section has a brief overview of messageauthentication, a more detailed survey can be found in [88].

A one-way hash function is not sufficient protection for a message. Hashfunctions such as MD5 rely on generating a hash value that isrepresentative of the original input, and the original input cannot bederived from the hash value. A simple attack by E, who is in-between Aand B, is to intercept the message from B, and substitute his own. Evenif A also sends a hash of the original message, E can simply substitutethe hash of his new message. Using a one-way hash function alone, A hasno way of knowing that B's message has been changed.

One solution to the problem of message authentication is the MessageAuthentication Code, or MAC.

When B sends message M, it also sends MAC(M] so that the receiver willknow that M is actually from B. For this to be possible, only B must beable to produce a MAC of M, and in addition, A should be able to verifyM against MAC[M]. Notice that this is different from encryption ofM−MACs are useful when M does not have to be secret.

The simplest method of constructing a MAC from a hash function is toencrypt the hash value with a symmetric algorithm:

-   1. Hash the input message H[M]-   2. Encrypt the hash E_(K)[H[M]]

This is more secure than first encrypting the message and then hashingthe encrypted message. Any symmetric or asymmetric cryptographicfunction can be used, with the appropriate advantages and disadvantageof each type described in Section 5.2 on page 629 and Section 5.3 onpage 632.

However, there are advantages to using a key-dependent one-way hashfunction instead of techniques that use encryption (such as that shownabove):

-   -   Speed, because one-way hash functions in general work much        faster than encryption;    -   Message size, because EK[M] is at least the same size as M,        while H[M] is a fixed size (usually considerably smaller than        M);    -   Hardware/software requirements—keyed one-way hash functions are        typically far less complex than their encryption-based        counterparts; and    -   One-way hash function implementations are not considered to be        encryption or decryption devices and therefore are not subject        to US export controls.

It should be noted that hash functions were never originally designed tocontain a key or to support message authentication. As a result, some adhoc methods of using hash functions to perform message authentication,including various functions that concatenate messages with secretprefixes, suffixes, or both have been proposed [56][56]. Most of thesead hoc methods have been successfully attacked by sophisticated means[42][42][42]. Additional MACs have been suggested based on XOR schemes[8] and Toeplitz matrices [49] (including the special case of LFSR-based(Linear Feed Shift Register) constructions).

5.5.4.1 HMAC

The HMAC construction [6][6] in particular is gaining acceptance as asolution for Internet message authentication security protocols. TheHMAC construction acts as a wrapper, using the underlying hash functionin a black-box way. Replacement of the hash function is straightforwardif desired due to security or performance reasons. However, the majoradvantage of the HMAC construct is that it can be proven secure providedthe underlying hash function has some reasonable cryptographicstrengths—that is, HMAC's strengths are directly connected to thestrength of the hash function [6].

Since the HMAC construct is a wrapper, any iterative hash function canbe used in an HMAC. Examples include HMAC-MD5, HMAC-SHA1, HMAC-RIPEMD160etc.

Given the following definitions: H = the hash function (e.g. MD5 orSHA-1) n = number of bits output from H (e.g. 160 for SHA-1, 128 bitsfor MD5) M = the data to which the MAC function is to be applied K = thesecret key shared by the two parties ipad = 0x36 repeated 64 times opad= 0x5C repeated 64 times

The HMAC algorithm is as follows:

-   1. Extend K to 64 bytes by appending 0x00 bytes to the end of K-   2. XOR the 64 byte string created in (1) with ipad-   3. append data stream M to the 64 byte string created in (2)-   4. Apply H to the stream generated in (3)-   5. XOR the 64 byte string created in (1) with opad-   6. Append the H result from (4) to the 64 byte string resulting from    (5)-   7. Apply H to the output of (6) and output the result

Thus:HMAC[M]=H[(K ⊕ opad)|H[(K ⊕ ipad)|M]]

The recommended key length is at least n bits, although it should not belonger than 64 bytes (the length of the hashing block). A key longerthan n bits does not add to the security of the function.

HMAC optionally allows truncation of the final output e.g. truncation to128 bits from 160 bits.

The HMAC designers' Request for Comments [51] was issued in 1997, oneyear after the algorithm was first introduced. The designers claimedthat the strongest known attack against HMAC is based on the frequencyof collisions for the hash function H (see Section 14.10 on page 700),and is totally impractical for minimally reasonable hash functions:

-   -   As an example, if we consider a hash function like MD5 where the        output length is 128 bits, the attacker needs to acquire the        correct message authentication tags computed (with the same        secret key K) on about 2⁶⁴ known plaintexts. This would require        the processing of at least 2⁶⁴ blocks under H, an impossible        task in any realistic scenario (for a block length of 64 bytes        this would take 250,000 years in a continuous 1 Gbps link, and        without changing the secret key K all this time). This attack        could become realistic only if serious flaws in the collision        behavior of the function H are discovered (e.g. Collisions found        after 2³⁰ messages). Such a discovery would determine the        immediate replacement of function H (the effects of such a        failure would be far more severe for the traditional uses of H        in the context of digital signatures, public key certificates        etc).

Of course, if a 160-bit hash function is used, then 2⁶⁴ should bereplaced with 2⁸⁰.

This should be contrasted with a regular collision attack oncryptographic hash functions where no secret key is involved and 2⁶⁴off-line parallelizable operations suffice to find collisions.

More recently, HMAC protocols with replay prevention components [62]have been defined in order to prevent the capture and replay of any M,HMAC[M] combination within a given time period.

Finally, it should be noted that HMAC is in the public domain [50], andincurs no licensing fees. There are no known patents infringed by HMAC.

5.6 Random Numbers and Time Varying Messages

The use of a random number generator as a one-way function has alreadybeen examined. However, random number generator theory is very muchintertwined with cryptography, security, and authentication.

There are a large number of issues concerned with defining good randomnumber generators. Knuth, in [48] describes what makes a generator good(including statistical tests), and the general problems associated withconstructing them. Moreau gives a high level survey of the current stateof the field in [60].

One of the uses for random numbers is to ensure that messages vary overtime. Consider a system where A encrypts commands and sends them to B.If the encryption algorithm produces the same output for a given input,an attacker could simply record the messages and play them back to foolB. There is no need for the attacker to crack the encryption mechanismother than to know which message to play to B (while pretending to beA). Consequently messages often include a random number and a time stampto ensure that the message (and hence its encrypted counterpart) varieseach time.

Random number generators are also often used to generate keys. AlthoughKlapper has recently shown [45] that a family of secure feedbackregisters for the purposes of building key-streams does exist, he doesnot give any practical construction. It is therefore best to say at themoment that all generators are insecure for this purpose. For example,the Berlekamp-Massey algorithm [54], is a classic attack on an LFSRrandom number generator. If the LFSR is of length n, then only 2n bitsof the sequence suffice to determine the LFSR, compromising the keygenerator.

If, however, the only role of the random number generator is to makesure that messages vary over time, the security of the generator andseed is not as important as it is for session key generation. Ifhowever, the random number seed generator is compromised, and anattacker is able to calculate future “random” numbers, it can leave someprotocols open to attack. Any new protocol should be examined withrespect to this situation.

The actual type of random number generator required will depend upon theimplementation and the purposes for which the generator is used.Generators include Blum, Blum, and Shub [10], stream ciphers such as RC4by Ron Rivest [71], hash functions such as SHA-1 [28] and RIPEMD-160[66], and traditional generators such LFSRs (Linear Feedback ShiftRegisters) [48] and their more recent counterpart FCSRs (Feedback withCarry Shift Registers) [44].

5.7 Attacks

This section describes the various types of attacks that can beundertaken to break an authentication cryptosystem. The attacks aregrouped into physical and logical attacks.

Logical attacks work on the protocols or algorithms rather than theirphysical implementation, and attempt to do one of three things:

-   -   Bypass the authentication process altogether    -   Obtain the secret key by force or deduction, so that any        question can be answered    -   Find enough about the nature of the authenticating questions and        answers in order to, without the key, give the right answer to        each question.

Regardless of the algorithms and protocol used by a security chip, thecircuitry of the authentication part of the chip can come under physicalattack. Physical attacks come in four main ways, although the form ofthe attack can vary:

-   -   Bypassing the security chip altogether    -   Physical examination of the chip while in operation (destructive        and non-destructive)    -   Physical decomposition of chip    -   Physical alteration of chip

The attack styles and the forms they take are detailed below.

This section does not suggest solutions to these attacks. It merelydescribes each attack type. The examination is restricted to the contextof an authentication chip (as opposed to some other kind of system, suchas Internet authentication) attached to some System.

5.7.1 Logical Attacks

These attacks are those which do not depend on the physicalimplementation of the cryptosystem. They work against the protocols andthe security of the algorithms and random number generators.

5.7.1.1 Ciphertext Only Attack

This is where an attacker has one or more encrypted messages, allencrypted using the same algorithm. The aim of the attacker is to obtainthe plaintext messages from the encrypted messages. Ideally, the key canbe recovered so that all messages in the future can also be recovered.

5.7.1.2 Known Plaintext Attack

This is where an attacker has both the plaintext and the encrypted formof the plaintext. In the case of an authentication chip, aknown-plaintext attack is one where the attacker can see the data flowbetween the system and the authentication chIP. The inputs and outputsare observed (not chosen by the attacker), and can be analyzed forweaknesses (such as birthday attacks or by a search for differentiallyinteresting input/output pairs).

A known plaintext attack can be carried out by connecting a logicanalyzer to the connection between the system and the authenticationchIP.

5.7.1.3 Chosen Plaintext Attacks

A chosen plaintext attack describes one where a cryptanalyst has theability to send any chosen message to the cryptosystem, and observe theresponse. If the cryptanalyst knows the algorithm, there may be arelationship between inputs and outputs that can be exploited by feedinga specific output to the input of another function.

The chosen plaintext attack is much stronger than the known plaintextattack since the attacker can choose the messages rather than simplyobserve the data flow.

On a system using an embedded authentication chip, it is generally verydifficult to prevent chosen plaintext attacks since the cryptanalyst canlogically pretend he/she is the system, and thus send any chosenbit-pattern streams to the authentication chIP.

5.7.1.4 Adaptive Chosen Plaintext Attacks

This type of attack is similar to the chosen plaintext attacks exceptthat the attacker has the added ability to modify subsequent chosenplaintexts based upon the results of previous experiments. This iscertainly the case with any system/authentication chip scenariodescribed for consumables such as photocopiers and toner cartridges,especially since both systems and consumables are made available to thepublic.

5.7.1.5 Brute Force Attack

A guaranteed way to break any key-based cryptosystem algorithm is simplyto try every key.

Eventually the right one will be found. This is known as a brute forceattack. However, the more key possibilities there are, the more keysmust be tried, and hence the longer it takes (on average) to find theright one. If there are N keys, it will take a maximum of N tries. Ifthe key is N bits long, it will take a maximum of 2^(N) tries, with a50% chance of finding the key after only half the attempts (2^(N−1)).The longer N becomes, the longer it will take to find the key, and hencethe more secure the key is. Of course, an attack may guess the key onthe first try, but this is more unlikely the longer the key is.

Consider a key length of 56 bits. In the worst case, all 2⁵⁶ tests(7.2×10¹⁶ tests) must be made to find the key. In 1977, Diffie andHellman described a specialized machine for cracking DES, consisting ofone million processors, each capable of running one million tests persecond [17]. Such a machine would take 20 hours to break any DES code.

Consider a key length of 128 bits. In the worst case, all 2¹²⁸ tests(3.4×10³⁸ tests) must be made to find the key. This would take tenbillion years on an array of a trillion processors each running 1billion tests per second.

With a long enough key length, a brute force attack takes too long to beworth the attacker's efforts.

5.7.1.6 Guessing Attack

This type of attack is where an attacker attempts to simply “guess” thekey. As an attack it is identical to the brute force attack (see Section5.7.1.5 on page 647) where the odds of success depend on the length ofthe key.

5.7.1.7 Quantum Computer Attack

To break an n-bit key, a quantum computer [83] (NMR, Optical, or CagedAtom) containing n qubits embedded in an appropriate algorithm must bebuilt. The quantum computer effectively exists in 2^(n) simultaneouscoherent states. The trick is to extract the right coherent statewithout causing any decoherence. To date this has been achieved with a 2qubit system (which exists in 4 coherent states). It is thought possibleto extend this to 6 qubits (with 64 simultaneous coherent states) withina few years.

Unfortunately, every additional qubit halves the relative strength ofthe signal representing the key. This rapidly becomes a seriousimpediment to key retrieval, especially with the long keys. used incryptographically secure systems.

As a result, attacks on a cryptographically secure key (e.g. 160 bits)using a Quantum Computer are likely not to be feasible and it isextremely unlikely that quantum computers will have achieved more than50 or so qubits within the commercial lifetime of the authenticationchips. Even using a 50 qubit quantum computer, 2¹¹⁰ tests are requiredto crack a 160 bit key.

5.7.1.8 Purposeful Error Attack

With certain algorithms, attackers can gather valuable information fromthe results of a bad input. This can range from the error message textto the time taken for the error to be generated.

A simple example is that of a userid/password scheme. If the errormessage usually says “Bad userid”, then when an attacker gets a messagesaying “Bad password” instead, then they know that the userid iscorrect. If the message always says “Bad userid/password” then much lessinformation is given to the attacker. A more complex example is that ofthe recent published method of cracking encryption codes from secure websites [41]. The attack involves sending particular messages to a serverand observing the error message responses. The responses give enoughinformation to learn the keys—even the lack of a response gives someinformation.

An example of algorithmic time can be seen with an algorithm thatreturns an error as soon as an erroneous bit is detected in the inputmessage. Depending on hardware implementation, it may be a simple methodfor the attacker to time the response and alter each bit one by onedepending on the time taken for the error response, and thus obtain thekey. Certainly in a chip implementation the time taken can be observedwith far greater accuracy than over the Internet.

5.7.1.9 Birthday Attack

This attack is named after the famous “birthday paradox” (which is notactually a paradox at all). The odds of one person sharing a birthdaywith another, is 1 in 365 (not counting leap years). Therefore theremust be 183 people in a room for the odds to be more than 50% that oneof them shares your birthday. However, there only needs to be 23 peoplein a room for there to be more than a 50% chance that any two share abirthday, as shown in the following relation:${Prob} = {{1 - \frac{n\quad\Pr}{n^{r}}} = {{1 - \frac{365{P23}}{365^{23}}} \approx 0.507}}$

Birthday attacks are common attacks against hashing algorithms,especially those algorithms that combine hashing with digitalsignatures.

If a message has been generated and already signed, an attacker mustsearch for a collision message that hashes to the same value (analogousto finding one person who shares your birthday). However, if theattacker can generate the message, the birthday attack comes into play.The attacker searches for two messages that share the same hash value(analogous to any two people sharing a birthday), only one message isacceptable to the person signing it, and the other is beneficial for theattacker. Once the person has signed the original message the attackersimply claims now that the person signed the alternativemessage—mathematically there is no way to tell which message was theoriginal, since they both hash to the same value.

Assuming a brute force attack is the only way to determine a match, theweakening of an n-bit key by the birthday attack is 2^(n/2). A keylength of 128 bits that is susceptible to the birthday attack has aneffective length of only 64 bits.

5.7.1.10 Chaining Attack

These are attacks made against the chaining nature of hash functions.They focus on the compression function of a hash function. The idea isbased on the fact that a hash function generally takes arbitrary lengthinput and produces a constant length output by processing the input nbits at a time. The output from one block is used as the chainingvariable set into the next block. Rather than finding a collisionagainst an entire input, the idea is that given an input chainingvariable set, to find a substitute block that will result in the sameoutput chaining variables as the proper message.

The number of choices for a particular block is based on the length ofthe block. If the chaining variable is c bits, the hashing functionbehaves like a random mapping, and the block length is b bits, thenumber of such b-bit blocks is approximately 2^(b)/2^(c). The challengefor finding a substitution block is that such blocks are a sparse subsetof all possible blocks.

For SHA-1, the number of 512 bit blocks is approximately 2⁵¹²/2¹⁶⁰, or2³⁵². The chance of finding a block by brute force search is about 1 in2¹⁶⁰.

5.7.1.11 Substitution with a Complete Lookup Table

If the number of potential messages sent to the chip is small, thenthere is no need for a clone manufacturer to crack the key. Instead, theclone manufacturer could incorporate a ROM in their chip that had arecord of all of the responses from a genuine chip to the codes sent bythe system. The larger the key, and the larger the response, the morespace is required for such a lookup table.

5.7.1.12 Substitution with a Sparse Lookup Table

If the messages sent to the chip are somehow predictable, rather thaneffectively random, then the clone manufacturer need not provide acomplete lookup table. For example:

-   -   If the message is simply a serial number, the clone manufacturer        need simply provide a lookup table that contains values for past        and predicted future serial numbers. There are unlikely to be        more than 10⁹ of these.    -   If the test code is simply the date, then the clone manufacturer        can produce a lookup table using the date as the address.    -   If the test code is a pseudo-random number using either the        serial number or the date as a seed, then the clone manufacturer        just needs to crack the pseudo-random number generator in the        system. This is probably not difficult, as they have access to        the object code of the system. The clone manufacturer would then        produce a content addressable memory (or other sparse array        lookup) using these codes to access stored authentication codes.        5.7.1.13 Differential Cryptanalysis

Differential cryptanalysis describes an attack where pairs of inputstreams are generated with known differences, and the differences in theencoded streams are analyzed.

Existing differential attacks are heavily dependent on the structure ofS boxes, as used in DES and other similar algorithms. Although otheralgorithms such as HMAC-SHA1 have no S boxes, an attacker can undertakea differential-like attack by undertaking statistical analysis of:

-   -   Minimal-difference inputs, and their corresponding outputs    -   Minimal-difference outputs, and their corresponding inputs

Most algorithms were strengthened against differential cryptanalysisonce the process was described. This is covered in the specific sectionsdevoted to each cryptographic algorithm. However some recent algorithmsdeveloped in secret have been broken because the developers had notconsidered certain styles of differential attacks [94] and did notsubject their algorithms to public scrutiny.

5.7.1.14 Message Substitution Attacks

In certain protocols, a man-in-the-middle can substitute part or all ofa message. This is where a real authentication chip is plugged into areusable clone chip within the consumable. The clone chip intercepts allmessages between the system and the authentication chip, and can performa number of substitution attacks.

Consider a message containing a header followed by content. An attackermay not be able to generate a valid header, but may be able tosubstitute their own content, especially if the valid response issomething along the lines of “Yes, I received your message”. Even if thereturn message is “Yes, I received the following message . . . ”, theattacker may be able to substitute the original message before sendingthe acknowledgment back to the original sender.

Message Authentication Codes were developed to combat messagesubstitution attacks.

5.7.1.15 Reverse Engineering the Key Generator

If a pseudo-random number generator is used to generate keys, there isthe potential for a clone manufacture to obtain the generator program orto deduce the random seed used. This was the way in which the securitylayer of the Netscape browser program was initially broken [33].

5.7.1.16 Bypassing the Authentication Process

It may be that there are problems in the authentication protocols thatcan allow a bypass of the authentication process altogether. With thesekinds of attacks the key is completely irrelevant, and the attacker hasno need to recover it or deduce it.

Consider an example of a system that authenticates at power-up, but doesnot authenticate at any other time. A reusable consumable with a cloneauthentication chip may make use of a real authentication chIP. Theclone authentication chip uses the real chip for the authenticationcall, and then simulates the real authentication chip's state data afterthat.

Another example of bypassing authentication is if the systemauthenticates only after the consumable has been used. A cloneauthentication chip can accomplish a simple authentication bypass bysimulating a loss of connection after the use of the consumable butbefore the authentication protocol has completed (or even started).

One infamous attack known as the “Kentucky Fried Chip” hack [2] involvedreplacing a microcontroller chip for a satellite TV system. When asubscriber stopped paying the subscription fee, the system would sendout a “disable” message. However the new micro-controller would simplydetect this message and not pass it on to the consumer's satellite TVsystem.

5.7.1.17 Garrote/Bribe Attack

If people know the key, there is the possibility that they could tellsomeone else. The telling may be due to coercion (bribe, garrote etc.),revenge (e.g. a disgruntled employee), or simply for principle. Theseattacks are usually cheaper and easier than other efforts at deducingthe key. As an example, a number of people claiming to be involved withthe development of the (now defunct) Divx standard for DVD claimed(before the standard was rejected by consumers) that they would like tohelp develop Divx specific cracking devices—out of principle.

5.7.2 Physical Attacks

The following attacks assume implementation of an authenticationmechanism in a silicon chip that the attacker has physical access to.The first attack, Reading ROM, describes an attack when keys are storedin ROM, while the remaining attacks assume that a secret key is storedin Flash memory.

5.7.2.1 Reading ROM

If a key is stored in ROM it can be read directly. A ROM can thus besafely used to hold a public key (for use in asymmetric cryptography),but not to hold a private key. In symmetric cryptography, a ROM iscompletely insecure. Using a copyright text (such as a haiku) as the keyis not sufficient, because we are assuming that the cloning of the chipis occurring in a country where intellectual property is not respected.

5.7.2.2 Reverse Engineering of Chip

Reverse engineering of the chip is where an attacker opens the chip andanalyzes the circuitry. Once the circuitry has been analyzed the innerworkings of the chip's algorithm can be recovered. Lucent Technologieshave developed an active method [4] known as TOBIC (Two photon OBIC,where OBIC stands for Optical Beam Induced Current), to image circuits.Developed primarily for static RAM analysis, the process involvesremoving any back materials, polishing the back surface to a mirrorfinish, and then focusing light on the surface. The excitationwavelength is specifically chosen not to induce a current in the IC.

A Kerckhoffs in the nineteenth century made a fundamental assumptionabout cryptanalysis: if the algorithm's inner workings are the solesecret of the scheme, the scheme is as good as broken [39]. Hestipulated that the secrecy must reside entirely in the key. As aresult, the best way to protect against reverse engineering of the chipis to make the inner workings irrelevant.

5.7.2.3 Usurping the Authentication Process

It must be assumed that any clone manufacturer has access to both thesystem and consumable designs.

If the same channel is used for communication between the system and atrusted system authentication chip, and a non-trusted consumableauthentication chip, it may be possible for the non-trusted chip tointerrogate a trusted authentication chip in order to obtain the“correct answer”. If this is so, a clone manufacturer would not have todetermine the key. They would only have to trick the system into usingthe responses from the system authentication chIP.

The alternative method of usurping the authentication process followsthe same method as the logical attack described in Section 5.7.1.16 onpage 652, involving simulated loss of contact with the system wheneverauthentication processes take place, simulating power-down etc.

5.7.2.4 Modification of System

This kind of attack is where the system itself is modified to acceptclone consumables. The attack may be a change of system ROM, a rewiringof the consumable, or, taken to the extreme case, a completely clonesystem.

Note that this kind of attack requires each individual system to bemodified, and would most likely require the owner's consent. There wouldusually have to be a clear advantage for the consumer to undertake sucha modification, since it would typically void warranty and would mostlikely be costly. An example of such a modification with a clearadvantage to the consumer is a software patch to change fixed-region DVDplayers into region-free DVD players (although it should be noted thatthis is not to use clone consumables, but rather originals from the samecompanies simply targeted for sale in other countries).

5.7.2.5 Direct Viewing of Chip Operation by Conventional Probing

If chip operation could be directly viewed using an STM (ScanningTunnelling Microscope) or an electron beam, the keys could be recordedas they are read from the internal non-volatile memory and loaded intowork registers.

These forms of conventional probing require direct access to the top orfront sides of the IC while it is powered.

5.7.2.6 Direct Viewing of the Non-Volatile Memory

If the chip were sliced so that the floating gates of the Flash memorywere exposed, without discharging them, then the key could probably beviewed directly using an STM or SKM (Scanning Kelvin Microscope).

However, slicing the chip to this level without discharging the gates isprobably impossible. Using wet etching, plasma etching, ion milling(focused ion beam etching), or chemical mechanical polishing will almostcertainly discharge the small charges present on the floating gates.

5.7.2.7 Viewing the Light Bursts Caused by State Changes

Whenever a gate changes state, a small amount of infrared energy isemitted. Since silicon is transparent to infrared, these changes can beobserved by looking at the circuitry from the underside of a chIP. Whilethe emission process is weak, it is bright enough to be detected byhighly sensitive equipment developed for use in astronomy. The technique[92], developed by IBM, is called PICA (Picosecond Imaging CircuitAnalyzer). If the state of a register is known at time t, then watchingthat register change over time will reveal the exact value at time t+n,and if the data is part of the key, then that part is compromised.

5.7.2.8 Viewing the Keys Using an SEPM

A non-invasive testing device, known as a Scanning Electric PotentialMicroscope (SEPM), allows the direct viewing of charges within a chip[37]. The SEPM has a tungsten probe that is placed a few micrometersabove the chip, with the probe and circuit forming a capacitor. Any ACsignal flowing beneath the probe causes displacement current to flowthrough this capacitor. Since the value of the current change depends onthe amplitude and phase of the AC signal, the signal can be imaged. Ifthe signal is part of the key, then that part is compromised.

5.7.2.9 Monitoring EMI

Whenever electronic circuitry operates, faint electromagnetic signalsare given off. Relatively inexpensive equipment can monitor thesesignals and could give enough information to allow an attacker to deducethe keys.

5.7.2.10 Viewing I_(dd) Fluctuations

Even if keys cannot be viewed, there is a fluctuation in currentwhenever registers change state. If there is a high enough signal tonoise ratio, an attacker can monitor the difference in I_(dd) that mayoccur when programming over either a high or a low bit. The change inI_(dd) can reveal information about the key. Attacks such as these havealready been used to break smart cards [46].

5.7.2.11 Differential Fault Analysis

This attack assumes introduction of a bit error by ionization, microwaveradiation, or environmental stress. In most cases such an error is morelikely to adversely affect the chip (e.g. cause the program code tocrash) rather than cause beneficial changes which would reveal the key.Targeted faults such as ROM overwrite, gate destruction etc. are farmore likely to produce useful results.

5.7.2.12 Clock Glitch Attacks

Chips are typically designed to properly operate within a certain clockspeed range. Some attackers attempt to introduce faults in logic byrunning the chip at extremely high clock speeds or introduce a clockglitch at a particular time for a particular duration [1]. The idea isto create race conditions where the circuitry does not functionproperly. An example could be an AND gate that (because of raceconditions) gates through Input₁ all the time instead of the AND ofInput, and Input₂.

If an attacker knows the internal structure of the chip, they canattempt to introduce race conditions at the correct moment in thealgorithm execution, thereby revealing information about the key (or inthe worst case, the key itself).

5.7.2.13 Power Supply Attacks

Instead of creating a glitch in the clock signal, attackers can alsoproduce glitches in the power supply where the power is increased ordecreased to be outside the working operating voltage range. The neteffect is the same as a clock glitch—introduction of error in theexecution of a particular instruction. The idea is to stop the CPU fromXORing the key, or from shifting the data one bit-position etc. Specificinstructions are targeted so that information about the key is revealed.

5.7.2.14 Overwriting ROM

Single bits in a ROM can be overwritten using a laser cutter microscope[1], to either 1 or 0 depending on the sense of the logic. If the ROMcontains instructions, it may be a simple matter for an attacker tochange a conditional jump to a non-conditional jump, or perhaps changethe destination of a register transfer. If the target instruction ischosen carefully, it may result in the key being revealed.

5.7.2.15 Modifying EEPROM/Flash

These attacks fall into two categories:

-   -   those similar to the ROM attacks except that the laser cutter        microscope technique can be used to both set and reset        individual bits. This gives much greater scope in terms of        modification of algorithms.    -   Electron beam programming of floating gates. As described in        [89] and [32], a focused electron beam can change a gate by        depositing electrons onto it. Damage to the rest of the circuit        can be avoided, as described in [31].        5.7.2.16 Gate Destruction

Anderson and Kuhn described the rump session of the 1997 workshop onFast Software Encryption (1], where Biham and Shamir presented an attackon DES. The attack was to use a laser cutter to destroy an individualgate in the hardware implementation of a known block cipher (DES). Thenet effect of the attack was to force a particular bit of a register tobe “stuck”. Biham and Shamir described the effect of forcing aparticular register to be affected in this way—the least significant bitof the output from the round function is set to 0. Comparing the 6 leastsignificant bits of the left half and the right half can recover severalbits of the key. Damaging a number of chips in this way can revealenough information about the key to make complete key recovery easy.

An encryption chip modified in this way will have the property thatencryption and decryption will no longer be inverses.

5.7.2.17 Overwrite Attacks

Instead of trying to read the Flash memory, an attacker may simply set asingle bit by use of a laser cutter microscope. Although the attackerdoesn't know the previous value, they know the new value. If the chipstill works, the bit's original state must be the same as the new state.If the chip doesn't work any longer, the bit's original state must bethe logical NOT of the current state. An attacker can perform thisattack on each bit of the key and obtain the n-bit key using at most nchips (if the new bit matched the old bit, a new chip is not requiredfor determining the next bit).

5.7.2.18 Test Circuitry Attack

Most chips contain test circuitry specifically designed to check formanufacturing defects. This includes BIST (Built In Self Test) and scanpaths. Quite often the scan paths and test circuitry includes access andreadout mechanisms for all the embedded latches. In some cases the testcircuitry could potentially be used to give information about thecontents of particular registers.

Test circuitry is often disabled once the chip has passed allmanufacturing tests, in some cases by blowing a specific connectionwithin the chIP. A determined attacker, however, can reconnect the testcircuitry and hence enable it.

5.7.2.19 Memory Remnants

Values remain in RAM long after the power has been removed [35],although they do not remain long enough to be considered non-volatile.An attacker can remove power once sensitive information has been movedinto RAM (for example working registers), and then attempt to read thevalue from RAM. This attack is most useful against security systems thathave regular RAM chips. A classic example is cited by [1], where asecurity system was designed with an automatic power-shut-off that istriggered when the computer case is opened. The attacker was able tosimply open the case, remove the RAM chips, and retrieve the key becausethe values persisted.

5.7.2.20 Chip Theft Attack

If there are a number of stages in the lifetime of an authenticationchip, each of these stages must be examined in terms of ramificationsfor security should chips be stolen. For example, if information isprogrammed into the chip in stages, theft of a chip between stages mayallow an attacker to have access to key information or reduced effortsfor attack. Similarly, if a chip is stolen directly after manufacturebut before programming, does it give an attacker any logical or physicaladvantage?

5.7.2.21 Trojan Horse Attack

At some stage the authentication chips must be programmed with a secretkey. Suppose an attacker builds a clone authentication chip and adds itto the pile of chips to be programmed. The attacker has especially builtthe clone chip so that it looks and behaves just like a realauthentication chip, but will give the key out to the attacker when aspecial attacker-known command is issued to the chIP. Of course theattacker must have access to the chip after the programming has takenplace, as well as physical access to add the Trojan horse authenticationchip to the genuine chips.

6 Requirements

Existing solutions to the problem of authenticating consumables havetypically relied on patents covering physical packaging. However thisdoes not stop home refill operations or clone manufacture in countrieswith weak industrial property protection. Consequently a much higherlevel of protection is required.

The authentication mechanism is therefore built into an authenticationchip that is embedded in the consumable and allows a system toauthenticate that consumable securely and easily. Limiting ourselves tothe system authenticating consumables (we don't consider the consumableauthenticating the system), two levels of protection can be considered:

Presence Only Authentication:

This is where only the presence of an authentication chip is tested. Theauthentication chip can be removed and used in other consumables as longas be used indefinitely.

Consumable Lifetime Authentication:

This is where not only is the presence of the authentication chip testedfor, but also the authentication chip must only last the lifetime of theconsumable. For the chip to be re-used it must be completely erased andreprogrammed.

The two levels of protection address different requirements. We areprimarily concerned with Consumable Lifetime authentication in order toprevent cloned versions of high volume consumables. In this case, eachchip should hold secure state information about the consumable beingauthenticated. It should be noted that a Consumable Lifetimeauthentication chip could be used in any situation requiring a PresenceOnly authentication chIP.

Requirements for authentication, data storage integrity and manufactureare considered separately. The following sections summarize requirementsof each.

6.1 Authentication

The authentication requirements for both Presence Only and ConsumableLifetime authentication are restricted to the case of a systemauthenticating a consumable. We do not consider bi-directionalauthentication where the consumable also authenticates the system. Forexample, it is not necessary for a valid toner cartridge to ensure it isbeing used in a valid photocopier.

For Presence Only authentication, we must be assured that anauthentication chip is physically present. For Consumable Lifetimeauthentication we also need to be assured that state data actually camefrom the authentication chip, and that it has not been altered en route.These issues cannot be separated—data that has been altered has a newsource, and if the source cannot be determined, the question ofalteration cannot be settled.

It is not enough to provide an authentication method that is secret,relying on a home-brew security method that has not been scrutinized bysecurity experts. The primary requirement therefore is to provideauthentication by means that have withstood the scrutiny of experts.

The authentication scheme used by the authentication chip should beresistant to defeat by logical means. Logical types of attack areextensive, and attempt to do one of three things:

-   -   Bypass the authentication process altogether    -   Obtain the secret key by force or deduction, so that any        question can be answered    -   Find enough about the nature of the authenticating questions and        answers in order to, without the key, give the right answer to        each question.

The logical attack styles and the forms they take are detailed inSection 5.7.1 on page 646.

The algorithm should have a flat keyspace, allowing any random bitstring of the required length to be a possible key. There should be noweak keys.

6.2 Data Storage Integrity

Although authentication protocols take care of ensuring data integrityin communicated messages, data storage integrity is also required. Twokinds of data must be stored within the authentication chip:

-   -   Authentication data, such as secret keys    -   Consumable state data, such as serial numbers, and media        remaining etc.

The access requirements of these two data types differ greatly. Theauthentication chip therefore requires a storage/access controlmechanism that allows for the integrity requirements of each type.

6.2.1 Authentication Data

Authentication data must remain confidential. It needs to be stored inthe chip during a manufacturing/programming stage of the chip's life,but from then on must not be permitted to leave the chIP. It must beresistant to being read from non-volatile memory. The authenticationscheme is responsible for ensuring the key cannot be obtained bydeduction, and the manufacturing process is responsible for ensuringthat the key cannot be obtained by physical means.

The size of the authentication data memory area must be large enough tohold the necessary keys and secret information as mandated by theauthentication protocols.

6.2.2 Consumable State Data

Consumable state data can be divided into the following types. Dependingon the application, there will be different numbers of each of thesetypes of data items.

-   -   Read Only    -   ReadWrite    -   Decrement Only

Read Only data needs to be stored in the chip during amanufacturing/programming stage of the chip's life, but from then onshould not be allowed to change. Examples of Read Only data items areconsumable batch numbers and serial numbers.

ReadWrite data is changeable state information, for example, the lasttime the particular consumable was used. ReadWrite data items can beread and written an unlimited number of times during the lifetime of theconsumable. They can be used to store any state information about theconsumable. The only requirement for this data is that it needs to bekept in non-volatile memory. Since an attacker can obtain access to asystem (which can write to ReadWrite data), any attacker can potentiallychange data fields of this type. This data type should not be used forsecret information, and must be considered insecure.

Decrement Only data is used to count down the availability of consumableresources. A photocopier's toner cartridge, for example, may store theamount of toner remaining as a Decrement Only data item. An inkcartridge for a color printer may store the amount of each ink color asa Decrement Only data item, requiring 3 (one for each of Cyan, Magenta,and Yellow), or even as many as 5 or 6 Decrement Only data items. Therequirement for this kind of data item is that once programmed with aninitial value at the manufacturing/programming stage, it can only reducein value. Once it reaches the minimum value, it cannot decrement anyfurther. The Decrement Only data item is only required by ConsumableLifetime authentication.

Note that the size of the consumable state data storage required is onlyfor that information required to be authenticated. Information whichwould be of no use to an attacker, such as ink color-curvecharacteristics or ink viscosity do not have to be stored in the securestate data memory area of the authentication chIP.

6.3 Manufacture

The authentication chip must have a low manufacturing cost in order tobe included as the authentication mechanism for low cost consumables.

The authentication chip should use a standard manufacturing process,such as Flash. This is necessary to:

-   -   Allow a great range of manufacturing location options    -   Use well-defined and well-behaved technology    -   Reduce cost

Regardless of the authentication scheme used, the circuitry of theauthentication part of the chip must be resistant to physical attack.Physical attack comes in four main ways, although the form of the attackcan vary:

-   -   Bypassing the authentication chip altogether    -   Physical examination of chip while in operation (destructive and        non-destructive)    -   Physical decomposition of chip    -   Physical alteration of chip

The physical attack styles and the forms they take are detailed inSection 5.7.2 on page 652. Ideally, the chip should be exportable fromthe USA, so it should not be possible to use an authentication chip as asecure encryption device. This is low priority requirement since thereare many companies in other countries able to manufacture theauthentication chips. In any case, the export restrictions from the USAmay change.

Authentication

7 Introduction

Existing solutions to the problem of authenticating consumables havetypically relied on physical patents on packaging. However this does notstop home refill operations or clone manufacture in countries with weakindustrial property protection. Consequently a much higher level ofprotection is required.

It is not enough to provide an authentication method that is secret,relying on a home-brew security method that has not been scrutinized bysecurity experts. Security systems such as Netscape's originalproprietary system and the GSM Fraud Prevention Network used by cellularphones are examples where design secrecy caused the vulnerability of thesecurity [33][33]. Both security systems were broken by conventionalmeans that would have been detected if the companies had followed anopen design process. The solution is to provide authentication by meansthat have withstood the scrutiny of experts.

In this section, we examine a number of protocols that can be used forconsumables authentication. We only use security methods that arepublicly described, using known behaviors in this new way. Readersshould be familiar with the concepts and terms described in Section 5 onpage 629. We avoid the Zero Knowledge Proof protocol since it ispatented.

For all protocols, the security of the scheme relies on a secret key,not a secret algorithm. In the nineteenth century, A Kerckhoffs made afundamental assumption about cryptanalysis: if the algorithm's innerworkings are the sole secret of the scheme, the scheme is as good asbroken [39]. He stipulated that the secrecy must reside entirely in thekey. As a result, the best way to protect against reverse engineering ofany authentication chip is to make the algorithmic inner workingsirrelevant (the algorithm of the inner workings must still be must bevalID, but not the actual secret).

The QA Chip is a programmable device, and can therefore be setup with anapplication-specific program together with an application-specific setof protocols. This section describes the following sets of protocols:

-   -   single key single memory vector    -   multiple key single memory vector    -   multiple key multiple memory vector

These protocols refer to the number of valid keys that an QA Chip knowsabout, and the size of data required to be stored in the chIP.

From these protocols it is straightforward to construct protocol setsfor the single key multiple memory vector case (of course the multiplememory vector can be considered to be. and multiple key single memoryvector. Other protocol sets can also be defined as necessary. Of coursemultiple memory vector can be conveniently

All the protocols rely on a time-variant challenge (i.e. the challengeis different each time), where the response depends on the challenge andthe secret. The challenge involves a random number so that any observerwill not be able to gather useful information about a subsequentidentification.

8 Single Key Single Memory Vector

8.1 Protocol Background

This protocol set is provided for two reasons:

-   -   the other protocol sets defined in this document are simply        extensions of this one; and    -   it is useful in its own right

The single key protocol set is useful for applications where only asingle key is required. Note that there can be many consumables andsystems, but there is only a single key that connects them all. Examplesinclude:

-   -   car and keys. A car and the car-key share a single key. There        can be multiple sets of car-keys, each effectively cut to the        same key. A company could have a set of cars, each with the same        key. Any of the car-keys could then be used to drive any of the        cars.    -   printer and ink cartridge. All printers of a certain model use        the same ink cartridge, with printer and cartridge sharing only        a single key. Note that to introduce a new printer model that        accepts the old ink cartridge the new model would need the same        key as the old model. See the multiple-key protocols for        alternative solutions to this problem.        8.2 Requirements of Protocol

Each QA Chip contains the following values: K The secret key forcalculating F_(K)[X]. K must not be stored directly in the QA Chip.Instead, each chip needs to store a random number R_(K) (different foreach chip), K⊕R_(K), and

K⊕R_(K). The stored K⊕R_(K) can be XORed with R_(K) to obtain the realK. Although

K⊕R_(K) must be stored to protect against differential attacks, it isnot used. R Current random number used to ensure time varying messages.Each chip instance must be seeded with a different initial value.Changes for each signature generation. M Memory vector of QA Chip. P 2element array of access permissions for each part of M. Entry 0 holdsaccess permissions for non-authenticated writes to M (no key required).Entry 1 holds access permissions for authenticated writes to M (keyrequired). Permission choices for each part of M are Read Only,Read/Write, and Decrement Only. C 3 constants used for generatingsignatures. C₁, C₂, and C₃ are constants that pad out a submessage to ahashing boundary, and all 3 must be different. Each QA Chip contains thefollowing private function: S_(K)[X] Internal function only. ReturnsS_(K)[X], the result of applying a digital signature function S to Xbased upon key K. The digital signature must be long enough to counterthe chances of someone generating a random signature. The length dependson the signature scheme chosen, although the scheme chosen for the QAChip is HMAC-SHA1 (see Section 13 on page 691), and therefore the lengthof the signature is 160 bits.

Additional functions are required in certain QA Chips, but these aredescribed as required.

8.3 Reads of M

In this case, we have a trusted chip (ChipT) connected to a System. TheSystem wants to authenticate an object that contains a non-trusted chip(ChipA). In effect, the System wants to know that it can securely read amemory vector (M) from ChipA: to be sure that ChipA is valid and that Mhas not been altered.

The protocol requires the following publicly available function inChipA:

-   -   Read[X] Advances R, and returns R, M, S_(K)[X|R|C₁|M]. The time        taken to calculate the signature must not be based on the        contents of X, R, M, or K.

The protocol requires the following publicly available functions inChipT:

-   -   Random        Returns R (does not advance R).    -   Test[)(, Y, Z] Advances R and returns 1 if S_(K)[R|X|C₁|Y]=Z.        Otherwise returns 0. The time taken to calculate and compare        signatures must be independent of data content.

To authenticate ChipA and read ChipA's memory M:

-   a. System calls ChipT's Random function;-   b. ChipT returns R_(T) to System;-   c. System calls ChipA's Read function, passing in the result from b;-   d. ChipA updates R_(A), then calculates and returns R_(A), M_(A),    S_(K)[R_(T)|R_(A)|C₁|M_(A)];-   e. System calls ChipT's Test function, passing in R_(A), M_(A),    S_(K)[R_(T)|R_(A)|C₁|M_(A)];-   f. System checks response from ChipT. If the response is 1, then    ChipA is considered authentic. If 0, ChipA is considered invalid.

The data flow for read authentication is shown in FIG. 334.

The protocol allows System to simply pass data from one chip to another,with no special processing. The protection relies on ChipT beingtrusted, even though System does not know K.

When ChipT is physically separate from System (eg is chip on a boardconnected to System) System must also occassionally (based on systemclock for example) call ChipT's Test function with bad data, expecting a0 response. This is to prevent someone from inserting a fake ChipT intothe system that always returns 1 for the Test function.

8.4 Writes

In this case, the System wants to update M in some chip referred to asChipU. This can be non-authenticated (for example, anyone is allowed tocount down the amount of consumable remaining), or authenticated (forexample, replenishing the amount of consumable remaining).

8.4.1 Non-Authenticated Writes

This is the most frequent type of write, and takes place between theSystem/consumable during normal everyday operation. In this kind ofwrite, System wants to change M in a way that doesn't require specialauthorization. For example, the System could be decrementing the amountof consumable remaining. Although System does not need to know K or evenhave access to a trusted chip, System must follow a non-authenticatedwrite by an authenticated read if it needs to know that the write wassuccessful.

The protocol requires the following publicly available function:

-   -   Write[X] Writes X over those parts of M subject to P₀ and the        existing value for M.

To authenticate a write of M_(new) to ChipA's memory M:

-   a. System calls ChipU's Write function, passing in M_(new);-   b. The authentication procedure for a Read is carried out (see    Section 8.3 on page 664);-   c. If ChipU is authentic and M_(new)=M returned in b, the write    succeeded. If not, it failed.    8.4.2 Authenticated Writes

In this kind of write, System wants to change Chip U's M in anauthorized way, without being subject to the permissions that applyduring normal operation (P₀). For example, the consumable may be at arefilling station and the normally Decrement Only section of M should beupdated to include the new valid consumable. In this case, the chipwhose M is being updated must authenticate the writes being generated bythe external System and in addition, apply permissions P₁ to ensure thatonly the correct parts of M are updated.

In this transaction protocol, the System's chip is referred to as ChipS,and the chip being updated is referred to as ChipU. Each chip distruststhe other.

The protocol requires the following publicly available functions inChipU:

-   -   Read[X] Advances R, and returns R, M, S_(K)[X|R|C₁|M]. The time        taken to calculate the signature must be identical for all        inputs.    -   WriteA[X, Y, Z]Returns 1, advances R, and replaces M by Y        subject to P₁ only if S_(K)[R|X|C₁|Y]=Z. Otherwise returns 0.        The time taken to calculate and compare signatures must be        independent of data content. This function is identical to        ChipT's Test function except that it additionally writes Y over        those parts of M subject to P₁ when the signature matches.

Authenticated writes require that the System has access to a ChipS thatis capable of generating appropriate signatures. ChipS requires thefollowing variables and function: CountRemaining Part of M that containsthe number of signatures that ChipS is allowed to generate. Decrementswith each successful call to SignM and SignP. Permissions in ChipS's P₀for this part of M needs to be ReadOnly once ChipS has been setup.Therefore CountRemaining can only be updated by another ChipS that willperform updates to that part of M (assuming ChipS's P₁ allows that partof M to be updated). Q Part of M that contains the write permissions forupdating ChipU's M. By adding Q to ChipS we allow different ChipSs thatcan update different parts of M_(U). Permissions in ChipS's P₀ for thispart of M needs to be ReadOnly once ChipS has been setup. Therefore Qcan only be updated by another ChipS that will perform updates to thatpart of M. SignM[V, W, X, Y, Z] Advances R, decrements CountRemainingand returns R, Z_(QX) (Z applied to X with permissions Q), followed byS_(K)[W|R|C₁|Z_(QX)] only if S_(K)[V|W|C₁|X] = Y and CountRemaining > 0.Otherwise returns all 0s. The time taken to calculate and comparesignatures must be independent of data content.

To update ChipU's M vector:

-   a. System calls ChipU's Read function, passing in 0 as the input    parameter;-   b. ChipU produces R_(U), M_(U), S_(K)[0|R_(U)|C₁|M_(U)] and returns    these to System;-   c. System calls ChipS's SignM function, passing in 0 (as used in a),    R_(U), M_(U), S_(K)[0|R_(U)|C₁|M_(U)], and M_(D) (the desired vector    to be written to ChipU);-   d. ChipS produces R_(S), M_(QD) (processed by running MD against    M_(U) using Q) and S_(K)[R_(U)|R_(S)|C₁|M_(QD)] if the inputs were    valID, and 0 for all outputs if the inputs were not valid.-   e. If values returned in d are non zero, then ChipU is considered    authentic. System can then call ChipU's WriteA function with these    values.-   f. ChipU should return a 1 to indicate success. A 0 should only be    returned if the data generated by ChipS is incorrect (e.g. a    transmission error).

The data flow for authenticated writes is shown in FIG. 335.

Note that Q in ChipS is part of ChipS's M. This allows a user to set upChipS with a permission set for upgrades. This should be done to ChipSand that part of M designated by P₀ set to ReadOnly before ChipS isprogrammed with K_(U). If K_(S) is programmed with K_(U) first, there isa risk of someone obtaining a half-setup ChipS and changing all of M_(U)instead of only the sections specified by Q.

The same is true of CountRemaining. The CountRemaining value needs to besetup (including making it ReadOnly in P₀) before ChipS is programmedwith K_(U). ChipS is therefore programmed to only perform a limitednumber of SignM operations (thereby limiting compromise exposure if aChipS is stolen). Thus ChipS would itself need to be upgraded with a newCountRemaining every so often.

8.4.3 Updating Permissions for Future Writes

In order to reduce exposure to accidental and malicious attacks on P andcertain parts of M, only authorized users are allowed to update P.Writes to P are the same as authorized writes to M, except that theyupdate P_(n) instead of M. Initially (at manufacture), P is set to beRead/Write for all parts of M. As different processes fill up differentparts of M, they can be sealed against future change by updating thepermissions. Updating a chip's P₀ changes permissions for unauthorizedwrites, and updating P₁ changes permissions for authorized writes.

P_(n) is only allowed to change to be a more restrictive form of itself.For example, initially all parts of M have permissions of Read/Write. Apermission of Read/Write can be updated to Decrement Only or Read Only.A permission of Decrement Only can be updated to become Read Only. ARead Only permission cannot be further restricted.

In this transaction protocol, the System's chip is referred to as ChipS,and the chip being updated is referred to as ChipU. Each chip distruststhe other.

The protocol requires the following publicly available functions inChipU:

-   -   Random        Returns R (does not advance R).    -   SetPermission[n,X,Y,Z] Advances R, and updates P_(n) according        to Y and returns 1 followed by the resultant P_(n) only if        S_(K)[R|X|Y|C₂]=Z. Otherwise returns 0. P_(n) can only become        more restricted. Passing in 0 for any permission leaves it        unchanged (passing in Y=0 returns the current P_(n)).

Authenticated writes of permissions require that the System has accessto a ChipS that is capable of generating appropriate signatures. ChipSrequires the following variables and function: CountRemaining Part of Mthat contains the number of signatures that ChipS is allowed togenerate. Decrements with each successful call to SignM and SignP.Permissions in ChipS's P₀ for this part of M needs to be ReadOnly onceChipS has been setup. Therefore CountRemaining can only be updated byanother ChipS that will perform updates to that part of M (assumingChipS's P₁ allows that part of M to be updated). SignP[X, Y] Advances R,decrements CountRemaining and returns R and S_(K)[X|R|Y|C₂] only ifCountRemaining > 0. Otherwise returns all 0s. The time taken tocalculate and compare signatures must be independent of data content.

To update ChipU's P_(n):

-   a. System calls ChipU's Random function;-   b. ChipU returns R_(U) to System;-   c. System calls ChipS's SignP function, passing in R_(U) and P_(D)    (the desired P to be written to ChipU);-   d. ChipS produces R_(S) and S_(K)[R_(U)|R_(S)|P_(D)|C₂] if it is    still permitted to produce signatures.-   e. If values returned in d are non zero, then System can then call    ChipU's SetPermission function with the desired n, R_(S), P_(D) and    S_(K)[R_(U)|R_(S)|P_(D)|C₂].-   f. ChipU verifies the received signature against    S_(K)[R_(U)|R_(S)|P_(D)|C₂] and applies P_(D) to P_(n) if the    signature matches-   g. System checks 1st output parameter. 1=success, 0=failure.

The data flow for authenticated writes to permissions is shown in FIG.336 below.

8.5 Programming K

In this case, we have a factory chip (ChipF) connected to a System. TheSystem wants to program the key in another chip (ChipP). System wants toavoid passing the new key to ChipP in the clear, and also wants to avoidthe possibility of the key-upgrade message being replayed on anotherChipP (even if the user doesn't know the key).

The protocol assumes that ChipF and ChipP already share a secret keyK_(old). This key is used to ensure that only a chip that knows K_(old)can set K_(new).

The protocol requires the following publicly available functions inChipP: Random[ ] Returns R (does not advance R). ReplaceKey[X, Y, Z]Replaces K by S_(Kold)[R|X|C₃]⊕Y, advances R, and returns 1 only ifS_(Kold)[X|Y|C₃] = Z. Otherwise returns 0. The time taken to calculatesignatures and compare values must be identical for all inputs.

And the following data and function in ChipF: CountRemaining Part of Mwith contains the number of signatures that ChipF is allowed togenerate. Decrements with each successful call to GetProgramKey.Permissions in P for this part of M needs to be ReadOnly once ChipF hasbeen setup. Therefore can only be updated by a ChipS that has authorityto perform updates to that part of M. K_(new) The new key to betransferred from ChipF to ChipP. Must not be visible. SetPartialKey[X,Y] If word X of K_(new) has not yet been set, set word X of K_(new) to Yand return 1. Otherwise return 0. This function allows K_(new) to beprogrammed in multiple steps, thereby allowing different people orsystems to know different parts of the key (but not the whole K_(new)).K_(new) is stored in ChipF's flash memory. Since there is a small numberof ChipFs, it is theoretically not necessary to store the inverse ofK_(new), but it is stronger protection to do so. GetProgramKey[X]Advances R_(F), decrements CountRemaining, outputs R_(F), the encryptedkey S_(Kold)[X|R_(F)|C₃]⊕K_(new) and a signature of the first twooutputs plus C₃ if CountRemaining > 0. Otherwise outputs 0. The time tocalculate the encrypted key & signature must be identical for allinputs.

To update P's key:

-   a. System calls ChipP's Random function;-   b. ChipP returns R_(P) to System;-   c. System calls ChipF's GetProgramKey function, passing in the    result from b;-   d. ChipF updates R_(F), then calculates and returns R_(F),    S_(Kold)[R_(P)|R_(F)|C₃]⊕K_(new), and    S_(Kold)[R_(F)|S_(Kold)[R_(P)|R_(F)|C₃]⊕K_(new)|C₃];-   e. If the response from d is not 0, System calls ChipP's ReplaceKey    function, passing in the response from d;-   f. System checks response from ChipP. If the response is 1, then    K_(P) has been correctly updated to K_(new). If the response is 0,    K_(P) has not been updated.

The data flow for key updates is shown in FIG. 337.

Note that K_(new) is never passed in the open. An attacker could sendits own R_(P), but cannot produce S_(Kold)[R_(P)|R_(F)|C₃] withoutK_(old). The third parameter, a signature, is sent to ensure that ChipPcan determine if either of the first two parameters have been changed enroute.

CountRemaining needs to be setup in M_(F) (including making it ReadOnlyin P) before ChipF is programmed with K_(P). ChipF should therefore beprogrammed to only perform a limited number of GetProgramKey operations(thereby limiting compromise exposure if a ChipF is stolen). Anauthorized ChipS can be used to update this counter if neccesary (seeSection 8.4 on page 665).

8.5.1 Chicken and Egg

Of course, for the Program Key protocol to work, both ChipF and ChipPmust both know K_(old). Obviously both chips had to be programmed withK_(old), and thus K_(old) can be thought of as an older K_(new):K_(old)can be placed in chips if another ChipF knows K_(older), and so on.

Although this process allows a chain of reprogramming of keys, with eachstage secure, at some stage the very first key (K_(first)) must beplaced in the chips. K_(first) is in fact programmed with the chip'smicrocode at the manufacturing test station as the last step inmanufacturing test. K_(first) can be a manufacturing batch key, changedfor each batch or for each customer etc, and can have as short a life asdesired. Compromising K_(first) need not result in a complete compromiseof the chain of K_(S).

9 Multiple Key Single Memory Vector

9.1 Protocol Background

This protocol set is an extension to the single key single memory vectorprotocol set, and is provided for two reasons:

-   -   the multiple key multiple memory vector protocol set defined in        this document is simply extensions of this one; and    -   it is useful in its own right

The multiple key protocol set is typically useful for applications wherethere are multiple types of systems and consumables, and they need towork with each other in various ways. This is typically in the followingsituations:

-   -   when different systems want to share some consumables, but not        others. For example printer models may share some ink cartridges        and not share others.    -   when there are different owners of data in M. Part of the memory        vector may be owned by one company (eg the speed of the printer)        and another may be owned by another (eg the serial number of the        chIP). In this case a given key K_(n) needs to be able to write        to a given part of M, and other keys K_(n) need to be disallowed        from writing to these same areas.        9.2 Requirements of Protocol

Each QA Chip contains the following values:

-   N The maximum number of keys known to the chIP.-   K_(N) Array of N secret keys used for calculating F_(Kn)[X] where    K_(n) is the nth element of the array. Each K_(n) must not be stored    directly in the QA Chip. Instead, each chip needs to store a single    random number R_(K) (different for each chIP), K_(n)⊕R_(K), and    K_(n)⊕R_(K). The stored K_(n)⊕R_(K) can be XORed with R_(K) to    obtain the real K_(n). Although    K_(n)⊕R_(K) must be stored to protect against differential attacks,    it is not used.-   R Current random number used to ensure time varying messages. Each    chip instance must be seeded with a different initial value. Changes    for each signature generation.-   M Memory vector of QA ChIP. A fixed part of M contains N in ReadOnly    form so users of the chip can know the number of keys known by the    chIP.-   P N+1 element array of access permissions for each part of M. Entry    0 holds access permissions for non-authenticated writes to M (no key    required). Entries 1 to N+1 hold access permissions for    authenticated writes to M, one for each K. Permission choices for    each part of M are Read Only, Read/Write, and Decrement Only.-   C 3 constants used for generating signatures. C₁, C₂, and C₃ are    constants that pad out a submessage to a hashing boundary, and all 3    must be different.

Each QA Chip contains the following private function:

-   S_(Kn)[N,X] Internal function only. Returns S_(Kn)[X], the result of    applying a digital signature function S to X based upon the    appropriate key K_(n). The digital signature must be long enough to    counter the chances of someone generating a random signature. The    length depends on the signature scheme chosen, although the scheme    chosen for the QA Chip is HMAC-SHA1 (see Section 13 on page 691),    and therefore the length of the signature is 160 bits.

Additional functions are required in certain QA Chips, but these aredescribed as required.

9.3 Reads

As with the single key scenario, we have a trusted chip (ChipT)connected to a System. The System wants to authenticate an object thatcontains a non-trusted chip (ChipA). In effect, the System wants to knowthat it can securely read a memory vector (M) from ChipA: to be surethat ChipA is valid and that M has not been altered.

The protocol requires the following publicly available functions:

-   -   Random        Returns R (does not advance R).    -   Read[n, X] Advances R, and returns R, M, S_(Kn)[X|R|C₁|M]. The        time taken to calculate the signature must not be based on the        contents of X, R, M, or K.    -   Test[n,X, Y, Z] Advances R and returns 1 if S_(Kn)[R|X|C₁|Y]=Z.        Otherwise returns 0. The time taken to calculate and compare        signatures must be independent of data content.

To authenticate ChipA and read ChipA's memory M:

-   a. System calls ChipT's Random function;-   b. ChipT returns R_(T) to System;-   c. System calls ChipA's Read function, passing in some key number n1    and the result from b;-   d. ChipA updates R_(A), then calculates and returns R_(A), M_(A),    S_(KAn1)[R_(T)|R_(A)|C₁|M_(A)];-   e. System calls ChipT's Test function, passing in n2, R_(A), M_(A),    S_(KAn1)[R_(T)|R_(A)|C₁|M_(A)];-   f. System checks response from ChipT. If the response is 1, then    ChipA is considered authentic. If 0, ChipA is considered invalid.

The choice of n1 and n2 must be such that ChipA's K_(n1)=ChipT's K_(n2).

The data flow for read authentication is shown in FIG. 338.

The protocol allows System to simply pass data from one chip to another,with no special processing. The protection relies on ChipT beingtrusted, even though System does not know K.

When ChipT is physically separate from System (eg is chip on a boardconnected to System) System must also occassionally (based on systemclock for example) call ChipT's Test function with bad data, expecting a0 response. This is to prevent someone from inserting a fake ChipT intothe system that always returns 1 for the Test function.

It is important that n1 is chosen by System. Otherwise ChipA would needto return N_(A) sets of signatures for each read, since ChipA does notknow which of the keys will satisfy ChipT. Similarly, system must alsochoose n2, so it can potentially restrict the number of keys in ChipTthat are matched against (otherwise ChipT would have to match againstall its keys). This is important in order to restrict how different keysare used. For example, say that ChipT contains 6 keys, keys 0-2 are forvarious printer-related upgrades, and keys 3-6 are for inks. ChipAcontains say 4 keys, one key for each printer model. At power-up, Systemgoes through each of chipA's keys 0-3, trying each out against ChipT'skeys 3-6. System doesn't try to match against ChipT's keys 0-2.Otherwise knowledge of a speed-upgrade key could be used to provide inkQA Chip chips. This matching needs to be done only once (eg at powerup). Once matching keys are found, System can continue to use those keynumbers.

Since System needs to know N_(T) and N_(A), part of M is used to hold N(eg in Read Only form), and the system can obtain it by calling the Readfunction, passing in key 0.

9.4 Writes

As with the single key scenario, the System wants to update M in ChipU.As before, this can be done in a non-authenticated and authenticatedway.

9.4.1 Non-Authenticated Writes

This is the most frequent type of write, and takes place between theSystem/consumable during normal everyday operation. In this kind ofwrite, System wants to change M subject to P. For example, the Systemcould be decrementing the amount of consumable remaining. AlthoughSystem does not need to know any of the K_(S) or even have access to atrusted chip to perform the write, System must follow anon-authenticated write by an authenticated read if it needs to knowthat the write was successful.

The protocol requires the following publicly available function:

-   Write[X] Writes X over those parts of M subject to P₀ and the    existing value for M.

To authenticate a write of M_(new) to ChipA's memory M:

-   a. System calls ChipU's Write function, passing in M_(new);-   b. The authentication procedure for a Read is carried out (see    Section 9.3 on page 671);-   c. If ChipU is authentic and M_(new)=M returned in b, the write    succeeded. If not, it failed.    9.4.2 Authenticated Writes

In this kind of write, System wants to change Chip U's M in anauthorized way, without being subject to the permissions that applyduring normal operation (P₀). For example, the consumable may be at arefilling station and the normally Decrement Only section of M should beupdated to include the new valid consumable. In this case, the chipwhose M is being updated must authenticate the writes being generated bythe external System and in addition, apply the appropriate permissionfor the key to ensure that only the correct parts of M are updated.Having a different permission for each key is required as when multiplekeys are involved, all keys should not necessarily be given open accessto M. For example, suppose M contains printer speed and a counter ofmoney available for franking. A ChipS that updates printer speed shouldnot be capable of updating the amount of money. Since P₀ is used fornon-authenticated writes, each K_(n) has a corresponding permissionP_(n+1) that determines what can be updated in an authenticated write.

In this transaction protocol, the System's chip is referred to as ChipS,and the chip being updated is referred to as ChipU. Each chip distruststhe other. The protocol requires the following publicly availablefunction in ChipU: Read[n, X] Advances R, and returns R, M,S_(Kn)[X|R|C₁|M]. The time taken to calculate the signature must not bebased on the contents of X, R, M, or K. WriteA[n, X, Y, Z] Advances R,replaces M by Y subject to P_(n+1), and returns 1 only ifS_(Kn)[R|X|C₁|Y] = Z. Otherwise returns 0. The time taken to calculateand compare signatures must be independent of data content. Thisfunction is identical to ChipT's Test function except that itadditionally writes Y subject to P_(n+1) to its M when the signaturematches. Authenticated writes require that the System has access to aChipS that is capable of generating appropriate signatures. ChipSrequires the following variables and function: CountRemaining Part of Mthat contains the number of signatures that ChipS is allowed togenerate. Decrements with each successful call to SignM and SignP.Permissions in ChipS's P₀ for this part of M needs to be ReadOnly onceChipS has been setup. Therefore CountRemaining can only be updated byanother ChipS that will perform updates to that part of M (assumingChipS's P allows that part of M to be updated). Q Part of M thatcontains the write permissions for updating ChipU's M. By adding Q toChipS we allow different ChipSs that can update different parts ofM_(U). Permissions in ChipS's P₀ for this part of M needs to be ReadOnlyonce ChipS has been setup. Therefore Q can only be updated by anotherChipS that will perform updates to that part of M. SignM[n, V, W, X, Y,Z] Advances R, decrements CountRemaining and returns R, Z_(QX) (Zapplied to X with permissions Q), S_(Kn)[W|R|C₁|Z_(QX)] only if Y =S_(Kn)[V|W|C₁|X] and CountRemaining > 0. Otherwise returns all 0s. Thetime taken to calculate and compare signatures must be independent ofdata content.

To update ChipU's M vector:

-   a. System calls ChipU's Read function, passing in n1 and 0 as the    input parameters;-   b. ChipU produces R_(U), M_(U), S_(Kn1)[0|R_(U)|C₁|M_(U)] and    returns these to System;-   c. System calls ChipS's SignM function, passing in n2 (the key to be    used in ChipS), 0 (as used in a), R_(U), M_(U),    S_(Kn1)[0|R_(U)|C₁|M_(U)], and M_(D) (the desired vector to be    written to ChipU);-   d. ChipS produces R_(S), M_(QD) (processed by running M_(D) against    M_(U) using Q) and S_(Kn2)[R_(U)|R_(S)|C₁|M_(QD)] if the inputs were    valID, and 0 for all outputs if the inputs were not valid.-   e. If values returned in d are non zero, then ChipU is considered    authentic. System can then call ChipU's WriteA function with these    values from d.-   f. ChipU should return a 1 to indicate success. A 0 should only be    returned if the data generated by ChipS is incorrect (e.g. a    transmission error).

The choice of n1 and n2 must be such that ChipU's K_(n1)=ChipS's K_(n2).

The data flow for authenticated writes is shown in FIG. 339 below.

Note that Q in ChipS is part of ChipS's M. This allows a user to set upChipS with a permission set for upgrades. This should be done to ChipSand that part of M designated by P₀ set to ReadOnly before ChipS isprogrammed with K_(U). If K_(S) is programmed with K_(U) first, there isa risk of someone obtaining a half-setup ChipS and changing all of M_(U)instead of only the sections specified by Q.

In addition, CountRemaining in ChipS needs to be setup (including makingit ReadOnly in P_(S)) before ChipS is programmed with K_(U). ChipSshould therefore be programmed to only perform a limited number of SignMoperations (thereby limiting compromise exposure if a ChipS is stolen).Thus ChipS would itself need to be upgraded with a new CountRemainingevery so often.

9.4.3 Updating Permissions for Future Writes

In order to reduce exposure to accidental and malicious attacks on P(and certain parts of M), only authorized users are allowed to update P.Writes to P are the same as authorized writes to M, except that theyupdate P_(n) instead of M. Initially (at manufacture), P is set to beRead/Write for all parts of M. As different processes fill up differentparts of M, they can be sealed against future change by updating thepermissions. Updating a chip's P₀ changes permissions for unauthorizedwrites, and updating P_(n+1) changes permissions for authorized writeswith key K_(n).

P_(n) is only allowed to change to be a more restrictive form of itself.For example, initially all parts of M have permissions of Read/Write. Apermission of Read/Write can be updated to Decrement Only or Read Only.A permission of Decrement Only can be updated to become Read Only. ARead Only permission cannot be further restricted.

In this transaction protocol, the System's chip is referred to as ChipS,and the chip being updated is referred to as ChipU. Each chip distruststhe other.

The protocol requires the following publicly available functions inChipU:

-   Random    Returns R (does not advance R).-   SetPermission[n,p,X,Y,Z] Advances R, and updates P_(p) according to    Y and returns 1 followed by the resultant P_(p) only if    S_(Kn)[R|X|Y|C₂]=Z. Otherwise returns 0. P_(p) can only become more    restricted. Passing in 0 for any permission leaves it unchanged    (passing in Y=0 returns the current P_(p)).

Authenticated writes of permissions require that the System has accessto a ChipS that is capable of generating appropriate signatures. ChipSrequires th following variables and function: CountRemaining Part of Mthat contains the number of signatures that ChipS is allowed togenerate. Decrements with each successful call to SignM and SignP.Permissions in ChipS's P₀ for this part of M needs to be ReadOnly onceChipS has been setup. Therefore CountRemaining can only be updated byanother ChipS that will perform updates to that part of M (assumingChipS's P_(n) allows that part of M to be updated). SignP[n, X, Y]Advances R, decrements CountRemaining and returns R and S_(Kn)[X|R|Y|C₂]only if CountRemaining > 0. Otherwise returns all 0s. The time taken tocalculate and compare signatures must be independent of data content.

To update ChipU's P_(n):

-   a. System calls ChipU's Random function;-   b. ChipU returns R_(U) to System;-   c. System calls ChipS's SignP function, passing in n1, R_(U) and    P_(D) (the desired P to be written to ChipU);-   d. ChipS produces R_(S) and S_(Kn1)[R_(U)|R_(S)|P_(D)|C₂] if it is    still permitted to produce signatures.-   e. If values returned in d are non zero, then System can then call    ChipU's SetPermission function with n2, the desired permission entry    p, R_(S), P_(D) and S_(Kn1)[R_(U)|R_(S)|P_(D)|C₂].-   f. ChipU verifies the received signature against    S_(Kn2)[R_(U)|R_(S)|P_(D)|C₂] and applies P_(D) to P_(n) if the    signature matches-   g. System checks 1st output parameter. 1=success, 0=failure.

The choice of n1 and n2 must be such that ChipU's K_(n1)=ChipS's K_(n2).

The data flow for authenticated writes to permissions is shown in FIG.340 below.

9.4.4 Protecting M in a Multiple Key System

To protect the appropriate part of M, the SetPermission function must becalled after the part of M has been set to the desired value.

For example, if adding a serial number to an area of M that is currentlyReadWrite so that noone is permitted to update the number again:

-   -   the Write function is called to write the serial number to M    -   SetPermission is called for n={1, . . . , N} to set that part of        M to be ReadOnly for authorized writes using key n−1.    -   SetPermission is called for 0 to set that part of M to be        ReadOnly for non-authorized writes

For example, adding a consumable value to M such that only keys 1-2 canupdate it, and keys 0, and 3-N cannot:

-   -   the Write function is called to write the amount of consumable        to M    -   SetPermission is called for n={1, 4, 5, . . . , N−1} to set that        part of M to be ReadOnly for authorized writes using key n−1.        This leaves keys 1 and 2 with ReadWrite permissions.    -   SetPermission is called for 0 to set that part of M to be        DecrementOnly for non-authorized writes. This allows the amount        of consumable to decrement.

It is possible for someone who knows a key to further restrict otherkeys, but it is not in anyone's interest to do so.

9.5 Programming K

In this case, we have a factory chip (ChipF) connected to a System. TheSystem wants to program the key in another chip (ChipP). System wants toavoid passing the new key to ChipP in the clear, and also wants to avoidthe possibility of the key-upgrade message being replayed on anotherChipP (even if the user doesn't know the key).

The protocol is a simple extension of the single key protocol in that itassumes that ChipF and ChipP already share a secret key K_(old). Thiskey is used to ensure that only a chip that knows K_(old) can setK_(new).

The protocol requires the following publicly available functions inChipP:

-   -   Random        Returns R (does not advance R).    -   ReplaceKey[n, X, Y, Z] Replaces K_(n) by S_(Kn)[R|X|C₃]⊕Y,        advances R, and returns 1 only if S_(Kn)[X|Y|C₃]=Z. Otherwise        returns 0. The time taken to calculate signatures and compare        values must be identical for all inputs.

And the following data and functions in ChipF: CountRemaining Part of Mwith contains the number of signatures that ChipF is allowed togenerate. Decrements with each successful call to GetProgramKey.Permissions in P for this part of M needs to be ReadOnly once ChipF hasbeen setup. Therefore can only be updated by a ChipS that has authorityto perform updates to that part of M. K_(new) The new key to betransferred from ChipF to ChipP. Must not be visible. SetPartialKey[X,Y] If word X of K_(new) has not yet been set, set word X of K_(new) to Yand return 1. Otherwise return 0. This function allows K_(new) to beprogrammed in multiple steps, thereby allowing different people orsystems to know different parts of the key (but not the whole K_(new)).K_(new) is stored in ChipF's flash memory. Since there is a small numberof ChipFs, it is theoretically not necessary to store the inverse ofK_(new), but it is stronger protection to do so. GetProgramKey[n, X]Advances R_(F), decrements CountRemaining, outputs R_(F), the encryptedkey S_(Kn)[X|R_(F)|C₃]⊕K_(new) and a signature of the first two outputsplus C₃ if CountRemaining > 0. Otherwise outputs 0. The time tocalculate the encrypted key & signature must be identical for allinputs.

To update P's key:

-   a. System calls ChipP's Random function;-   b. ChipP returns R_(P) to System;-   c. System calls ChipF's GetProgramKey function, passing in n1 (the    desired key to use) and the result from b;-   d. ChipF updates R_(F), then calculates and returns R_(F),    S_(Kn1)[R_(P)|R_(F)|C₃]⊕K_(new), and    S_(Kn1)[R_(F)|S_(Kn1)[R_(P)|R_(F)|C₃]⊕K_(new)|C₃];-   e. If the response from d is not 0, System calls ChipP's ReplaceKey    function, passing in n2 (the key to use in ChipP) and the response    from d;-   f. System checks response from ChipP. If the response is 1, then    K_(Pn2) has been correctly updated to K_(new). If the response is 0,    K_(Pn2) has not been updated.

The choice of n1 and n2 must be such that ChipF's K_(n1)=ChipP's K_(n2).

The data flow for key updates is shown in FIG. 341 below.

Note that K_(new) is never passed in the open. An attacker could sendits own R_(P), but cannot produce S_(Kn1)[R_(P)|R_(F)|C₃] withoutK_(n1). The signature based on K_(new) is sent to ensure that ChipP willbe able to determine if either of the first two parameters have beenchanged en route.

CountRemaining needs to be setup in M_(F) (including making it ReadOnlyin P) before ChipF is programmed with K_(P). ChipF should therefore beprogrammed to only perform a limited number of GetProgramKey operations(thereby limiting compromise exposure if a ChipF is stolen). Anauthorized ChipS can be used to update this counter if neccesary (seeSection 9.4 on page 673).

9.5.1 Chicken and Egg

As with the single key protocol, for the Program Key protocol to work,both ChipF and ChipP must both know K_(old). Obviously both chips had tobe programmed with K_(old), and thus K_(old) can be thought of as anolder K_(new):K_(old) can be placed in chips if another ChipF knowsK_(older), and so on.

Although this process allows a chain of reprogramming of keys, with eachstage secure, at some stage the very first key (K_(first)) must beplaced in the chips. K_(first) is in fact programmed with the chip'smicrocode at the manufacturing test station as the last step inmanufacturing test. K_(first) can be a manufacturing batch key, changedfor each batch or for each customer etc, and can have as short a life asdesired. Compromising K_(first) need not result in a complete compromiseof the chain of Ks.

Depending on the reprogramming requirements, K_(first) can be the sameor different for all K_(n).

10 Multiple Keys Multiple Memory Vectors

10.1 Protocol Background

This protocol set is a slight restriction of the multiple key singlememory vector protocol set, and is the expected protocol. It is arestriction in that M has been optimized for Flash memory utilization.

M is broken into multiple memory vectors (semi-fixed and variablecomponents) for the purposes of optimizing flash memory utilization.Typically M contains some parts that are fixed at some stage of themanufacturing process (eg a batch number, serial number etc), and onceset, are not ever updated. This information does not contain the amountof consumable remaining, and therefore is not read or written to withany great frequency.

We therefore define M₀ to be the M that contains the frequently updatedsections, and the remaining Ms to be rarely written to. Authenticatedwrites only write to M₀, and non-authenticated writes can be directed toa specific M_(n). This reduces the size of permissions that are storedin the QA Chip (since key-based writes are not required for Ms otherthan M₀). It also means that M₀ and the remaining Ms can be manipulatedin different ways, thereby increasing flash memory longevity.

10.2 Requirements of Protocol

Each QA Chip contains the following values:

-   N The maximum number of keys known to the chIP.-   T The number of vectors M is broken into.-   K_(N) Array of N secret keys used for calculating F_(Kn)[X] where    K_(n) is the nth element of the array. Each K_(n) must not be stored    directly in the QA Chip. Instead, each chip needs to store a single    random number R_(K) (different for each chIP), K_(n)⊕R_(K), and    K_(n)⊕R_(K). The stored K_(n)⊕R_(K) XORed with R_(K) to obtain the    real K_(n). Although    K_(n)⊕R_(K) must be stored to protect against differential attacks,    it is not used.-   R Current random number used to ensure time varying messages. Each    chip instance must be seeded with a different initial value. Changes    for each signature generation.-   M_(T) Array of T memory vectors. Only M₀ can be written to with an    authorized write, while all Ms can be written to in an unauthorized    write. Writes to M₀ are optimized for Flash usage, while updates to    any other M_(n) are expensive with regards to Flash utilization, and    are expected to be only performed once per section of M_(n). M₁    contains T and N in ReadOnly form so users of the chip can know    these two values.-   P_(T+N) T+N element array of access permissions for each part of M.    Entries n={0 . . . T−1} hold access permissions for    non-authenticated writes to M_(n) (no key required). Entries n={T to    T+N−1}hold access permissions for authenticated writes to M₀ for    K_(n). Permission choices for each part of M are Read Only,    Read/Write, and Decrement Only.-   C 3 constants used for generating signatures. C₁, C₂, and C₃ are    constants that pad out a submessage to a hashing boundary, and all 3    must be different.

Each QA Chip contains the following private function: S_(Kn)[N, X]Internal function only. Returns S_(Kn)[X], the result of applying adigital signature function S to X based upon the appropriate key K_(n).The digital signature must be long enough to counter the chances ofsomeone generating a random signature. The length depends on thesignature scheme chosen, although the scheme chosen for the QA Chip isHMAC-SHA1, and therefore the length of the signature is 160 bits.

Additional functions are required in certain QA Chips, but these aredescribed as required.

10.3 Reads

As with the previous scenarios, we have a trusted chip (ChipT) connectedto a System. The System wants to authenticate an object that contains anon-trusted chip (ChipA). In effect, the System wants to know that itcan securely read a memory vector (M_(t)) from ChipA: to be sure thatChipA is valid and that M has not been altered.

The protocol requires the following publicly available functions:Random[ ] Returns R (does not advance R). Read[n, t, X] Advances R, andreturns R, M_(t), S_(Kn)[X|R|C₁|M_(t)]. The time taken to calculate thesignature must not be based on the contents of X, R, M_(t), or K. If tis invalid, the function assumes t = 0. Test[n, X, Y, Z] Advances R andreturns 1 if S_(Kn)[R|X|C₁|Y] = Z. Otherwise returns 0. The time takento calculate and compare signatures must be independent of data content.

To authenticate ChipA and read ChipA's memory M:

-   a. System calls ChipT's Random function;-   b. ChipT returns R_(T) to System;-   c. System calls ChipA's Read function, passing in some key number    n1, the desired M number t, and the result from b;-   d. ChipA updates R_(A), then calculates and returns R_(A), M_(At),    S_(KAn1)[R_(T)|R_(A)|C₁|M_(At)];-   e. System calls ChipT's Test function, passing in n2, R_(A), M_(At),    S_(KAn1)[R_(T)|R_(A)|C₁|M_(At)];-   f. System checks response from ChipT. If the response is 1, then    ChipA is considered authentic. If 0, ChipA is considered invalid.

The choice of n1 and n2 must be such that ChipA's K_(n1)=ChipT's K_(n2).

The data flow for read authentication is shown in FIG. 342 below.

The protocol allows System to simply pass data from one chip to another,with no special processing. The protection relies on ChipT beingtrusted, even though System does not know K.

When ChipT is physically separate from System (eg is chip on a boardconnected to System) System must also occassionally (based on systemclock for example) call ChipT's Test function with bad data, expecting a0 response. This is to prevent someone from inserting a fake ChipT intothe system that always returns 1 for the Test function.

It is important that n1 is chosen by System. Otherwise ChipA would needto return NA sets of signatures for each read, since ChipA does not knowwhich of the keys will satisfy ChipT. Similarly, system must also choosen2, so it can potentially restrict the number of keys in ChipT that arematched against (otherwise ChipT would have to match against all itskeys). This is important in order to restrict how different keys areused. For example, say that ChipT contains 6 keys, keys 0-2 are forvarious printer-related upgrades, and keys 3-6 are for inks. ChipAcontains say 4 keys, one key for each printer model. At power-up, Systemgoes through each of chipA's keys 0-3, trying each out against ChipT'skeys 3-6. System doesn't try to match against ChipT's keys 0-2.Otherwise knowledge of a speed-upgrade key could be used to provide inkQA Chip chips. This matching needs to be done only once (eg at powerup). Once matching keys are found, System can continue to use those keynumbers.

Since System needs to know N_(T), N_(A), and T_(A), part of M₁ is usedto hold N (eg in Read Only form), and the system can obtain it bycalling the Read function, passing in key 0 and t=1.

10.4 Writes

As with the previous scenarios, the System wants to update M_(t) inChipU. As before, this can be done in a non-authenticated andauthenticated way.

10.4.1 Non-Authenticated Writes

This is the most frequent type of write, and takes place between theSystem/consumable during normal everyday operation for M₀, and duringthe manufacturing process for M_(t).

In this kind of write, System wants to change M subject to P. Forexample, the System could be decrementing the amount of consumableremaining. Although System does not need to know and of the K_(S) oreven have access to a trusted chip to perform the write, System mustfollow a non-authenticated write by an authenticated read if it needs toknow that the write was successful.

The protocol requires the following publicly available function:

-   -   Write[t, X] Writes X over those parts of M_(t) subject to P_(t)        and the existing value for M.

To authenticate a write of M_(new) to ChipA's memory M:

-   a. System calls ChipU's Write function, passing in M_(new);-   b. The authentication procedure for a Read is carried out (see    Section 9.3 on page 671);-   c. If ChipU is authentic and M_(new)=M returned in b, the write    succeeded. If not, it failed.    10.4.2 Authenticated Writes

In the multiple memory vectors protocol, only M₀ can be written to an anauthenticated way. This is because only M₀ is considered to havecomponents that need to be upgraded.

In this kind of write, System wants to change Chip U's M₀ in anauthorized way, without being subject to the permissions that applyduring normal operation. For example, the consumable may be at arefilling-station and the normally Decrement Only section of M₀ shouldbe updated to include the new valid consumable. In this case, the chipwhose M₀ is being updated must authenticate the writes being generatedby the external System and in addition, apply the appropriate permissionfor the key to ensure that only the correct parts of M₀ are updated.Having a different permission for each key is required as when multiplekeys are involved, all keys should not necessarily be given open accessto M₀. For example, suppose M₀ contains printer speed and a counter ofmoney available for franking. A ChipS that updates printer speed shouldnot be capable of updating the amount of money. Since P_(0 . . . T−1) isused for non-authenticated writes, each K_(n) has a correspondingpermission P_(T+n) that determines what can be updated in anauthenticated write.

In this transaction protocol, the System's chip is referred to as ChipS,and the chip being updated is referred to as ChipU. Each chip distruststhe other.

The protocol requires the following publicly available functions inChipU: Read[n, t, X] Advances R, and returns R, M_(t),S_(Kn)[X|R|C₁|M_(t)]. The time taken to calculate the signature must notbe based on the contents of X, R, M_(t), or K. WriteA[n, X, Y, Z]Advances R, replaces M₀ by Y subject to P_(T+n), and returns 1 only ifS_(Kn)[R|X|C₁|Y] = Z. Otherwise returns 0. The time taken to calculateand compare signatures must be independent of data content. Thisfunction is identical to ChipT's Test function except that itadditionally writes Y subject to P_(T+n) to its M when the signaturematches.

Authenticated writes require that the System has access to a ChipS thatis capable of generating appropriate signatures. ChipS requires thefollowing variables and function: CountRemaining Part of M that containsthe number of signatures that ChipS is allowed to generate. Decrementswith each successful call to SignM and SignP. Permissions in ChipS'sP_(0..T−1) for this part of M needs to be ReadOnly once ChipS has beensetup. Therefore CountRemaining can only be updated by another ChipSthat will perform updates to that part of M (assuming ChipS's P allowsthat part of M to be updated). Q Part of M that contains the writepermissions for updating ChipU's M. By adding Q to ChipS we allowdifferent ChipSs that can update different parts of M_(U). Permissionsin ChipS's P_(0..T−1) for this part of M needs to be ReadOnly once ChipShas been setup. Therefore Q can only be updated by another ChipS thatwill perform updates to that part of M. SignM[n, V, W, X, Y, Z] AdvancesR, decrements CountRemaining and returns R, Z_(QX) (Z applied to X withpermissions Q), S_(Kn)[W|R|C₁|Z_(QX)] only if Y = S_(Kn) [V|W|C₁|X] andCountRemaining > 0. Otherwise returns all 0s. The time taken tocalculate and compare signatures must be independent of data content.

To update ChipU's M vector:

-   a. System calls ChipU's Read function, passing in n1, 0 and 0 as the    input parameters;-   b. ChipU produces R_(U), M_(U0), S_(Kn1)[0|R_(U)|C₁|M_(U0)] and    returns these to System;-   c. System calls ChipS's SignM function, passing in n2 (the key to be    used in ChipS), 0 (as used in a), R_(U), M_(U0),    S_(Kn1)[0|R_(U)|C₁|M_(U0)], and M_(D) (the desired vector to be    written to ChipU);-   d. ChipS produces R_(S), M_(QD) (processed by running M_(D) against    M_(U0) using Q) and S_(Kn2)[R_(U)|R_(S)|C₁|M_(QD)] if the inputs    were valID, and 0 for all outputs if the inputs were not valid.-   e. If values returned in d are non zero, then ChipU is considered    authentic. System can then call ChipU's WriteA function with these    values from d.-   f. ChipU should return a 1 to indicate success. A 0 should only be    returned if the data generated by ChipS is incorrect (e.g. a    transmission error).

The choice of n1 and n2 must be such that ChipU's K_(n1)=ChipS's K_(n2).

The data flow for authenticated writes is shown in FIG. 343 below.

Note that Q in ChipS is part of ChipS's M. This allows a user to set upChipS with a permission set for upgrades. This should be done to ChipSand that part of M designated by P_(0..T−1) set to ReadOnly before ChipSis programmed with K_(U). If K_(S) is programmed with K_(U) first, thereis a risk of someone obtaining a half-setup ChipS and changing all ofM_(U) instead of only the sections specified by Q.

In addition, CountRemaining in ChipS needs to be setup (including makingit ReadOnly in P_(S)) before ChipS is programmed with K_(U). ChipSshould therefore be programmed to only perform a limited number of SignMoperations (thereby limiting compromise exposure if a ChipS is stolen).Thus ChipS would itself need to be upgraded with a new CountRemainingevery so often.

10.4.3 Updating Permissions for Future Writes

In order to reduce exposure to accidental and malicious attacks on P(and certain parts of M), only authorized users are allowed to update P.Writes to P are the same as authorized writes to M, except that theyupdate P_(n) instead of M. Initially (at manufacture), P is set to beRead/Write for all M. As different processes fill up different parts ofM, they can be sealed against future change by updating the permissions.Updating a chip's P_(0..T−1) changes permissions for unauthorized writesto M_(n), and updating P_(T..T+N−1) changes permissions for authorizedwrites with key K_(n).

P_(n) is only allowed to change to be a more restrictive form of itself.For example, initially all parts of M have permissions of Read/Write. Apermission of Read/Write can be updated to Decrement Only or Read Only.A permission of Decrement Only can be updated to become Read Only. ARead Only permission cannot be further restricted.

In this transaction protocol, the System's chip is referred to as ChipS,and the chip being updated is referred to as ChipU. Each chip distruststhe other.

The protocol requires the following publicly available functions inChipU:

-   -   Random        Returns R (does not advance R).    -   SetPermission[n,p,X,Y,Z] Advances R, and updates P_(p) according        to Y and returns 1 followed by the resultant P_(p) only if        S_(Kn)[R|X|Y|C₂]=Z. Otherwise returns 0. P_(p) can only become        more restricted. Passing in 0 for any permission leaves it        unchanged (passing in Y=0 returns the current P_(p)).

Authenticated writes of permissions require that the System has accessto a ChipS that is capable of generating appropriate signatures. ChipSrequires the following variables and function: CountRemaining Part ofChipS's M₀ that contains the number of signatures that ChipS is allowedto generate. Decrements with each successful call to SignM and SignP.Permissions in ChipS's P_(0..T−1) for this part of M₀ needs to beReadOnly once ChipS has been setup. Therefore CountRemaining can only beupdated by another ChipS that will perform updates to that part of M₀(assuming ChipS's P_(n) allows that part of M₀ to be updated). SignP[n,X, Y] Advances R, decrements CountRemaining and returns R andS_(Kn)[X|R|Y|C₂] only if CountRemaining > 0. Otherwise returns all 0s.The time taken to calculate and compare signatures must be independentof data content.

To update ChipU's P_(n):

-   a. System calls ChipU's Random function;-   b. ChipU returns R_(U) to System;-   c. System calls ChipS's SignP function, passing in n1, R_(U) and    P_(D) (the desired P to be written to ChipU);-   d. ChipS produces R_(S) and S_(Kn1)[R_(U)|R_(S)|P_(D)|C₂] if it is    still permitted to produce signatures.-   e. If values returned in d are non zero, then System can then call    ChipU's SetPermission function with n2, the desired permission entry    p, R_(S), P_(D) and S_(Kn1)[R_(U)|R_(S)|P_(D)|C₂].-   f. ChipU verifies the received signature against    S_(Kn2)[R_(U)|R_(S)|P_(D)|C₂] and applies P_(D) to P_(n) if the    signature matches-   g. System checks 1 st output parameter. 1=success, 0=failure.

The choice of n1 and n2 must be such that ChipU's K_(n1)=ChipS's K_(n2).

The data flow for authenticated writes to permissions is shown in FIG.344 below.

10.4.4 Protecting M in a Multiple Key Multiple M System

To protect the appropriate part of M_(n) against unauthorized writes,call SetPermissions[n] for n=0 to T−1. To protect the appropriate partof M₀ against authorized writes with key n, call SetPermissions[T+n] forn=0 to N−1.

Note that only M₀ can be written in an authenticated fashion.

Note that the SetPermission function must be called after the part of Mhas been set to the desired value.

For example, if adding a serial number to an area of M₁ that iscurrently ReadWrite so that noone is permitted to update the numberagain:

-   -   the Write function is called to write the serial number to M₁    -   SetPermission(1) is called for to set that part of M to be        ReadOnly for non-authorized writes.

If adding a consumable value to M₀ such that only keys 1-2 can updateit, and keys 0, and 3-N cannot:

-   -   the Write function is called to write the amount of consumable        to M    -   SetPermission is called for 0 to set that part of M₀ to be        DecrementOnly for non-authorized writes. This allows the amount        of consumable to decrement.    -   SetPermission is called for n={T, T+3, T+4 . . . , T+N−1} to set        that part of M₀ to be ReadOnly for authorized writes using all        but keys 1 and 2. This leaves keys 1 and 2 with ReadWrite        permissions to M₀.

It is possible for someone who knows a key to further restrict otherkeys, but it is not in anyone's interest to do so.

10.5 Programming K

This section is identical to the multiple key single memory vector(Section 9.5 on page 677). It is repeated here with mention to M₀instead of M for CountRemaining.

In this case, we have a factory chip (ChipF) connected to a System. TheSystem wants to program the key in another chip (ChipP). System wants toavoid passing the new key to ChipP in the clear, and also wants to avoidthe possibility of the key-upgrade message being replayed on anotherChipP (even if the user doesn't know the key).

The protocol is a simple extension of the single key protocol in that itassumes that ChipF and ChipP already share a secret key K_(old). Thiskey is used to ensure that only a chip that knows K_(old) can setK_(new).

The protocol requires the following publicly available functions inChipP:

-   -   Random        Returns R (does not advance R).    -   ReplaceKey[n, X, Y, Z] Replaces K_(n) by S_(Kn)[R|X|C₃]⊕Y,        advances R, and returns 1 only if S_(Kn)[X|Y|C₃]=Z. Otherwise        returns 0. The time taken to calculate signatures and compare        values must be identical for all inputs.

And the following data and functions in ChipF: CountRemaining Part of M₀with contains the number of signatures that ChipF is allowed togenerate. Decrements with each successful call to GetProgramKey.Permissions in P for this part of M₀ needs to be ReadOnly once ChipF hasbeen setup. Therefore can only be updated by a ChipS that has authorityto perform updates to that part of M₀. K_(new) The new key to betransferred from ChipF to ChipP. Must not be visible. SetPartialKey[X,Y] If word X of K_(new) has not yet been set, set word X of K_(new) to Yand return 1. Otherwise return 0. This function allows K_(new) to beprogrammed in multiple steps, thereby allowing different people orsystems to know different parts of the key (but not the whole K_(new)).K_(new) is stored in ChipF's flash memory. Since there is a small numberof ChipFs, it is theoretically not necessary to store the inverse ofK_(new), but it is stronger protection to do so. GetProgramKey[n, X]Advances R_(F), decrements CountRemaining, outputs R_(F), the encryptedkey S_(Kn)[X|R_(F)|C₃]⊕K_(new) and a signature of the first two outputsplus C₃ if CountRemaining > 0. Otherwise outputs 0. The time tocalculate the encrypted key & signature must be identical for allinputs.

To update P's key:

-   a. System calls ChipP's Random function;-   b. ChipP returns R_(P) to System;-   c. System calls ChipF's GetProgramKey function, passing in n1 (the    desired key to use) and the result from b;-   d. ChipF updates R_(F), then calculates and returns R_(F),    S_(Kn1)[R_(P)|R_(F)|C₃]⊕K_(new), and    S_(Kn1)[R_(F)|S_(Kn1)[R_(P)|R_(F)|C₃]⊕K_(new)|C₃];-   e. If the response from d is not 0, System calls ChipP's ReplaceKey    function, passing in n2 (the key to use in ChipP) and the response    from d;-   f. System checks response from ChipP. If the response is 1, then    K_(Pn2) has been correctly updated to K_(new). If the response is 0,    K_(Pn2) has not been updated.

The choice of n1 and n2 must be such that ChipF's K_(n1)=ChipP's K_(n2).

The data flow for key updates is shown in FIG. 345 below.

Note that K_(new) is never passed in the open. An attacker could sendits own R_(P), but cannot produce S_(Kn1)[R_(P)|R_(F)|C₃] withoutK_(n1). The signature based on K_(new) is sent to ensure that ChipP willbe able to determine if either of the first two parameters have beenchanged en route.

CountRemaining needs to be setup in M_(F0) (including making it ReadOnlyin P) before ChipF is programmed with K_(P). ChipF should therefore beprogrammed to only perform a limited number of GetProgramKey operations(thereby limiting compromise exposure if a ChipF is stolen). Anauthorized ChipS can be used to update this counter if neccesary (seeSection 9.4 on page 673).

10.5.1 Chicken and Egg

As with the single key protocol, for the Program Key protocol to work,both ChipF and ChipP must both know K_(old). Obviously both chips had tobe programmed with K_(old), and thus K_(old) can be thought of as anolder K_(new):K_(old) can be placed in chips if another ChipF knowsK_(older), and so on.

Although this process allows a chain of reprogramming of keys, with eachstage secure, at some stage the very first key (K_(first)) must beplaced in the chips. K_(first) is in fact programmed with the chip'smicrocode at the manufacturing test station as the last step inmanufacturing test. K_(first) can be a manufacturing batch key, changedfor each batch or for each customer etc, and can have as short a life asdesired. Compromising K_(first) need not result in a complete compromiseof the chain of Ks. Depending on reprogramming requirements, K_(first)can be the same or different for all K_(n).

10.5.2 Security Note

Different ChipFs should have different R_(F) values to prevent K_(new)from being determined as follows: The attacker needs 2 ChipFs, both withthe same R_(F) and K_(n) but different values for K_(new). By knowingK_(new1) the attacker can determine K_(new2). The size of R_(F) is 2¹⁶⁰,and assuming a lifespan of approximately 2³² R_(S), an attacker needsabout 2⁶⁰ ChipFs with the same K_(n) to locate the correct chIP. Giventhat there are likely to be only hundreds of ChipFs with the same K_(n),this is not a likely attack. The attack can be eliminated completely bymaking C₃ different per chip and transmitting it with the new signature.

11 Summary of Functions for All Protocols

All protocol sets, whether single key, multiple key, single M ormultiple M, all rely on the same set of functions. The function set islisted here:

11.1 All Chips

Since every chip must act as ChipP, ChipA and potentially ChipU, allchips require the following functions:

-   -   Random    -   ReplaceKey    -   Read    -   Write    -   WriteA    -   SetPermissions        11.2 ChipT

Chips that are to be used as ChipT also require:

-   -   Test        11.3 ChipS

Chips that are to be used as ChipS also require either or both of:

-   -   SignM    -   SignP        11.4 ChipF

Chips that are to be used as ChipF also require:

-   -   SetPartialKey    -   GetProgramKey        12 Remote Upgrades        12.1 Basic Remote Upgrades

Regardless of the number of keys and the number of memory vectors, theuse of authenticated reads and writes, and of replacing a new keywithout revealing K_(new) or K_(old) allows the possibility of remoteupgrades of ChipU and ChipP. The upgrade typically involves a remoteserver and follows two basic steps:

-   a. During the first stage of the upgrade, the remote system    authenticates the user's system to ensure the user's system has the    setup that it claims to have.-   b. During the second stage of the upgrade, the user's system    authenticates the remote system to ensure that the upgrade is from a    trusted source.    12.1.1 User Requests Upgrade

The user requests that he wants to upgrade. This can be done by runninga specific upgrade application on the user's computer, or by visiting aspecific website.

12.1.2 Remote System Gathers Info Securely About User's Current Setup

In this step, the remote system determines the current setup for theuser. The current setup must be authenticated, to ensure that the usertruly has the setup that is claimed. Traditionally, this has been bychecking the existence of files, generating checksums from those files,or by getting a serial number from a hardware dongle, although thesetraditional methods have difficulties since they can be generatedlocally by “hacked” software.

The authenticated read protocol described in Section 8.3 on page 664 canbe used to accomplish this step. The use of random numbers has theadvantage that the local user cannot capture a successful transactionand play it back on another computer system to fool the remote system.

12.1.3 Remote System Gives User Choice of Upgrade Possibilities & UserChooses

If there is more than one upgrade possibility, the various upgradeoptions are now presented to the user. The upgrade options could varybased on a number of factors, including, but not limited to:

-   -   current user setup    -   user's preference for payment schemes (e.g. single payment vs.        multiple payment)    -   number of other products owned by user

The user selects an appropriate upgrade and pays if necessary (by somescheme such as via a secure web site). What is important to note here isthat the user chooses a specific upgrade and commences the upgradeoperation.

12.1.4 Remote System Sends Upgrade Request to Local System

The remote system now instructs the local system to perform the upgrade.However, the local system can only accept an upgrade from the remotesystem if the remote system is also authenticated. This is effectivelyan authenticated write. The use of R_(U) in the signature prevents theupgrade message from being replayed on another ChipU.

If multiple keys are used, and each chip has a unique key, the remotesystem can use a serial number obtained from the current setup(authenticated by a common key) to lookup the unique key for use in theupgrade. Although the random number provides time varying messages, useof an unknown K that is different for each chip means that collectionand examination of messages and their signatures is made even moredifficult.

12.2 OEM Upgrades

OEM upgrades are effectively the same as remote upgrades, except thatthe user interacts with an OEM server for upgrade selection. The OEMserver may send sub-requests to the manufacturer's remote server toprovide authentication, upgrade availability lists, and base-levelpricing information.

An additional level of authentication may be incorporated into theprotocol to ensure that upgrade requests are coming from the OEM server,and not from a 3rd party. This can readily be incorporated into bothauthentication steps.

13 Choice of Signature Function

Given that all protocols make use of keyed signature functions, thechoice of function is examined here.

Table 232 outlines the attributes of the applicable choices (see Section5.2 on page 629 and Section 5.5 on page 636 for more information). Theattributes are phrased so that the attribute is seen as an advantage.TABLE 232 Attributes of Applicable Signature Functions Triple RandomHMAC- HMAC- HMAC- DES Blowfish RC5 IDEA Sequences MD5 SHA1 RIPEMD160Free of patents ● ● ● ● ● ● Random key generation ● ● ● Can be exportedfrom the ● ● ● ● USA Fast ● ● ● ● Preferred Key Size (bits)  168¹ 128128 128 512 128 160 160 for use in this application Block size (bits) 64  64  64  64 256 512 512 512 Cryptanalysis Attack-Free ● ● ● ● ●(apart from weak keys) Output size given input ≧N ≧N ≧N ≧N 128 128 160160 size N Low storage requirements ● ● ● ● Low silicon complexity ● ● ●● NSA designed ● ●¹Only gives protection equivalent to 112-bit DES

An examination of Table 232 shows that the choice is effectively betweenthe 3 HMAC constructs and the Random Sequence. The problem of key sizeand key generation eliminates the Random Sequence. Given that a numberof attacks have already been carried out on MD5 and since the hashresult is only 128 bits, HMAC-MD5 is also eliminated. The choice istherefore between HMAC-SHA1 and HMAC-RIPEMD160. Of these, SHA-1 is thepreferred function, since:

-   -   SHA-1 has been more extensively cryptanalyzed without being        broken;    -   SHA-1 requires slightly less intermediate storage than        RIPE-MD-160;    -   SHA-1 is algorithmically less complex than RIPE-MD-160;

Although SHA-1 is slightly faster than RIPE-MD-160, this was not areason for choosing SHA-1.

13.1 HMAC-SHA1

The mechanism for authentication is the HMAC-SHA1 algorithm. Thissection examines the HMAC-SHA1 algorithm in greater detail than coveredso far, and describes an optimization of the algorithm that requiresfewer memory resources than the original definition.

13.1.1 HMAC

Given the following definitions: H = the hash function (e.g. MD5 orSHA-1) n = number of bits output from H (e.g. 160 for SHA-1, 128 bitsfor MD5) M = the data to which the MAC function is to be applied K = thesecret key shared by the two parties ipad = 0x36 repeated 64 times opad= 0x5C repeated 64 times

The HMAC algorithm is as follows:

-   a. Extend K to 64 bytes by appending 0×00 bytes to the end of K-   b. XOR the 64 byte string created in (1) with ipad-   c. append data stream M to the 64 byte string created in (2)-   d. Apply H to the stream generated in (3)-   e. XOR the 64 byte string created in (1) with opad-   f. Append the H result from (4) to the 64 byte string resulting from    (5)-   g. Apply H to the output of (6) and output the result

Thus:HMAC[M]=H[(K ⊕ opad)|H[(K ⊕ ipad)|M]]

-   -   The HMAC-SHA1 algorithm is simply HMAC with H=SHA-1.        13.1.2 SHA-1

The SHA1 hashing algorithm is described in the context of other hashingalgorithms in Section 5.5.3.3 on page 640, and completely defined in[28]. The algorithm is summarized here.

Nine 32-bit constants are defined in Table 233. There are 5 constantsused to initialize the chaining variables, and there are 4 additiveconstants. TABLE 233 Constants used in SHA-1 Initial Additive ChainingValues Constants h₁ 0x67452301 y₁ 0x5A827999 h₂ 0xEFCDAB89 y₂ 0x6ED9EBA1h₃ 0x98BADCFE y₃ 0x8F1BBCDC h₄ 0x10325476 y₄ 0xCA62C1D6 h₅ 0xC3D2E1F0

Non-optimized SHA-1 requires a total of 2912 bits of data storage:

-   -   Five 32-bit chaining variables are defined: H₁, H₂, H₃, H₄ and        H₅.    -   Five 32-bit working variables are defined: A, B, C, D, and E.    -   One 32-bit temporary variable is defined: t.    -   Eighty 32-bit temporary registers are defined: X₀₋₇₉.

The following functions are defined for SHA-1: TABLE 234 Functions usedin SHA-1 Symbolic Nomenclature Description + Addition modulo 2³² X << YResult of rotating X left through Y bit positions f(X, Y, Z) (X

Y)

(

X

Z) g(X, Y, Z) (X

Y)

(X

Z)

(Y

Z) h(X, Y, Z) X ⊕ Y ⊕ Z

The hashing algorithm consists of firstly padding the input message tobe a multiple of 512 bits and initializing the chaining variables H₁₋₅with h₁₋₅. The padded message is then processed in 512-bit chunks, withthe output hash value being the final 160-bit value given by theconcatenation of the chaining variables: H₁|H₂|H₃|H₄|H₅.

The steps of the SHA-1 algorithm are now examined in greater detail.

13.1.2.1 Step 1. Preprocessing

The first step of SHA-1 is to pad the input message to be a multiple of512 bits as follows and to initialize the chaining variables. TABLE 235Steps to follow to preprocess the input message Pad the input messageAppend a 1 bit to the message Append 0 bits such that the length of thepadded message is 64-bits short of a multiple of 512 bits. Append a64-bit value containing the length in bits of the original inputmessage. Store the length as most significant bit through to leastsignificant bit. Initialize the chaining H₁

h₁, H₂

h₂, H₃

h₃, H₄

h₄, variables H₅

h₅13.1.2.2 Step 2. Processing

The padded input message is processed in 512-bit blocks. Each 512-bitblock is in the form of 16 32-bit words, referred to as InputWord₀₋₁₅.TABLE 236 Steps to follow for each 512 bit block (InputWord₀₋₁₅) Copythe 512 input For j = 0 to 15 bits into X₀₋₁₅  X_(j) = InputWord_(j)Expand X₀₋₁₅ into For j = 16 to 79 X₁₆₋₇₉  Xj

((X_(j−3) ⊕ X_(j−8) ⊕ X_(j−14) ⊕ X_(j−16)) << 1) Initialize working A

H₁, B

H₂, C

H₃, D

H₄, variables E

H₅ Round 1 For j = 0 to 19  t

((A << 5) + f(B, C, D) + E + Xj + y₁)  E

D, D

C, C

(B << 30), B

A,  A

t Round 2 For j = 20 to 39  t

((A << 5) + h(B, C, D) + E + Xj + y₂)  E

D, D

C, C

(B << 30), B

A,  A

t Round 3 For j = 40 to 59  t

((A << 5) + g(B, C, D) + E + Xj + y₃)  E

D, D

C, C

(B << 30), B

A,  A

t Round 4 For j = 60 to 79  t

((A << 5) + h(B, C, D) + E + Xj + y₄)  E

D, D

C, C

(B << 30), B

A,  A

t Update chaining H₁

H₁ + A, H₂

H₂ + B, variables H₃

H₃ + C, H₄

H₄ + D, H₅

H₅ + E

The bold text is to emphasize the differences between each round.

13.1.2.3 Step 3. Completion

After all the 512-bit blocks of the padded input message have beenprocessed, the output hash value is the final 160-bit value given by:H₁|H₂|H₃|H₄|H₅.

13.1.2.4 Optimization for Hardware Implementation

The SHA-1 Step 2 procedure is not optimized for hardware. In particular,the 80 temporary 32-bit registers use up valuable silicon on a hardwareimplementation. This section describes an optimization to the SHA-1algorithm that only uses 16 temporary registers. The reduction insilicon is from 2560 bits down to 512 bits, a saving of over 2000 bits.It may not be important in some applications, but in the QA Chip storagespace must be reduced where possible.

The optimization is based on the fact that although the original 16-wordmessage block is expanded into an 80-word message block, the 80 wordsare not updated during the algorithm. In addition, the words rely on theprevious 16 words only, and hence the expanded words can be calculatedon-the-fly during processing, as long as we keep 16 words for thebackward references. We require rotating counters to keep track of whichregister we are up to using, but the effect is to save a large amount ofstorage.

Rather than index X by a single value j, we use a 5 bit counter to countthrough the iterations. This can be achieved by initializing a 5-bitregister with either 16 or 20, and decrementing it until it reaches 0.In order to update the 16 temporary variables as if they were 80, werequire 4 indexes, each a 4-bit register. All 4 indexes increment (withwraparound) during the course of the algorithm. TABLE 237 OptimisedSteps to follow for each 512 bit block (InputWord₀₋₁₅) Initializeworking A

H₁, B

H₂, C

H₃, D

H₄, variables E

H₅ N₁

13, N₂

8, N₃

2, N₄

0 Round 0 Do 16 times Copy the 512 input X_(N4) = InputWord_(N4) bitsinto X₀₋₁₅ [

N₁,

N₂,

N₃]_(optional)

N₄ Round 1A Do 16 times t

((A << 5) + f(B, C, D) + E + X_(N4) + y₁) [

N₁,

N₂,

N₃]_(optional)

N₄ E

D, D

C, C

(B << 30), B

A, A

t Round 1B Do 4 times X_(N4)

((X_(N1) ⊕ X_(N2) ⊕ X_(N3) ⊕ X_(N4)) << 1) t

((A << 5) + f(B, C, D) + E + X_(N4) + y₁)

N₁,

N₂,

N₃,

N₄ E

D, D

C, C

(B << 30), B

A, A

t Round 2 Do 20 times X_(N4)

((X_(N1) ⊕ X_(N2) ⊕ X_(N3) ⊕ X_(N4)) << 1) t

((A << 5) + h(B, C, D) + E + X_(N4) + y₂)

N₁,

N₂,

N₃,

N₄ E

D, D

C, C

(B << 30), B

A, A

t Round 3 Do 20 times X_(N4)

((X_(N1) ⊕ X_(N2) ⊕ X_(N3) ⊕ X_(N4)) << 1) t

((A << 5) + g(B, C, D) + E + X_(N4) + y₃)

N₁,

N₂,

N₃,

N₄ E

D, D

C, C

(B << 30), B

A, A

t Round 4 Do 20 times X_(N4)

((X_(N1) ⊕ X_(N2) ⊕ X_(N3) ⊕ X_(N4)) << 1) t

((A << 5) + h(B, C, D) + E + X_(N4) + y₄)

N₁,

N₂,

N₃,

N₄ E

D, D

C, C

(B << 30), B

A, A

t Update chaining H₁

H₁ + A, H₂

H₂ + B, variables H₃

H₃ + C, H₄

H₄ + D, H₅

H₅ + E

The bold text is to emphasize the differences between each round.

The incrementing of N₁, N₂, and N₃ during Rounds 0 and 1A is optional. Asoftware implementation would not increment them, since it takes time,and at the end of the 16 times through the loop, all 4 counters will betheir original values. Designers of hardware may wish to increment all 4counters together to save on control logic.

Round 0 can be completely omitted if the caller loads the 512 bits ofX₀₋₁₅.

14 Holding Out Against Attacks

The authentication protocols described in Section 7 on page 661 onwardshould be resistant to defeat by logical means. This section detailseach type of attack in turn with reference to the Read Authenticationprotocol.

14.1 Brute Force Attack

A brute force attack is guaranteed to break any protocol. However thelength of the key means that the time for an attacker to perform a bruteforce attack is too long to be worth the effort.

An attacker only needs to break K to build a clone authentication chIP.A brute force attack on K must therefore break a 160-bit key.

An attack against K requires a maximum of 2¹⁶⁰ attempts, with a 50%chance of finding the key after only 2¹⁵⁹ attempts. Assuming an array ofa trillion processors, each running one million tests per second, 2¹⁵⁹(7.3×10⁴⁷) tests takes 2.3×10²² years, which is longer than the totallifetime of the universe. There are around 100 million personalcomputers in the world. Even if these were all connected in an attack(e.g. via the Internet), this number is still 10,000 times smaller thanthe trillion-processor attack described. Further, if the manufacture ofone trillion processors becomes a possibility in the age ofnanocomputers, the time taken to obtain the key is still longer than thetotal lifetime of the universe.

14.2 Guessing the Key Attack

It is theoretically possible that an attacker can simply “guess thekey”. In fact, given enough time, and trying every possible number, anattacker will obtain the key. This is identical to the brute forceattack described above, where 2¹⁵⁹ attempts must be made before a 50%chance of success is obtained.

The chances of someone simply guessing the key on the first try is 2¹⁶⁰.For comparison, the chance of someone winning the top prize in a U.S.state lottery and being killed by lightning in the same day is only 1 in2⁶¹ (78]. The chance of someone guessing the authentication chip key onthe first go is 1 in 2¹⁶⁰, which is comparable to two people choosingexactly the same atoms from a choice of all the atoms in the Earth i.e.extremely unlikely.

14.3 Quantum Computer Attack

To break K, a quantum computer containing 160 qubits embedded in anappropriate algorithm must be built. As described in Section 5.7.1.7 onpage 648, an attack against a 160-bit key is not feasible. An outsideestimate of the possibility of quantum computers is that 50 qubits maybe achievable within 50 years. Even using a 50 qubit quantum computer,2¹¹⁰ tests are required to crack a 160 bit key. Assuming an array of 1billion 50 qubit quantum computers, each able to try 2⁵⁰ keys in 1microsecond (beyond the current wildest estimates) finding the key wouldtake an average of 18 billion years.

14.4 Ciphertext Only Attack

An attacker can launch a ciphertext only attack on K by monitoring callsto Random and Read.

However, given that all these calls also reveal the plaintext as well asthe hashed form of the plaintext, the attack would be transformed into astronger form of attack—a known plaintext attack.

14.5 Known Plaintext Attack

It is easy to connect a logic analyzer to the connection between theSystem and the authentication chip, and thereby monitor the flow ofdata. This flow of data results in known plaintext and the hashed formof the plaintext, which can therefore be used to launch a knownplaintext attack against K.

To launch an attack against K, multiple calls to Random and Test must bemade (with the call to Test being successful, and therefore requiring acall to Read on a valid chIP). This is straightforward, requiring theattacker to have both a system authentication chip and a consumableauthentication chIP. For each set of calls, an X, S_(K)[X] pair isrevealed. The attacker must collect these pairs for further analysis.

The question arises of how many pairs must be collected for a meaningfulattack to be launched with this data. An example of an attack thatrequires collection of data for statistical analysis is differentialcryptanalysis (see Section 14.13 on page 703). However, there are noknown attacks against SHA-1 or HMAC-SHA1 [7][7][7], so there is no usefor the collected data at this time.

14.6 Chosen Plaintext Attacks

The golden rule for the QA Chip is that it never signs something that issimply given to it—i.e. it never lets the user choose the message thatis signed.

Although the attacker can choose both R_(T) and possibly M, ChipAadvances its random number R_(A) with each call to Read. The resultantmessage X therefore contains 160 bits of changing data each call thatare not chosen by the attacker.

To launch a chosen text attack the attacker would need to locate a chipwhose R was the desired R. This makes the search effectively impossible.

14.7 Adaptive Chosen Plaintext Attacks

The HMAC construct provides security against all forms of chosenplaintext attacks [7]. This is primarily because the HMAC construct has2 secret input variables (the result of the original hash, and thesecret key). Thus finding collisions in the hash function itself whenthe input variable is secret is even harder than finding collisions inthe plain hash function. This is because the former requires directaccess to SHA-1 in order to generate pairs of input/output from SHA-1.

Since R changes with each call to Read, the user cannot choose thecomplete message. The only value that can be collected by an attacker isHMAC[R₁|R₂|M₂]. These are not attacks against the SHA-1 hash functionitself, and reduce the attack to a differential cryptanalysis attack(see Section 14.13 on page 703), examining statistical differencesbetween collected data. Given that there is no differentialcryptanalysis attack known against SHA-1 or HMAC, the protocols areresistant to the adaptive chosen plaintext attacks.

14.8 Purposeful Error Attack

An attacker can only launch a purposeful error attack on the Testfunction, since this is the only function in the Read protocol thatvalidates input against the keys.

With the Test function, a 0 value is produced if an error is found inthe input—no further information is given. In addition, the time takento produce the 0 result is independent of the input, giving the attackerno information about which bit(s) were wrong.

A purposeful error attack is therefore fruitless.

14.9 Chaining Attack

Any form of chaining attack assumes that the message to be hashed isover several blocks, or the input variables can somehow be set. TheHMAC-SHA1 algorithm used by Protocol C1 only ever hashes one or two512-bit blocks. Chaining attacks are not possible when only one block isused, and are extremely limited when two blocks are used.

14.10 Birthday Attack

The strongest attack known against HMAC is the birthday attack, based onthe frequency of collisions for the hash function [7][7]. However thisis totally impractical for minimally reasonable hash functions such asSHA-1. And the birthday attack is only possible when the attacker hascontrol over the message that is hashed.

Since in the protocols described for the QA Chip, the message to besigned is never chosen by the attacker (at least one 160-bit R value ischosen by the chip doing the signing), the attacker has no control overthe message that is hashed. An attacker must instead search for acollision message that hashes to the same value (analogous to findingone person who shares your birthday).

The clone chip must therefore attempt to find a new value R₂ such thatthe hash of R₁, R₂ and a chosen M₂ yields the same hash value asH[R₁|R₂|M]. However ChipT does not reveal the correct hash value (theTest function only returns 1 or 0 depending on whether the hash value iscorrect).

Therefore the only way of finding out the correct hash value (in orderto find a collision) is to interrogate a real ChipA. But to find thecorrect value means to update M, and since the decrement-only parts of Mare one-way, and the read-only parts of M cannot be changed, a cloneconsumable would have to update a real consumable before attempting tofind a collision. The alternative is a brute force attack search on theTest function to find a success (requiring each clone consumable to haveaccess to a System consumable). A brute force search, as describedabove, takes longer than the lifetime of the universe, in this case, perauthentication.

There is no point for a clone consumable to launch this kind of attack.

14.11 Substitution with a Complete Lookup Table

The random number seed in each System is 160 bits. The best casesituation for an attacker is that no state data has been changed.Assuming also that the clone consumable does not advance its R, there isa constant value returned as M. A clone chip must therefore returnS_(K)[R|c] (where c is a constant), which is a 160 bit value.

Assuming a 160-bit lookup of a 160-bit result, this requires 2.9×10⁴⁹bytes, or 2.6×10³⁷ terabytes, certainly more space than is feasible forthe near future. This of course does not even take into account themethod of collecting the values for the ROM. A complete lookup table istherefore completely impossible.

14.12 Substitution with a Sparse Lookup Table

A sparse lookup table is only feasible if the messages sent to theauthentication chip are somehow predictable, rather than effectivelyrandom.

The random number R is seeded with an unknown random number, gatheredfrom a naturally System authentication chip's Random function, anditerating some random event. There is no possibility for a clonemanufacturer to know what the possible range of R is for all Systems,since each bit has an unrelated chance of being 1 or 0.

Since the range of R in all systems is unknown, it is not possible tobuild a sparse lookup table that can be used in all systems. The generalsparse lookup table is therefore not a possible attack.

However, it is possible for a clone manufacturer to know what the rangeof R is for a given System. This can be accomplished by loading a LFSRwith the current result from a call to a specific number of times intothe future. If this is done, a special ROM can be built which will onlycontain the responses for that particular range of R, i.e. a ROMspecifically for the consumables of that particular System. But theattacker still needs to place correct information in the ROM. Theattacker will therefore need to find a valid authentication chip andcall it for each of the values in R. Suppose the clone authenticationchip reports a full consumable, and then allows a single use beforesimulating loss of connection and insertion of a new full consumable.The clone consumable would therefore need to contain responses forauthentication of a full consumable and authentication of a partiallyused consumable. The worst case ROM contains entries for full andpartially used consumables for R over the lifetime of System. However, avalid authentication chip must be used to generate the information, andbe partially used in the process. If a given System only produces nR-values, the sparse lookup-ROM required is 20n bytes (20=160/8)multiplied by the number of different values for M. The time taken tobuild the ROM depends on the amount of time enforced between calls toRead.

After all this, the clone manufacturer must rely on the consumerreturning for a refill, since the cost of building the ROM in the firstplace consumes a single consumable. The clone manufacturer's business insuch a situation is consequently in the refills.

The time and cost then, depends on the size of R and the number ofdifferent values for M that must be incorporated in the lookup. Inaddition, a custom clone consumable ROM must be built to match each andevery System, and a different valid authentication chip must be used foreach System (in order to provide the full and partially used data). Theuse of an authentication chip in a System must therefore be examined todetermine whether or not this kind of attack is worthwhile for a clonemanufacturer.

As an example, of a camera system that has about 10,000 prints in itslifetime. Assume it has a single Decrement Only value (number of printsremaining), and a delay of 1 second between calls to Read. In such asystem, the sparse table will take about 3 hours to build, and consumes100K. Remember that the construction of the ROM requires the consumptionof a valid authentication chip, so any money charged must be worth morethan a single consumable and the clone consumable combined. Thus it isnot cost effective to perform this function for a single consumable(unless the clone consumable somehow contained the equivalent ofmultiple authentic consumables).

If a clone manufacturer is going to go to the trouble of building acustom ROM for each owner of a System, an easier approach would be toupdate System to completely ignore the authentication chIP.

Consequently, this attack is possible as a per-System attack, and adecision must be made about the chance of this occurring for a givenSystem/Consumable combination. The chance will depend on the cost of theconsumable and authentication chips, the longevity of the consumable,the profit margin on the consumable, the time taken to generate the ROM,the size of the resultant ROM, and whether customers will come back tothe clone manufacturer for refills that use the same clone chip etc.

14.13 Differential Cryptanalysis

Existing differential attacks are heavily dependent on the structure ofS boxes, as used in DES and other similar algorithms. Although HMAC-SHA1has no S boxes, an attacker can undertake a differential-like attack byundertaking statistical analysis of:

-   -   Minimal-difference inputs, and their corresponding outputs    -   Minimal-difference outputs, and their corresponding inputs

To launch an attack of this nature, sets of input/output pairs must becollected. The collection can be via known plaintext, or from apartially adaptive chosen plaintext attack. Obviously the latter, beingchosen, will be more useful.

Hashing algorithms in general are designed to be resistant todifferential analysis. SHA-1 in particular has been specificallystrengthened, especially by the 80 word expansion so that minimaldifferences in input will still produce outputs that vary in a largernumber of bit positions (compared to 128 bit hash functions). Inaddition, the information collected is not a direct SHA-1 input/outputset, due to the nature of the HMAC algorithm. The HMAC algorithm hashesa known value with an unknown value (the key), and the result of thishash is then rehashed with a separate unknown value. Since the attackerdoes not know the secret value, nor the result of the first hash, theinputs and outputs from SHA-1 are not known, making any differentialattack extremely difficult.

There are no known differential attacks against SHA-1 or HMAC-SHA-1[56][56].

The following is a more detailed discussion of minimally differentinputs and outputs from the QA ChIP.

14.13.1 Minimal Difference Inputs

This is where an attacker takes a set of X, S_(K)[X] values where the Xvalues are minimally different, and examines the statistical differencesbetween the outputs S_(K)[X]. The attack relies on X values that onlydiffer by a minimal number of bits. The question then arises as to howto obtain minimally different X values in order to compare the S_(K)[X]values.

Although the attacker can choose both R_(T) and possibly M, ChipAadvances its random number R_(A) with each call to Read. The resultant Xtherefore contains 160 bits of changing data each call, and is thereforenot minimally different.

14.13.2 Minimal Difference Outputs

This is where an attacker takes a set of X, S_(K)[X] values where theS_(K)[X] values are minimally different, and examines the statisticaldifferences between the X values. The attack relies on S_(K)[X] valuesthat only differ by a minimal number of bits.

There is no way for an attacker to generate an X value for a givenS_(K)[X]. To do so would violate the fact that S is a one-way function(HMAC-SHA1). Consequently the only way for an attacker to mount anattack of this nature is to record all observed X, S_(K)[X] pairs in atable. A search must then be made through the observed values for enoughminimally different S_(K)[X] values to undertake a statistical analysisof the X values.

14.14 Message Substitution Attacks

In order for this kind of attack to be carried out, a clone consumablemust contain a real authentication chip, but one that is effectivelyreusable since it never gets decremented. The clone authentication chipwould intercept messages, and substitute its own. However this attackdoes not give success to the attacker.

A clone authentication chip may choose not to pass on a Write command tothe real authentication chIP. However the subsequent Read command mustreturn the correct response (as if the Write had succeeded). To returnthe correct response, the hash value must be known for the specific Rand M. An attacker can only determine the hash value by actuallyupdating M in a real Chip, which the attacker does not want to do. Evenchanging the R sent by System does not help since the Systemauthentication chip must match the R during a subsequent Test.

A message substitution attack would therefore be unsuccessful. This isonly true if System updates the amount of consumable remaining before itis used.

14.15 Reverse Engineering the Key Generator

If a pseudo-random number generator is used to generate keys, there isthe potential for a clone manufacture to obtain the generator program orto deduce the random seed used. This was the way in which the securitylayer of the Netscape browser was initially broken [33].

14.16 Bypassing the Authentication Process

The System should ideally update the consumable state data before theconsumable is used, and follow every write by a read (to authenticatethe write). Thus each use of the consumable requires an authentication.If the System adheres to these two simple rules, a clone manufacturerwill have to simulate authentication via a method above (such as sparseROM lookup).

14.17 Reuse of Authentication Chips

Each use of the consumable requires an authentication. If a consumablehas been used up, then its authentication chip will have had theappropriate state-data values decremented to 0. The chip can thereforenot be used in another consumable.

Note that this only holds true for authentication chips that holdDecrement-Only data items. If there is no state data decremented witheach usage, there is nothing stopping the reuse of the chIP. This is thebasic difference between Presence-Only authentication and ConsumableLifetime authentication. All described protocols allow both.

The bottom line is that if a consumable has Decrement Only data itemsthat are used by the System, the authentication chip cannot be reusedwithout being completely reprogrammed by a valid programming stationthat has knowledge of the secret key (e.g. an authorized refillstation).

14.18 Management Decision to Omit Authentication to Save Costs

Although not strictly an external attack, a decision to omitauthentication in future Systems in order to save costs will have widelyvarying effects on different markets.

In the case of high volume consumables, it is essential to remember thatit is very difficult to introduce authentication after the market hasstarted, as systems requiring authenticated consumables will not workwith older consumables still in circulation. Likewise, it is impracticalto discontinue authentication at any stage, as older Systems will notwork with the new, unauthenticated, consumables. In the second case,older Systems can be individually altered by replacing the Systemprogram code.

Without any form of protection, illegal cloning of high volumeconsumables is almost certain. However, with the patent and copyrightprotection, the probability of illegal cloning may be, say 50%. However,this is not the only loss possible. If a clone manufacturer were tointroduce clone consumables which caused damage to the System (e.g.clogged nozzles in a printer due to poor quality ink), then the loss inmarket acceptance, and the expense of warranty repairs, may besignificant.

In the case of a specialized pairing, such as a car/car-keys, ordoor/door-key, or some other similar situation, the omission ofauthentication in future systems is trivial and without repercussions.This is because the consumer is sold the entire set of System andConsumable authentication chips at the one time.

14.19 Garrote/Bribe Attack

If humans do not know the key, there is no amount of force or briberythat can reveal them. The use of ChipF and the ReplaceKey protocol isspecifically designed to avoid the requirement of the programmingstation having to know the new key. However ChipF must be told the newkey at some stage, and therefore it is the person(s) who enter the newkey into ChipF that are at risk.

The level of security against this kind of attack is ultimately adecision for the System/Consumable owner, to be made according to thedesired level of service.

For example, a car company may wish to keep a record of all keysmanufactured, so that a person can request a new key to be made fortheir car. However this allows the potential compromise of the entirekey database, allowing an attacker to make keys for any of themanufacturer's existing cars. It does not allow an attacker to make keysfor any new cars. Of course, the key database itself may also beencrypted with a further key that requires a certain number of people tocombine their key portions together for access. If no record is kept ofwhich key is used in a particular car, there is no way to makeadditional keys should one become lost. Thus an owner will have toreplace his car's authentication chip and all his car-keys. This is notnecessarily a bad situation.

By contrast, in a consumable such as a printer ink cartridge, the onekey combination is used for all Systems and all consumables. Certainlyif no backup of the keys is kept, there is no human with knowledge ofthe key, and therefore no attack is possible. However, a no-backupsituation is not desirable for a consumable such as ink cartridges,since if the key is lost no more consumables can be made. Themanufacturer should therefore keep a backup of the key information inseveral parts, where a certain number of people must together combinetheir portions to reveal the full key information. This may be requiredif case the chip programming station needs to be reloaded.

In any case, none of these attacks are against the authenticated readprotocol, since no humans are involved in the authentication process.

Logical Interface

15 Introduction

The QA Chip has a physical and a logical external interface. Thephysical interface defines how the QA Chip can be connected to aphysical System, while the logical interface determines how that Systemcan communicate with the QA ChIP. This section deals with the logicalinterface.

15.1 Operating Modes

The QA Chip has four operating modes—Idle Mode, Program Mode, Trim Modeand Active Mode.

-   -   Idle Mode is used to allow the chip to wait for the next        instruction from the System.    -   Trim Mode is used to determine the clock speed of the chip and        to trim the frequency during the initial programming stage of        the chip (when Flash memory is garbage). The clock frequency        must be trimmed via Trim Mode before Program Mode is used to        store the program code.    -   Program Mode is used to load up the operating program code, and        is required because the operating program code is stored in        Flash memory instead of ROM (for security reasons).    -   Active Mode is used to execute the specific authentication        command specified by the System. Program code is executed in        Active Mode. When the results of the command have been returned        to the System, the chip enters Idle Mode to wait for the next        instruction.        15.1.1 Idle Mode

The QA Chip starts up in Idle Mode. When the Chip is in Idle Mode, itwaits for a command from the master by watching the primary id on theserial line.

-   -   If the primary id matches the global id (0x00, common to all QA        Chips), and the following byte from the master is the Trim Mode        id byte, the QA Chip enters Trim Mode and starts counting the        number of internal clock cycles until the next byte is received.    -   If the primary id matches the global id (0x00, common to all QA        Chips), and the following byte from the master is the Program        Mode id byte, the QA Chip enters Program Mode.    -   If the primary id matches the global id (0x00, common to all QA        Chips), and the following byte from the master is the Active        Mode id byte, the QA Chip enters Active Mode and executes        startup code, allowing the chip to set itself into a state to        receive authentication commands (includes setting a local ID).    -   If the primary id matches the chip's local ID, and the following        byte is a valid command code, the QA Chip enters Active Mode,        allowing the command to be executed.

The valid 8-bit serial mode values sent after a global id are as shownin Table 238. They are specified to minimize the chances of themoccurring by error after a global id (e.g. 0xFF and 0x00 are not used):TABLE 238 Id byte values to place chip in specific mode ValueInterpretation 10100101 (0xA5) Trim Mode 10001110 (0x8E) Program Mode01111000 (0x78) Active Mode15.1.2 Trim Mode

Trim Mode is enabled by sending a global id byte (0x00) followed by theTrim Mode command byte. The purpose of Trim Mode is to set the trimvalue (an internal register setting) of the internal ring oscillator sothat Flash erasures and writes are of the correct duration. This isnecessary due to the variation of the clock speed due to processvariations. If writes an erasures are too long, the Flash memory willwear out faster than desired, and in some cases can even be damaged.

Trim Mode works by measuring the number of system clock cycles thatoccur inside the chip from the receipt of the Trim Mode command byteuntil the receipt of a data byte. When the data byte is received, thedata byte is copied to the trim register and the current value of thecount is transmitted to the outside world.

Once the count has been transmitted, the QA Chip returns to Idle Mode.

At reset, the internal trim register setting is set to a known value r.The external user can now perform the following operations:

-   -   send the global id+write followed by the Trim Mode command byte    -   send the 8-bit value v over a specified time t    -   send a stop bit to signify no more data    -   send the global id+read followed by the Trim Mode command byte    -   receive the count c    -   send a stop bit to signify no more data

At the end of this procedure, the trim register will be v, and theexternal user will know the relationship between external time t andinternal time c. Therefore a new value for v can be calculated.

The Trim Mode procedure can be repeated a number of times, varying botht and v in known ways, measuring the resultant c. At the end of theprocess, the final value for v is established (and stored in the trimregister for subsequent use in Program Mode). This value v must also bewritten to the flash for later use (every time the chip is placed inActive Mode for the first time after power-up).

15.1.3 Program Mode

Program Mode is enabled by sending a global id byte (0x00) followed bythe Program Mode command byte.

The QA Chip determines whether or not the internal fuse has been blown(by reading 32-bit word 0 of the information block of flash memory).

If the fuse has been blown the Program Mode command is ignored, and theQA Chip returns to Idle Mode.

If the fuse is still intact, the chip enters Program Mode and erases theentire contents of Flash memory. The QA Chip then validates the erasure.If the erasure was successful, the QA Chip receives up to 4096 bytes ofdata corresponding to the new program code and variable data. The bytesare transferred in order byte₀ to byte₄₀₉₅.

Once all bytes of data have been loaded into Flash, the QA Chip returnsto Idle Mode.

Note that Trim Mode functionality must be performed before a chip entersProgram Mode for the first time.

Once the desired number of bytes have been downloaded in Program Mode,the LSS Master must wait for 80 μs (the time taken to write two bytes toflash at nybble rates) before sending the new transaction (eg ActiveMode). Otherwise the last nybbles may not be written to flash.

15.1.4 Active Mode

Active Mode is entered either by receiving a global id byte (0x00)followed by the Active Mode command byte, or by sending a local id bytefollowed by a command opcode byte and an appropriate number of databytes representing the required input parameters for that opcode.

In both cases, Active Mode causes execution of program code previouslystored in the flash memory via Program Mode. As a result, we never enterActive Mode after Trim Mode, without a Program Mode in between. Howeveronce programmed via Program Mode, a chip is allowed to enter Active Modeafter power-up, since valid data will be in flash.

If Active Mode is entered by the global id mechanism, the QA Chipexecutes specific reset startup code, typically setting up the local idand other IO specific data.

If Active Mode is entered by the local id mechanism, the QA Chipexecutes specific code depending on the following byte, which functionsas an opcode. The opcode command byte format is shown in Table 239:TABLE 239 Command byte bits Description 2-0 Opcode 5-3

opcode 7-6 count of number of bits set in opcode (0 to 3)

The interpretation of the 3-bit opcode is shown in Table 240: TABLE 240QA Chip opcodes Op² Mn³ Description 000 RST Reset 001 RND Random 010 RDMRead M 011 TST Test 100 WRM Write M with no authentication 101 WRA Writewith Authentication (to M, P, or K) 110 chip specific - reserved forChipF, ChipS etc 111 chip specific - reserved for ChipF, ChipS etc²Opcode³Mnemonic

The command byte is designed to ensure that errors in transmission aredetected. Regular QA Chip commands are therefore comprised of an opcodeplus any associated parameters. The commands are listed in Table 241:TABLE 241 QA Chip commands Input Output Command opcode Additional parmsReturn value Reset RST — — Random RND — [20] Read RDM [1, 1, 20] [20,64, 20]⁴ Test TST [1, 20, 64, 20] 89⁵ if successful, 76 if not Write WRM[1, 64, 20] 89 if successful, 76 if not WriteAuth WRA 76 [20, 64, 20] 89if successful, 76 if not ReplaceKey WRA 89 76 [1, 20, 20, 20] 89 ifsuccessful, 76 if not SetPermissions WRA 89 89 [1, 1, 20, 4, 20] [4]SignM⁶ ChipS only [1, 20, 20, 64, 20, 64] [20, 64, 20] SignP⁷ ChipS only[1, 20, 20, 4, 20, 4] [20, 64, 20] GetProgKey ChipF only [1, 20] [20,20, 20] SetPartialKey ChipF only [1, 4] 89 if successful, 76 if not⁴[n, m] = list of parameters where n bytes for first parameter, and mbytes for the second etc.⁵n = actual byte pattern required (in hex). The bytes 0x76 and 0x89 werechosen as the boolean values 0 and 1 as they are inverses of each other,and should not be generated accidentally.⁶It is expected that most QA Chips will implement SignM as a functionthat returns 0x00. Only a limited number of chips will be programmed toallow SignM functionality. It is included here as an example of howsignatures can be generated for authenticated writes.⁷It is expected that most QA Chips will implement SignP as a functionthat returns 0x00. Only a limited number of chips will be programmed toallow SignP functionality. It is included here as an example of howsignatures can be generated for authenticated writes.

Apart from the Reset command, the next four commands are the commandsmost likely to be used during regular operation. The next three commandsare used to provide authenticated writes (which are expected to beuncommon). The final set of commands (including SignM), are expected tobe specially implemented on ChipS and ChipF QA Chips only.

The input parameters are sent in the specified order, with eachparameter being sent least significant byte first and most significantbyte last.

Return (output) values are read in the same way—least significant bytefirst and most significant byte last. The client must know how manybytes to retrieve. The QA Chip will time out and return to Idle Mode ifan incorrect number of bytes is provided or read.

In most cases, the output bytes from one chip's command (the returnvalues) can be fed directly as the input bytes to another chip'scommand. An example of this is the RND and RD commands. The output datafrom a call to RND on a trusted QA Chip does not have to be kept by theSystem. Instead, the System can transfer the output bytes directly tothe input of the non-trusted QA Chip's RD command. The description ofeach command points out where this is so.

Each of the commands is examined in detail in the subsequent sections.Note that some algorithms are specifically designed because flash memoryis assumed for the implementation of non-volatile variables.

15.1.5 Non Volatile Variables

The memory within the QA Chip contains some non-volatile (Flash) memoryto store the variables required by the authentication protocol. Table242 summarizes the variables. TABLE 242 Non volatile variables requiredby the authentication protocol Size Name (bits) Description N  8 Numberof keys known to the chip T  8 Number of vectors M is broken into K_(n)160 per key, Array of N secret keys used for calculating F_(Kn)[X] R_(K)160 for R_(K) where K_(n) is the nth element of the array. Each K_(n)must not be stored directly in the QA Chip. Instead, each chip needs tostore a single random number R_(K) (different for each chip),K_(n)⊕R_(K), and

K_(n)⊕R_(K). The stored K_(n)⊕R_(K) can be XORed with R_(K) to obtainthe real K_(n). Although

K_(n)⊕R_(K) must be stored to protect against differential attacks, itis not used. R 160 Current random number used to ensure time varyingmessages. Each chip instance must be seeded with a different initialvalue. Changes for each signature generation. M_(T) 512 per M Array of Tmemory vectors. Only M₀ can be written to with an authorized write,while all Ms can be written to in an unauthorized write. Writes to M₀are optimized for Flash usage, while updates to any other M_(n) areexpensive with regards to Flash utilization, and are expected to be onlyperformed once per section of M_(n). M₁ contains T and N in ReadOnlyform so users of the chip can know these two values. P_(T+N) 32 per PT+N element array of access permissions for each part of M. Entries n ={0... T−1} hold access permissions for non-authenticated writes to M_(n)(no key required). Entries n={T to T+N −1}hold access permissions forauthenticated writes to M₀ for K_(n). Permission choices for each partof M are Read Only, Read/Write, and Decrement Only MinTicks  32 Theminimum number of clock ticks between calls to key-based functions.Note that since these variables are in Flash memory, writes should beminimized. The it is not a simple matter to write a new value to replacethe old. Care must be taken with flash endurance, and speed of access.This has an effect on the algorithms used to change Flash memory basedregisters. For example, Flash memory should not be used as a shiftregister.

A reset of the QA Chip has no effect on the non-volatile variables.

15.1.5.1 M and P

M_(n) contains application specific state data, such as serial numbers,batch numbers, and amount of consumable remaining. M_(n) can be readusing the Read command and written to via the Write and WriteA commands.

M₀ is expected to be updated frequently, while each part of M_(1-n)should only be written to once. Only M₀ can be written to via the WriteAcommand.

M₁ contains the operating parameters of the chip as shown in Table 243,and M_(2-n), are application specific. TABLE 243 Interpretation of M₁Length Bits interpretation 8 7-0 Number of available keys 8 15-8  Numberof available M vectors 16 31-16 Revision of chip 96 127-32  Manufactureid information 128 255-128 Serial number 8 263-256 Local id of chip 248511-264 reserved

Each M_(n) is 512 bits in length, and is interpreted as a set of16×32-bit words. Although M_(n) may contain a number of differentelements, each 32-bit word differs only in write permissions. Each32-bit word can always be read. Once in client memory, the 512 bits canbe interpreted in any way chosen by the client. The different writepermissions for each P are outlined in Table 244: TABLE 244 Writepermissions Data type permission description Read Only Can never bewritten to ReadWrite Can always be written to Decrement Only Can only bewritten to if the new value is less than the old value. Decrement Onlyvalues can be any multiple of 32 bits.

To accomplish the protection required for writing, a 2-bit permissionvalue P is defined for each of the 32-bit words. Table 245 defines theinterpretation of the 2-bit permission bit-pattern: TABLE 245 Permissionbit interpretation Bits Op Interpretation Action taken during Writecommand 00 RW ReadWrite The new 32-bit value is always written to M[n].01 MSR Decrement Only The new 32-bit value is only written (MostSignificant to M[n] if it is less than the Region) value currently inM[n]. This is used for access to the Most Significant 16 bits of aDecrement Only number. 10 NMSR Decrement Only The new 32-bit value isonly written (Not the Most to M[n] if M[n − 1] could also be Significantwritten. The NMSR access mode Region) allows multiple precision valuesof 32 bits and more (multiples of 32 bits) to decrement. 11 RO Read OnlyThe new 32-bit value is ignored. M[n] is left unchanged.

The 16 sets of permission bits for each 512 bits of M are gatheredtogether in a single 32-bit variable P, where bits 2n and 2n+1 of Pcorrespond to word n of M as follows:

Each 2-bit value is stored as a pair with the msb in bit 1, and the lsbin bit 0. Consequently, if words 0 to 5 of M had permission MSR, withwords 6-15 of M permission RO, the 32-bit P variable would be0xFFFFF555:

11-11-11-11-11-11-11-11-11-11-01-01-01-01-01-01

During execution of a Write and WriteA command, the appropriatePermissions[n] is examined for each M[n] starting from n=15 (msw of M)to n=0 (lsw of M), and a decision made as to whether the ne M[n] valuewill replace the old. Note that it is important to process the M[n] frommsw to lsw to correctly interpret the access permissions.

Permissions are set and read using the QA Chip's SetPermissions command.The default for P is all 0s (RW) with the exception of certain parts ofM₁.

Note that the Decrement Only comparison is unsigned, so any DecrementOnly values that require negative ranges must be shifted into a positiverange. For example, a consumable with a Decrement Only data item rangeof −50 to 50 must have the range shifted to be 0 to 100. The System mustthen interpret the range 0 to 100 as being −50 to 50. Note that mostinstances of Decrement Only ranges are N to 0, so there is no rangeshift required.

For Decrement Only data items, arrange the data in order from mostsignificant to least significant 32-bit quantities from M[n] onward. Theaccess mode for the most significant 32 bits (stored in M[n]) should beset to MSR. The remaining 32-bit entries for the data should have theirpermissions set to NMSR.

If erroneously set to NMSR, with no associated MSR region, each NMSRregion will be considered independently instead of being amulti-precision comparison.

Examples of allocating M and Permission bits can be found in [86].

15.1.5.2 K and R_(K)

K is the 160-bit secret key used to protect M and to ensure that thecontents of M are valid (when M is read from a non trusted chIP). K isinitially programmed after manufacture, and from that point on, K canonly be updated to a new value if the old K is known. Since K must bekept secret, there is no command to directly read it.

K is used in the keyed one-way hash function HMAC-SHA1. As such itshould be programmed with a physically generated random number, gatheredfrom a physically random phenomenon. K must NOT be generated with acomputer-run random number generator. The security of the QA Chipsdepends on K being generated in a way that is not deterministic.

Each K_(n) must not be stored directly in the QA ChIP. Instead, eachchip needs to store a single random number R_(K) (different for eachchIP), K_(n)⊕R_(K), and

K_(n)⊕R_(K). The stored K_(n)⊕R_(K) XORed with R_(K) to obtain the realK_(n). Although

K_(n)R_(K) must be stored to protect against differential attacks, it isnot used.

15.1.5.3 R

R is a 160-bit random number seed that is set up after manufacture (whenthe chip is programmed) and from that point on, cannot be changed. R isused to ensure that each signed item contains time varying information(not chosen by an attacker), and each chip's R is unrelated from onechip to the next.

R is used during the Test command to ensure that the R from the previouscall to Random was used as the session key in generating the signatureduring Read. Likewise, R is used during the WriteAuth command to ensurethat the R from the previous call to Read was used as the session keyduring generation of the signature in the remote Authenticated chIP.

The only invalid value for R is 0. This is because R is changed via a160-bit maximal period LFSR (Linear Feedback Shift Register) with tapson bits 0, 2, 3, and 5, and is changed only by a successful call to asignature generating function (e.g. Test, WriteAuth).

The logical security of the QA Chip relies not only upon the randomnessof K and the strength of the HMAC-SHA1 algorithm. To prevent an attackerfrom building a sparse lookup table, the security of the QA Chip alsodepends on the range of R over the lifetime of all Systems. What thismeans is that an attacker must not be able to deduce what values of Rthere are in produced and future Systems. Ideally, R should beprogrammed with a physically generated random number, gathered from aphysically random phenomenon (must not be deterministic). R must NOT begenerated with a computer-run random number generator.

15.1.5.4 MinTicks

There are two mechanisms for preventing an attacker from generatingmultiple calls to key-based functions in a short period of time. Thefirst is an internal ring oscillator that is temperature-filtered. Thesecond mechanism is the 32-bit MinTicks variable, which is used tospecify the minimum number of QA Chip clock ticks that must elapsebetween calls to key-based functions.

The MinTicks variable is set to a fixed value when the QA Chip isprogrammed. It could possibly be stored in M₁.

The effective value of MinTicks depends on the operating clock speed andthe notion of what constitutes a reasonable time between key-basedfunction calls (application specific). The duration of a single tickdepends on the operating clock speed. This is the fastest speed of thering oscillator generated clock (i.e. at the lowest valid operatingtemperature).

Once the duration of a tick is known, the MinTicks value can to be set.The value for MinTicks will be the minimum number of ticks required topass between calls to the key-based functions (there is no need toprotect Random as this produces the same output each time it is calledmultiple times in a row). The value is a real-time number, and dividedby the length of an operating tick.

It should be noted that the MinTicks variable only slows down anattacker and causes the attack to cost more since it does not stop anattacker using multiple System chips in parallel.

15.1.6 GetProgramKey Input: n, R_(E) = [1 byte, 20 bytes] Output: R_(L),E_(Kx)[S_(Kn)[R_(E)|R_(L)|C₃]],S_(Kx)[R_(L)|E_(Kx)[S_(Kn)[R_(E)|R_(L)|C₃]|C₃] = [20, 20, 20] Changes:R_(L)Note:The GetProgramKey command is only implemented in ChipF, and not in allQA Chips.The GetProgramKey command is used to produce the bytestream required forupdating a specified key in ChipP.Only an QA Chip programmed with the correct values of the old K_(n) canrespond correctly to the GetProgramKey request.The output bytestream from the Random command can be fed as the inputbytestream to the ReplaceKey command on the QA Chip being programmed(ChipP).

The input bytestream consists of the appropriate opcode followed by thedesired key to generate the signature, followed by 20 bytes of R_(E)(representing the random number read in from ChipP).

The local random number R_(L) is advanced, and signed in combinationwith R_(E) and C₃ by the chosen key to generate a time varying secretnumber known to both ChipF and ChipP. This signature is then XORed withthe new key K_(x) (this encrypts the new key). The first two outputparameters are signed with the old key to ensure that ChipP knows itdecoded K_(x) correctly.

This whole procedure should only be allowed a given number of times. Theactual number can conveniently be stored in the local M₀[0] (eg word 0of M₀) with ReadOnly permission. Of course another chip could perform anAuthorised write to update the number (via a ChipS) should it bedesired.

The GetProgramKey command is implemented by the following steps: Loopthrough all of Flash, reading each word (will trigger checks) Accept nRestrict n to N Accept R_(E) If (M₀[0] = 0)  Output 60 bytes of 0x00 #no more keys allowed to be generated from this chipF  Done EndIf AdvanceR_(L) SIG

S_(Kn)[R_(L)|R_(E)|C₃] # calculation must take constant time Tmp

SIG ⊕ K_(X) Output R_(L) Output Tmp Decrement M₀[0]  #  reduce  the number  of  allowable  key generations by 1 SIG

S_(KX)[R_(L)|Tmp|C₃]  # calculation must take constant time Output SIG

15.1.7 Random Input: None Output: R_(L) = [20 bytes] Changes: None

The Random command is used by a client to obtain an input for use in asubsequent authentication procedure. Since the Random command requiresno input parameters, it is therefore simply 1 byte containing the RNDopcode.

The output of the Random command from a trusted QA Chip can be fedstraight into the non-trusted chip's Read command as part of the inputparameters. There is no need for the client to store them at all, sincethey are not required again. However the Test command will only succeedif the data passed to the Read command was obtained first from theRandom command.

If a caller only calls the Random function multiple times, the sameoutput will be returned each time.

R will only advance to the next random number in the sequence after asuccessful call to a function that returns or tests a signature (e.g.Test, see Section 15.1.13 on page 725 for more information).

The Random command is implemented by the following steps:

-   -   Loop through all of Flash, reading each word (will trigger        checks)    -   Output R_(L)

15.1.8 Read Input: n, t, R_(E) = [1 byte, 1 byte, 20 bytes] Output:R_(L), M_(Lt), S_(Kn)[R_(E)|R_(L)|C₁|M_(Lt)] = [20 bytes, 64 bytes, 20bytes] Changes: R_(L)

The Read command is used to read the entire state data (M_(t)) from anQA ChIP. Only an QA Chip programmed with the correct value of K_(n) canrespond correctly to the Read request. The output bytestream from theRead command can be fed as the input bytestream to the Test command on atrusted QA Chip for verification, with M_(t) stored for later use ifTest returns success.

The input bytestream consists of the RD opcode followed by the keynumber to use for the signature, which M to read, and the bytes 0-19 ofR_(E). 23 bytes are transferred in total. R_(E) is obtained by callingthe trusted QA Chip's Random command. The 20 bytes output by the trustedchip's Random command can therefore be fed directly into the non-trustedchip's Read command, with no need for these bits to be stored by System.

Calls to Read must wait for MinTicksRemaining to reach 0 to ensure thata minimum time will elapse between calls to Read.

The output values are calculated, MinTicksRemaining is updated, and thesignature is returned. The contents of M_(Lt) are transferred leastsignificant byte to most significant byte. The signatureS_(Kn)[R_(E)|R_(L)|C₁|M_(Lt)] must be calculated in constant time.

The next random number is generated from R using a 160-bit maximalperiod LFSR (tap selections on bits 5, 3, 2, and 0). The initial 160-bitvalue for R is set up when the chip is programmed, and can be any randomnumber except 0 (an LFSR filled with 0s will produce a never-endingstream of 0s). R is transformed by XORing bits 0, 2, 3, and 5 together,and shifting all 160 bits right 1 bit using the XOR result as the inputbit to b₁₅₉. The process is shown in FIG. 347 below.

Care should be taken when updating R since it lives in Flash. Programcode must assume power could be removed at any time.

The Read command is implemented with the following steps: Wait forMinTicksRemaining to become 0 Loop through all of Flash, reading eachword (will trigger checks) Accept n Accept t Restrict n to N Restrict tto T Accept R_(E) Advance R_(L) Output R_(L) Output M_(Lt) Sig

S_(Kn)[R_(E)|R_(L)|C₁|M_(Lt)] # calculation must take constant timeMinTicksRemaining

MinTicks Output Sig Wait for MinTicksRemaining to become 0

15.1.9 Set Permissions Input: n, p, R_(E), P_(E), SIG_(E) = [1 byte, 1byte, 20 bytes, 4 bytes, 20 bytes] Output: P_(p) Changes: P_(p), R_(L)

The SetPermissions command is used to securely update the contents ofP_(p) (containing QA Chip permissions). The WriteAuth command onlyattempts to replace P_(p) if the new value is signed combined with ourlocal R.

It is only possible to sign messages by knowing K_(n). This can beachieved by a call to the SignP command (because only a ChipS can knowK_(n)). It means that without a chip that can be used to produce therequired signature, a write of any value to P_(p) is not possible.

The process is very similar to Test, except that if the validationsucceeds, the P_(E) input parameter is additionally ORed with thecurrent value for P_(p). Note that this is an OR, and not a replace.Since the SetParms command only sets bits in P_(p), the effect is toallow the permission bits corresponding to M[n] to progress from RW toeither MSR, NMSR, or RO.

The SetPermissions command is implemented with the following steps: Waitfor MinTicksRemaining to become 0 Loop through all of Flash, readingeach word (will trigger checks) Accept n Restrict n to N Accept pRestrict p to T+N Accept R_(E) Accept P_(E) SIG_(L)

S_(Kn)[R_(L)|R_(E)|P_(E)|C₂] # calculation must take constant timeAccept SIG_(E) If (SIG_(E) = SIG_(L))  Update R_(L)  P_(P)

P_(P)

P_(E) EndIf Output P_(P) # success or failure will be determined byreceiver MinTicksRemaining

MinTicks

15.1.10 ReplaceKey Input: n, R_(E), V, SIG_(E) = [1 byte, 20 bytes, 20bytes, 20 bytes] Output: Boolean (0x76 = failure, 0x89 = success)Changes: K_(n), M_(L), R_(L)

The ReplaceKey command is used to replace the specified key in the QAChip flash memory. However K_(n) can only be replaced if the previousvalue is known. A return byte of 0x89 is produced if the key wassuccessfully updated, while 0x76 is returned for failure.

A ReplaceKey command consists of the WR_(A) command opcode followed by0x89, 0x76, and then the appropriate parameters. Note that the new keyis not sent in the clear, it is sent encrypted with the signature ofR_(L), R_(E) and C₃ (signed with the old key). The first two inputparameters must be verified by generating a signature using the old key.

The ReplaceKey command is implemented with the following steps: Loopthrough all of Flash, reading each word (will trigger checks) Accept nRestrict n to N Accept R_(E) # session key from ChipF Accept V #encrypted key SIG_(L)

S_(Kn)[R_(E)|V|C₃] # calculation must take constant time Accept SIG_(E)If (SIG_(L) = SIG_(E2)) # comparison must take constant time  SIG_(L)

S_(Kn)[R_(L)|R_(E)|C₃] # calculation must take constant time  AdvanceR_(L)  K_(E)

SIG_(L) ⊕ V  K_(n)

K_(E)    # involves storing (K_(E) ⊕ R_(K)) and (

K_(E) ⊕ R_(K))  Output 0x89 # success Else  Output 0x76 # failure EndIf

15.1.11 SignM Input: n, R_(X), R_(E), M_(E), SIG_(E), M_(desired) = [1byte, 20 bytes, 20 bytes, 64 bytes, 32 bytes] Output: R_(L), M_(new),S_(Kn)[R_(E)|R_(L)|C₁|M_(new)] = [20 bytes, 64 bytes, 20 bytes] Changes:R_(L)Note:The SignM command is only implemented in ChipS, and not in all QA Chips.

The SignM command is used to produce a valid signed M for use in anauthenticated write transaction. Only an QA Chip programmed with correctvalue of K_(n) can respond correctly to the SignM request. The outputbytestream from the SignM command can be fed as the input bytestream tothe WriteA command on a different QA ChIP.

The input bytestream consists of the SMR opcode followed by 1 bytecontaining the key number to use for generating the signature, 20 bytesof Rx (representing the number passed in as R to ChipU's READ command,i.e. typically 0), the output from the READ command (namely R_(E),M_(E), and SIG_(E)), and finally the desired M to write to ChipU.

The SignM command only succeeds whenSIG_(E)=S_(K)[R_(X)|R_(E)|C₁|M_(E)], indicating that the request wasgenerated from a chip that knows K. This generation and comparison musttake the same amount of time regardless of whether the input parametersare correct or not. If the times are not the same, an attacker can gaininformation about which bits of the supplied signature are incorrect. Ifthe signatures match, then R_(L) is updated to be the next random numberin the sequence.

Since the SignM function generates signatures, the function must waitfor the MinTicksRemaining register to reach 0 before processing takesplace.

Once all the inputs have been verified, a new memory vector is producedby applying a specially stored P value (eg word 1 of M₀) and M_(desired)against M_(E). Effectively, it is performing a regular Write, but withseparate P against someone else's M. The M_(new) is signed with anupdated R_(L) (and the passed in R_(E)), and all three values are output(the random number R_(L), M_(new), and the signature). The time taken togenerate this signature must be the same regardless of the inputs.

Typically, the SignM command will be acting as a form of consumablecommand, so that a given ChipS can only generate a given number ofsignatures. The actual number can conveniently be stored in M₀ (eg word0 of M₀) with ReadOnly permissions. Of course another chip could performan Authorised write to update the number (using another ChipS) should itbe desired.

The SignM command is implemented with the following steps: Wait forMinTicksRemaining to become 0 Loop through all of Flash, reading eachword (will trigger checks) Accept n Restrict n to N Accept R_(X)      #don't care what this number is Accept R_(E) Accept M_(E) SIG_(L)

S_(Kn)[R_(X)|R_(E)|C₁|M_(E)] # calculation must take constant timeAccept SIG_(E) Accept M_(desired) If ((SIG_(E) ≠ SIG_(L)) OR (M_(L)[0] =0)) # fail if bad signature or if allowed sigs = 0  Output appropriatenumber of 0  # report failure  Done EndIf Update R_(L) # Create the newversion of M in ram from W and Permissions # This is the same as thecore process of Write function # except that we don't write the resultsback to M DecEncountered

0 EqEncountered

0 Permissions = M_(L)[1]      #  assuming  M₀ contains appropriatepermissions For n

msw to lsw #(word 15 to 0)  AM

Permissions[n]  LT

(M_(desired)[n] < M_(E)[n])# comparison is unsigned  EQ

(M_(desired)[n] = M_(E)[n])  WE

(AM = RW)

((AM = MSR)

LT)

((AM = NMSR)

(DecEncountered

LT))  DecEncountered

((AM = MSR)

LT)     

((AM = NMSR)

DecEncountered)     

((AM = NMSR)

EqEncountered

LT)  EqEncountered

((AM = MSR)

EQ)

((AM = NMSR)

EqEncountered

EQ)  If (

WE)

(M_(E)[n] ≠ M_(desired)[n])   Output appropriate number of 0  # reportfailure  EndIf EndFor # At this point, M_(desired) is correct OutputR_(L) Output M_(desired) # M_(desired) is now effectively M_(new) Sig

S_(Kn)[R_(E)|R_(L)|C₁|M_(desired)] # calculation must take constant timeMinTicksRemaining

MinTicks Decrement M_(L)[0]  # reduce the number of allowable signaturesby 1 Output Sig

15.1.12 SignP Input: n, R_(E), P_(desired) = [1 byte, 20 bytes, 4 bytes]Output: R_(L), S_(Kn)[R_(E)|R_(L)|P_(desired)|C₂] = [20 bytes, 20 bytes]Changes: R_(L)Note:The SignP command is only implemented in ChipS, and not in all QA Chips.

The SignP command is used to produce a valid signed P for use in aSetPermissions transaction.

Only an QA Chip programmed with correct value of K_(n) can respondcorrectly to the SignP request. The output bytestream from the SignPcommand can be fed as the input bytestream to the SetPermissions commandon a different QA ChIP.

The input bytestream consists of the SMP opcode followed by 1 bytecontaining the key number to use for generating the signature, 20 bytesof R_(E) (representing the number obtained from ChipU's RND command, andfinally the desired P to write to ChipU.

Since the SignP function generates signatures, the function must waitfor the MinTicksRemaining register to reach 0 before processing takesplace.

Once all the inputs have been verified, the P_(desired) is signed withan updated R_(L) (and the passed in R_(E)), and both values are output(the random number R_(L) and the signature). The time taken to generatethis signature must be the same regardless of the inputs.

Typically, the SignP command will be acting as a form of consumablecommand, so that a given ChipS can only generate a given number ofsignatures. The actual number can conveniently be stored in M₀ (eg word0 of M₀) with ReadOnly permissions. Of course another chip could performan Authorised write to update the number (using another ChipS) should itbe desired.

The SignM command is implemented with the following steps:

-   -   Wait for MinTicksRemaining to become 0

Loop through all of Flash, reading each word (will trigger checks)Accept n Restrict n to N Accept R_(E) Accept P_(desired) If (M_(L)[0] =0) # fail if allowed sigs = 0  Output appropriate number of 0  # reportfailure  Done EndIf Update R_(L) Output R_(L) Sig

S_(Kn)[R_(E)|R_(L)|P_(desired)|C₂] # calculation must take constant timeMinTicksRemaining

MinTicks Decrement M_(L)[0]  # reduce the number of allowable signaturesby 1 Output Sig

15.1.13 Test Input: n, R_(E), M_(E), SIG_(E) = [1 byte, 20 bytes, 64bytes, 20 bytes] Output: Boolean (0x76 = failure, 0x89 = success)Changes: R_(L)

The Test command is used to authenticate a read of an M from anon-trusted QA ChIP.

The Test command consists of the TST command opcode followed by inputparameters: n, R_(E), M_(E), and SIG_(E). The byte order is leastsignificant byte to most significant byte for each command component.All but the first input parameter bytes are obtained as the output bytesfrom a Read command to a non-trusted QA ChIP. The entire data does nothave to be stored by the client. Instead, the bytes can be passeddirectly to the trusted QA Chip's Test command, and only M should bekept from the Read.

Calls to Test must wait for the MinTicksRemaining register to reach 0.

S_(Kn)[R_(L)|R_(E)|C₁|M_(E)] is then calculated, and compared againstthe input signature SIG_(E). If they are different, R_(L) is notchanged, and 0x76 is returned to indicate failure. If they are the same,then R_(L) is updated to be the next random number in the sequence and0x89 is returned to indicate success. Updating R_(L) only after successforces the caller to use a new random number (via the Random command)each time a successful authentication is performed.

The calculation of S_(Kn)[R_(L)|R_(E)|C₁|M_(E)] and the comparisonagainst SIG_(E) must take identical time so that the time to evaluatethe comparison in the TST function is always the same. Thus no attackercan compare execution times or number of bits processed before an outputis given.

The Test command is implemented with the following steps:

-   -   Wait for MinTicksRemaining to become 0

Loop through all of Flash, reading each word (will trigger checks)Accept n Restrict n to N Accept R_(E) Accept M_(E) SIG_(L)

S_(Kn)[R_(L)|R_(E)|C₁|M_(E)] # calculation must take constant timeAccept SIG_(E) If (SIG_(E) = SIG_(L))  Update R_(L)  Output 0x89 #success Else  Output 0x76     # report failure EndIf MinTicksRemaining

MinTicks

15.1.14 Write Input: t, M_(new), SIG_(E) = [1 byte, 64 bytes, 20 bytes]Output: Boolean (0x76 = failure, 0x89 = success) Changes: M_(t)

The Write command is used to update M_(t) according to the permissionsin P_(t). The WR command by itself is not secure, since a clone QA Chipmay simply return success every time. Therefore a Write command shouldbe followed by an authenticated read of M_(t) (e.g. via a Read command)to ensure that the change was actually made.

The Write command is called by passing the WR command opcode followed bywhich M to be updated, the new data to be written to M, and a digitalsignature of M. The data is sent least significant byte to mostsignificant byte.

The ability to write to a specific 32-bit word within M_(t) is governedby the corresponding Permissions bits as stored in P_(t). P_(t) can beset using the SetPermissions command.

The fact that M_(t) is Flash memory must be taken into account whenwriting the new value to M. It is possible for an attacker to removepower at any time. In addition, only the changes to M should be storedfor maximum utilization. In addition, the longevity of M will need to betaken into account. This may result in the location of M being updated.

The signature is not keyed, since it must be generated by the consumableuser.

The Write command is implemented with the following steps: Loop throughall of Flash, reading each word (will trigger checks) Accept t Restrictt to T Accept M_(E)   # new M Accept SIG_(E) SIG_(L) = GenerateSHA1[M_(E)] If (SIG_(L) = SIG_(E))  output 0x76 # failure due to invalidsignature  exit EndIf DecEncountered

0 EqEncountered

0 For i

msw to lsw #(word 15 to 0)  P

P_(t)[i]  LT

(M_(E)[i] < M_(t)[i]) # comparison is unsigned  EQ

(M_(E)[i] = M_(t)[i])  WE 

 (P = RW) 

 ((P = MSR) 

 LT) 

 ((P =  NMSR) 

(DecEncountered

LT))  DecEncountered

((P = MSR)

LT)     

((P = NMSR)

DecEncountered)     

((P = NMSR)

EqEncountered

LT)  EqEncountered

((P = MSR)

EQ)

((P =  NMSR)

EqEncountered

EQ)  If (

WE)

(M_(E)[i] ≠ M_(t)[i])   output 0x76 # failure due to wanting a changebut not allowed it  EndIf EndFor # At this point, M_(E) (desired) iscorrect to be written to the flash M_(t)

M_(E)    # update flash output 0x89   # success

15.1.15 WriteAuth Input: n, R_(E), M_(E), SIG_(E) = [1 byte, 20 bytes,64 bytes, 20 bytes] Output: Boolean (0x76 = failure, 0x89 = success)Changes: M₀, R_(L)

The WriteAuth command is used to securely replace the entire contents ofM₀ (containing QA Chip application specific data) according to theP_(T+n). The WriteAuth command only attempts to replace M₀ if the newvalue is signed combined with our local R.

It is only possible to sign messages by knowing K_(n). This can beachieved by a call to the SignM command (because only a ChipS can knowK_(n)). It means that without a chip that can be used to produce therequired signature, a write of any value to M₀ is not possible.

The process is very similar to Write, except that if the validationsucceeds, the M_(E) input parameter is processed against M₀ usingpermissions P_(T+n).

The WriteAuth command is implemented with the following steps: Wait forMinTicksRemaining to become 0 Loop through all of Flash, reading eachword (will trigger checks) Accept n Restrict n to N Accept R_(E) AcceptM_(E) SIG_(L)

S_(Kn)[R_(L)|R_(E)|C₁|M_(E)] # calculation must take constant timeAccept SIG_(E) If (SIG_(E) = SIG_(L))  Update R_(L)  DecEncountered

0  EqEncountered

0  For i

msw to lsw #(word 15 to 0)   P

P_(T+n)[i]   LT

(M_(E)[i] < M₀[i]) # comparison is unsigned   EQ

(M_(E)[i] = M₀[i])   WE 

 (P = RW) 

 ((P = MSR) 

 LT) 

  DecEncountered

((P = MSR)

LT)     

((P = NMSR)

DecEncountered)     

((P = NMSR)

EqEncountered

LT)   EqEncountered 

 ((P = MSR) 

 EQ) 

((P = NMSR) 

 EqEncountered

EQ)   If ((

WE)

(M_(E)[i] ≠ M₀[i]))    output 0x76 # failure due to wanting a change butnot allowed it   EndIf  EndFor  # At this point, M_(E) (desired) iscorrect to be written to the flash  M₀

M_(E)    # update flash  output 0x89   # success EndIf MinTicksRemaining

MinTicks16 Manufacture

This chapter makes some general comments about the manufacture andimplementation of authentication chips. While the comments presentedhere are general, see [84] for a detailed description of animplementation of an authentication chIP.

The authentication chip algorithms do not constitute a strong encryptiondevice. The net effect is that they can be safely manufactured in anycountry (including the USA) and exported to anywhere in the world.

The circuitry of the authentication chip must be resistant to physicalattack. A summary of manufacturing implementation guidelines ispresented, followed by specification of the chip's physical defenses(ordered by attack).

Note that manufacturing comments are in addition to any legal protectionundertaken, such as patents, copyright, and license agreements (forexample, penalties if caught reverse engineering the authenticationchIP).

16.1 Guidelines for Manufacturing

The following are general guidelines for implementation of anauthentication chip in terms of manufacture (see [84] for a detaileddescription of an authentication chIP). No special security is requiredduring the manufacturing process.

-   -   Standard process    -   Minimum size (if possible)    -   Clock Filter    -   Noise Generator    -   Tamper Prevention and Detection circuitry    -   Protected memory with tamper detection    -   Boot circuitry for loading program code    -   Special implementation of FETs for key data paths    -   Data connections in polysilicon layers where possible    -   OverUnderPower Detection Unit    -   No test circuitry    -   Transparent epoxy packaging

Finally, as a general note to manufacturers of Systems, the data line tothe System authentication chip and the data line to the Consumableauthentication chip must not be the same line. See Section 16.2.3 onpage 736.

16.1.1 Standard Process

The authentication chip should be implemented with a standardmanufacturing process (such as Flash). This is necessary to:

-   -   allow a great range of manufacturing location options    -   take advantage of well-defined and well-behaved technology    -   reduce cost

Note that the standard process still allows physical protectionmechanisms.

16.1.2 Minimum Size

The authentication chip must have a low manufacturing cost in order tobe included as the authentication mechanism for low cost consumables. Itis therefore desirable to keep the chip size as low as reasonablypossible.

Each authentication chip requires 962 bits of non-volatile memory. Inaddition, the storage required for optimized HMAC-SHA1 is 1024 bits. Theremainder of the chip (state machine, processor, CPU or whatever ischosen to implement Protocol C1) must be kept to a minimum in order thatthe number of transistors is minimized and thus the cost per chip isminimized. The circuit areas that process the secret key information orcould reveal information about the key should also be minimized (seeSection 16.1.8 on page 734 for special data paths).

16.1.3 Clock Filter

The authentication chip circuitry is designed to operate within aspecific clock speed range. Since the user directly supplies the clocksignal, it is possible for an attacker to attempt to introducerace-conditions in the circuitry at specific times during processing. Anexample of this is where a high clock speed (higher than the circuitryis designed for) may prevent an XOR from working properly, and of thetwo inputs, the first may always be returned. These styles of transientfault attacks can be very efficient at recovering secret keyinformation, and have been documented in [5] and [1]. The lesson to belearned from this is that the input clock signal cannot be trusted.

Since the input clock signal cannot be trusted, it must be limited tooperate up to a maximum frequency. This can be achieved a number ofways.

One way to filter the clock signal is to use an edge detect unit passingthe edge on to a delay, which in turn enables the input clock signal topass through.

FIG. 348 shows clock signal flow within the Clock Filter.

The delay should be set so that the maximum clock speed is a particularfrequency (e.g. about 4 MHz). Note that this delay is notprogrammable—it is fixed.

The filtered clock signal would be further divided internally asrequired.

16.1.4 Noise Generator

Each authentication chip should contain a noise generator that generatescontinuous circuit noise. The noise will interfere with otherelectromagnetic emissions from the chip's regular activities and addnoise to the I_(dd) signal. Placement of the noise generator is not anissue on an authentication chip due to the length of the emissionwavelengths.

The noise generator is used to generate electronic noise, multiple statechanges each clock cycle, and as a source of pseudo-random bits for theTamper Prevention and Detection circuitry (see Section 16.1.5 on page731).

A simple implementation of a noise generator is a 64-bit maximal periodLFSR seeded with a non-zero number. The clock used for the noisegenerator should be running at the maximum clock rate for the chip inorder to generate as much noise as possible.

16.1.5 Tamper Prevention and Detection Circuitry

A set of circuits is required to test for and prevent physical attackson the authentication chIP. However what is actually detected as anattack may not be an intentional physical attack. It is thereforeimportant to distinguish between these two types of attacks in anauthentication chip:

-   -   where you can be certain that a physical attack has occurred.    -   where you cannot be certain that a physical attack has occurred.

The two types of detection differ in what is performed as a result ofthe detection. In the first case, where the circuitry can be certainthat a true physical attack has occurred, erasure of Flash memory keyinformation is a sensible action. In the second case, where thecircuitry cannot be sure if an attack has occurred, there is stillcertainly something wrong. Action must be taken, but the action shouldnot be the erasure of secret key information. A suitable action to takein the second case is a chip RESET. If what was detected was an attackthat has permanently damaged the chip, the same conditions will occurnext time and the chip will RESET again. If, on the other hand, what wasdetected was part of the normal operating environment of the chip, aRESET will not harm the key.

A good example of an event that circuitry cannot have knowledge about,is a power glitch. The glitch may be an intentional attack, attemptingto reveal information about the key. It may, however, be the result of afaulty connection, or simply the start of a power-down sequence. It istherefore best to only RESET the chip, and not erase the key. If thechip was powering down, nothing is lost. If the System is faulty,repeated RESETs will cause the consumer to get the System repaired. Inboth cases the consumable is still intact.

A good example of an event that circuitry can have knowledge about, isthe cutting of a data line within the chIP. If this attack is somehowdetected, it could only be a result of a faulty chip (manufacturingdefect) or an attack. In either case, the erasure of the secretinformation is a sensible step to take.

Consequently each authentication chip should have 2 Tamper DetectionLines—one for definite attacks, and one for possible attacks. Connectedto these Tamper Detection Lines would be a number of Tamper Detectiontest units, each testing for different forms of tampering. In addition,we want to ensure that the Tamper Detection Lines and Circuitsthemselves cannot also be tampered with.

At one end of the Tamper Detection Line is a source of pseudo-randombits (clocking at high speed compared to the general operatingcircuitry). The Noise Generator circuit described above is an adequatesource. The generated bits pass through two different paths—one carriesthe original data, and the other carries the inverse of the data. Thewires carrying these bits are in the layer above the general chipcircuitry (for example, the memory, the key manipulation circuitryetc.). The wires must also cover the random bit generator. The bits arerecombined at a number of places via an XOR gate. If the bits aredifferent (they should be), a 1 is output, and used by the particularunit (for example, each output bit from a memory read should be ANDedwith this bit value). The lines finally come together at the Flashmemory Erase circuit, where a complete erasure is triggered by a 0 fromthe XOR. Attached to the line is a number of triggers, each detecting aphysical attack on the chIP. Each trigger has an oversize nMOStransistor attached to GND. The Tamper Detection Line physically goesthrough this nMOS transistor. If the test fails, the trigger causes theTamper Detect Line to become 0. The XOR test will therefore fail oneither this clock cycle or the next one (on average), thus RESETing orerasing the chIP.

FIG. 349 illustrates the basic principle of a Tamper Detection Line interms of tests and the XOR connected to either the Erase or RESETcircuitry.

The Tamper Detection Line must go through the drain of an outputtransistor for each test, as illustrated by FIG. 350:

It is not possible to break the Tamper Detect Line since this would stopthe flow of 1 s and 0s from the random source. The XOR tests wouldtherefore fail. As the Tamper Detect Line physically passes through eachtest, it is not possible to eliminate any particular test withoutbreaking the Tamper Detect Line.

It is important that the XORs take values from a variety of places alongthe Tamper Detect Lines in order to reduce the chances of an attack.FIG. 351 illustrates the taking of multiple XORs from the Tamper DetectLine to be used in the different parts of the chIP. Each of these XORscan be considered to be generating a ChipOK bit that can be used withineach unit or sub-unit.

A sample usage would be to have an OK bit in each unit that is ANDedwith a given ChipOK bit each cycle. The OK bit is loaded with 1 on aRESET. If OK is 0, that unit will fail until the next RESET. If theTamper Detect Line is functioning correctly, the chip will either RESETor erase all key information. If the RESET or erase circuitry has beendestroyed, then this unit will not function, thus thwarting an attacker.

The destination of the RESET and Erase line and associated circuitry isvery context sensitive. It needs to be protected in much the same way asthe individual tamper tests. There is no point generating a RESET pulseif the attacker can simply cut the wire leading to the RESET circuitry.The actual implementation will depend very much on what is to be clearedat RESET, and how those items are cleared.

Finally, FIG. 352 shows how the Tamper Lines cover the noise generatorcircuitry of the chIP. The generator and NOT gate are on one level,while the Tamper Detect Lines run on a level above the generator.

16.1.6 Protected Memory with Tamper Detection

It is not enough to simply store secret information or program code inFlash memory. The Flash memory and RAM must be protected from anattacker who would attempt to modify (or set) a particular bit ofprogram code or key information. The mechanism used must conform tobeing used in the Tamper Detection Circuitry (described above).

The first part of the solution is to ensure that the Tamper DetectionLine passes directly above each Flash or RAM bit. This ensures that anattacker cannot probe the contents of Flash or RAM. A breach of thecovering wire is a break in the Tamper Detection Line. The breach causesthe Erase signal to be set, thus deleting any contents of the memory.The high frequency noise on the Tamper Detection Line also obscurespassive observation.

The second part of the solution for Flash is to use multi-level datastorage, but only to use a subset of those multiple levels for valid bitrepresentations. Normally, when multi-level Flash storage is used, asingle floating gate holds more than one bit. For example, a4-voltage-state transistor can represent two bits. Assuming a minimumand maximum voltage representing 00 and 11 respectively, the two middlevoltages represent 01 and 10. In the authentication chip, we can use thetwo middle voltages to represent a single bit, and consider the twoextremes to be invalid states. If an attacker attempts to force thestate of a bit one way or the other by closing or cutting the gate'scircuit, an invalid voltage (and hence invalid state) results.

The second part of the solution for RAM is to use a parity bit. The datapart of the register can be checked against the parity bit (which willnot match after an attack).

The bits coming from Flash and RAM can therefore be validated by anumber of test units (one per bit) connected to the common TamperDetection Line. The Tamper Detection circuitry would be the firstcircuitry the data passes through (thus stopping an attacker fromcutting the data lines).

While the multi-level Flash protection is enough for non-secretinformation, such as program code, R, and MinTicks, it is not sufficientfor protecting K₁ and K₂. If an attacker adds electrons to a gate (seeSection 5.7.2.15 on page 656) representing a single bit of K₁, and thechip boots up yet doesn't activate the Tamper Detection Line, the keybit must have been a 0. If it does activate the Tamper Detection Line,it must have been a 1. For this reason, all other non-volatile memorycan activate the Tamper Detection Line, but K₁ and K₂ must not.Consequently Checksum is used to check for tampering of K₁ and K₂. Asignature of the expanded form of K₁ and K₂ (i.e. 320 bits instead of160 bits for each of K₁ and K₂) is produced, and the result comparedagainst the Checksum. Any non-match causes a clear of all keyinformation.

16.1.7 Boot Circuitry for Loading Program Code

Program code should be kept in multi-level Flash instead of ROM, sinceROM is subject to being altered in a non-testable way. A boot mechanismis therefore required to load the program code into Flash memory (Flashmemory is in an indeterminate state after manufacture).

The boot circuitry must not be in ROM—a small state-machine wouldsuffice. Otherwise the boot code could be modified in an undetectableway.

The boot circuitry must erase all Flash memory, check to ensure theerasure worked, and then load the program code. Flash memory must beerased before loading the program code. Otherwise an attacker could putthe chip into the boot state, and then load program code that simplyextracted the existing keys. The state machine must also check to ensurethat all Flash memory has been cleared (to ensure that an attacker hasnot cut the Erase line) before loading the new program code.

The loading of program code must be undertaken by the secure ProgrammingStation before secret information (such as keys) can be loaded. Thisstep must be undertaken as the first part of the programming process.

16.1.8 Special Implementation of FETs for Key Data Paths

The normal situation for FET implementation for the case of a CMOSInverter (which involves a pMOS transistor combined with an nMOStransistor) as shown in FIG. 353:

During the transition, there is a small period of time where both thenMOS transistor and the pMOS transistor have an intermediate resistance.The resultant power-ground short circuit causes a temporary increase inthe current, and in fact accounts for the majority of current consumedby a CMOS device. A small amount of infrared light is emitted during theshort circuit, and can be viewed through the silicon substrate (siliconis transparent to infrared light). A small amount of light is alsoemitted during the charging and discharging of the transistor gatecapacitance and transmission line capacitance.

For circuitry that manipulates secret key information, such informationmust be kept hidden. An alternative non-flashing CMOS implementationshould therefore be used for all data paths that manipulate the key or apartially calculated value that is based on the key.

The use of two non-overlapping clocks φ1 and φ2 can provide anon-flashing mechanism. φ1 is connected to a second gate of all nMOStransistors, and φ2 is connected to a second gate of all pMOStransistors. The transition can only take place in combination with theclock. Since φ1 and φ2 are non-overlapping, the pMOS and nMOStransistors will not have a simultaneous intermediate resistance. Thesetup is shown in FIG. 354:

Finally, regular CMOS inverters can be positioned near criticalnon-Flashing CMOS components. These inverters should take their inputsignal from the Tamper Detection Line above. Since the Tamper DetectionLine operates multiple times faster than the regular operatingcircuitry, the net effect will be a high rate of light-bursts next toeach non-Flashing CMOS component. Since a bright light overwhelmsobservation of a nearby faint light, an observer will not be able todetect what switching operations are occurring in the chip proper. Theseregular CMOS inverters will also effectively increase the amount ofcircuit noise, reducing the SNR and obscuring useful EMI.

There are a number of side effects due to the use of non-Flashing CMOS:

-   -   The effective speed of the chip is reduced by twice the rise        time of the clock per clock cycle. This is not a problem for an        authentication chIP.    -   The amount of current drawn by the non-Flashing CMOS is reduced        (since the short circuits do not occur). However, this is offset        by the use of regular CMOS inverters.    -   Routing of the clocks increases chip area, especially since        multiple versions of φ1 and φ2 are required to cater for        different levels of propagation. The estimation of chip area is        double that of a regular implementation.    -   Design of the non-Flashing areas of the authentication chip are        slightly more complex than to do the same with a with a regular        CMOS design. In particular, standard cell components cannot be        used, making these areas full custom. This is not a problem for        something as small as an authentication chip, particularly when        the entire chip does not have to be protected in this manner.        16.1.9 Connections in Polysilicon Layers Where Possible

Wherever possible, the connections along which the key or secret dataflows, should be made in the polysilicon layers. Where necessary, theycan be in metal 1, but must never be in the top metal layer (containingthe Tamper Detection Lines).

16.1.10 OverUnderPower Detection Unit

Each authentication chip requires an OverUnderPower Detection Unit toprevent Power Supply Attacks. An OverUnderPower Detection Unit detectspower glitches and tests the power level against a Voltage Reference toensure it is within a certain tolerance. The Unit contains a singleVoltage Reference and two comparators. The OverUnderPower Detection Unitwould be connected into the RESET Tamper Detection Line, thus causing aRESET when triggered.

A side effect of the OverUnderPower Detection Unit is that as thevoltage drops during a power-down, a RESET is triggered, thus erasingany work registers.

16.1.11 No Test Circuitry

Test hardware on an authentication chip could very easily introducevulnerabilities. As a result, the authentication chip should not containany BIST or scan paths.

The authentication chip must therefore be testable with external testvectors. This should be possible since the authentication chip is notcomplex.

16.1.12 Transparent Epoxy Packaging

The authentication chip needs to be packaged in transparent epoxy so itcan be photo-imaged by the programming station to prevent Trojan horseattacks. The transparent packaging does not compromise the security ofthe authentication chip since an attacker can fairly easily remove achip from its packaging. For more information see Section 16.2.20 onpage 743 and [86].

16.2 Resistance to Physical Attacks

While this chapter only describes manufacture in general terms (sincethis document does not cover a specific implementation of a Protocol C1authentication chIP), we can still make some observations about such achip's resistance to physical attack. A description of the general formof each physical attack can be found in Section 5.7.2 on page 652.

16.2.1 Reading ROM

This attack depends on the key being stored in an addressable ROM. Sinceeach authentication chip stores its authentication keys in internalFlash memory and not in an addressable ROM, this attack is irrelevant.

16.2.2 Reverse Engineering the Chip

Reverse engineering a chip is only useful when the security ofauthentication lies in the algorithm alone. However our authenticationchips rely on a secret key, and not in the secrecy of the algorithm. Ourauthentication algorithm is, by contrast, public, and in any case, anattacker of a high volume consumable is assumed to have been able toobtain detailed plans of the internals of the chIP.

In light of these factors, reverse engineering the chip itself, asopposed to the stored data, poses no threat.

16.2.3 Usurping the Authentication Process

There are several forms this attack can take, each with varying degreesof success. In all cases, it is assumed that a clone manufacturer willhave access to both the System and the consumable designs.

An attacker may attempt to build a chip that tricks the System intoreturning a valid code instead of generating an authentication code.This attack is not possible for two reasons. The first reason is thatSystem authentication chips and Consumable authentication chips,although physically identical, are programmed differently. Inparticular, the RD opcode and the RND opcode are the same, as are the WRand TST opcodes. A System authentication Chip cannot perform a RDcommand since every call is interpreted as a call to RND instead. Thesecond reason this attack would fail is that separate serial data linesare provided from the System to the System and Consumable authenticationchips. Consequently neither chip can see what is being transmitted to orreceived from the other.

If the attacker builds a clone chip that ignores WR commands (whichdecrement the consumable remaining), Protocol C1 ensures that thesubsequent RD will detect that the WR did not occur. The System willtherefore not go ahead with the use of the consumable, thus thwartingthe attacker. The same is true if an attacker simulates loss of contactbefore authentication—since the authentication does not take place, theuse of the consumable doesn't occur.

An attacker is therefore limited to modifying each System in order forclone consumables to be accepted (see Section 16.2.4 on page 737 fordetails of resistance this attack).

16.2.4 Modification of System

The simplest method of modification is to replace the System'sauthentication chip with one that simply reports success for each callto TST. This can be thwarted by System calling TST several times foreach authentication, with the first few times providing false values,and expecting a fail from TST. The final call to TST would be expectedto succeed. The number of false calls to TST could be determined by somepart of the returned result from RD or from the system clock.Unfortunately an attacker could simply rewire System so that the newSystem clone authentication chip can monitor the returned result fromthe consumable chip or clock. The clone System authentication chip wouldonly return success when that monitored value is presented to its TSTfunction. Clone consumables could then return any value as the hashresult for RD, as the clone System chip would declare that value valid.There is therefore no point for the System to call the Systemauthentication chip multiple times, since a rewiring attack will onlywork for the System that has been rewired, and not for all Systems.

A similar form of attack on a System is a replacement of the System ROM.The ROM program code can be altered so that the Authentication neveroccurs. There is nothing that can be done about this, since the Systemremains in the hands of a consumer. Of course this would void anywarranty, but the consumer may consider the alteration worthwhile if theclone consumable were extremely cheap and more readily available thanthe original item.

The System/consumable manufacturer must therefore determine how likelyan attack of this nature is. Such a study must include given the pricingstructure of Systems and Consumables, frequency of System service,advantage to the consumer of having a physical modification performed,and where consumers would go to get the modification performed.

The likelihood of physical alteration increases with the perceivedartificiality of the consumable marketing scheme. It is one thing for aconsumable to be protected against clone manufacturers. It is quiteanother for a consumable's market to be protected by a form of exclusivelicensing arrangement that creates what is viewed by consumers asartificial markets. In the former case, owners are not so likely to goto the trouble of modifying their system to allow a clone manufacturer'sgoods. In the latter case, consumers are far more likely to modify theirSystem. A case in point is DVD. Each DVD is marked with a region code,and will only play in a DVD player from that region. Thus a DVD from theUSA will not play in an Australian player, and a DVD from Japan, Europeor Australia will not play in a USA DVD player. Given that certain DVDtitles are not available in all regions, or because of qualitydifferences, pricing differences or timing of releases, many consumershave had their DVD players modified to accept DVDs from any region. Themodification is usually simple (it often involves soldering a singlewire), voids the owner's warranty, and often costs the owner some money.But the interesting thing to note is that the change is not made so theconsumer can use clone consumables—the consumer will still only buy realconsumables, but from different regions. The modification is performedto remove what is viewed as an artificial barrier, placed on theconsumer by the movie companies. In the same way, a System/Consumablescheme that is viewed as unfair will result in people makingmodifications to their Systems.

The limit case of modifying a system is for a clone manufacturer toprovide a completely clone System which takes clone consumables. Thismay be simple competition or violation of patents. Either way, it isbeyond the scope of the authentication chip and depends on thetechnology or service being cloned.

16.2.5 Direct Viewing of Chip Operation by Conventional Probing

In order to view the chip operation, the chip must be operating.However, the Tamper Prevention and Detection circuitry covers thosesections of the chip that process or hold the key. It is not possible toview those sections through the Tamper Prevention lines.

An attacker cannot simply slice the chip past the Tamper Preventionlayer, for this will break the Tamper Detection Lines and cause anerasure of all keys at power-up. Simply destroying the erasure circuitryis not sufficient, since the multiple ChipOK bits (now all 0) feedinginto multiple units within the authentication chip will cause the chip'sregular operating circuitry to stop functioning.

To set up the chip for an attack, then, requires the attacker to deletethe Tamper Detection lines, stop the Erasure of Flash memory, andsomehow rewire the components that relied on the ChipOK lines. Even ifall this could be done, the act of slicing the chip to this level willmost likely destroy the charge patterns in the non-volatile memory thatholds the keys, making the process fruitless.

16.2.6 Direct Viewing of the Non-Volatile Memory

If the authentication chip were sliced so that the floating gates of theFlash memory were exposed, without discharging them, then the keys couldprobably be viewed directly using an STM or SKM. However, slicing thechip to this level without discharging the gates is probably impossible.Using wet etching, plasma etching, ion milling, or chemical mechanicalpolishing will almost certainly discharge the small charges present onthe floating gates. This is true of regular Flash memory, but even moreso of multi-level Flash memory.

16.2.7 Viewing the Light Bursts Caused by State Changes

All sections of circuitry that manipulate secret key information areimplemented in the non-Flashing CMOS described above. This prevents theemission of the majority of light bursts. Regular CMOS inverters placedin close proximity to the non-Flashing CMOS will hide any faintemissions caused by capacitor charge and discharge. The inverters areconnected to the Tamper Detection circuitry, so they change state manytimes (at the high clock rate) for each non-Flashing CMOS state change.

16.2.8 Viewing the Keys Using an SEPM

An SEPM attack can be simply thwarted by adding a metal layer to coverthe circuitry. However an attacker could etch a hole in the layer, sothis is not an appropriate defense.

The Tamper Detection circuitry described above will shield the signal aswell as cause circuit noise. The noise will actually be a greater signalthan the one that the attacker is looking for. If the attacker attemptsto etch a hole in the noise circuitry covering the protected areas, thechip will not function, and the SEPM will not be able to read any data.

An SEPM attack is therefore fruitless.

16.2.9 Monitoring EMI

The Noise Generator described above will cause circuit noise. The noisewill interfere with other electromagnetic emissions from the chip'sregular activities and thus obscure any meaningful reading of internaldata transfers.

16.2.10 Viewing I_(dd) Fluctuations

The solution against this kind of attack is to decrease the SNR in theI_(dd) signal. This is accomplished by increasing the amount of circuitnoise and decreasing the amount of signal.

The Noise Generator circuit (which also acts as a defense against EMIattacks) will also cause enough state changes each cycle to obscure anymeaningful information in the I_(dd) signal.

In addition, the special Non-Flashing CMOS implementation of thekey-carrying data paths of the chip prevents current from flowing whenstate changes occur. This has the benefit of reducing the amount ofsignal.

16.2.11 Differential Fault Analysis

Differential fault bit errors are introduced in a non-targeted fashionby ionization, microwave radiation, and environmental stress. The mostlikely effect of an attack of this nature is a change in Flash memory(causing an invalid state) or RAM (bad parity). Invalid states and badparity are detected by the Tamper Detection Circuitry, and cause anerasure of the key.

Since the Tamper Detection Lines cover the key manipulation circuitry,any error introduced in the key manipulation circuitry will be mirroredby an error in a Tamper Detection Line. If the Tamper Detection Line isaffected, the chip will either continually RESET or simply erase the keyupon a power-up, rendering the attack fruitless.

Rather than relying on a non-targeted attack and hoping that “just theright part of the chip is affected in just the right way”, an attackeris better off trying to introduce a targeted fault (such as overwriteattacks, gate destruction etc.). For information on these targeted faultattacks, see the relevant sections below.

16.2.12 Clock Glitch Attacks

The Clock Filter (described above) eliminates the possibility of clockglitch attacks.

16.2.13 Power Supply Attacks

The OverUnderPower Detection Unit (described above) eliminates thepossibility of power supply attacks.

16.2.14 Overwriting ROM

Authentication chips store program code, keys and secret information inFlash memory, and not in ROM. This attack is therefore not possible.

16.2.15 Modifying EEPROM/Flash

Authentication chips store program code, keys and secret information inmulti-level Flash memory. However the Flash memory is covered by twoTamper Prevention and Detection Lines. If either of these lines isbroken (in the process of destroying a gate via a laser-cutter) theattack will be detected on power-up, and the chip will either RESET(continually) or erase the keys from Flash memory. This process isdescribed in Section 16.1.6 on page 733.

Even if an attacker is able to somehow access the bits of Flash anddestroy or short out the gate holding a particular bit, this will forcethe bit to have no charge or a full charge. These are both invalidstates for the authentication chip's usage of the multi-level Flashmemory (only the two middle states are valID). When that data value istransferred from Flash, detection circuitry will cause the ErasureTamper Detection Line to be triggered—thereby erasing the remainder ofFlash memory and RESETing the chIP. This is true for program code, andnon-secret information. As key data is read from multi-level flashmemory, it is not imediately checked for validity (otherwise informationabout the key is given away). Instead, a specific key validationmechanism is used to protect the secret key information.

An attacker could theoretically etch off the upper levels of the chip,and deposit enough electrons to change the state of the multi-levelFlash memory by ⅓. If the beam is high enough energy it might bepossible to focus the electron beam through the Tamper Prevention andDetection Lines. As a result, the authentication chip must perform avalidation of the keys before replying to the Random, Test or Randomcommands. The SHA-1 algorithm must be run on the keys, and the resultscompared against an internal checksum value. This gives an attacker a 1in 2¹⁶⁰ chance of tricking the chip, which is the same chance asguessing either of the keys.

A Modify EEPROM/Flash attack is therefore fruitless.

16.2.16 Gate Destruction Attacks

Gate Destruction Attacks rely on the ability of an attacker to modify asingle gate to cause the chip to reveal information during operation.However any circuitry that manipulates secret information is covered byone of the two Tamper Prevention and Detection lines. If either of theselines is broken (in the process of destroying a gate) the attack will bedetected on power-up, and the chip will either RESET (continually) orerase the keys from Flash memory.

To launch this kind of attack, an attacker must first reverse-engineerthe chip to determine which gate(s) should be targeted. Once thelocation of the target gates has been determined, the attacker mustbreak the covering Tamper Detection line, stop the Erasure of Flashmemory, and somehow rewire the components that rely on the ChipOK lines.Rewiring the circuitry cannot be done without slicing the chip, and evenif it could be done, the act of slicing the chip to this level will mostlikely destroy the charge patterns in the non-volatile memory that holdsthe keys, making the process fruitless.

16.2.17 Overwrite Attack

An overwrite attack relies on being able to set individual bits of thekey without knowing the previous value. It relies on probing the chip,as in the conventional probing attack and destroying gates as in thegate destruction attack. Both of these attacks (as explained in theirrespective sections), will not succeed due to the use of the TamperPrevention and Detection Circuitry and ChipOK lines.

However, even if the attacker is able to somehow access the bits ofFlash and destroy or short out the gate holding a particular bit, thiswill force the bit to have no charge or a full charge. These are bothinvalid states for the authentication chip's usage of the multi-levelFlash memory (only the two middle states are valID). When that datavalue is transferred from Flash detection circuitry will cause theErasure Tamper Detection Line to be triggered—thereby erasing theremainder of Flash memory and RESETing the chIP. In the same way, aparity check on tampered values read from RAM will cause the ErasureTamper Detection Line to be triggered.

An overwrite attack is therefore fruitless.

16.2.18 Memory Remanence Attack

Any working registers or RAM within the authentication chip may beholding part of the authentication keys when power is removed. Theworking registers and RAM would continue to hold the information forsome time after the removal of power. If the chip were sliced so thatthe gates of the registers/RAM were exposed, without discharging them,then the data could probably be viewed directly using an STM.

The first defense can be found above, in the description of defenseagainst power glitch attacks. When power is removed, all registers andRAM are cleared, just as the RESET condition causes a clearing ofmemory.

The chances then, are less for this attack to succeed than for a readingof the Flash memory. RAM charges (by nature) are more easily lost thanFlash memory. The slicing of the chip to reveal the RAM will certainlycause the charges to be lost (if they haven't been lost simply due tothe memory not being refreshed and the time taken to perform theslicing).

This attack is therefore fruitless.

16.2.19 Chip Theft Attack

There are distinct phases in the lifetime of an authentication chIP.Chips can be stolen when at any of these stages:

-   -   After manufacture, but before programming of key    -   After programming of key, but before programming of state data    -   After programming of state data, but before insertion into the        consumable or system    -   After insertion into the system or consumable

A theft in between the chip manufacturer and programming station wouldonly provide the clone manufacturer with blank chips. This merelycompromises the sale of authentication chips, not anything authenticatedby the authentication chips. Since the programming station is the onlymechanism with consumable and system product keys, a clone manufacturerwould not be able to program the chips with the correct key. Clonemanufacturers would be able to program the blank chips for their ownSystems and Consumables, but it would be difficult to place these itemson the market without detection.

The second form of theft can only happen in a situation where anauthentication chip passes through two or more distinct programmingphases. This is possible, but unlikely. In any case, the worst situationis where no state data has been programmed, so all of M is read/write.If this were the case, an attacker could attempt to launch an adaptivechosen text attack on the chIP. The HMAC-SHA1 algorithm is resistant tosuch attacks. For more information see Section 14.7 on page 699.

The third form of theft would have to take place in between theprogramming station and the installation factory. The authenticationchips would already be programmed for use in a particular system or foruse in a particular consumable. The only use these chips have to a thiefis to place them into a clone System or clone Consumable. Clone systemsare irrelevant—a cloned System would not even require an authenticationchIP. For clone Consumables, such a theft would limit the number ofcloned products to the number of chips stolen. A single theft should notcreate a supply constant enough to provide clone manufacturers with acost-effective business.

The final form of theft is where the System or Consumable itself isstolen. When the theft occurs at the manufacturer, physical securityprotocols must be enhanced. If the theft occurs anywhere else, it is amatter of concern only for the owner of the item and the police orinsurance company. The security mechanisms that the authentication chipuses assume that the consumables and systems are in the hands of thepublic. Consequently, having them stolen makes no difference to thesecurity of the keys.

16.2.20 Trojan Horse Attack

A Trojan horse attack involves an attacker inserting a fakeauthentication chip into the programming station and retrieving the samechip after it has been programmed with the secret key information. Thedifficulty of these two tasks depends on both logical and physicalsecurity, but is an expensive attack—the attacker has to manufacture afalse authentication chip, and it will only be useful where the effortis worth the gain. For example, obtaining the secret key for a specificcar's authentication chip is most likely not worth an attacker'sefforts, while the key for a printer's ink cartridge may be veryvaluable.

The problem arises if the programming station is unable to tell a Trojanhorse authentication chip from a real one—which is the problem ofauthenticating the authentication chIP.

One solution to the authentication problem is for the manufacturer tohave a programming station attached to the end of the production line.Chips passing the manufacture QA tests are programmed with themanufacturer's secret key information. The chip can therefore beverified by the C1 authentication protocol, and give information such asthe expected batch number, serial number etc. The information can beverified and recorded, and the valid chip can then be reprogrammed withthe System or Consumable key and state data. An attacker would have tosubstitute an authentication chip with a Trojan horse programmed withthe manufacturer's secret key information and copied batch number datafrom the removed authentication chIP. This is only possible if themanufacturer's secret key is compromised (the key is changed regularlyand not known by a human) or if the physical security at themanufacturing plant is compromised at the end of the manufacturingchain.

Even if the solution described were to be undertaken, the possibility ofa Trojan horse attack does not go away—it merely is removed to themanufacturer's physical location. A better solution requires no physicalsecurity at the manufacturing location.

The preferred solution then, is to use transparent epoxy on the chip'spackaging and to image the chip before programming it. Once the chip hasbeen mounted for programming it is in a known fixed orientation. It cantherefore be high resolution photo-imaged and X-rayed from multipledirections, and the images compared against “signature”images. Any chipnot matching the image signature is treated as a Trojan horse andrejected.

1 Refill of Ink in Printers—Printer Based Refill Device

1.1 Functional Purpose

The functional purpose of the printer based refill device is as follows:

-   -   To refill ink into printers by physically connecting the refill        device to the printer.    -   To ensure that the correct ink is used for the correct operation        of the printer (i.e. will not damage the printhead).    -   To ensure accurate measure of ink is transferred from the        refilling device to the printer during refills.    -   The refill device is controlled by the printer. Apart from the        QA Chip¹ the refill device has no other processing power.        ¹General Note: Througout this document, if secure refilling is        required then a physical QA Chip or any other virtual device        performing the QA Chip protocol can be used. Refer to [1].        1.2 Basic Components of the Refill Device

FIG. 355 shows the components of the printer based refill device.

The printer based refill device will consist of following components:

-   -   An ink reservoir—which stores the ink. Each refill device will        allow ink reservoirs of various capacities. When the ink        reservoir empties out, it is replaced by another reservoir        containing more ink of the same type or different type or        refilled (for example through a refill station as described in        Section 2 and Section 3).    -   An ink output device—which dispenses ink to the printer being        refilled when physically connected to the printer.    -   A QA Chip and associated circuitry—which stores the amount of        ink in the reservoir along with the attributes of the ink in a        digital format.    -   The electrical connections to the QA ChIP.    -   NB—No additional microprocessors are required to be present in        the refill device. Hence the refill device uses the processing        power of the printer to oversee the refilling process.    -   An ink transfer mechanism (optional) which controls the flow ink        from the refill device to the printer and is controlled by the        printer. Therefore the control connections for the ink transfer        mechanism will be connected to the printer.    -   Alternatively, the ink transfer mechanism could be in the        printer. Refer to Section 1.3.        1.3 Printer Description and Functions

Printers which will be refilled by these refilling devices must have thefollowing components:

-   -   Microprocessor assembly which will control the refill procedure        as described Section 1.4. The microprocessor assembly will        access the QA Chip and ink transfer mechanism of the refill        device.    -   A QA Chip storing the ink amount remaining in the printer.    -   An optional ink transfer mechanism to control the flow of ink        from the refill device to the printer. This ink transfer        mechanism must be present in the printer if the refill device        doesn't have one of its own.        1.4 Operational Procedure

The operational procedure can be divided into two parts:

-   -   Refilling printers using the refill device.    -   Refilling of the ink reservoir in the refill device. See Section        2 and Section 3.        1.4.1 Refilling of Printers

FIG. 356 shows a printer being refilled by a printer based refilldevice. The ink transfer mechanism is located in the printer in thiscase. The ink transfer mechanism could be also located in the refilldevice as described in Section 1.2.

The following is a description for refilling of printers using theprinter based refill device:

-   -   Ink output device from the refilling device is connected to the        printer.    -   The QA Chip electrical connection is connected to the printer.    -   The refill option is selected on the user interface of the        printer. The microprocessor assembly in the printer will then do        the following:    -   a. Read ink attributes (for example ink type, ink        characteristics, ink colour, ink manufacturer etc) stored in the        QA Chip of the ink reservoir unit. Refer to [1].    -   b. Compare the ink attributes as required by the printer for        correct operation. This may require reading of data from the QA        Chip in the printer.    -   c. Only if Step b is successful, then do the following:        -   i. Determine the amount of ink to be transferred by any or            all of the following means, ensuring that the reservoir has            enough ink for the transfer:    -   Fixed amount (e.g. based on a pre-programmed value or printer        model).    -   User-selectable amount.        -   ii. Decrement the amount of ink transferred from the QA Chip            in the refill station and increment the QA Chip in the            printer (which stores the amount of ink in the printer) with            corresponding ink amount.        -   iii. Command the ink transfer mechanism to release the ink            to the printer through the output device.            2 Home Use Refill Station            2.1 Functional Purpose

The functional purpose of the commercial refill station is as follows:

-   -   To refill ink into ink cartridges at home or in a small office.    -   Single ink cartridge is filled at a time.    -   To ensure that the correct ink present in the refill station is        transferred to the correct ink cartridge.    -   To ensure accurate measure of ink is transferred from the        refilling station to the ink cartridge during refills.    -   The refilling station provides the processing power required to        perform refills of ink cartridges.        2.2 Basic Components

FIG. 357 shows the components of a home refill station.

A home refill station will consist of one of the following ink refillunits:

-   -   A single reservoir ink refill unit suitable for black ink (or        any other single colour).    -   A multi reservoir ink refill unit suitable for coloured ink for        example CMY (Cyan, Magenta, Yellow).        2.2.1 Ink Reservoir Unit

FIG. 358 shows the components of a three-ink reservoir unit.

The ink reservoir unit will consist of the following:

-   -   Multiple ink reservoirs or a single ink reservoir which stores        ink. Each refill station will allow ink reservoirs of various        capacities. When the ink reservoir empties out, it is replaced        by another reservoir containing more ink of the same or        different type or refilled (for example through a refill station        as described in Section 3).    -   A QA Chip and associated circuitry in each of the ink        reservoirs—which stores the amount of ink in the reservoir along        with the attributes of the ink.    -   The electrical connections to each of the QA Chips.        2.2.2 Ink Transfer Unit

The ink reservoir unit will consist of the following:

-   -   Ink output device from each ink reservoir.    -   The output ink transfer mechanism controls the flow ink from the        ink refill unit to the ink cartridge and is controlled by the        microprocessor assembly.    -   Final ink output devices to the cartridge interface assembly        2.2.3 Cartridge Interface Unit

This unit will provide the physical interface to the ink cartridges.Each ink cartridge interface unit will hold a single or multiplecartridges of particular physical dimension.

The cartridge interface unit can removed from the ink refill unit andreplaced with another interface unit to cater for other physicallydifferent cartridges.

2.2.4 Microprocessor Assembly

The controls connections for the ink transfer mechanism and theelectrical connections of the QA Chip are connected to themicroprocessor assembly. The microprocessor assembly oversees andcontrols the refill process.

The microprocessor assembly will communicate with a user interface toaccept commands and provide responses for various refill operations.

2.3 Ink Cartridge Description

Ink cartridges which will be refilled in a home refill station must havea QA Chip storing the following components:

-   -   Ink amount remaining.    -   Ink attributes (for example—ink type, ink characteristics, ink        colour, ink manufacturer).        2.4 Operational Procedure

The operational procedure can be divided into two parts:

-   -   Refilling of ink cartridges using the home refill station.    -   Refilling the ink reservoirs used in the refill station is        discussed in Section 3.        2.5 Refilling of Ink Cartridges Using the Home Refill Station

FIG. 359 shows the refill of ink cartridges in a home refill station.

The following is a description for refilling of ink cartridges in thehome refill station:

-   -   Load the ink cartridge into the cartridge interface unit of the        ink refill unit. This will connect the QA Chip of the ink        cartridge to the microprocessor assembly. It will also connect        the ink output device of the ink refill unit to the ink        cartridge.    -   The model number of the ink cartridge is read from the QA Chip        by the microprocessor assembly controlling the ink refill units.    -   The microprocessor assembly will determine whether the ink        refill unit is suitable for the ink cartridge model.    -   The refill option is selected on the microprocessor assembly        through the user interface. The microprocessor assembly will        then do the following:    -   a. Read ink attributes (for example ink type, ink        characteristics, ink colour, ink manufacturer etc) stored in the        QA Chip of the ink cartridge. Refer to [1].    -   b. Compare the read ink attributes to the ink attribute list in        the refill station. This may also require reading of the ink        attributes stored in the QA Chip of the ink reservoirs in the        refill unit.    -   c. Only if Step b is successful, then do the following:        -   i. Determine the amount of ink to be transferred by any or            all of the following means, ensuring that the reservoir has            enough ink for the transfer:    -   Fixed amount (e.g. based on a pre-programmed value cartridge        model or reservoir type).    -   User-selectable amount.        -   ii. Check the ink reservoir in the ink refill unit has            adequate amount of ink to refill the ink cartridge        -   iii. Decrement the amount of ink transferred from the QA            Chip in the ink refill unit and increment the QA Chip in the            ink cartridge with corresponding ink amount.        -   iv. If incrementing of the QA Chip with ink amount is            successful then a command is sent to the ink transfer            mechanism to release the ink to the ink cartridge through            the output device.            3 Commercial Refill Station            3.1 Functional Purpose

The functional purpose of the commercial refill station is as follows:

-   -   To refill ink into ink cartridges that are taken to the refill        station for refilling.    -   Multiple ink cartridges of different models can be refilled. To        ensure that the correct ink present in the refill station is        transferred to the ink cartridge.    -   To ensure accurate measure of ink is transferred from the        refilling station to the ink cartridge during refills.    -   The refilling station provides all processing power required to        perform refills of ink cartridges.        3.2 Basic Components of the Refill Station

FIG. 360 shows the components of a commercial refill station.

A commercial refill station will consist of multiple ink refill unitscontrolled by a single microprocessor assembly. Each ink refill unit canrefill a single ink cartridge at a time.

Each ink refill unit will consist of the following sub units:

-   -   Ink reservoir unit    -   Switch unit    -   Ink transfer unit    -   Multiple cartridge interface unit        3.2.1        Ink Reservoir Unit

FIG. 361 shows the components of a ink reservoir unit.

The ink reservoir unit will consist of the following:

-   -   Multiple ink reservoirs—which stores ink. Each refill device        will allow ink reservoirs of various capacities. When the ink        reservoir empties out, it is replaced by another reservoir        containing more ink of the same or different type or refilled.        Refer to Section 3.5.    -   A QA Chip and associated circuitry in each of the ink        reservoirs—which stores the amount of ink in the reservoir along        with the attributes of the ink in digital format.    -   The electrical connections of each of the QA Chips are connected        to the microprocessor assembly.        3.2.2 Switch Unit

This unit will switch the inks selected from different ink reservoirs tothe ink transfer unit to be dispensed into ink cartridges.

The switch unit will prevent mixing of any residual ink left indispensing devices after each ink cartridge is refilled.

3.2.3 Ink Transfer Unit

The ink reservoir unit will consist of the following:

-   -   Ink output device from each ink reservoir.    -   An output ink transfer mechanism which controls the flow ink        from the ink refill unit to the ink cartridge and is controlled        by the microprocessor assembly.    -   Final ink output devices to the multiple cartridge interface        assembly        3.2.4 Multiple Cartridge Interface Unit

This unit will provide the physical interface to the ink cartridges.Each ink cartridge interface will hold cartridges of different physicaldimensions.

Each cartridge interface unit can provide an interface for about 20physically different cartridges.

The cartridge interface unit can removed from the ink refill unit andreplaced with another interface unit to cater for other physicallydifferent cartridges.

3.2.5 Microprocessor Assembly with a User Interface

The controls connections for the ink transfer mechanism and theelectrical connections of the QA Chip are connected to themicroprocessor assembly. The microprocessor assembly will oversee andcontrol the refill process.

The microprocessor assembly will communicate with a user interface toaccept commands and provide responses for various refill operations.

3.3 Ink Cartridge Description

Ink cartridges which will be refilled in a commercial refill stationmust have a QA Chip storing the following components:

-   -   Ink amount remaining.    -   Ink attributes (for example—ink type, ink characteristics, ink        colour, ink manufacturer).        3.4 Operational Procedure

The operational procedure can be divided into two parts:

-   -   Refilling of ink cartridges using the commercial refill station.    -   Refilling the ink reservoirs used in the refill station is        covered in Section 3.5.        3.4.1 Refilling Ink Cartridges Using the Commercial Refill        Station

FIG. 362 shows the refill of ink cartridges in a commercial refillstation.

The following is a description for refilling of ink cartridges in thecommercial refill station:

-   -   Load the ink cartridge into the multiple cartridge interface        unit of the ink refill unit. This will connect the QA Chip of        the ink cartridge to the microprocessor assembly. It will also        connect the ink output device of the ink refill unit to the ink        cartridge.    -   The model number of the ink cartridge automatically is read from        the QA Chip by the microprocessor assembly controlling the ink        refill units.    -   The microprocessor assembly will determine whether the ink        refill unit is suitable for the ink cartridge model.    -   The refill option is selected on the microprocessor assembly        through the user interface. The microprocessor assembly will        then do the following:    -   a. Read ink attributes (for example ink type, ink        characteristics, ink colour, ink manufacturer etc) stored in the        QA Chip of the ink cartridge. Refer to [1].    -   b. Compare the read ink attributes to the ink attribute list in        the refill station. This may also require reading of the ink        attributes stored in the QA Chip of the ink reservoirs in the        refill unit.    -   c. Only if Step b is successful, then do the following:        -   i. Determine the amount of ink to be transferred by any or            all of the following means, ensuring that the reservoir has            enough ink for the transfer:    -   Fixed amount (e.g. based on a pre-programmed value, cartridge        model or reservoir type).    -   User-selectable amount.        -   ii. The microprocessor assembly will calculate the cost of            ink amount and interrogate the user for a payment            method—credit card or cash. If credit card option is            selected it will request a credit card number to be selected            and interface to a payment system to complete the            transaction before proceeding further.        -   iii. Decrement the amount of ink transferred from the QA            Chip in the ink refill unit and increment the QA Chip in the            ink cartridge with corresponding ink amount.        -   iv. If incrementing of the QA Chip with ink amount is            successful then a command is sent to the ink transfer            mechanism to release the ink to the ink cartridge through            the output device.            3.5 Refilling the Ink Reservoirs

The ink reservoirs of any ink refill device can be refilled recursivelyby the procedure described in Section 3.4.1, the only exception beingthe ink cartridge replaced by the ink reservoir.

3.6 Commercial Refill Station for a Production Environment

This refill station resembles a commercial refill station but fillsmultiple ink cartridges of the same type at the same time. This willserve as a filling station for new cartridges in a productionenvironment.

Logical Interface Specification for Preferred Form of QA Chip

1 Introduction

This document defines the QA Chip Logical Interface, which providesauthenticated manipulation of specific printer and consumableparameters. The interface is described in terms of data structures andthe functions that manipulate them, together with examples of use. Whilethe descriptions and examples are targetted towards the printerapplication, they are equally applicable in other domains.

2 Scope

The document describes the QA Chip Logical Interface as follows:

-   -   data structures and their uses (Section 5 to Section 9).    -   functions, including inputs, outputs, signature formats, and a        logical implementation sequence (Section 10 to Section 30).    -   typical functional sequences of printers and consumables, using        the functions and data structures of the interface (Section 31        to Section 32).

The QA Chip Logical Interface is a logical interface, and is thereforeimplementation independent.

Although this document does not cover implementation details onparticular platforms, expected implementations include:

-   -   Software only    -   Off-the-shelf cryptographic hardware.    -   ASICs, such as SBR4320 [2] and SOPEC [3] for physical insertion        into printers and ink cartridges    -   Smart cards.        3 Nomenclature        3.1 Symbols

The following symbolic nomenclature is used throughout this document:TABLE 246 Summary of symbolic nomenclature Symbol Description F[X]Function F, taking a single parameter X F[X, Y] Function F, taking twoparameters, X and Y X|Y X concatenated with Y X

Y Bitwise X AND Y X

Y Bitwise X OR Y (inclusive-OR) X ⊕ Y Bitwise X XOR Y (exclusive-OR)

X Bitwise NOT X (complement) X

Y X is assigned the value Y X

{Y, Z} The domain of assignment inputs to X is Y and Z X = Y X is equalto Y X ≠ Y X is not equal to Y

X Decrement X by 1 (floor 0)

X Increment X by 1 (modulo register length) Erase X Erase Flash memoryregister X SetBits[X, Y] Set the bits of the Flash memory register Xbased on Y Z

ShiftRight[X, Shift register X right one bit position, taking input bitY] from Y and placing the output bit in Z a.b Data field or memberfunction ‘b’ in object a.3.2 Pseudocode3.2.1 Asynchronous

The following pseudocode:

-   -   var=expression        -   means the var signal or output is equal to the evaluation of            the expression.            3.2.2 Synchronous

The following pseudocode:

-   -   var←expression        means the var register is assigned the result of evaluating the        expression during this cycle.        3.2.3 Expression

Expressions are defined using the nomenclature in Table 246 above.Therefore:

-   -   var=(a=b)        is interpreted as the var signal is 1 if a is equal to b, and 0        otherwise.        4 Terms        4.1 QA Device and System

An instance of a QA Chip Logical Interface (on any platform) is a QADevice.

QA Devices cannot talk directly to each other. A System is a logicalentity which has one or more QA Devices connected logically (orphysically) to it, and calls the functions on the QA Devices. The systemis considered secure and the program running on the system is consideredto be trusted.

4.2 Types of QA Devices

4.2.1 Trusted QA Device

The Trusted QA Device forms an integral part of the system itself andresides within the trusted environment of the system. It enables thesystem to extend trust to external QA Device s. The Trusted QA Device isonly trusted because the system itself is trusted.

4.2.2 External Untrusted QA Device

The External untrusted QA Device is a QA Device that resides external tothe trusted environment of the system and is therefore untrusted. Thepurpose of the QA Chip Logical Interface is to allow the externaluntrusted QA Devices to become effectively trusted. This is accomplishedwhen a Trusted QA Device shares a secret key with the external untrustedQA Device, or with a Translation QA Device (see below).

In a printing application external untrusted QA Devices would typicallybe instances of SBR4320 implementations located in a consumable or theprinter.

4.2.3 Translation QA Device

A Translation QA Device is used to translate signatures between QADevices and extend effective trust when secret keys are not directlyshared between QA Devices.

The Translation QA Device must share a secret key with the Trusted QADevice that allows the Translation QA Device to effectively becometrusted by the Trusted QA Device and hence trusted by the system. TheTranslation QA Device shares a different secret key with anotherexternal untrusted QA Device (which may in fact be a Translation QADevice etc). Although the Trusted QA Device doesn't share (know) the keyof the external untrusted QA Device, signatures generated by thatuntrusted device can be translated by the Translation QA Device intosignatures based on the key that the Trusted QA Device does know, andthus extend trust to the otherwise untrusted external QA Device.

In a SoPEC-based printing application, the Printer QA Device acts as aTranslation QA Device since it shares a secret key with the SoPEC, and adifferent secret key with the ink carridges.

4.2.4 Consumable QA Device

A Consumable QA Device is an external untrusted QA Device located in aconsumable. It typically contains details about the consumable,including how much of the consumable remains.

In a printing application the consumable QA Device is typically found inan ink cartridge and is referred to as an Ink QA Device, or simply InkQA since ink is the most common consumable for printing applications.However, other consumables in printing applications include media andimpression counts, so consumable QA Device is more generic.

4.2.5 Printer QA Device

A Printer QA Device is an external untrusted device located in theprinter. It contains details about the operating parameters for theprinter, and is often referred to as a Printer QA.

4.2.6 Value Upgrader QA Device

A Value Upgrader QA Device contains the necessary functions to allow asystem to write an initial value (e.g. an ink amount) into another QADevice, typically a consumable QA Device. It also allows a system torefill/replenish a value in a consumable QA Device after use.

Whenever a value upgrader QA Device increases the amount of value inanother QA Device, the value in the value upgrader QA Device iscorrespondingly decreased. This means the value upgrader QA Devicecannot create value—it can only pass on whatever value it itself hasbeen issued with. Thus a value upgrader QA Device can itself bereplenished or topped up by another value upgrader QA Device.

An example of a value upgrader is an Ink Refill QA Device, which is usedto fill/refill ink amount in an Ink QA Device.

4.2.7 Parameter Upgrader QA Device

A Parameter Upgrader QA Device contains the necessary functions to allowa system to write an initial parameter value (e.g. a print speed) intoanother QA Device, typically a printer QA Device. It also allows asystem to change that parameter value at some later date.

A parameter upgrader QA Device is able to perform a fixed number ofupgrades, and this number is effectively a consumable value. Thus thenumber of available upgrades decreases by 1 with each upgrade, and canbe replenished by a value upgrader QA Device.

4.2.8 Key Programmer QA Device

Secret batch keys are inserted into QA Devices during instantiation(e.g. manufacture). These keys must be replaced by the final secret keyswhen the purpose of the QA Device is known. The Key Programmer QA Deviceimplements all necessary functions for replacing keys in other QADevices.

4.3 Signature

Digital signatures are used throughout the authentication protocols ofthe QA Chip Logical Interface.

A signature is produced by passing data plus a secret key through akeyed hash function. The signature proves that the data was signed bysomeone who knew the secret key.

The signature function used throughout the QA Chip Logical Interface isHMAC-SHA1 [1].

4.3.4 Authenticated Read

This is a read of data from a non-trusted QA Device that also includes acheck of the signature (see Section 4.3.3). When the System determinesthat the signature is correct for the returned data (e.g. by asking atrusted QA Device to test the signature) then the System is able totrust that the data has not been tampered en route from the read, andwas actually stored on the non-trusted QA Device.

4.3.5 Authenticated Write

An authenticated write is a write to the data storage area in a QADevice where the write request includes both the new data and asignature. The signature is based on a key that has write accesspermissions to the region of data in the QA Device, and proves to thereceiving QA Device that the writer has the authority to perform thewrite. For example, a Value Upgrader Refilling Device is able toauthorize a system to perform an authenticated write to upgrade aConsumable QA Device (e.g. to increase the amount of ink in an Ink QADevice).

The QA Device that receives the write request checks that the signaturematches the data (so that it hasn't been tampered with en route) andalso that the signature is based on the correct authorization key.

An authenticated write can be followed by an authenticated read toensure (from the system's point of view) that the write was successful.

4.3.6 Non-Authenticated Write

A non-authenticated write is a write to the data storage area in a QADevice where the write request includes only the new data (and nosignature). This kind of write is used when the system wants to updateareas of the QA Device that have no access-protection.

The QA Device verifies that the destination of the write request hasaccess permissions that permit anyone to write to it. If access ispermitted, the QA Device simply performs the write as requested. Anon-authenticated write can be followed by an authenticated read toensure (from the system's point of view) that the write was successful.

4.3.7 Authorized Modification of Data

Authorized modification of data refers to modification of data viaauthenticated writes (see Section 4.3.5).

Table 2 provides a summary of the data structures used in the QA ChipLogical Interface. TABLE 2 List of data structures Group Representeddescription Name by Size Description QA Device Chip Identifier ChipId 48bits Unique identifier for this QA Device. instance identifier Key andkey Number of Keys NumKeys 8 Number of key slots available in this QADevice. related data Key K 160 bits per K is the secret key used forcalculating signatures. key K^(n) is the key stored in the nth key slot.Key Identifier KeyId 31 bits per key Unique identifier for each keyKeyId^(n) is the key identifier for the key stored in slot n. KeyLockKeyLock 1 bit per key Flag indicates whether the key is locked in thecorresponding slot or not. KeyLock^(n) is the key lock flag for slot n.Operating and Number of Memory Vectors NumVectors 4 Number of 512 bitmemory vectors in this QA Device. state data Memory Vector M 512 bitsper M M is a 512 bit memory vector. The 512-bit vector is divided into16 × 32 bit words. M⁰ M⁰ stores application specific data that isprotected by access permissions for key-based and non-key based writes.M¹ M¹ stores the attributes for M⁰, and is write-once-only. M²⁺ M²⁺stores application specific data that is protected only by non key-basedaccess permissions. Permissions P^(n) 16 bits per P Access permissionsfor each word ofM¹⁺. n = number of M^(1+ vectors) Session data RandomNumber R 160 bits Current random number used to ensure time varyingmessages. Changes after each successful authentication or signaturegeneration.6 Instance/Device Identifier

Each QA Device requires an identifier that allows unique identificationof that QA Device by external systems, ensures that messages arereceived by the correct QA Device, and ensures that the same device canbe used across multiple transactions.

Strictly speaking, the identifier only needs to be unique within thecontext of a key, since QA Devices only accept messages that areappropriately signed. However it is more convenient to have the instanceidentifier completely unique, as is the case with this design.

The identifier functionality is provided by ChipId.

6.1 ChipId

ChipId is the unique 64-bit QA Device identifier. The ChipId is set whenthe QA Device is instantiated, and cannot be changed during the lifetimeof the QA Device.

A 64-bit ChipId gives a maximum of 1844674 trillion unique QA Devices.

7 Key and Key Related Data

7.1 NumKeys, K, keyID, and KeyLock

Each QA Device contains a number of secret keys that are used forsignature generation and verification. These keys serve two basicfunctions:

-   -   For reading, where they are used to verify that the read data        came from the particular QA Device and was not altered en route.    -   For writing, where they are used to ensure only authorised        modification of data.

Both of these functions are achieved by signature generation; a key isused to generate a signature for subsequent transmission from thedevice, and to generate a signature to compare against a receivedsignature.

The number of secret keys in a QA Device is given by NumKeys. For thisversion of the QA Chip Logical Interface, NumKeys has a maximum value of8.

Each key is referred to as K, and the subscripted form K_(n) refers tothe nth key where n has the range 0 to NumKeys-1 (i.e. 0 to 7). Forconvenience we also refer to the nth key as being the key in the nthkeyslot.

The length of each key is 160-bits. 160-bits was chosen because theoutput signature length from the signature generation function(HMAC-SHA1) is 160 bits, and a key longer than 160-bits does not add tothe security of the function.

The security of the digital signatures relies upon keys being keptsecret. To safeguard the security of each key, keys should be generatedin a way that is not deterministic. Ideally each key should beprogrammed with a physically generated random number, gathered from aphysically random phenomenon. Each key is initially programmed during QADevice instantiation.

Since all keys must be kept secret and must never leave the QA Device,each key has a corresponding 31-bit KeyId which can be read to determinethe identity or label of the key without revealing the value of the keyitself. Since the relationship between keys and KeyIds is 1:1, a systemcan read all the KeyIds from a QA Device and know which keys are storedin each of the keyslots.

Finally, each keyslot has a corresponding 1-bit KeyLock statusindicating whether the key in that slot/position is allowed to bereplaced (securely replaced, and only if the old key is known). Once akey has been locked into a slot, it cannot be unlocked i.e. it is thefinal key for that slot. A key can only be used to perform authenticatedwrites of data when it has been locked into its keyslot (i.e. itsKeyLock status=1). Refer to Section 8.1.1.5 for further details.

Thus each of the NumKeys keyslots contains a 160-bit key, a 31-bitKeyID, and a 1-bit KeyLock.

7.2 Common and Variant Signature Generation

To create a digital signature, we pass the data to be signed togetherwith a secret key through a key dependent one-way hash function. The keydependent one-way hash function used throughout the QA Chip LogicalInterface is HMAC-SHA1[1].

Signatures are only of use if they can be validated i.e. QA Device Aproduces a signature for data and QA Device B can check if the signaturewas valid for that particular data. This implies that A and B must sharesome secret information so that they can generate equivalent signatures.

Common key signature generation is when QA Device A and QA Device Bshare the exact same key i.e. key K_(A)=key K_(B). Thus the signaturefor a message produced by A using K_(A) can be equivalently produced byB using K_(B). In other words SIG_(KA)(message)=SIG_(KB)(message)because key K_(A)=key K_(B).

Variant key signature generation is when QA Device B holds a base key,and QA Device A holds a variant of that key such thatK_(A)=owf(K_(B),U_(A)) where owf is a one-way function based upon thebase key (K_(B)) and a unique number in A (U_(A)). Thus A can produceSIG_(KA)(message), but for B to produce an equivalent signature it mustproduce K_(A) by reading U_(A) from A and using its base key K_(B).K_(A) is referred to as a variant key and K_(B) is referred to as thebase/common key. Therefore, B can produce equivalent signatures frommany QA Devices, each of which has its own unique variant of K_(B).Since ChipId is unique to a given QA Device, we use that as U_(A). Aone-way function is required to create K_(A) from K_(B) or it would bepossible to derive K_(B) if K_(A) were exposed.

Common key signature generation is used when A and B are equallyavailable¹ to an attacker. For example, Printer QA Devices and Ink QADevices are equally available to attackers (both are commonly availableto an attacker), so shared keys between these two devices should becommon keys.¹The term “equally available” is relative. It typically means that theease of availability of both are the effectively the same, regardless ofprice (e.g. both A and B are commercially available and effectivelyequally easy to come by).

Variant key signature generation is used when B is not readily availableto an attacker, and A is readily available to an attacker. If anattacker is able to determine K_(A), they will not know K_(A) for anyother QA Device of class A, and they will not be able to determineK_(B).

The QA Device producing or testing a signature needs to know if it mustuse the common or variant means of signature generation. Likewise, whena key is stored in a QA Device, the status of the key (whether it is abase or variant key) must be stored along with it for future reference.Both of these requirements are met using the KeyId as follows:

The 31-bit KeyId is broken into two parts:

-   -   A 30-bit unique identifier for the key. Bits 30-1 represents the        Id.    -   A 1-bit Variant Flag, which represents whether the key is a base        key or a variant key. Bit 0. represents the Variant Flag.

Table 247 describes the relationship of the Variant Flag with the key.TABLE 247 Variant Flag representation value Key represented 0 Base key 1Variant key7.2.1 Equivalent Signature Generation Between QA Devices

Equivalent signature generation between 4 QA Devices A, B, C and D isshown in FIG. 363. Each device has a single key. KeyId.Id of all fourkeys are the same i.eKeyId_(A).Id=KeyId_(B).Id=KeyId_(C).Id=KeyId_(D).Id.

If KeyId_(A). VariantFlag=0 and KeyId_(B). VariantFlag=0, then asignature produced by A, can be equivalently produced by B becauseK_(A)=K_(B).

If KeyId_(B). VariantFlag=0 and KeyId_(C). VariantFlag=1, then asignature produced by C, is equivalently produced by B because K_(C)=f(K_(B), ChipId_(C)).

If KeyId_(C). VariantFlag=1 and KeyId_(D). VariantFlag=1, then asignature produced by C, cannot be equivalently produced by D becausethere is no common base key between the two devices.

If KeyId_(D). VariantFlag=1 and KeyId_(A). VariantFlag=0, then asignature produced by D, can be equivalently produced by A becauseK_(D)=f (K_(A), ChipId_(D)).

8 Operating and State Data

The primary purpose of a QA Device is to securely holdapplication-specific data. For example if the QA Device is an Ink QADevice it may store ink characteristics and the amount of ink-remaining.If the QA Device is a Printer QA Device it may store the maximum speedand width of printing.

For secure manipulation of data:

-   -   Data must be clearly identified (includes typing of data).    -   Data must have clearly defined access criteria and permissions.

The QA Chip Logical Interface contains structures to permit theseactivities.

The QA Device contains a number of kinds of data with differing accessrequirements:

-   -   Data that can be decremented by anyone, but only increased in an        authorised fashion e.g. the amount of ink-remaining in an ink        cartridge.    -   Data that can only be decremented in an authorised fashion e.g.        the number of times a Parameter Upgrader QA Device has upgraded        another QA Device.    -   Data that is normally read-only, but can be written to (changed)        in an authorised fashion e.g. the operating parameters of a        printer.    -   Data that is always read-only and doesn't ever need to be        changed e.g. ink attributes or the serial number of an ink        cartridge or printer.    -   Data that is written by QACo/Silverbrook, and must not be        changed by the OEM or end user e.g. a licence number containing        the OEM's identification that must match the software in the        printer.    -   Data that is written by the OEM and must not be changed by the        end-user e.g. the machine number that filled the ink cartridge        with ink (for problem tracking).        8.1 M

M is the general term for all of the memory (or data) in a QA Device. Mis further subscripted to refer to those different parts of M that havedifferent access requirements as follows:

-   -   M₀ contains all of the data that is protected by access        permissions for key-based (authenticated) and non-key-based        (non-authenticated) writes.    -   M₁ contains the type information and access permissions for the        M₀ data, and has write-once permissions (each sub-part of M₁ can        only be written to once) to avoid the possibility of changing        the type or access permissions of something after it has been        defined.    -   M₂, M₃ etc., referred to as M₂₊, contains all the data that can        be updated by anyone until the permissions for those sub-parts        of M₂₊ have changed from read/write to read-only.

While all QA Devices must have at least M₀ and M₁, the exact number ofmemory vectors (M_(n)s) available in a particular QA Device is given byNumVectors. In this version of the QA Chip Logical Interface there areexactly 4 memory vectors, so NumVectors=4.

Each M_(n) is 512 bits in length, and is further broken into 16×32 bitwords. The ith word of M_(n) is referred to as M_(n)[i]. M_(n)[0] is theleast significant word of M_(n), and M_(n)[15] is the most significantword of M_(n).

8.1.1 M₀ and M₁

In the general case of data storage, it is up to the external accessorto interpret the bits in any way it wants. Data structures can bearbitrarily arranged as long as the various pieces of software andhardware that interpret those bits do so consistently. However if thosebits have value, as in the case of a consumable, it is vital that thevalue cannot be increased without appropriate authorisation, or one typeof value cannot be added to another incompatible kind e.g. dollarsshould never be added to yen.

Therefore M₀ is divided into a number of fields, where each field has asize, a position, a type and a set of permissions. M₀ contains all ofthe data that requires authenticated write access (one data element perfield), and M₁ contains the field information i.e. the size, type andaccess permissions for the data stored in M₀.

Each 32-bit word of M₁ defines a field. Therefore there is a maximum of16 defined fields. M₁[0] defines field 0, M₁[1] defines field 1 and soon. Each field is defined in terms of:

-   -   size and position, to permit external accessors determine where        a data item is    -   type, to permit external accessors determine what the data        represents    -   permissions, to ensure approriate access to the field by        external accessors.

The 32-bit value M₁[n] defines the conceptual field attributes for fieldn as follows: With regards to consistency of interpretation, the type,size and position information stored in the various words of M₁ allows asystem to determine the contents of the corresponding fields (in M₀)held in the QA Device. For example, a 3-color ink cartridge may have anInk QA Device that holds the amount of cyan ink in field 0, the amountof magenta ink in field 1, and the amount of yellow ink in field 2,while another single-color Ink QA Device may hold the amount of yellowink in field 0, where the size of the fields in the two Ink QA Devicesare different.

A field must be defined (in M₁) before it can be written to (in M₀). AtQA Device instantiation, the whole of M₀ is 0 and no fields are defined(all of M₁ is 0). The first field (field 0) can only be created bywriting an appropriate value to M₁[0]. Once field 0 has been defined,the words of M₀ corresponding to field 0 can be written to (via theappropriate permissions within the field definition M₁[0]).

Once a field has been defined (i.e. M₁[n] has been written to), thesize, type and permissions for that field cannot be changed i.e. M₁ iswrite-once. Otherwise, for example, a field could be defined to be liraand given an initial value, then the type changed to dollars.

The size of a field is measured in terms of the number of consecutive32-bit words it occupies.

Since there are only 16×32-bit words in M₀, there can only be 16 fieldswhen all 16 fields are defined to be 1 word sized each. Likewise, themaximum size of a field is 512 bits when only a single field is defined,and it is possible to define two fields of 256-bits each.

Once field 0 has been created, field 1 can be created, and so on. Whenenough fields have been created to allocate all of M₀, the remainingwords in M₁ are available for write-once general data storage purposes.

It must be emphasised that when a field is created the permissions forthat field are final and cannot be changed. This also means that anykeys referred to by the field permissions must be already locked intotheir keyslots. Otherwise someone could set up a field's permissionsthat the key in a particular keyslot has write access to that fieldwithout any guarantee that the desired key will be ever stored in thatslot (thus allowing potential mis-use of the field's value).

8.1.1.1 Field Size and Position

A field's size and position are defined by means of 4 bits (referred toas EndPos) that point to the least significant word of the field, withan implied position of the field's most significant word. The impliedposition of field 0's most significant word is M₀[15]. The positions andsizes of all fields can therefore be calculated by starting from field 0and working upwards until all the words of M₀ have been accounted for.

The default value of M₁[0] is 0, which means field0.endPos=0. Sincefield0.startPos=15, field 0 is the only field and is 16 words long.

8.1.1.1.1 EXAMPLE

Suppose for example, we want to allocate 4 fields as follows:

-   -   field 0: 128 bits (4×32-bit words)    -   field 1: 32 bits (1×32-bit word)    -   field 2: 160 bits (5×32-bit words)    -   field 3: 192 bits (6×32-bit words)

Field 0's position and size is defined by M₁[0], and has an assumedstart position of 15, which means the most significant word of field 0must be in M₀[15]. Field 0 therefore occupies M₀[12] through to M₀[15],and has an endPos value of 12.

Field 1's position and size is defined by M₁[1], and has an assumedstart position of 11 (i.e. M₁[0].endPos-1). Since it has a length of 1word, field 1 therefore occupies only M₀[11] and its end position is thesame as its start position i.e. its endPos value is 11.

Likewise field 2's position and size is defined by M₁[2], and has anassumed start position of 10 (i.e. M₁[1].endPos-1). Since it has alength of 5 words, field 2 therefore occupies M₀[6] through to M₀[10]and and has an endPos value of 6.

Finally, field 3's position and size is defined by M₁[3], and has anassumed start position of 5 (i.e. M₁[2].endPos-1). Since it has a lengthof 6 words, field 3 therefore occupies M₀[5] through to M₀[0] and andhas an endPos value of 0.

Since all 16 words of M₀ are now accounted for in the 4 fields, theremaining words of M₁ (i.e. M₁[4] though to M₁[15]) are ignored, and canbe used for any write-once (and thence read-only) data.

FIG. 365 shows the same example in diagramatic format.

8.1.1.1.2 Determining the Number of Fields

The following pseudocode illustrates a means of determining the numberof fields: fieldNum FindNumFields(M1) startPos

15 fieldNum

0 While (fieldNum < 16)  endPos

M1[fieldNum].endPos  If (endPos > startPos)   # error in this field...so must be an attack   attackDetected( ) # most likely clears all keysand data  EndIf  fieldNum++  If (endPos = 0)   return fieldNum # isalready incremented  Else   startPos

endPos − 1 # endpos must be > 0  EndIf EndWhile # error if get heresince 16 fields are consumed in 16 words at most attackDetected( ) #most likely clears all keys and data8.1.1.1.3 Determining the Sizes of All Fields

The following pseudocode illustrates a means of determing the sizes ofall valid fields: FindFieldSizes(M1, fieldSize[ ]) numFields

FindNumFields(M1) # assumes that FindNumFields does all checkingntartPos

15 fieldNum

0 While (fieldNum < numFields)  EndPos

M1[fieldNum].endPos  fieldSize[fieldNum] = startPos − endPos + 1 startPos

endPos − 1 # endpos must be > 0  fieldNum++ EndWhile While (fieldNum <16)  fieldSize[fieldNum]

0  fieldNum++ EndWhile8.1.1.2 Field Type

The system must be able to identify the type of data stored in a fieldso that it can perform operations using the correct data. For example, aprinter system must be able identify which of a consumable's fields areink fields (and which field is which ink) so that the ink usage can becorrectly applied during printing.

A field's type is defined by 15 bits. Table 332 in Appendix A lists thefield types that are specifically required by the QA Chip LogicalInterface and therefore apply across all applications.

The default value of M₁[0] is 0, which means field0.type=0 (i.e.non-initialised).

Strictly speaking, the type need only be interpreted by all who cansecurely read and write to that field i.e. within the context of one ormore keys. However it is convenient if possible to keep all types uniquefor simplistic identification of data across all applications.

In the general case, an external system communicating with a QA Devicecan identify the data stored in M0 in the following way:

-   -   Read the KeyId of the key that has permission to write to the        field. This will a give broad identification of the data type,        which may be sufficient for certain applications.    -   Read the type attribute for the field to narrow down the        identity within the broader context of the KeyId.

For example, the printer system can read the KeyId to deduce that thedata stored in a field can be written to via the HP_Network_InkRefillkey, which means that any data is of the general ink category known toHP Network printers. By further reading the type attribute for the fieldthe system can determine that the ink is Black ink.

8.1.1.3 Field Permissions

All fields can be ready by everyone. However writes to fields aregoverned by 13-bits of permissions that are present in each field'sattribute definition. The permissions describe who can do what to aspecific field.

Writes to fields can either be authenticated (i.e. the data to bewritten is signed by a key and this signature must be checked by thereceiving device before write access is given) or non-authenticated(i.e. the data is not signed by a key). Therefore we define a single bit(AuthRW) that specifies whether authenticated writes are permitted, anda single bit (NonAuthRW) specifying whether non-authenticated writes arepermitted. Since it is pointless to permit both authenticated andnon-authenticated writes to write any value (the authentciated writesare pointless), we further define the case when both bits are set to beinterpreted as authenticated writes are permitted, but non-authenticatedwrites only succeed when the new value is less than the previous valuei.e. the permission is decrement-only. The interpretation of these twobits is shown in Table 249. TABLE 249 Interpretation of AuthRW andNonAuthRW NonAuthRW AuthRW Interpretation 0 0 Read-only access (no-onecan write to this field). This is the initial state for each field. Atinstantiation all of M₁ is 0 which means AuthRW and NonAuthRW are 0 foreach field, and hence none of M₀ can be written to until a field isdefined. 0 1 Authenticated write access is permitted Non-authenticatedwrite acecss is not permitted 1 0 Authenticated write access is notpermitted Non-authenticated write access is permitted (i.e. anyone canwrite to this field) 1 1 Authenticated write access is permittedNon-authenticated write access is decrement-only.

If authenticated write access is permitted, there are 11 additional bits(bringing the total number of permission bits to 13) to more fullydescribe the kind of write access for each key. We only permit a singlekey to have the ability to write any value to the field, and theremaining keys are defined as being either not permitted to write, or ashaving decrement-only write access. A 3-bit KeyNum represents the slotnumber of the key that has the ability to write any value to the field(as long as the key is locked into its key slot), and an 8-bit KeyPermsdefines the write permissions for the (maximum of) 8 keys as follows:

-   -   KeyPerms[n]=0: The key in slot n (i.e. K_(n)) has no write        access to this field (except when n=KeyNum). Setting KeyPerms to        0 prohibits a key from transferring value (when an amount is        deducted from field in one QA Device and transferred to another        field in a different QA Device)    -   KeyPerms[n]=1: The key in slot n (i.e. K_(n)) is permitted to        perform decrement-only writes to this field (as long as K_(n) is        locked in its key slot). Setting KeyPerms to 1 allows a key to        transfer value (when an amount is deducted from field in one QA        Device and transferred to another field in a different QA        Device).

The 13-bits of permissions (within bits 4-16 of M₁[n]) are allocated asfollows:

8.1.1.3.1 Example 1

FIG. 367 shows an example of permission bits for a field.

In this example we can see:

-   -   NonAuthRW=0 and AuthRW=1, which means that only authenticated        writes are allowed i.e. writes to the field without an        appropriate signature are not permitted.    -   KeyNum=3, so the only key permitted to write any value to the        field is key 3 (i.e. K₃).    -   KeyPerms[3]=0, which means that although key 3 is permitted to        write to this field, key 3 can't be used to transfer value from        this field to other QA Devices.    -   KeyPerms[0,4,5,6,7]=0, which means that these respective keys        cannot write to this field.    -   KeyPerms[1,2]=1, which means that keys 1 and 2 have        decrement-only access to this field i.e. they are permitted to        write a new value to the field only when the new value is less        than the current value.

8.1.1.3.2 Example 2

FIG. 368 shows a second example of permission bits for a field.

In this example we can see:

-   -   NonAuthRW and AuthRW=1, which means that authenticated writes        are allowed and writes to the field without a signature are only        permitted when the new value is less than the current value        (i.e. non-authenticated writes have decrement-only permission).    -   KeyNum=3, so the only key permitted to write any value to the        field is key 3 (i.e. K₃).    -   KeyPerms[3]=1, which means that key 3 is permitted to write to        this field, and can be used to transfer value from this field to        other QA Devices.    -   KeyPerms[0,4,5,6,7]=0, which means that these respective keys        cannot write to this field.    -   KeyPerms[1,2]=1, which means that keys 1 and 2 have        decrement-only access to this field i.e. they are permitted to        write a new value to the field only when the new value is less        than the current value.        8.1.1.4 Summary of Field Attributes

FIG. 369 shows the breakdown of bits within the 32-bit field attributevalue M₁[n]. Table 250 summarises each attribute. TABLE 250 Attributesfor a field Size Attribute Sub-attribute name in bits InterpretationType Type 15 Gives additional identification of the data stored in thefield within the context of the accessors of that field. PermissionsKeyNum 3 The slot number of the key that has authenticated write accessto the field. NonAuthRW 1 0 = non-authenticated writes are not permittedto this field. 1 = non-authenticated writes are permitted to this field(see Table 249). AuthRW 1 0 = authenticated writes are not permitted tothis field. 1 = authenticated writes are permitted to this field.KeyPerms 8 Bitmap representing the write permissions for each of thekeys when AuthRW = 1. For each bit: 0 = no write access for this key(except for key KeyNum) 1 = decrement-only access is permitted for thiskey. Size and EndPos 4 The word number in M₀ that holds the lsw Positionof the field. The msw is held in M1[fieldNum−1], where msw of field 0 is15.8.1.1.5 Permissions of M₁

M₁ holds the field attributes for data stored in M₀, and each word of M₁can be written to once only.

It is important that a system can determine which words are availablefor writing. While this can be determined by reading M₁ and determiningwhich of the words is non-zero, a 16-bit permissions value P₁ isavailable, with each bit indicating whether or not a given word in M₁has been written to. Bit n of P₁ represents the permissions for M₁[n] asfollows: TABLE 251 Interpretation of P₁[n] i.e. bit n of M₁'s permissionDescription 0 writes to M₁[n] are not permitted i.e. this word is nowread-only 1 writes to M₁[n] are permitted

Since M₁ is write-once, whenever a word is written to in M₁, thecorresponding bit of P₁ is also cleared, i.e. writing to M₁[n] clearsP₁[n].

Writes to M₁[n] only succeed when all of M₁[0...n−1] have alreadywritten to (i.e. previous fields are defined) i.e.

-   -   M₁[0..n−1] must have already been written to (i.e. P₁[0..n−1]        are 0)    -   P₁[n]=1 (i.e. it has not yet been written to)

In addition, if M₁[n−1].endPos≠0, the new M₁[n] word will define theattributes of field n, so must be further checked as follows:

-   -   The new M₁[n].endPos must be valid (i.e. must be less than        M₁[n−1].endPos)    -   If the new M₁[n].authRW is set, K_(keyNum) must be locked, and        all keys referred to by the new M₁[n].keyPerms must also be        locked.

However if M₁[n−1].endPos=0, then all of M₀ has been defined in terms offields. Since enough fields have been created to allocate all of M₀, anyremaining words in M₁ are available for write-once general data storagepurposes, and are not checked any further.

8.1.2 M2+

M₂, M₃ etc., referred to as M₂+, contains all the data that can beupdated by anyone (i.e. no authenticated write is required) until thepermissions for those sub-parts of M₂₊ have changed from read/write toread-only.

The same permissions representation as used for M₁ is also used for M₂₊.Consequently P_(n) is a 16-bit value that contains the permissions forM_(n) (where n>0). The permissions for word w of M_(n) is given by asingle bit P_(n)[w]. However, unlike writes to M₁, writes to M₂₊ do notautomatically clear bits in P. Only when the bits in P₂₊ are explictlycleared (by anyone) do those corresponding words become read-only andfinal.

9 Session Data

Data that is valid only for the duration of a particular communicationsession is referred to as session data. Session data ensures that everysignature contains different data (sometimes referred to as a nonce) andthis prevents replay attacks.

9.1 R

R is a 160-bit random number seed that is set up (when the QA Device isinstantiated) and from that point on it is internally managed andupdated by the QA Device. R is used to ensure that each signed itemcontains time varying information (not chosen by an attacker), and eachQA Device's R is unrelated from one QA Device to the next.

This R is used in the generation and testing of signatures.

An attacker must not be able to deduce the values of R in present andfuture devices. Therefore, R should be programmed with acryptographically strong random number, gathered from a physicallyrandom phenomenon (must not be deterministic).

9.2 Advancing R

The session component of the message must only last for a single session(challenge and response).

The rules for updating R are as follows:

-   -   Reads of R do not advance R.    -   Everytime a signature is produced with R, R is advanced to a new        random number.    -   Everytime a signature including R is tested and is found to be        correct, R is advanced to a new random number.        9.3 R_(L) and R_(E)

Each signature contains 2 pieces of session data i.e. 2 Rs:

-   -   One R comes from the QA Device issuing the challenge i.e. the        challenger. This is so the challenger can ensure that the        challenged QA Device isn't simply replaying an old signature        i.e. the challenger is protecting itself against the challenged.    -   One R comes from the device responding to the challenge i.e. the        challenged. This is so the challenged never signs anything that        is given to it without inserting some time varying change i.e.        protects the challenged from the challenger in case the        challenger is actually an attacker performing a chosen text        attack

Since there are two Rs, we need to distinguish between them. We do so bydefining each R as external (R_(E)) or local (R_(L)) depending on itsuse in a given function. For example, the challenger sends out its localR, referred to as R_(L). The device being challenged receives thechallenger's R as an external R, i.e R_(E). It then generates asignature using its R_(L) and the challenger's R_(E). The resultantsignature and R_(L) are sent to the challenger as the response. Thechallenger receives the signature and R_(E) (signature and R_(L)produced by the device being challenged), produces its own signatureusing R_(L) (sent to the device being challenged earlier) and R_(E)received, and compares that signature to the signature received asresponse.

Signature Functions

10 Objects

10.1 KeyRef

10.1.1 Object Description

Instead of passing keys directly into a function, a KeyRef (i.e. keyreference) object is passed instead. A KeyRef object encapsulates theprocess by which a key is formed for common and variant forms ofsignature generation (based on the setting of the variables within theobject). A KeyRef defines which key to use, whether it is a common orvariant form of that key, and, if it is a variant form, the ChipId touse to create the variant. For more information about common and variantforms of keys, see Section 7.2.

Users pass KeyRef objects in as input parameters to public functions ofthe QA Chip Logical Interface, and these KeyRefs are subsequently passedto the signature function (called within the interface function). Note,however, that the method functions for KeyRef objects are not availableoutside the QA Chip Logical Interface.

10.1.2 Object Variables

Table 252 describes each of the variables within a KeyRef object. TABLE252 Description of object variables for KeyRef object ParameterDescription keyNum Slot number of the key to use as the basis for keyformation useChipId 0 = the key to be formed is a common key (i.e. isthe same as K_(keyNum)) 1 = the key to be formed is a variant key basedon K_(keyNum) ChipId When useChipId = 1, this is the ChipId to be usedto form the variant key (this will be the ChipId of the QA Device whichstores the variant of K_(keyNum)) When useChipId = 0, chipId is not used10.1.3 Object Methods10.1.3.1 getKey

-   -   public key getKey(void)        10.1.3.1.1 Method Description

This method is a public method (public in object oriented terms, notpublic to users of the QA Chip Logical Interface) and is called by theGenerateSignature function to return the key for use in signaturegeneration.

If useChipId is true, the formKeyVariant method is called to form thekey using chipid and then return the variant key. If useChipId is false,the key stored in slot keyNum is returned.

10.1.3.1.2 Method Sequence

The getKey method is illustrated by the following pseudocode: If(useChipId = 0)  key

K_(keyNum) Else  key

formKeyVariant( ) EndIf Return key10.1.3.2 formKeyVariant

-   -   private key formKeyVariant (voID)        10.1.3.2.1 Method Description

This method produces the variant form of a key, based on the K_(keyNum)and chipId. As described in Section 7.2, the variant form of keyK_(keyNum) is generated by owf (K_(keyNum), chipID) where owf is aone-way function.

In addition, the time taken by owf must not depend on the value of thekey i.e. the timing should be effectively constant. This prevents timingattacks on the key.

At present, owf is SHA1, although this still needs to be verified. Thusthe variant key is defined to be SHA1(K_(keyNum)|chipID).

10.1.3.2.2 Method Sequence

The formKeyVariant method is illustrated by the following pseudocode:key

SHA1(K_(keyNum)| chipId) # Calculation must take constant time Returnkey11 Functions

Digital signatures form the basis of all authentication protocols withinthe QA Chip Logical Interface. The signature functions are not directlyavailable to users of the QA Chip Logical Interface, since a golden ruleof digital signatures is never to sign anything exactly as it has beengiven to you.

Instead, these signature functions are internally available to thefunctions that comprise the public interface, and are used by thosefunctions for the formation of keys and the generation of signatures.

11.1GenerateSignature Input: KeyRef, Data, Random1, Random2 Output: SIGChanges: None Availability: All devices11.1.1 Function Description

This function uses KeyRef to obtain the actual key required forsignature generation, appends Random1 and Random2 to Data, and performsHMAC_SHA1[key, Data] to output a signature. HMAC_SHA1 is described in[1]. In addition, this operation must take constant time irrespective ofthe value of the key (see Section 10.1.3.2 for more details).

11.1.2 Input Parameter Description

Table 253 describes each of the input parameters: TABLE 253 Descriptionof input parameters for GenerateSignature Parameter Description KeyRefThis is an instance of the KeyRef object for use by theGenerateSignature function. For common key signature generation:KeyRef.keyNum = Slot number of the key to be used to produce thesignature. KeyRef.useChipId = 0 For variant key signature generation:KeyRef.keyNum = Slot number of the key to be used for generating thevariant key, where the variant key is to be used to produce thesignature KeyRef.useChipId = 1 KeyRef.chipId = ChipId of the QA Devicewhich stores the variant of K_(KeyRef.keyNum), and uses the variant keyfor signature generation. Data Preformatted data to be signed. Random1and Random2 are appended to Data before the signature is generated toensure that the signature is session based (applicable only to a singlesession). Random1 This is the session component from the QA Device thatis responding to the challenge. Random2 This is the session componentfrom the QA Device that issued the challenge.11.1.3 Output Parameter Description

Table 254 describes each of the output parameters. TABLE 254 Descriptionof output parameters for GenerateSignature Parameter Description SIG SIG= SIG_(key)(Data|Random1|Random2) where key = KeyRef.getKey( )11.1.4 Function Sequence

The GenerateSignature function is illustrated by the followingpseudocode: key

KeyRef.getKey( ) dataToBeSigned

Data|Random1|Random2 SIG

HMAC_SHA1(key, dataToBeSigned) # Calculation must take constant timeOutput SIG ReturnBasic Functions12 Definitions

This section defines return codes and constants referred to by functionsand pseudocode.

12.1 ResultFlag

The ResultFlag is a byte that indicates the return status from afunction. Callers can use the value of ResultFlag to determine whether acall to a function succeeded or failed, and if the call failed, thespecific error condition.

Table 255 describes the ResultFlag values and the mnemonics used in thepseudocode. TABLE 255 ResultFlag value description Mnemonic DescriptionPossible causes Pass Function completed Function successfully completedrequested task. sucessfully Fail General Failure An error occurredduring function processing. BadSig Signature mismatch Input signaturedidn't match the generated signature. InvalidKey KeyRef incorrect InputKeyRef.keyNum > 3. InvalidVector VectNum incorrect Input M_(VectNum) >3. InvalidPermission Permission not adqeuate to Trying to perform aWrite or WriteAuth with incorrect perform operation. permissions.KeyAlreadyLocked Key already locked. Key cannot be changed because ithas already been locked.12.2 Constants

Table 256 describes the constants referred to by functions andpseudocode. TABLE 256 Constants Definition Value MaxKey NumKeys − 1(typically 7) MaxM NumVectors − 1 (typically 3) MaxWordInM 16 − 1 = 15

13 GetInfo Input: None Output: ResultFlag, SoftwareReleaseIdMajor,SoftwareReleaseIdMinor, NumVectors, NumKeys, ChipId DepthOfRollBackCache(for an upgrade device only) Changes: None Availability: All devices13.1 Function Description

Users of QA Devices must call the GetInfo function on each QA Devicebefore calling any other functions on that device.

The GetInfo function tells the caller what kind of QA Device this is,what functions are available and what properties this QA Device has. Thecaller can use this information to correctly call functions withappropriately formatted parameters.

The first value returned, SoftwareReleaseIdMajor, effectively identifieswhat kind of QA Device this is, and therefore what functions areavailable to callers. SoftwareReleaseIdMinor tells the caller whichversion of the specific type of QA Device this is. The mapping betweenthe SoftwareReleaseIdMajor and type of device and their differentfunctions is described in Table 258 Every QA Device also returnsNumVectors, NumKeys and ChipId which are required to set input parametervalues for commands to the device.

Additional information may be returned depending on the type of QADevice. The VarDataLen and VarData fields of the output hold thisadditional information.

13.2 Output parameters

Table 257 describes each of the output parameters. TABLE 257 Descriptionof output parameters for GetInto function Parameter #bytes DescriptionResultFlag Indicates whether the function completed successfully or not.If it did not complete successfully, the reason for the failure isreturned here. See Section 12.1. SoftwareReleaseIdMajor 1 This definesthe function set that is available on this QA Device.SoftwareReleaseIdMinor 1 This defines minor software releases within amajor release, and are incremental changes to the software mainly todeal with bug fixes. NumVectors 1 Total number of memory vectors in thisQA Device. NumKeys 1 Total number of keys in this QA Device. ChipId 6This QA Device's ChipId VarDataLen 1 Length of bytes to follow. VarData(VarDataLen This is additional application specific data, and will be ofbytes) length VarDataLen (i.e. may be 0).

Table 258 shows the mapping between the SoftwareReleaseIdMajor, the typeof QA Device and the available device functions. TABLE 258 Mappingbetween SoftwareReleaseIdMajor and available device functionsSoftwareReleaseId Major Device description Functions available 1 Ink orPrinter QA Device GetInfo Random Read Test Translate WriteM1+WriteFields WriteFieldsAuth SetPerm ReplaceKey 2 Value Upgrader QADevice (e.g. Ink All functions in the Ink or Printer Refill QA Device)Device, plus: StartXfer XferAmount StartRollBack RollBackAmount 3Parameter Upgrader QA Device All functions in the Ink or Printer device,plus: StartXfer XferField StartRollBack RollBackField 4 Key Replacementdevice All functions in the Ink or Printer Device, plus: GetProgramKeyReplaceKey - is different from the Ink or Printer device 5 Trusteddevice All functions in the Ink or Printer Device, plus: SignM

Table 259 shows the VarData components for Value Upgrader and ParameterUpgrader QA Devices. TABLE 259 VarData for Value and Parameter UpgraderQA Devices VarData Length in Components bytes DescriptionDepthOfRollBackCache 1 The number of datasets that can be accommodatedin the Xfer Entry cache of the device.13.3 Function Sequence

The GetInfo command is illustrated by the following pseudocode:

-   -   Output SoftwareReleaseIdMajor    -   Output SoftwareReleaseIdMinor    -   Output NumVectors    -   Output NumKeys    -   Output ChipId    -   VarDataLen ←1# In case of an upgrade device    -   Output    -   Return

14 Random Input: None Output: R_(L) Changes: None Availability: Alldevices

The Random command is used by the caller to obtain a session component(challenge) for use in subsequent signature generation.

If a caller calls the Random function multiple times, the same outputwill be returned each time. R_(L) (i.e. this QA Device's R) will onlyadvance to the next random number in the sequence after a successfultest of a signature or after producing a new signature. The same R_(L)can never be used to produce two signatures from the same QA Device.

The Random command is illustrated by the following pseudocode:

-   -   Output R_(L)    -   Return

15Read Input: KeyRef, SigOnly, MSelect, KeyIdSelect, WordSelect, R_(E)Output: ResultFlag, SelectedWordsOfSelectedMs, SelectedKeyIds, R_(L),SIG_(out) Changes: R_(L) Availability: All devices15.1 Function Description

The Read command is used to read data and keyIds from a QA Device. Thecaller can specify which words from M and which KeyIds are read.

The Read command can return both data and signature, or just thesignature of the requested data.

Since the return of data is based on the caller's input request, itprevents unnecessary information from being sent back to the caller.Callers typically request only the signature in order to confirm thatlocally cached values match the values on the QA Device.

The data read from an untrusted QA Device (A) using a Read command isvalidated by a trusted QA Device (B) using the Test command. The R_(L)and SIG_(out) produced as output from the Read command are input (alongwith correctly formatted data) to the Test command on a trusted QADevice for validation of the signature and hence the data. SIG_(out) canalso optionally be passed through the Translate command on a number ofQA Devices between Read and Test if the QA Devices A and B do not sharekeys.

15.2 Input Parameters

Table 260 describes each of the input parameters: TABLE 260 Descriptionof input parameters for Read Parameter Description KeyRef For common keysignature generation: KeyRef.keyNum = Slot number of the key to be usedfor producing the output signature. KeyRef.useChipId = 0 No variant keysignature generation required SigOnly Flag indicating return ofsignature and data. 0- indicates both the signature and data are to bereturned. 1- indicates only the signature is to be returned. MselectSelection of memory vectors to be read - each bit corresponding to agiven memory vector (a maximum of NumVector bits) 0- indicates thememory vector must not be read. 1- indicates memory vector must be read.KeyIdSelect Selection of KeyIds to be read - each bit corresponds to agiven KeyId (a maximum of NumKey bits). 0- indicates KeyId must not beread. 1- indicates KeyId must be read. WordSelect Selection of wordsread from a desired M as requested in MSelect. Each WordSelect is 16bits corresponding to each bit in MSelect. Each bit in the WordSelectindicates whether or not to read the corresponding word for theparticular M. 0- indicates word must not be read. 1- indicates word mustbe read. R_(E) External random value required for output signaturegeneration (i.e the challenge). R_(E) is obtained by calling the Randomfunction on the device which will receive the SIG_(out) from the Readfunction.15.3 Output Parameters

Table 261 describes each of the output parameters. Parameter DescriptionResultFlag Indicates whether the function completed successfully or not.If it did not complete successfully, the reason for the failure isreturned here. See Section 12.1. SelectedWordsOfSelected Selected wordsfrom selected memory Ms vectors as requested by MSelect and WordSelect.SelectedKeyIds Selected KeyIds as requested by KeyIdSelect. R_(L) Localrandom value added to the output signature(i.e SIG_(out)). Refer to FIG.370. SIG_(out) SIG_(out) = SIG_(KeyRef)(data|R_(L)|R_(E)) as shown inFIG. 8. Refer to Section 10.1.3.1 for details.15.3.1 SIG_(out)

FIG. 370 shows the formatting of data for output signature generation.

Table 262 gives the parameters included in SIG_(out) Value set ParameterLength in bits Value set internally from Input RWSense 3 read constant =000 Refer to Section 15.3.1.1 MSelect 4 ● KeyIdSelect 8 ● ChipId 48 ThisQA Device's ChipId WordSelect 16 per M ● SelectedWordsOfSelected 32 perword The appropriate words from the ● Ms various Ms as selected by thecaller R_(L) 160 This QA Device's current R R_(E) 160 ●15.3.1.1 RWSense

An RWSense value is present in the signed data to distinguish whether asignature was produced from a Read or produced for a WriteAuth.

The RWSense is set to a read constant (000) for producing a signaturefrom a read function. The RWSense is set to a write constant (001) forproducing a signature for a write function.

The RWSense prevents signatures produced by Read to be subsequently sentinto a WriteAuth function. Only signatures produced with RWSense set towrite (001), are accepted by a write function.

15.4 Function sequence

The Read command is illustrated by the following pseudocode: Acceptinput parameters- KeyRef, SigOnly, MSelect, KeyIdSelect # Accept inputparameter WordSelect based on MSelect For i

0 to MaxM  If(MSelect[i] = 1)   Accept next WordSelect  WordSelectTemp[i]

WordSelect  EndIf EndFor Accept R_(E) Check range of KeyRef.keyNum Ifinvalid  ResultFlag

InvalidKey  Output ResultFlag  Return EndIf #BuildSelectedWordsOfSelectedMs k

0 # k stores the word count for SelectedWordsOfSelectedMsSelectedWordsOfSelectedMs[k]

0 For i

0 to 3  If(MSelect[i] = 1)   For j

0 to MaxWordInM    If(WordSelectTemp[i] [j] = 1)    SelectedWordsOfSelectedMs[k]

(M_(i)[j])     k++    EndIf   EndFor  EndIf EndFor #Build SelectedKeyIds1

0 # 1 stores the word count for SelectedKeyIds SelectedKeyIds[1]

0 For i

0 to MaxKey  If(KeyIdSelect[i] = 1)   SelectedKeyIds[1]

KeyId[i]   1++  EndIf EndFor #Generate message for passing into theGenerateSignature function data

(RWSense|MSelect|KeyIdSelect|ChipId|WordSelect    |SelectedWordsOfSelectedMs|SelectedKeyIds) # Refer to Figure 370.#Generate Signature function SIG_(L)

GenerateSignature(KeyRef,data,R_(L),R_(E)) # See Section 11.1 UpdateR_(L) to R_(L2) ResultFlag

Pass Output ResultFlag If(SigOnly = 0)  OutputSelectedWordsOfSelectedMs, SelectedKeyIds EndIf Output R_(L), SIG_(L)Return

16 Test Input: KeyRef, DataLength, Data, R_(E), SIG_(E) Output:ResultFlag Changes: R_(L) Availability: All devices except ink device16.1 Function Description

The Test command is used to validate data that has been read from anuntrusted QA Device according to a digital signature SIG_(E). The datawill typically be memory vector and KeyId data. SIG_(E) (and its relatedR_(E)) is the most recent signature—this will be the signature producedby Read if Translate was not used, or will be the output from the mostrecent Translate if Translate was used. The Test function produces alocal signature (SIG_(L)=SIG_(key)(Data|R_(E)|R_(L)) and compares it tothe input signature (SIG_(E)). If the two signatures match the functionreturns ‘Pass’, and the caller knows that the data read can be trusted.

The key used to produce SIG_(L) depends on whether SIG_(E) was producedby a QA Device sharing a common key or a variant key. The KeyRef objectpassed into the interface must be set appropriately to reflect this.

The Test function accepts preformatted data (as DataLength number ofwords), and appends the external R_(E) and local R_(L) to thepreformatted data to generate the signature as shown in FIG. 371.

16.2 Input Parameters

Table 263 describes each of the input parameters. TABLE 263 Descriptionof input parameters for Test Parameter Description KeyRef For testingcommon key signature: KeyRef.keyNum = Slot number of the key to be usedfor testing the signature. SIG_(E) produced using K_(KeyRef.keyNum) bythe external device. KeyRef.useChipId = 0 For testing variant keysignature: KeyRef.keyNum = Slot number of the key to be used forgenerating the variant key. SIG_(E) produced using a variant ofK_(KeyRef.keyNum by the external device. KeyRef.useChipId = 1)KeyRef.chipId = ChipId of the device which generated SIG_(E) using avariant of K_(KeyRef.keyNum). DataLength Length of preformatted data inwords. Must be non zero. Data Preformatted data to be used for producingthe signature. R_(E) External random value required for verifying theinput signature. This will be the R from the input signature generator(i.e the device generating SIG_(E)). SIG_(E) External signature requiredfor authenticating input data as shown in FIG. 371. The externalsignature is generated either by a Read function or a Translatefunction. A correct SIG_(E) = SIG_(KeyRef)(Data|R_(E)|R_(L)).16.2.1 Input Signature Verification Data Format

FIG. 371 shows the formatting of data for input signature verification.

The data in FIG. 371 (i.e. not R_(E) or R_(L)) is typically output froma Read function (formatted as per FIG. 370). The data may also begenerated in the same format by the system from its cache as will be thecase when it performs a Read using SigOnly=1.

16.3 Output Parameters

Table 264 describes each of the output parameters. TABLE 264 Descriptionof output parameters for Test Parameter Description ResultFlag Indicateswhether the function completed successfully or not. If it did notcomplete successfully, the reason for the failure is returned here. SeeSection 12.1.16.4 Function Sequence

The Test command is illustrated by the following pseudocode:

Accept input parameters—KeyRef, DataLength Accept inputparameters-KeyRef, DataLength # Accept input parameter- Data based onDataLength For i

0 to (DataLength − 1)  Accept next word of Data EndFor Accept inputparameters - R_(E), SIG_(E) Check range of KeyRef.keyNum If invalid ResultFlag

InvalidKey  Output ResultFlag  Return EndIf #Generate signature SIG_(L)

GenerateSignature(KeyRef,Data,R_(E),R_(L)) # Refer to Figure 371. #Checksignature If(SIG_(L) = SIG_(E))  Update R_(L) to R_(L2)  ResultFlag

Pass Else  ResultFlag

BadSig EndIf Output ResultFlag Return

17 Translate Input: InputKeyRef, DataLength, Data, R_(E), SIG_(E),OutputKeyRef, R_(E2) Output: ResultFlag, R_(L2), SIG_(Out) Changes:R_(L) Availability: Printer device, and possibly on other devices17.1 Function Description

It is possible for a system to call the Read function on QA Device A toobtain data and signature, and then call the Test function on QA DeviceB to validate the data and signature. In the same way it is possible fora system to call the SignM function on a trusted QA Device B and thencall the WriteAuth function on QA Device B to actually store data on B.Both of these actions are only possible when QA Devices A and B sharesecret key information.

If however, A and B do not share secret keys, we can create a validationchain (and hence extension of trust) by means of translation ofsignatures. A given QA Device can only translate signatures if it knowsthe key of the previous stage in the chain as well as the key of thenext stage in the chain. The Translate function provides thisfunctionality.

The Translate function translates a signature from one based on one keyto one based another key. The Translate function first performs a testof the input signature using the InputKeyRef, and if the test succeedsproduces an output signature using the OutputKeyRef. The Translatefunction can therefore in some ways be considered to be a combination ofthe Test and Read function, except that the data is input into the QADevice instead of being read from it.

The InputKeyRef object passed into Translate must be set appropriatelyto reflect whether SIG_(E) was produced by a QA Device sharing a commonkey or a variant key.

The key used to produce output signature SIG_(out) depends on whetherthe translating device shares a common key or a variant key with the QADevice receiving the signature. The OutputKeyRef object passed intoTranslate must be set appropriately to reflect this.

Since the Translate function does not interpret or generate the data inany way, only preformatted data can be passed in. The Translate functiondoes however append the external R_(E) and local R_(L) to thepreformatted data for verifying the input signature, then advances R_(L)to R_(L2), and appends R_(L2) and R_(E2) to the preformatted data toproduce the output signature. This is done to protect the keys andprevent replay attacks.

The Translate Functions Translates:

-   -   signatures for subsequent use in Test, typically originating        from Read    -   signatures for subsequent use in WriteAuth, typically        originating from SignM

In both cases, preformatted data is passed into the Translate functionby the system. For translation of data destined for Test, the datashould be preformatted as per FIG. 370 (all words except the Rs). Fortranslation of signatures for use in WriteAuth, the data should bepreformatted as per FIG. 373 (all words except the Rs).

17.2 Input Parameters

Table 265 describes each of the input parameters. TABLE 265 Descriptionof input parameters for Translate Parameter Description InputKeyRef Fortranslating common key input signature: InputKeyRef.keyNum = Slot numberof the key to be used for testing the signature. SIG_(E) produced usingK_(InputKeyRef.keyNum) by the external device. InputKeyRef.useChipId = 0For translating variant key input signatures: InputKeyRef.keyNum = Slotnumber of the key to be used for generating the variant key. SIG_(E)produced using a variant of K_(InputKeyRef.keyNum) by the externaldevice. InputKeyRef.useChipId = 1 InputKeyRef.chipId = ChipId of thedevice which generated SIG_(E) using a variant ofK_(InputKeyRef.keyNum). DataLength: Length of data in words. Data Dataused for testing the input signature and for producing the outputsignature. R_(E) External random value required for verifying inputsignature. This will be the R from the input signature generator (i.edevice generating SIG_(E)). SIG_(E) External signature required forauthenticating input data. The external signature is either generated bya Read function, a Xfer/Rollback function or a Translate function. Acorrect SIG_(E) = SIG_(KeyRef)(Data|R_(E)|R_(L)). OutputKeyRef Forgenerating common key output signature: OutputKeyRef.keyNum = Slotnumber of the key for producing the output signature. SIGout producedusing K_(OutputKeyRef.keyNum) because the device receiving SIGout sharesK_(OutputKeyRef.keyNum) with the translating device.OutputKeyRef.useChipId = 0 For generating variant key output signature:OutputKeyRef.keyNum = Slot number of the key to be used for generatingthe variant key. SIGout produced using a variant ofK_(OutputKeyRef.keyNum) because the device receiving SIGout shares avariant of K_(OutputKeyRef.keyNum) with the translating device.OutputKeyRef.useChipId = 1 OutputKeyRef.chipId = ChipId of the devicewhich receives SIG_(out) produced by a variant ofK_(OutputKeyRef.keyNum). R_(E2) External random value required foroutput signature generation. This will be the R from the destination ofSIG_(out). R_(E2) is obtained by calling the Random function on thedevice which will receive the SIG_(out) from the Translate function.17.2.1 Input Signature Verification Data Format

This is the same format as used in the Test function. Refer to Section16.2.1.

17.3 Output parameters

Table 266 describes each of the output parameters. TABLE 266 Descriptionof output parameters for Translate Parameter Description ResultFlagIndicates whether the function completed successfully or not. If it didnot complete successfully, the reason for the failure is returned here.See Section 12.1. R_(L2) Local random value used in output signature(i.e SIG_(Out)). SIG_(Out) Output signature produced usingOutputKeyRef.keyNum using the data format described in FIG. 372.SIG_(Out) = SIG_(OutKeyRef)(Data|R_(L2)|R_(E2)). Refer to Section10.1.3.1for details.17.3.1 SIG_(out)

FIG. 372 shows the data format for output signature generation from theTranslate function.

17.4 Function Sequence

The Translate command is illustrated by the following pseudocode: Acceptinput parameters-InputKeyRef, DataLength # Accept input parameter- Databased on DataLength For i

0 to (DataLength − 1)  Accept next Data EndFor Accept input parameters -R_(E), SIG_(E,)OutputKeyRef, R_(E2) Check range of InputKeyRef.keyNumand OutputKeyRef.keyNum If invalid  ResultFlag

Invalidkey  Output ResultFlag  Return EndIf #Generate Signature SIG_(L)

GenerateSignature(InputKeyRef,Data,R_(E),R_(L)) # Refer to Figure 371.#Validate input signature If(SIG_(L) = SIG_(E))  Update R_(L) to R_(L2)Else  ResultFlag

BadSig  Output ResultFlag  Return EndIf #Generate output signatureSIG_(Out)

GenerateSignature(OutputKeyRef,Data,R_(E),R_(L)) # Refer to Figure 372.Update R_(L2) to R_(L3) ResultFlag

Pass Output ResultFlag, R_(L2), SIG_(Out) Return

18 WriteM1+ Input: VectNum, WordSelect, MVal Output: ResultFlag Changes:M_(VectNum) Availability: All devices18.1 Function description

The WriteM1+ function is used to update selected words of M1+, subjectto the permissions corresponding to those words stored in P_(VectNum).

Note: Unlike WriteAuth, a signature is not required as an input to thisfunction.

18.2 Input Parameters

Table 267 describes each of the input parameters. TABLE 267 Descriptionof input parameters for WriteM1+ Parameter Description VectNum Number ofthe memory vector to be written. Must be in range 1 to (NumVectors −1)WordSelect Selection of words to be written. 0 - indicates correspondingword is not written. 1 - indicates corresponding word is to be writtenas per input. If WordSelect[N bit] is set, then write to M_(VectNum)word N. MVal Multiple of words corresponding to the number of wordsselected for write. Starts with LSW of M_(VectNum).

Note: Since this function has no accompanying signatures, additionalinput parameter error checking is required.

18.3 Output Parameters

Table 268 describes each of the output parameters. TABLE 268 Descriptionof output parameters for WriteM1+ Parameter Description ResultFlagIndicates whether the function completed successfully or not. If it didnot complete successfully, the reason for the failure is returned here.See Section 12.1.18.4 Function Sequence

The WriteM1+ command is illustrated by the following pseudocode: Acceptinput parameters VectNum, WordSelect #Accept MVal as per WordSelectMValTemp[16]

0 # Temporary buffer to hold MVal after being read For i

0 to MaxWordInM # word 0 to word 15  If(WordSelect[i] = 1)   Accept nextMVal   MValTemp[i]

MVal # Store MVal in temporary buffer  EndIf EndFor Check range ofVectNum If invalid  ResultFlag

InvalidVector  Output ResultFlag  Return EndIf #Checking nonauthenticated write permission for M1+ PermOK

CheckM1+Perm(VectNum,WordSelect) #Writing M with MVal If(PermOK =1) WriteM(VectNum,MValTemp[ ])  ResultFlag

Pass Else  ResultFlag

InvalidPermission EndIf Output ResultFlag Return18.4.1 PermOK CheckM1+Perm (VectNum, WordSelect)

This function checks WordSelect against permission P_(VectNum) for theselected word For i

0 to MaxWordInM # word 0 to word 15  If(WordSelect[i] = 1)

(P_(VectNum)[i] = 0) # Trying to write a ReadOnly word   Return PermOK

0  EndIf EndFor Return PermOK

118.4.2 WriteM(VectNum, MvalTemp

)

This function copies MvalTemp to M_(VectNum). For i

0 to MaxWordInM # Copying word from temp buff to M   If(VectNum = 1) #If M1    P_(VectNum)[i]

0 # Set permission to ReadOnly before writing   EndIf   M_(VectNum)[i]

MValTemp[i] #       copy word buffer to M word  EndIf EndFor

19 WriteFields Input: FieldSelect, FieldVal Output: ResultFlag Changes:M_(VectNum) Availability: All devices19.1 Function Description

The WriteFields function is used to write new data to selected fields(stored in M0). The write is carried out subject to thenon-authenticated write access permissions of the fields as stored inthe appropriate words of M1 (see Section 8.1.1.3).

The WriteFields function is used whenever authorization for a write(i.e. a valid signature) is not required. The WriteFieldsAuth functionis used to perform authenticated writes to fields. For example,decrementing the amount of ink in an ink cartridge field is permitted byanyone via the WriteFields, but incrementing it during a refilloperation is only permitted using WriteFieldsAuth. Therefore WriteFieldsdoes not require a signature as one of its inputs.

19.2 Input Parameters

Table 269 describes each of the input parameters. TABLE 269 Descriptionof input parameters for WriteFields Parameter Description FieldSelectSelection of fields to be written. 0 - indicates corresponding field isnot written. 1 - indicates corresponding field is to be written as perinput. If FieldSelect [N bit] is set, then write to Field N of M0.FieldVal Multiple of words corresponding to the words for all selectedfields. Since Field0 starts at M0[15], FieldVal words starts with MSW oflower field.19.3 Output Parameters

Table 270 describes each of the output parameters. TABLE 270 Descriptionof output parameters for WriteFields Parameter Description ResultFlagIndicates whether the function completed successfully or not. If it didnot complete successfully, the reason for the failure is returned here.See Section 12.1.19.4 Function Sequence

The WriteFields command is illustrated by the following pseudocode:Accept input parameters FieldSelect #Accept FieldVal as per FieldSelectinto a temporary buffer MValTemp #Find the size of each FieldNum toaccept FieldData FieldSize[16]

0 # Array to hold FieldSize assuming there are 16 fields NumFields

FindNumberOfFieldsInM0(M1,FieldSize) MValTemp[16]

0 # Temporary buffer to hold FieldVal after being read For i

0 to NumFields  If FieldSelect[i] = 1   If i = 0 # Check if field numberis 0    PreviousFieldEndPos

MaxWordInM   Else    PreviousFieldEndPos

M1[i−1].EndPos # position of the last word for the                      # previous field   EndIf   For j

(PreviousFieldEndPos −1) to M1[FieldNum].EndPos( )    MValTemp[j] = NextFieldVal word #Store FieldVal in MValTemp.   EndFor  EndIf EndFor #Checknon-authenticated write permissions for all fields in FieldSelect PermOK

CheckM0NonAuthPerm(FieldSelect,MValTemp,M0,M1) #Writing M0 with MValTempif permissions allow writing If(PermOK =1)  WriteM(0,MValTemp) ResultFlag

Pass Else  ResultFlag

InvalidPermission EndIf Output ResultFlag Return19.4.1 NumFields FindNumOfFieldsInM0(M1,FieldSize

)

This function returns the number of fields in M0 and an array FieldSizewhich stores the size of each field. CurrPos

0 NumFields

0 FieldSize[16]

0 # Array storing field sizes For FieldNum

0 to MaxWordInM  If(CurrPos = 0) # check if last field has reached  Return FieldNum #FieldNum indicates number of fields in M0  EndIf FieldSize[FieldNum]

CurrPos − M1[FieldNum].EndPos  If(FieldSize[FieldNum] < 0)   Error #Integrity problem with field attributes   Return FieldNum # Lower M0fields are still valid but higher M0 fields are          # ignored  Else  CurrPos

M1[FieldNum].EndPos  EndIf EndFor19.4.2 Word BitMapForField GetWordMapForField(FieldNum,M1)

This function returns the word bitmap corresponding to a field i.e thefield consists of which consecutive words. WordBitMapForField

0 WordMapTemp

0 PreviousFieldEndPos

M1[FieldNum −1].EndPos # position of the last word for the                        # previous field For j

(PreviousFieldEndPos +1) to M1[FieldNum].EndPos( )  # Set bitcorresponding to the word position  WordMapTemp

SHIFTLEFT(1, j)  WordBitMapForField

WordMapTemp

WordBitMapForField EndFor Return WordBitMapForField

Return WordBitMapForField

19.4.3 PermOK CheckM0NonAuthPerm(FieldSelect,MValTemp

,M0,M1)

This functions checks non-authenticated write permissions for all fieldsin FieldSelect. PermOK CheckM0NonAuthPerm( ) FieldSize[16]

0 NumFields

FindNumOfFieldsInM0(FieldSize) # Loop through all fields in FieldSelectand check their # non-authenticated permission For i

0 to NumFields  If FieldSelect[i] = 1 # check selected  WordBitMapForField

GetWordMapForField(i,M1) #get word bitmap for field   PermOK

CheckFieldNonAuthPerm(i,WordBitMapForField,MValTemp,M0,)        # Checkpermission for field i in FieldSelect   If(PermOK = 0) #Writing is notallowed, return if permissions for field       # doesn't allow writing   Return PermOK   EndIf  EndIf EndFor Return PermOK19.4.4 PermOK

CheckFieldNonAuthPerm(FieldNum,WordBitMapForField, MValTemp

, M0)

This function checks non authenticated write permissions for the field.DecrementOnly

0 AuthRW

M1[FieldNum].AuthRW NonAuthRW

M1[FieldNum].AuthRW If(NonAuthRW = 0) # No NonAuth write allowed  ReturnPermOK

0 EndIf If((AuthRW = 0)

(NonAuthRW = 1))# NonAuthRW allowed  Return PermOK

1 ElseIf(AuthRW = 1)

(NonAuthRW = 1)# NonAuth DecrementOnly allowed  PermOK

CheckInputDataForDecrementOnly(M0,MValTemp, WordBitMapForField)  ReturnPermOK EndIf19.4.5 PermOK CheckInputDataForDecrementOnly(M0,MValTemp

,WordBitMapForField)

This function checks the data to be written to the field is less thanthe current value. DecEncountered

0 LessThanFlag

0 EqualToFlag

0 For i = MaxWordInM to 0  If(WordBitMapForField[i] = 1) # starting wordof the field - starting at MSW  # comparing the word of temp buffer withM0 current value  LessThanFlag

M0[i] < MValTemp[i]  EqualToFlag

M0[i] = MValTemp[i]  # current value is less or previous value has beendecremented  If(LessThanFlag =1)

(DecEncountered = 1)   DecEncountered

1   PermOK

1   Return PermOK  ElseIf(EqualToFlag≠1) # Only if the value is greaterthan current and decrement not encountered in previous words    PermOK

0    Return PermOK   EndIf  EndIf EndFor19.4.6 WriteM(VectNum, MValTemp

)

Refer to Section 18.4.2 for details.

20 WriteFieldsAuth Input: KeyRef, FieldSelect, FieldVal, R_(E), SIG_(E)Output: ResultFlag Changes: _(M0) and R_(L) Availability: All devices20.1 Function Description

The WriteFieldsAuth command is used to securely update a number offields (in _(M0)). The write is carried out subject to the authenticatedwrite access permissions of the fields as stored in the appropriatewords of M1 (see Section 8.1.1.3). WriteFieldsAuth will either updateall of the requested fields or none of them; the write only succeedswhen all of the requested fields can be written to.

The WriteFieldsAuth function requires the data to be accompanied by anappropriate signature based on a key that has appropriate writepermissions to the field, and the signature must also include the localR (i.e. nonce/challenge) as previously read from this QA Device via theRandom function.

The appropriate signature can only be produced by knowing K_(KeyRef).This can be achieved by a call to an appropriate command on a QA Devicethat holds a key matching K_(KeyRef). Appropriate commands includeSignM, XferAmount, XferField, StartXfer, and StartRollBack.

20.2 Input Parameters

Table 271 describes each of the input parameters for WriteAuth.Parameter Description KeyRef For common key signature generation:KeyRef.keyNum = Slot number of the key to be used for testing the inputsignature. KeyRef.useChipId = 0 No variant key signature generationrequired FieldSelect Selection of fields to be written. 0 - indicatescorresponding field is not written. 1 - indicates corresponding field isto be written as per input. If FieldSelect [N bit] is set, then write toField N of M0. FieldVal Multiple of words corresponding to the totalnumber of words for all selected fields. Since Field0 starts at M0[15],FieldVal words starts with MSW of lower field. RE External random valueused to verify input signature. This will be the R from the inputsignature generator (i.e device generating SIG_(E)). SIGE Externalsignature required for authenticating input data. The external signatureis either generated by a Translate or one of the Xfer functions. Acorrect SIG_(E) = SIG_(KeyRef)(data|R_(E)|R_(L)).20.2.1 Input Signature Verification Data Format

FIG. 373 shows the input signature verification data format for theWriteAuth function. Value set Parameter Length in bits Value setinternally from Input RWSense  3 write constant = 001 Refer to Section15.3.1.1 FieldNum  4 ● ChipID  48 This QA Device's ChipId FieldData 32per word ● R_(E) 160 ● R_(L) 160 random value from device20.3 Output Parameters

Table 273 describes each of the output parameters. TABLE 273 Descriptionof output parameters for WriteAuth Parameter Description ResultFlagIndicates whether the function completed successfully or not. If it didnot complete successfully, the reason for the failure is returned here.See Section 12.1.20.4 Function Sequence

The WriteAuth command is illustrated by the following pseudocode: Acceptinput parameters-KeyRef, FieldSelect, #Accept FieldVal as perFieldSelect into a temporary buffer MValTemp #Find the size of eachFieldNum to accept FieldData FieldSize[16]

0 # Array to hold FieldSize assuming there are 16 fields NumFields

FindNumberOfFieldsInM0(M1,FieldSize) MValTemp[16]

0 # Temporary buffer to hold FieldVal after being read For i

0 to NumFields  If i = 0 # Check if field number is 0  PreviousFieldEndpos

MaxWordInM  Else   PreviousFieldEndpos

M1[i−1].EndPos # position of the last word for the previous field  EndIf For j

(PreviousFieldEndPos −1) to M1[FieldNum].EndPos( )   MValTemp[j] = NextFieldVal word #Store FieldVal in MValTemp.  EndFor  EndIf EndFor AcceptR_(E), SIG_(E) Check range of KeyRef.keyNum If invalid range  ResultFlag

InvalidKey  Output ResultFlag  Return EndIf #Generate message forpassing to GenerateSignature function data

(RWSense|FieldSelect|ChipId|FieldVal #Generate Signature SIG_(L)

GenerateSignature(KeyRef,data,R_(E),R_(L)) # Refer to Figure 373. #Checksignature If(SIG_(L) = SIG_(E))  Update R_(L) to R_(L2) Else  ResultFlag

BadSig  Output ResultFlag  Return EndIf #Check authenticated writepermission for all fields in FieldSelect using KeyRef PermOK

CheckM0AuthPerm(FieldSelect,MValTemp,M0,M1,KeyRef) If(PermOK = 1) WriteM(0,MValTemp[ ])# Copy temp buffer to M0  ResultFlag

Pass Else  ResultFlag

InvalidPermission EndIf Output ResultFlag Return20.4.1 PermOK CheckM0AuthPerm(FieldSelect,MValTemp, M0, M1, KeyRef)

This functions checks non-authenticated write permissions for all fieldsin FieldSelect using KeyRef. PermOK CheckM0NonAuthPerm( ) FieldSize[16]

0 NumFields

FindNumOfFieldsInM0(FieldSize) # Loop through fields For i

0 to NumFields  If FieldSelect[i] = 1 # check selected  WordBitMapForField

GetWordMapForField(i,M1) #get word bitmap for field   PermOK

CheckAuthFieldPerm(i,WordBitMapForField, MValTemp,M0,KeyRef)      #Check permission for field i in FieldSelect   If(PermOK = 0)   #Writingis not allowed, return if     #permissions for field doesn't allowwriting    Return PermOK   EndIf  EndIf EndFor Return PermOK20.4.2 PermOK CheckAuthFieldPerm(FieldNum, WordMapForField,MValTemp

, M0,KeyRef)

This function checks authenticated permissions for an M₀ field usingKeyRef (whether KeyRef has write permissions to the field). AuthRW

M1[FieldNum].AuthRW KeyNumAtt

M1[FieldNum].KeyNum If(AuthRW = 0) # Check whether any key has writepermissions  Return PermOK

0 # No authenticated write permissions EndIf # Check KeyRef hasReadWrite Permission to the field and it is locked If(KeyLock_(KeyNum) =locked)

(KeyNumAtt = KeyRef.keyNum)  Return PermOK

1 Else # KeyNum is not a ReadWrite Key  KeyPerms

M1[FieldNum].DOForKeys # Isolate KeyPerms for FieldNum  # CheckDecrement Only Permission for Key  If(KeyPerms[KeyRef.keyNum] = 1) # Keyis allowed to Decrement field    PermOK

CheckInputDataForDecrementOnly(M0,MValTemp,WordMapForField)   Else    #Key is a ReadOnly key    PermOK

0  EndIf EndIf Return PermOK20.4.3 WordBitMapField GetWordMapForField(FieldNum,M1)

Refer to Section 19.4.2 for details.

20.4.4 PermOK CheckInputDataForDecrementOnly(M0,MValTemp

,WordMapForField)

Refer to Section 19.4.5 for details.

20.4.5 WriteM(VectNum, MValTemp

)

Refer to Section 18.4.2 for details.

21 SetPerm Input: VectNum, PermVal Output: ResultFlag, NewPerm Changes:P_(n) Availability: All devices21.1 Function Description

The SetPerm command is used to update the contents of P_(VectNum) (whichstores the permission for M_(VectNum)).

The new value for P_(VectNum) is a combination of the old and newpermissions in such a way that the more restrictive permission for eachpart of P_(VectNum) is kept.

M0's permissions are set by M1 therefore they can't be changed.

M1's permissions cannot be changed by SetPerm. M1 is a write-once memoryvector and its permissions are set by writing to it.

See Section 8.1.1.3 and Section 8.1.1.5 for more information aboutpermissions.

21.2 Input Parameters

Table 274 describes each of the input parameters for SetPerm. ParameterDescription VectNum Number of the memory vector whose permission isbeing changed. PermVal Bitmap of permission for the corresponding MemoryVector.

Note: Since this function has no accompanying signatures, additionalinput parameter error checking is required.

21.3 Output Parameters

Table 275 describes each of the output parameters for SetPerm. ParameterDescription ResultFlag Indicates whether the function completedsuccessfully or not. If it did not complete successfully, the reason forthe failure is returned here. See Section 12.1. Perm If VectNum = 0,then no Perm is returned. If VectNum = 1, then old Perm is returned. IfVectNum > 1, then new Perm is returned after P_(VectNum) has beenchanged based on PermVal.21.4 Function Sequence

The SetPerm command is illustrated by the following pseudocode: Acceptinput parameters- VectNum, PermVal Check range of VectNum If invalid ResultFlag

InvalidVector  Output ResultFlag  Return EndIf If(VectNum = 0) # Nopermssions for M0  ResultFlag

Pass  Output ResultFlag  Return ElseIf(VectNum = 1)   ResultFlag

Pass   Output ResultFlag   Output P₁   Return ElseIf(VectNum >1)  #Check that only ‘RW’ parts are being changed  # RW(1) → RO(0), RO(0) →RO(0), RW(1) → RW(1) - valid change  # RO(0) → RW(1) - Invalid change  #checking for change from ReadOnly to ReadWrite  temp

˜P_(VectNum)

PermVal  If(temp =1)# If invalid change is 1   ResultFlag

InvalidPermission   Output ResultFlag  Else   P_(VectNum)

PermVal   ResultFlag

Pass   Output ResultFlag   Output P_(VectNum)  EndIf  Return EndIf

22 ReplaceKey Input: KeyRef, KeyId, KeyLock, EncryptedKey, R_(E),SIG_(E) Output: ResultFlag Changes: K_(KeyRef.keyNum) and R_(L)Availability: All devices22.1 Function Description

The ReplaceKey command is used to replace the contents of a non-lockedkeyslot, which means replacing the key, its associated keyID, and thelock status bit for the keyslot. A key can only be replaced if the slothas not been locked i.e. the KeyLock for the slot is 0. The procedurefor replacing a key also requires knowledge of the value of the currentkey in the keyslot i.e. you can only replace a key if you know thecurrent key.

Whenever the ReplaceKey function is called, the caller has the abilityto make this new key the final key for the slot. This is accomplished bypassing in a new value for the KeyLock flag. A new KeyLock flag of 0keeps the slot unlocked, and permits further replacements. A new KeyLockflag of 1 means the slot is now locked, with the new key as the finalkey for the slot i.e. no further key replacement is permitted for thatslot.

22.2 Input Parameters

Table 276 describes each of the input parameters for ReplaceKey.Parameter Description KeyRef For common key signature generation:KeyRef.keyNum = Slot number of the key to be used for testing the inputsignature, and will be replaced by the new key. KeyRef.useChipId = 0 Novariant key signature generation required KeyId KeyId of the new key.The LSB represents whether the new key is a variant or a common key.KeyLock Flag indicating whether the new key should be the final key forthe slot or not. (1 = final key, 0 = not final key) EncryptedKeySIG_(Kold)(R_(E)|R_(L)) ⊕ K_(new) where K_(old) = KeyRef.getkey(). Referto Section 10.1.3.1 RE External random value required for verifyinginput signature. This will be the R from the input signature generator(device generating SIG_(E)). In this case the input signature is agenerated by calling the GetProgramKey function on a Key Programmingdevice. SIGE External signature required for authenticating input dataand determining the new key from the EncryptedKey.22.2.1 Input Signature Generation Data Format

FIG. 374 shows the input signature generation data format for theReplaceKey function.

Table 277 gives the parameters included in SIG_(E) for ReplaceKey. Valueset Parameter Length in bits Value set internally from Input ChipId  48This QA Device's ChipId KeyId  32 ● R_(E) 160 ● EncryptedKey 160 ●22.3 Output Parameters

Table 278 describes each of the output parameters for ReplaceKey.Parameter Description ResultFlag Indicates whether the functioncompleted successfully or not. If it did not complete successfully, thereason for the failure is returned here. See Section 12.1.22.4 Function Sequence

The ReplaceKey command is illustrated by the following pseudocode:Accept input parameters - KeyRef, KeyId, KeyLock, EncryptedKey,R_(E),SIG_(E) Check KeyRef.keyNum range If invalid   ResultFlag

InvalidKey   Output ResultFlag   Return EndIf #Generate message forpassing to GenerateSignature function data

(ChipId|KeyId|KeyLock|R_(E)|EncryptedKey) #Generate Signature SIG_(L)

GenerateSignature(KeyRef,data,Null,Null) # Refer to Figure 374. # Checkif the key slot is unlocked If(KeyLock # unlock)   ResultFlag

KeyAlreadyLocked   Output ResultFlag   Return EndIf #Test SIG_(E) If(SIG_(L) # SIG_(E))   ResultFlag

BadSig   Output ResultFlag   Return EndIf SIG_(L)

GenerateSignature(Key,null,R_(E),R_(L))   Advance R_(L)   # Must beatomic - must not be possible to remove power and have KeyId and KeyNummismatched. Also preferable for KeyLock, although not strictly required.  K_(KeyNum)

SIG_(L) ⊕ EncryptedKey   KeyId_(KeyNum)

KeyId   KeyLock_(KeyNum)

KeyLock   ResultFlag

Pass   Output ResultFlag Return

23 SignM Input: KeyRef, FieldSelect, FieldValLength, FieldVal, ChipId,R_(E) Output: ResultFlag, R_(L), SIG_(out) Changes: R_(L) Availability:Trusted device only23.1 Function Description

The SignM function is used to generate the appropriate digital signaturerequired for the authenticated write function WriteFieldsAuth. The SignMfunction is used whenever the caller wants to write a new value to afield that requires key-based write access.

The caller typically passes the new field value as input to the SignMfunction, together with the nonce (R_(E)) from the QA Device who willreceive the generated signature. The SignM function then produces theappropriate signature SIG_(out). Note that SIG_(out) may need to betranslated via the Translate function on its way to the finalWriteFieldsAuth QA Device.

The SignM function is typically used by the system to updatepreauthorisation fields (Section 31.4.3).

The key used to produce output signature SIG_(out) depends on whetherthe trusted device shares a common key or a variant key with the QADevice directly receiving the signature. The KeyRef object passed intothe interface must be set appropriately to reflect this.

23.2 Input Parameters

Table 279 describes each of the input parameters for SignM. ParameterDescription KeyRef For generating common key output signature:Ref.keyNum = Slot number of the key for producing the output signature.SIG_(out) produced using K_(KeyRef.keyNum) because the device receivingSIG_(out) shares K_(KeyRef.keyNum) with the trusted device.KeyRef.useChipId = 0 For generating variant key output signature:KeyRef.keyNum = Slot number of the key to be used for generating thevariant key. SIG_(out) produced using a variant of K_(KeyRef.keyNum)because the device receiving SIG_(out) shares a variant ofK_(KeyRef.keyNum) with the trusted device. KeyRef.useChipId = 1KeyRef.chipId = ChipId of the device which receives SIG_(out). FieldNumField number of the field that will be written to. FieldDataLength Thelength of the FieldData in words. FieldData The value that will bewritten to the field selected by FieldNum. R_(E) External random valueused in the output signature generation. R_(E) is obtained by callingthe Random function on the device, which will receive the SIG_(out) fromthe SignM function, which in this case is the WriteAuth function or theTranslate function. ChipId Chip identifier of the device whose WriteAuthfunction will be called subsequently to perform an authenticated writeto its FieldNum of M0.23.3 Output Parameters

Table 280 describes each of the output parameters. TABLE 280 Descriptionof output parameters for SignM Parameter Description ResultFlagIndicates whether the function completed successfully or not. If it didnot complete successfully, the reason for the failure is returned here.See Section 12.1. R_(L) Internal random value used in the outputsignature. SIG_(out) SIG_(out) = SIG_(KeyRef)(data|R_(L)|R_(E)) as shownin FIG. 373. As per FIG. 373, R_(E) is actually R_(L) and R_(L) is R_(E)with respect to device producing SIG_(out) to be applied to WriteAuthfunction.23.3.1 SIG_(out)

Refer to Section 20.2.1.

23.4 Function Sequence

The SignM command is illustrated by the following pseudocode: Acceptinput parameters - KeyRef, FieldNum, FieldDataLength # Accept FieldDatawords For i = 0 to FieldValLength  Accept next FieldData EndFor AcceptChipId, R_(E) Check KeyRef.keyNum range If invalid  ResultFlag

InvalidKey  Output ResultFlag  Return EndIf #Generate message forpassing into the GenerateSignature function data

(RWSense|FieldSelect|ChipId|FieldVal) #Generate Signature SIG_(out)

GenerateSignature(KeyRef,data,R_(L,)R_(E)) # Refer to Section 20.2.1.Advance R_(L)to R_(L2) ResultFlag

Pass Output parameters ResultFlag, R_(L,)SIG_(out) ReturnFUNCTIONS ON AKEY PROGRAMMING QA DEVICE24 Concepts

The key programming device is used to replace keys in other devices.

The key programming device stores both the old key which will bereplaced in the device being programmed, and the new key which willreplace the old key in the device being programmed. The keys reside innormal key slots of the key programming device.

Any key stored in the key programming device can be used as an old keyor a new key for the device being programmed, provided it is permittedby the key replacement map stored within the key programming device.

FIG. 375 is representation of a key replacement map. The 1 s indicatesthat the new key is permitted to replace the old key. The 0s indicatesthat key replacement is not permitted for those positions. The positionsin FIG. 13 which are blank indicate a 0.

According to the key replacement map in FIG. 13, K₅ can replace K₁, K₆can replace K₃, K₄, K₅,K₇, K₃ can replace K₂, K₀ can replace K₂, and K₂can replace K₆. No key can replace itself.

FIG. 375._Key Replacement Map

The key replacement map must be readable from an external system andmust be updateable by an authenticated write. Therefore, the keyreplacement map must be stored in an M0 field. This requires one of thekeys residing in the key programming device to be have ReadWrite accessto the key replacement map. This key is referred to as the keyreplacement map key and is used to update the key replacement map.

There will one key replacement map field in a key programming device.

No key replacement mappings are allowed to the key replacement map keybecause it should not be used in another device being programmed. Toprevent the key replacement map key from being used in key replacement,in case the mapping has been accidentally changed, the key replacementmap key is allocated a fixed key slot of 0 in all key programmingdevices. If a GetProgram function is invoked on the key programmingdevice with the key replacement map key slot number 0 it immediatelyreturns an error, even before the key replacement map is checked.

The keys K₀ to K₇ in the key programming device are initially set duringthe instantiation of the key programming device. Thereafter, any key canbe replaced on the key programming device by another key programmingdevice If a key in a key slot of the key programming device is beingreplaced, the key replacement map for the old key must be invalidatedautomatically. This is done by setting the row and column for thecorresponding key slot to 0 For example, if K₁ is replaced, then column1 and row 1 are set to 0, as indicated in FIG. 376.

The new mapping information for K, is then entered by performing anauthenticated write of the key replacement map field using the keyreplacement map key.

24.1 Key Replacement Map Data Structure

As mentioned in Section 24, the key replacement map must be readable byexternal systems and must be updateable using an authenticated write bythe key replacement map key. Therefore, the key replacement map isstored in an M0 field of the key programming device. The map is 8×8 bitsin size and therefore can be stored in a two word field. The LSW of keyreplacement map stores the mappings for K₀-K₃. The MSW of keyreplacement map stores the mappings for K₄-K₇. Referring to FIG. 375,key replacement map LSW is 0x40092000 and MSW is 0x40224040. Referringto FIG. 376, after K₁ is replaced in the key programming device, thevalue of the key replacement map LSW is 0x40090000 and MSW is0x40224040.

The key replacement map field has an M1 word representing itsattributes. The attribute setting for this field is specified in Table281. TABLE 281 Key replacement map attribute setting Attribute nameValue Explanation Type TYPE_KEY_MAP Indicates that the field value Referto represents a key replacement map. Appendix A. Only one such field perkey programming QA Device. KeyNum 0 Slot number of the key replacementmap key. NonAuthRW 0 No non authenticated writes is permitted. AuthRW 1Authenticated write is permitted. KeyPerms 0 No Decrement Onlypermission for any key. EndPos Value such that field size is 2 words24.2 Basic Scheme

The Key Replacement sequence is shown FIG. 377.

Following is a sequential description of the transfer and rollbackprocess:

-   1. The System gets a Random number from the QA Device whose keys are    going to be replaced.-   2. The System makes a GetProgramKey Request to the Key Programming    QA Device. The Key Programming QA Device must contain both keys for    QA Device whose keys are being replaced—Old Keys which are the keys    that exist currently (before key replacement), and the New Keys    which are the keys which the QA Device will have after a successful    processing of the ReaplceKey Request. The GetProgramKey Request is    called with the Key number of the Old Key (in the Key Programming QA    Device) and the Key Number of the New Key (in the Key Programming QA    Device), and the Random number from (1). The Key Programming QA    Device validates the GetProgramKey Request based on the    KeyReplacement map, and then produces the necessary GetProgramKey    Output. The GetProgramKey Output consists of the encrypted New Key    (encryption done using the Old Key), along with a signature using    the Old Key.-   3. The System then applies GetProgramKey Output to the QA Device    whose key is being replaced, by calling the ReplaceKey function on    it, passing in the GetProgramKey Output. The ReplaceKey function    will decrypt the encrypted New Key using the Old Key, and then    replace its Old Key with the decrypted New Key.    25 Functions

25.1 GetProgamKey Input: OldKeyRef, ChipId, R_(E), KeyLock, NewKeyRefOutput: ResultFlag, R_(L), EncryptedKey, KeyIdOfNewKey, SIG_(out)Changes: R_(L) Availability: Key programming device25.1.1 Function Description

The GetProgramKey works in conjunction with the ReplaceKey command, andis used to replace the specified key and its KeyId. This function isavailable on a key programming device and produces the necessary inputsfor the ReplaceKey function. The ReplaceKey command is then run on thedevice whose key is being replaced.

The key programming device must have both the old key and the new keyprogrammed as its keys, and the key replacement map stored in one of itsM0 field, before GetProgramKey can be called on the device.

Depending on the OldKeyRef object and the NewKeyRef object passed in,the GetProgramKey will produce a signature to replace a common key by acommon key, a variant key by a common key, a common key by a variant keyor a variant key by a variant key.

25.1.2 Input Parameters

Table 282 describes each of the input parameters for GetProgramKey,Parameter Description OldKeyRef Old key is a common key:OldKeyRef.keyNum = Slot number of the old key in the Key Programming QADevice. The device whose key is being replaced, shares a common keyK_(OldKeyRef.keyNum)with the key programming device. OldKeyRef.useChipId= 0 Old key is a variant key KeyRef.keyNum = Slot number of the oldkeyin the Key Programming QA Device. that will be used to generate thevariant key. The device whose key is being replaced, shares a variant ofK_(OldKeyRef.keyNum) with the key programming device.OldKeyRef.useChipId = 1 OldKeyRef.chipId = ChipId of the device whosevariant of K_(OldKeyRef.keyNum) key is being replaced. ChipId Chipidentifier of the device whose key is being replaced. RE External randomvalue which will be used in output signature generation. R_(E) isobtained by calling the Random function on the device being programmed.This will also receive the SIGout from the GetProgramKey function.SIGout is passed in to ReplaceKey function. KeyLock Flag indicatingwhether the new key should be unlocked/locked into its slot. NewKeyRefNew key is a common key: NewKeyRef.keyNum = Slot number of the new keyinthe Key Programming QA Device. The device whose key is being replaced,will receive a common key K_(NewKeyRef.keyNum) from the key programmingdevice. NewKeyRef.useChipId = 0 NewKey is a variant key:NewKeyRef.keyNum = Slot number of the new key in the Key Programming QADevice. that will be used to generate the new variant key. The devicewhose key is being replaced, will receive a new key which is a variantof K_(NewKeyRef.keyNum) from the key programming device.NewKeyRef.useChipId = 1 NewKeyRef.ChipId = ChipId of the devicereceiving a new key, the new key is a variant of theK_(NewKeyRef.keyNum).25.1.3 Output Parameters

Table 283 describes each of the output parameters for GetProgamKey.Parameter Description ResultFlag Indicates whether the functioncompleted successfully or not. If it did not complete successfully, thereason for the failure is returned here. See Section 12.1 and Table 284R_(L) Internal random value used in the output signature. EncryptedKeySIG_(Kold)(R_(L)|R_(E)) ⊕ K_(new) KeyIdOfNewKey KeyId of the new key.The LSB represents whether the new key is a variant or a common key.SIG_(out) SIG_(out) = SIG_(Kold)(data|R_(L)|R_(E))

TABLE 284 ResultFlag definitions for GetProgramKey Result FlagDescription InvalidKeyReplacementMap Key replacement map field invalidor doesn't exist. KeyReplacementNotAllowed Key replacement not allowedas per key replacement map.25.1.3.1 SIG_(out)

FIG. 378 shows the output signature generation data format for theGetProgramKey function.

25.1.4 Function Sequence

The GetProgramKey command is illustrated by the following pseudocode:Accept input parameters - OldKeyRef, ChipId, R_(E), KeyLock, NewKeyRef---------------------------------------------------------------- # keyreplacement map key stored in K0, must not be used for key replacementIf(OldKeyRef.keyNum = 0)

(NewKeyRef.keyNum = 0)  ResultFlag

Fail  Output ResultFlag  Return EndIf----------------------------------------------------------------CheckRange(OldKeyRef.keyNum) If invalid  ResultFlag

InvalidKey  Output ResultFlag  Return EndIf----------------------------------------------------------------CheckRange(NewKeyRef.keyNum) If invalid  ResultFlag

InvalidKey  Output ResultFlag  Return EndIf---------------------------------------------------------------- # FindM0 words that represent the key replacement map WordSelectForKeyMapField

GetWordSelectForKeyMapField(M1) If(WordSelectForKeyMapField =0) ResultFlag

InvalidKeyReplacementMap  Output ResultFlag  Return EndIf----------------------------------------------------------------#CheckMapPermits key replacement ReplaceOK

CheckMapPermits(WordSelectForKeyMapField,OldKeyNum, NewKeyNum)If(ReplaceOK = 0)  ResultFlag

KeyReplacementNotAllowed  Output ResultFlag  Return EndIf---------------------------------------------------------------- #Allchecks are OK, now generate Signature with OldKey SIG_(L)

GenerateSignature(OldKeyRef,null,R_(L,)R_(E)) #Get new key K_(NewKey)

NewKeyRef.getKey( ) #Generate Encrypted Key EncryptedKey

SIG_(L) ⊕ K_(NewKey) #Set base key or variant key - bit 0 of KeyIdIf(NewKeyRef.useChipId = 1)  KeyId

0x0001

0x0001 Else  KeyId

0x0001

0x0000 EndIf #Set the new key KeyId to the KeyId - bits 1-30 of KeyIdKeyIdOfNewKey

SHIFTLEFT(KeyIdOfNewKey,1) KeyId

KeyId

KeyIdOfNewKey #Set the KeyLock as per input - bit 31 of KeyId KeyLock

SHIFTLEFT(KeyLock,31) #KeyId

KeyId

KeyLock #Generate message for passing in to the GenerateSignaturefunction data

ChipId|KeyId|R_(L)|EncryptedKey #Generate output signature SIG_(out)

GenerateSignature(OldKeyRef,data,null,null) # Refer to Figure 378Advance R_(L)to R_(L2) ResultFlag

Pass Output ResultFlag, R_(L,)SIG_(out),KeyId, EncryptedKey Return25.1.4.1 WordSelectForField GetWordSelectForKeyMapField(M1)

This function gets the words corresponding to the key replacement map inM0. FieldSize[16]

0 # Array to hold FieldSize assuming there are 16 fields NumFields

FindNumberOfFieldsInM0(M1,FieldSize) #Find the key replacement map fieldFor i

0 to NumFields  If(TYPE_KEY_MAP = M1[i].Type) # Field is key map field  MapFieldNum

i   Return  Endif EndFor #Get the words corresponding to the keyreplacement map WordMapForField

GetWordMapForField(MapFieldNum, M1) Return WordSelectForField25.1.4.2 NumFields FindNumOfFieldsInM0(M1, FieldSize

)

Refer to Figure 19.4.1 for details

25.1.4.3 WordMapForField GetWordMapForField(FieldNum,M1)

Refer to Section 19.4.2 for details.

25.1.4.4 ReplaceOK CheckMapPermits(WordSelectForKeyMapField, OldKeyNum,NewKeyNum,M0)

This function checks whether key replacement map permits keyreplacement. #Isolate KeyReplacementMap based onWordSelectForKeyMapField and M0  KeyReplacementMap[64 bit]  #Isolatepermission bit corresponding for NewKeyNum in the map for  OldKeyNm ReplaceOK

KeyReplacementMap[(OldKeyNum × 8 +  NewKeyNum)bit]  Return ReplaceOK

25.2 ReplaceKey Input: KeyRef, KeyId, KeyLock, EncryptedKey, R_(E),SIG_(E) Output: ResultFlag Changes: K_(KeyNum) and R_(L) Availability:Key programming device25.2.1 Function Description

This function is used for replacing a key in a key programming deviceand is similar to the generic ReplaceKey function(Refer to Section 24),with an additional step of setting the KeyRef.keyNum column andKeyRef.keyNum row key replacement map to 0.

25.2.2 Input Parameters

Refer to Section 22.

25.2.3 Output Parameters

Refer to Section 22.

25.2.4 Function Sequence

The ReplaceKey command is illustrated by the following pseudocode:Accept input parameters - KeyRef, KeyId, EncryptedKey, R_(E), SIG_(E)#Generate message for passing into GenerateSignature function data

(ChipId|KeyId|R_(E)|EncryptedKey)# Refer to Figure 374.---------------------------------------------------------------- #Validate KeyRef, and then verify signature ResultFlag =ValidateKeyRefAndSignature(KeyRef,data,R_(E),R_(L)) If (ResultFlag ≠Pass)  Output ResultFlag  Return EndIf---------------------------------------------------------------- # Checkif the key slot is unlocked Isolate KeyLock for KeyRef If(KeyLock =lock)  ResultFlag

KeyAlreadyLocked  Output ResultFlag  Return EndIf SIG_(L)

GenerateSignature(Key,Null,R_(E),R_(L)) Advance R_(L) # Find M0 wordsthat represent the key replacement map WordSelectForKeyMapField

GetWordSelectForKeyMapField(M1) # Set the bits corresponding to theKeyRef.keyNum row and column to 0 # i.e invalidate the key replacementmap for KeyRef.keyNum. #Must be done before the key is replaced and mustbe atomic with key replacement. SetFlag

SetKeyMapForKeyNum(WordSelectForKeyMapField, KeyRef.keyNum,M0)If(SetFlag = 1)  # Must be atomic - must not be possible to remove powerand have KeyId and  KeyNum mismatched  K_(KeyNum)

SIG_(L) ⊕ EncryptedKey  KeyId_(KeyNum)

KeyId  KeyLock_(KeyNum)

KeyLock  ResultFlag

Pass Else  ResultFlag

Fail EndIf Output ResultFlag Return25.2.4.1 WordSelectForField GetWordSelectForKeyMapField(M1)

Refer to Figure 25.1.4.1 for details.

25.2.4.2 SetFlag SetKeyMapForKeyNum(WordSelectForKeyMapField,KeyNum, M0)

This function invalidates the key replacement map for KeyNum. #IsolateKeyReplacementMap based on WordSelectForKeyMapField and M0KeyReplacementMap[64 bit] # Set KeyNum row (all bits) to 0 in theKeyReplacementMap For i = 0 to 7  KeyReplacementMap[(KeyNum × 8 + i)bit]

0 EndFor # Set KeyNum column to 0 in the KeyReplacementMap For i = 0 to7  KeyReplacementMap[(i×8 + KeyNum)bit]

0 EndFor SetFlag

1 Return SetFlagFunctionsUpgrade Device(Ink Re/fill)26 Concepts26.1 Purpose

In a printing application, an ink cartridge contains an Ink QA Devicestoring the ink-remaining values for that ink cartridge. Theink-remaining values decrement as the ink cartridge is used to print.

When an ink cartridge is physically re/filled, the Ink QA Device needsto be logically re/filled as well. Therefore, the main purpose of anupgrade is to re/fill the ink-remaining values of an Ink QA Device in anauthorised manner.

The authorisation for a re/fill is achieved by using a Value Upgrader QADevice which contains all the necessary functions to re/write to the InkQA Device. In this case, the value upgrader is called an Ink Refill QADevice, which is used to fill/refill ink amount in an Ink QA Device.

When an Ink Refill QA Device increases (additive) the amount ofink-remaining in an Ink QA Device, the amount of ink-remaining in theInk Refill QA Device is correspondingly decreased. This means that theInk Refill QA Device can only pass on whatever ink-remaining value ititself has been issued with. Thus an Ink Refill QA Device can itself bereplenished or topped up by another Ink Refill QA Device.

The Ink Refill QA Device can also be referred to as the Upgrading QADevice, and the Ink QA Device can also be referred to as the QA Devicebeing upgraded.

The refill of ink can also be referred to as a transfer of ink, ortransfer of amount/valu, or an upgrade.

Typically, the logical transfer of ink is done only after a physicaltransfer of ink is successful.

26.2 Requirements

The transfer process has two basic requirements:

-   -   The transfer can only be performed if the transfer request is        valid. The validity of the transfer request must be completely        checked by the Ink Refill QA Device, before it produces the        required output for the transfer. It must not be possible to        apply the transfer output to the Ink QA Device, if the Ink        Refill QA Device has been already been rolled back for that        particular transfer.    -   A process of rollback is available if the transfer was not        received by the Ink QA Device. A rollback is performed only if        the rollback request is valid. The validity of the rollback        request must be completely checked by the Ink Refill QA Device,        before it adjusts its value to a previous value before the        transfer request was issued. It must not be possible to rollback        an Ink Refill QA Device for a transfer which has already been        applied to the Ink QA Device i.e the Ink Refill QA Device must        only be rolled back for transfers that have actually failed.        26.3 Basic Scheme

The transfer and rollback process is shown in FIG. 379.

Following is a sequential description of the transfer and rollbackprocess:

1. The System Reads the memory vectors M0 and M1 of the Ink QA Device.The output from the read which includes the M0 and M1 words of the InkQA Device, and a signature, is passed as an input to the TransferRequest. It is essential that M0 and M1 are read together. This ensuresthat the field information for M0 fields are correct, and have not beenmodified, or substituted from another device. Entire M0 and M1 must beread to verify the correctness of the subsequent Transfer Request by theInk Refill QA Device.

2. The System makes a Transfer Request to the Ink Refill QA Device withthe amount that must be transferred, the field in the Ink Refill QADevice the amount must be transferred from, and the field in Ink QADevice the amount must be transferred to. The Transfer Request alsoincludes the output from Read of the Ink QA Device. The Ink Refill QADevice validates the Transfer Request based on the Read output, checksthat it has enough value for a successful transfer, and then producesthe necessary Transfer Output. The Transfer Output typically consists ofnew field data for the field being refilled or upgraded, additionalfield data required to ensure the correctness of the transfer/rollback,along with a signature.

3. The System then applies the Transfer Output to the Ink QA Device, bycalling an authenticated Write function on it, passing in the TransferOutput. The Write is either successful or not. If the Write is notsuccessful, then the System will repeat calling the Write function usingthe same transfer output, which may be successful or not. If unsuccesfulthe System will initiate a rollback of the transfer. The rollback mustbe performed on the Ink Refill QA Device, so that it can adjust itsvalue to a previous value before the current Transfer Request wasinitiated. It is not necessary to perform a rollback immediately after afailed Transfer. The Ink QA Device can still be used to print, if thereis any ink remaining in it.

4. The System starts a rollback by Reading the memory vectors M0 and M1of the Ink QA Device.

5. The System makes a StartRollBack Request to the Ink Refill QA Devicewith same input parameters as the Transfer Request, and the output fromRead in (4). The Ink Refill QA Device validates the StartRollBackRequest based on the Read output, and then produces the necessaryPre-rollback output. The Pre-rollback output consists only of additionalfield data along with a signature.

6. The System then applies the Pre-rollback Output to the Ink QA Device,by calling an authenticated Write function on it, passing in thePre-rollback output. The Write is either successful or not. If the Writeis not successful, then either (6), or (5) and (6) must be repeated.

7. The System then Reads the memory vectors M0 and M1 of the Ink QADevice.

8. The System makes a RollBack Request to the Ink Refill QA Device withsame input parameters as the Transfer Request, and the output from Read(7). The Ink Refill QA Device validates the RollBack Request based onthe Read output, and then rolls back its field corresponding to thetransfer.

26.3.1 Transfer

As we mentioned, the Ink QA Device stores ink-remaining values in its M0fields, and its corresponding M₁ words contains field information forits ink-remaining fields. The field information consists of the size ofthe field, the type of data stored in field and the access permission tothe field. See Section 8.1.1 for details.

The Ink Refill QA Device also stores its ink-remaining values in its M0fields, and its coressponding M₁ words contains field information forits ink-remaining fields.

26.3.1.1 Authorisation

The basic authorisation for a transfer comes from a key, which hasauthenticated ReadWrite permission (stored in field information asKeyNum) to the ink-remaining field (to which ink will be transferrred)in the Ink QA Device. We will refer to this key as the refill key. Therefill key must also have authenticated decrement-only permission forthe ink-remaining field (from which ink will be transferred) in the InkRefill QA Device.

After validating the input transfer request, the Ink Refill QA Devicewill decrement the amount to be transferred from its ink-remainingfield, and produce a transfer amount (previous ink-remaining amount inthe Ink QA Device+transfer amount), additional field data, and asignature using the refill key. Note that the Ink Refill QA Device candecrement its ink-remaining field only if the refill key has thepermission to decrement it.

The signature produced by the Ink Refill QA Device is subsequentlyapplied to the Ink QA Device. The Ink QA Device will accept the transferamount only if the signature is valid. Note that the signature will onlybe valid if it was produced using the refill key which has writepermission to the ink-remaining field being written.

26.3.1.2 Data Type Matching

The Ink Refill QA Device validates the transfer request by matching theType of the data in ink-remaining information field of Ink QA Device tothe Type of data in ink-remaining information field of the Ink Refill QADevice. This ensures that equivalent data Types are transferred i.eNetwork_OEM1_infrared ink is not transferred to Network_OEM1_cyan ink.

26.3.1.3 Addition Validation

Additional validation of the transfer request must also be performedbefore a transfer output is generated by the Ink Refill QA Device. Theseare as follows:

-   -   For the Ink Refill QA Device:    -   1. Whether the field being upgraded is actually present.    -   2. Whether the field being upgraded can hold the upgraded        amount.    -   For the Ink QA Device:    -   1. Whether the field from which the amount is transferred is        actually present.

2. Whether the field has sufficient amount required for the transfer.

26.3.1.4 Rollback Facilitation

To facilitate a rollback, the Ink Refill QA Device will store a list oftransfer requests processed by it. This list is referred to as the XferEntry cache. Each record in the list consists of the transfer parameterscorresponding to the transfer request.

26.3.2 Rollback

A rollback request is validated by looking through the Xfer Entry of theInk Refill QA Device and finding the request that should be rolled back.After the right transfer request is found the Ink Refill QA Devicechecks that the output from the transfer request was not applied to theInk QA Device by comparing the current Read of the Ink QA Device to thevalues in the Xfer Entry cache, and finally rolls back its ink-remainingfield (from which the ink was transferred) to a previous value beforethe transfer request was issued.

The Ink Refill QA Device must be absolutely sure that the Ink QA Devicedidn't receive the transfer. This factor determines the additionalfields that must be written along with transfer amount, and also theparameters of the transfer request that must be stored in the Xfer Entrycache to facilitate a rollback, to prove that the Printer QA Devicedidn't actually receive the transfer.

26.3.2.1 Sequence Fields

The rollback process must ensure that the transfer output (which waspreviously produced) for which the rollback is being performed, cannotbe applied after the rollback has been performed. How do we achievethis? There are two separate decrement-only sequence fields (SEQ_(—)1and SEQ_(—)2) in the Ink QA Device which can only be decremented by theInk Refill QA Device using the refill key. The nature of data to bewritten to the sequence fields is such that either the transfer outputor the pre-rollback output can be applied to the Ink QA Device, but notboth i.e they must be mutually exclusive.Refer to Table 285 for details.TABLE 285 Sequence field data for Transfer and Pre-rollback SequenceField data written to Ink QA Device Function SEQ_1 SEQ_2 ExplanationInitialised 0xFFFFFFFF 0xFFFFFFFF Written using the sequence key whichis different from the refill key Write using (Previous Value − 2)(Previous Value − 1) Written using the refill key using Transfer IfPrevious Value = intialised If Previous Value = intialised the refillkey which has Output value then 0xFFFFFFFD value decrement-only then0xFFFFFFFE permission on the fields. Value cannot be written if pre-rollback output is already written. Write usiing (Previous Value − 1)(Previous Value − 2) Written using the refill key using Pre-rollback IfPrevious Value = intialised If Previous Value = intialised the refillkey which has value value decrement-only then 0xFFFFFFFE then 0xFFFFFFFDpermissionon the fields. Value can be written only if Transfer Outputhas not been written.

The two sequence fields are initialised to 1xFFFFFFFF using sequencekey. The sequence key is different to the refill key, and hasauthenticated ReadWrite permission to both the sequence fields. Thetransfer output consists of the new data for the field being upgraded,field data of the two sequence fields, and a signature using the refillkey. The field data for SEQ_(—)1 is decremented by 2 from the originalvalue that was passed in with the transfer request. The field data forSEQ_(—)2 is decremented by 1 from the original value that was passed inwith the transfer request.

The pre-rollback output consists only of the field data of the twosequence fields, and a signature using the refill key. The field datafor SEQ_(—)1 is decremented by 1 from the original value that was passedin with the transfer request. The field data for SEQ_(—)2 is decrementedby 2 from the original value that was passed in with the transferrequest.

Since the two sequence fields are decrement-only fields, the writing ofthe transfer output to QA Device being upgraded will prevent the writingof the pre-rollback output to QA Device being upgraded. If the writingof the transfer output fails, then pre-rollback can be written. However,the transfer output cannot be written after the pre-rollback has beenwritten.

Before a rollback is performed, the Ink Refill QA Device must confirmthat the sequence fields was successfully written to the pre-rollbackvalues in the Ink QA Device. Because the sequence fields areDecrement-Only fields, the Ink QA Device will allow pre-rollback outputto be written only if the upgrade output has not been written. It alsomeans that the transfer output cannot be written after the pre-rollbackvalues have been written.

26.3.2.1.1 Field Information of the Sequence Data Field

For a device to be upgradeable the device must have two sequence fieldsSEQ_(—)1 and SEQ_(—)2 which are written with sequence data during thetransfer sequence. Thus all upgrading QA devices, ink QA Devices andprinter QA Devices must have two sequence fields. The upgrading QADevices must also have these fields because they can be upgraded aswell.

The sequence field information is defined in Table 286. TABLE 286Sequence field information Attribute Name Value Explanation TypeTYPE_SEQ_1 or TYPE_SEQ_2. See Appendix A for exact value. KeyNum Slotnumber of the sequence key. Only the sequence key has authenticatedReadWrite access to this field. Non Auth RW 0 Non authenticatedReadWrite Perm is not allowed to the field. Auth RW Perm 1 Authenticated(key based) ReadWrite access is allowed to the field. KeyPermKeyPerms[KeyNum] = 0 KeyNum is the slot number of the sequence key,which has ReadWrite permission to the field. KeyPerms[Slot number of therefill Refill key can decrement the sequence key] = 1 field.KeyPerms[others = 0 ..7(except refill All other keys have ReadOnlyaccess. key)] = 0 End Pos Set as required. Size is typically 1 word.26.3.3 Upgrade States

There are three states in an transfer sequence, the first state isinitiated for every transfer, while the next two states are initiatedonly when the transfer fails. The states are—Xfer, StartRollback, andRollback.

26.3.3.1 Upgrade Flow

FIG. 380 shows a typical upgrade flow.

26.3.3.2 Xfer

This state indicates the start of the transfer process, and is the onlystate required if the transfer is successful. During this state, the InkRefill QA Device adds a new record to its Xfer Entry cache, decrementsits amount, produces new amount, new sequence data (as described inSection 26.3.2.1) and a signature based on the refill key.

The Ink QA Device will subsequently write the new amount and newsequence data, after verifying the signature. If the new amount can besuccessfully written to the Ink QA Device, then this will finish asuccessful transfer.

If the writing of the new amount is unsuccessful (result returned is BADSIG), the System will re-transmit the transfer output to the Ink QADevice, by calling the authenticated Write function on it again, usingthe same transfer output.

If retrying to write the same transfer output fails repeatedly, theSystem will start the rollback process on Ink Refill QA Device, bycalling the Read function on the Ink QA Device, and subsequently callingthe StartRollBack function on the Ink Refill QA Device. After asuccessful rollback is performed, the System will invoke the transfersequence again.

26.3.3.3 StartRollBack

This state indicates the start of the rollback process. During thisstate, the Ink Refill QA Device produces the next sequence data and asignature based on the refill key. This is also called a pre-rollback,as described in Section 26.3.2.

The pre-rollback output can only be written to the Ink QA Device, if theprevious transfer output has not been written. The writing of thepre-rollback sequence data also ensures, that if the previous transferoutput was captured and not applied, then it cannot be applied to theInk QA Device in the future.

If the writing of the pre-rollback output is unsuccessful (resultreturned is BAD SIG), the System will re-transmit the pre-rollbackoutput to the Ink QA Device, by calling the authenticated Write functionon it again, using the same pre-rollback output.

If retrying to write the same pre-rollback output fails repeatedly, theSystem will call the StartRollback on the Ink Refill QA Device again,and subsequently calling the authenticated Write function on the Ink QADevice using this output.

26.3.3.4 Rollback

This state indicates a successful deletion (completion) of a transfersequence. During this state, the Ink Refill QA Device verifies thesequence data produced from StartRollBack has been correctly written toInk Refill QA Device, then rolls its ink-remaining field to a previousvalue before the transfer request was issued.

26.3.4 Xfer Entry Cache

The Xfer Entry data structure must allow for the following:

-   -   Stores the transfer state and sequence data for a given transfer        sequence.    -   Store all data corresponding to a given transfer, to facilitate        a rollback to the previous value before the transfer output was        generated.

The Xfer Entry cache depth will depend on the QA Chip Logical Interfaceimplementation. For some implementations a single Xfer Entry value willbe saved. If the Ink Refill QA Device has no powersafe storage of XferEntry cache, a power down will cause the erasure of the Xfer Entry cacheand the Ink Refill QA Device will not be able to rollback to apre-power-down value.

A dataset in the Xfer Entry cache will consist of the following:

-   -   Information about the QA Device being upgraded:    -   a. ChipId of the device.    -   b. FieldNum of the M0 field (i.e what was being upgraded).    -   Information about the upgrading QA Device:    -   a. FieldNum of the M0 field used to transfer the amount from.    -   XferVal—the transfer amount.    -   Xfer State—indicating at which state the transfer sequence is.        This will consist of:    -   a. State definition which could be one of the following: —Xfer,        StartRollBack and complete/deleted.    -   b. The value of sequence data fields SEQ_(—)1 and SEQ_(—)2.        26.3.4.1 Adding New Dataset

A new dataset is added to Xfer Entry cache by the Xfer function.

There are three methods which can be used to add new dataset to the XferEntry cache. The methods have been listed below in the order of theirpriority:

-   -   1. Replacing existing dataset in Xfer Entry cache with new        dataset based on ChipId and FieldNum of the Ink QA Device in the        new dataset. A matching ChipId and FieldNum could be found        because a previous transfer output corresponding to the dataset        stored in the Xfer Entry cache has been correctly received and        processed by the Ink Refill QA Device, and a new transfer        request for the same Ink QA Device, same field, has come through        to the Ink Refill QA Device.

2. Replace existing dataset cache with new dataset based on the XferState. If the Xfer State for a dataset indicates deleted (complete),then such a dataset will not be used for any further functions, and canbe overwritten by a new dataset.

3. Add new dataset to the end of the cache. This will automaticallydelete the oldest dataset from the cache regardless of the Xfer State.

26.4 Different Types of Transfer

There can be three types of transfer:

-   -   Peer to Peer Transfer—This transfer could be one of the 2 types        described below:    -   a. From an Ink Refill QA Device to a Ink QA Device. This is        performed when the Ink QA Device is refilled by the Ink Refill        QA Device.    -   b. From one Ink Refill QA Device to another Ink Refill QA        Device, where both QA Devices belong to the same OEM. This is        typically performed when OEM divides ink from one Ink Refill QA        Device to another Ink Refill QA Device, where both devices        belong to the same OEM    -   Heirachical Transfer—This is a transfer from one Ink Refill QA        Device to another Ink Refill QA Device, where the QA Devices        belong to different organisation, say ComCo and OEM. This is        typically performed when ComCo divides ink from its refill        device to several refill devices belonging to several OEMs.

FIG. 381 is a representation of various authorised ink refill paths inthe printing system.

26.4.1 Hierarchical Transfer

Referring to FIG. 381, this transfer is typically performed when ink istransferred from ComCo's Ink Refill QA Device to OEM's Ink Refill QADevice, or from QACo's Ink Refill QA Device to ComCo's Ink Refill QADevice.

26.4.1.1 Keys and Access Permission

We will explain this using a transfer from ComCo to OEM.

There is an ink-remaining field associated with the ComCo's Ink RefillQA Device. This ink-remaining field has two keys associated with:

-   -   The first key transfers ink to the device from another refill        device (which is higher in the heirachy), fills/refills        (upgrades) the device itself. This key has authenticated        ReadWrite permission to the field.    -   The second key transfers ink from it to other devices (which are        lower in the heirachy), fills/refills (upgrades) other devices        from it. This key has authenticated decrement-only permission to        the field.

There is an ink-remaining field associated with the OEM's Ink refilldevice. This ink-remaining field has a single key associated with:

-   -   This key transfers ink to the device from another refill device        (which is higher or at the same level in the hierarchy),        fills/refills (upgrades) the device itself, and additionally        transfers ink from it to other devices (which are lower in the        heirachy), fills/refills (upgrades) other devices from it.        Therefore, this key has both authenticated ReadWrite and        decrement-only permission to the field. For a successful        transfer ink from ComCo's refill device to an OEM's refill        device, the ComCo's refill device and the OEM's refill device        must share a common key or a variant key. This key is        fill/refill key with respect to the OEM's refill device and it        is the transfer key with respect to the ComCo's refill device.

For a ComCo to successfully fill/refill its refill device from anotherrefill device (which is higher in the heirachy possibly belonging to theQACo), the ComCo's refill device and the QACo's refill device must sharea common key or a variant key. This key is fill/refill key with respectto the ComCo's refill device and it is the transfer key with respect tothe QACo's refill device.

26.4.1.1.1 Ink—Remaining Field Information

Table 287 shows the field information for an _(M0) field storing logicalink-remaining amounts in the refill device and which has the ability totransfer down the heirachy. Attribute Name Value Explanation Type Fore.g - Type describing the logical ink stored inTYPE_HIGHQUALITY_BLACK_INK^(a) the ink-remaining field in the refilldevice. KeyNum Slot number of the refill key. Only the refill key hasauthenticated ReadWrite access to this field. Non Auth RW 0 Nonauthenticated ReadWrite Perm^(b) is not allowed to the field. Auth RWPerm^(c) 1 Authenticated (key based) ReadWrite access is allowed to thefield. KeyPerm KeyPerms[KeyNum] = 0 KeyNum is the slot number of therefill key, which has ReadWrite permission to the field. KeyPerms[SlotNum of transfer key] = 1 Transfer key can decrement the field.KeyPerms[others = 0..7(except transfer All other keys have ReadOnlyaccess. key)] = 0 End Pos Set as required. Depends on the amount oflogical ink the device can store and storage resolution - i.e inpicolitres or in microlitres.^(a)This is a sample type only and is not included in the Type Map inAppendix A.^(b)Non authenticated Read Write permission.^(c)Authenticated Read Write permission.

-   a. This is a sample type only and is not included in the Type Map in    Appendix A.-   b. Non authenticated Read Write permission.-   c. Authenticated Read Write permission.    26.4.2 Peer to Peer Transfer

Referring to FIG. 381, this transfer is typically performed when ink istransferred from OEM's Ink Refill Device to another Ink Refill Devicebelonging to the same OEM, or OEM's Ink Refill Device to Ink Devicebelonging to the same OEM.

26.4.2.1 Keys and Access Permission

There is an ink-remaining field associated with the refill device whichtransfers ink amounts to other refill devices (peer devices), or toother ink devices. This ink-remaining field has a single key associatedwith:

-   -   This key transfers ink to the device from another refill device        (which is higher or at the same level in the heirachy),        fills/refills (upgrades) the device itself, and additionally        transfers ink from it to other devices (which are lower in the        heirachy), fills/refills (upgrades) other devices from it.

This key is referred to as the fill/refill key and is used for bothfill/refill and transfer. Hence, this key has both ReadWrite andDecrement-Only permission to the ink-remaining field in the refilldevice.

26.4.2.1.1 Ink-Remaining Field Information

Table 288 shows the field information for an _(M0)field storing logicalink-remaining amounts in the refill device with the ability to transferbetween peers. Attribute Name Value Explanation Type For e.g - Typedescribing the logical ink stored in the ink-TYPE_HIGHQUALITY_BLACK_INK^(a) remaining field in the refill device.KeyNum Slot number of the refill Only the refill key has authenticatedkey. ReadWrite access to this field. Non Auth RW 0 Non authenticatedReadWrite Perm^(b) is not allowed to the field. Auth RW Perm^(c) 1Authenticated (key based) ReadWrite access is allowed to the field.KeyPerm KeyPerms[KeyNum] = 1 KeyNum is the slot number of the refillkey, which has ReadWrite and Decrement permission to the field.KeyPerms[others = 0 All other keys have ReadOnly access. ..7(exceptKeyNum)] = 0 End Pos Set as required. Depends on the amount of logicalink the device can store and storage resolution - i.e in picolitres orin microlitres.^(a)This is a sample type only and is not included in the Type Map inAppendix A.^(b)Non authenticated Read Write permission.^(c)Authenticated Read Write permission.27 Functions

27.1 XferAmount Input: KeyRef, _(M0)OfExternal, _(M1)OfExternal, ChipId,FieldNumL, FieldNumE, XferValLength, XferVal, InputParameterCheck(optional), R_(E), SIG_(E), R_(E2) Output: ResultFlag, FieldSelect,FieldVal, R_(L2), SIG_(out) Changes: _(M0) and R_(L) Availability Inkrefill QA Device27.1.1 Function Description

The XferAmount function produces data and signature for updating a given_(M0) field. This data and signature when applied to the appropriatedevice through the WriteFieldsAuth function, will update the _(M0) fieldof the device.

The system calls the XferAmount function on the upgrade device with acertain XferVal, this XferVal is validated by the XferAmount functionfor various rules as described in Section 27.1.4, the function thenproduces the data and signature for the passing into the WriteFieldsAuthfunction for the device being upgraded.

The transfer amount output consists of the new data for the field beingupgraded, field data of the two sequence fields, and a signature usingthe refill key. When a transfer output is produced, the sequence fielddata in SEQ_(—)1 is decremented by 2 from the previous value (as passedin with the input), and the sequence field data in SEQ 2 is decrementedby 1 from the previous value (as passed in with the input).

Additional InputParameterCheck value must be provided for the parametersnot included in the SIG_(E), if the transmission between the System andInk Refill QA Device is error prone, and these errors are not correctedby the transimission protocol itself. InputParameterCheck isSHA-1[FieldNumL|FieldNumE|XferValLength|XferVal], and is required toensure the integrity of these parameters, when these inputs are receivedby the Ink Refill QA Device. This will prevent an incorrect transferamount being deducted.

The XferAmount function must first calculate theSHA-1[FieldNumL|FieldNumE|XferValLength|XferVal], compare the calculatedvalue to the value received (InputParameterCheck) and only if the valuesmatch act upon the inputs.

27.1.2 Input Parameters

Table 289 describes each of the input parameters for XferAmountfunction. Parameter Description KeyRef For comsmon key input and outputsignature: KeyRef.keyNum = Slot number of the key to be used for testinginput signature and producing the output signature. SIG_(E) producedusing K_(KeyRef.keyNum) by the QA Device being upgraded. SIGout producedusing K_(KeyRef.keyNum) for delivery to the QA Device being upgraded.KeyRef.useChipId = 0 For variant key input and output signatures:KeyRef.keyNum = Slot number of the key to be used for generating thevariant key. SIG_(E) produced using a variant of K_(KeyRef.keyNum) bythe QA Device being upgraded. SIGout produced using a variant ofK_(KeyRef.keyNum) for delivery to the QA Device being upgraded.KeyRef.useChipId = 1 KeyRef.chipId = ChipId of the device whichgenerated SIG_(E) and will receive SIGout. _(M0)OfExternal All 16 wordsof _(M0) of the QA Device being upgraded. _(M1)OfExternal All 16 wordsof _(M1) of the QA Device being upgraded. ChipId ChipId of the QA Devicebeing upgraded. FieldNumL _(M0) field number of the local (refill)device from which the value will be transferred. FieldNumE _(M0) fieldnumber of the QA Device being upgraded to which the value will betransferred. XferValLength XferVal length in words. Non zero lengthrequired. XferVal The logical amount that will be transferred from thelocal device to the external device. R_(E) External random value used toverify input signature. This will be the R from the input signaturegenerator (i.e device generating SIG_(E)). The input signal generator inthis case, is the device being upgraded or a translation device. R_(E2)External random value used to produce output signature. This will be Robtained by calling the Random function on the device which will receivethe SIG_(out) from the XferAmount function. The device receiving theSIG_(out) in this case, is the device being upgraded or a translationdevice. SIG_(E) External signature required for authenticating inputdata. The input data in this case, is the output from the Read functionperformed on the device being upgraded. A correct SIG_(E) =SIG_(KeyRef)(Data|R_(E)|R_(L)).27.1.2.1 Input Signature Verification Data Format

The input signature passed in to the XferAmount function is the outputsignature from the Read function of the Ink QA Device.

FIG. 382 shows the input signature verification data format for theXferAmount function.

Table 290 gives the parameters included in SIG_(E) for XferAmount.Length in Value set Value set from Parameter bits internally InputRWSense 3 000 Refer to Section 15.3.1.1 MSelect 4 0011 KeyIdSelect 800000000 ChipId 48 ChipId of the QA Device being upgraded WordSelect forM₀ 16 All bits set to 1 WordSelect for M₁ 16 All bits set to 1 M0 512 ●M1 512 ● R_(E) 160 ● R_(L) 160 Based on the ● internal R

The XferAmount function is not passed all the parameters required togenerate SIG_(E). For producing SIG_(L) which is used to test SIG_(E),the function uses the expected values of some the parameters.

27.1.3 Output Parameters

Table 291 describes each of the output parameters for XferAmount.Parameter Description ResultFlag Indicates whether the functioncompleted successfully or not. If it did not complete successfully, thereason for the failure is returned here. See Table 47. FieldSelectSelection of fields to be written In this case the bit corresponding toSEQ_1, SEQ_2 and to FieldNumE are set to 1. All other bits are set to 0.FieldVal Updated data words for Sequence data field and FieldNumE for QADevice being upgraded. Starts with LSW of lower field. This must bepassed as input to the WriteFieldsAuth function of the QA Device beingupgraded. R_(L2) Internal random value required to generate outputsignature. This must be passed as input to the WriteFieldsAuth functionor Translate function of the QA Device being upgraded. SIG_(out) Outputsignature which must be passed as an input to the WriteFieldsAuthfunction of the QA Device being upgraded. SIG_(out) =SIG_(KeyRef)(data|R_(L2)|R_(E2)) as per FIG. 373.

Table 292. Result Flag definitions for XferAmount. TABLE 292 Result Flagdefinitions for XferAmount ResultFlag Definition DescriptionFieldNumEInvalid Field Num to which the amount is being transferred, orwhich is being upgraded in the QA Device being upgraded is invalid.SeqFieldInvalid The sequence field for the QA Device being upgraded isinvalid. FieldNumEWritePermInvalid FieldNum to which the amount is beingtransferred, or which is being upgraded in the QA Device being upgradedhas no authenticated write permission. FieldNumLInvalid FieldNum fromwhich the amount is being transferred, or from which the value is beingcopied in the Upgrading QA Device is invalid. FieldNumLWritePermInvalidFieldNum from which the amount is being transferred in the Upgrading QADevice has no authenticated permission, or no authenticated permissionwith the KeyRef. TypeMismatch Type of the data from which the amount isbeing transferred in the Upgrading QA Device, doesn't match the Type ofdata to which the amount in being transferred in the Device beingupgraded. UpgradeFieldEInvalid Only applicable for transferringcount-remaining values. The upgrade field associated with thecount-remaining field in the QA Device being upgraded is invalid.UpgradeFieldLInvalid Only applicable for transferring count-remainingvalues. The upgrade field associated with the count-remaining field inthe Upgrading QA Device is invalid. UpgradeFieldMismatch Only applicablefor transferring count-remaining values. Type of the data in the upgradefield in the Upgrading QA Device, doesn't match the Type of data in theupgrade field in the Device being upgraded. FieldNumESizeInsufficientFieldNum to which the amount is being transferred, or which is beingupgraded in the QA Device is not big enough to store the transferreddata. FieldNumLAmountInsufficient FieldNum in the Upgrading QA Devicefrom which the amount is being transferred doesn't have the amountrequired for the transfer.27.1.3.1 SIG_(out)

Refer to Section 20.2.1 for details.

27.1.4 Function Sequence

The XferAmount command is illustrated by the following pseudocode:

Accept input parameters-KeyRef, M0OfExternal, M1OfExternal, ChipId,FieldNumL, FieldNumE, XferValLength  # Accept XferVal words  For i

0 to XferValLength   Accept next XferVal  EndFor  Accept R_(E), SIG_(E),R_(E2)  #Generate message for passing into ValidateKeyRefAndSignature function  data

(RWSense|MSelect|KeyIdSelect|ChipId|WordSelect|M0|M1)    # Refer toFigure 382. ----------------------------------------------------------------  #Validate KeyRef, and then verify signature  ResultFlag =ValidateKeyRefAndSignature(KeyRef,data,R_(E),R_(L))  If (ResultFlag ≠Pass)   Output ResultFlag   Return  EndIf ---------------------------------------------------------------- #Validate FieldNumE  # FieldNumE is present in the device beingupgraded  PresentFlagFieldNumE

GetFieldPresent(M1OfExternal,FieldNumE)  # Check FieldNumE present flag If(PresentFlagFieldNumE ≠ 1)   ResultFlag

FieldNumEInvalid   Output ResultFlag   Return  EndIf ------------------------------------------------------------------ ---------------  # Check Seq Fields Exist and get their Field Num  #Get Seqdata field SEQ_1 num for the device being upgraded XferSEQ_1FieldNum

GetFieldNum(M1OfExternal, SEQ_1)  # Check if the Seqdata field SEQ_1 isvalid  If(XferSEQ_1FieldNum invalid)   ResultFlag

SeqFieldInvalid   Output ResultFlag   Return  EndIf  # Get Seqdata fieldSEQ_2 num for the device being upgraded  XferSEQ_2FieldNum

GetFieldNum(M1OfExternal, SEQ_2)  # Check if the Seqdata field SEQ_2 isvalid  If(XferSEQ_2FieldNum invalid)   ResultFlag

SeqFieldInvalid   Output ResultFlag   Return  EndIf ---------------------------------------------------------------- #Checkwrite permission for FieldNumE  PermOKFieldNumE

CheckFieldNumEPerm(M1OfExternal,  FieldNumE)  If(PermOKFieldNumE ≠ 1)  ResultFlag

FieldNumEWritePermInvalid   Output ResultFlag   Return  EndIf ---------------------------------------------------------------- #Check that both SeqData fields have Decrement-Only permission  withthe same key  #that has write permission on FieldNumE  PermOKXferSeqData

CheckSeqDataFieldPerms(M1OfExternal,         XferSEQ_1FieldNum, XferSEQ_2FieldNum,FieldNumE)  If(PermOKXferSeqData ≠ 1)   ResultFlag

SeqWritePermInvalid   Output ResultFlag   Return  EndIf ----------------------------------------------------------------  # GetSeqData SEQ_1 data from device being upgraded GetFieldDataWords(XferSEQ_1FieldNum,  XferSEQ_1DataFromDevice,M0OfExternal,M1OfExternal)  # Get SeqDataSEQ_2 data from device being upgraded GetFieldDataWords(XferSEQ_2FieldNum,         XferSEQ_2DataFromDevice, M0OfExternal,M1OfExternal) ----------------------------------------------------------------  #FieldNumL is a present in the refill device  PresentFlagFieldNumL

GetFieldPresent(M1,FieldNumL)  If(PresentFlagFieldNumL ≠ 1)   ResultFlag

FieldNumLInvalid   Output ResultFlag   Return  EndIf  #Check permissionfor FieldNumL  PermOKFieldNumL

CheckFieldNumLPerm(M1,FieldNumL,  KeyRef)  If(PermOKFieldNumL ≠ 1)  ResultFlag

FieldNumLWritePermInvalid   Output ResultFlag   Return  EndIf ----------------------------------------------------------------  #Findthe type attribute for FieldNumE  TypeFieldNumE

FindFieldNumType(M1OfExternal,FieldNumE)  #Find the type attribute forFieldNumL  TypeFieldNumL

FindFieldNumType(M1,FieldNumL)  # Check type attribute for both fieldsmatch  If(TypeFieldNumE ≠TypeFieldNumL)   ResultFlag

TypeMismatch   Output ResultFlag   Return  EndIf ---------------------------------------------------------------------------------------------------------------------------------------Do this if the Refill Device is tranferring Count-remaining for Printerupgrades  # If the Type is count remaining, check that upgrade values associated with  # the count remaining are valid. Refer to Section 28.for further  details on  # count remaining and upgrade value. If(TypeFieldNumL = TYPE_COUNT_REMAINING)

 (TypeFieldNumE =TYPE_COUNT_REMAINING)   #Upgrade value field is loweradjoining field   UpgradeValueFieldNumE = FieldNumE −1  If(UpgradeValueFieldNumE < 0) # upgrade field doesn't exist for  QADevice being upgraded    ResultFlag

UpgradeFieldEInvalid    Output ResultFlag    Return   EndIf  UpgradeValueFieldNumL = FieldNumL − 1   If(UpgradeValueFieldNumL < 0)# upgrade field doesn't exist for  local device    ResultFlag

UpgradeFieldLInvalid    Output ResultFlag    Return   EndIf  UpgradeValueCheckOK

 UpgradeValCheck(UpgradeValueFieldNumL,M0,M1,  UpgradeValueFieldNumL,M0OfExternal,M1OfExternal,KeyRef)  If(UpgradeValueCheckOK = 0)    ResultFlag

UpgradeFieldMismatch    Output ResultFlag    Return   EndIf  EndIf  # Dothis if Field Type is Count Remaining........end ---------------------------------------------------------------- #Check whether the device being upgraded can hold the transfer  amount #(XferVal + AmountLeft  OverFlow

CanHold(FieldNumE,M0OfExternal,XferVal)  If OverFlow error   ResultFlag

FieldNumESizeInsufficient   Output ResultFlag   Return  EndIf ---------------------------------------------------------------- #Check the refill device has the desired amount (XferVal < = AmountLeft)  UnderFlow

HasAmount(FieldNumL,M0,XferVal)  If UnderFlow error   ResultFlag

FieldNumLAmountInsufficient   Output ResultFlag   Return  EndIf ----------------------------------------------------------------  # Allchecks complete .....  # Generate Seqdata for SEQ_1 and SEQ_2 fields XferSEQ_1DataToDevice = XferSEQ_1DataFromDevice − 2 XferSEQ_2DataToDevice = XferSEQ_2DataFromDevice − 1  # Add DataSet toXfer Entry Cache  AddDataSetToXferEntryCache(ChipId,FieldNumE,FieldNumL,  XferLength, XferVal, XferSEQ_1DataFromDevice, XferSEQ_2DataFromDevice)  # Get current FieldDataE field data words towrite to Xfer Entry  cache GetFieldDataWords(FieldNumE,FieldDataE,M0OfExternal,  M1OfExternal) #Deduct XferVal from FieldNumL and Write new value DeductAndWriteValToFieldNumL(XferVal,FieldNumL,M0)  #Generate new fielddata words for FieldNumE. The current  FieldDataE is added to  # XferValto generate new FieldDataE GenerateNewFieldData(FieldNumE,XferVal,FieldDataE)  # GenerateFieldSelect and FieldVal for SeqData field SEQ_1, SEQ_2  and  #FieldDataE...  CurrentFieldSelect

0  FieldVal

0  GenerateFieldSelectAndFieldVal(FieldNumE, FieldDataE, XferSEQ_1FieldNum, XferSEQ_1DataToDevice, XferSEQ_2FieldNum,XferSEQ_2DataToDevice,  FieldSelect,FieldVal) #Generate message for passing into GenerateSignature function  data

(RWSense|FieldSelect|ChipId|FieldVal)# Refer to Figure 373.  #Createoutput signature for FieldNumE  SIG_(out)

GenerateSignature(KeyRef,data,R_(L2),R_(E2))  Update R_(L2) to R_(L3) ResultFlag

Pass  Output ResultFlag, FieldData, R_(L2) _(,)SIG_(out)  Return  EndIf27.1.4.1 ResultFlag ValidateKeyRefAndSignature(KeyRef,data,R_(E),R_(L))

This function checks KeyRef is valID, and if KeyRef is valID, then inputsignature is verified using KeyRef. CheckRange(KeyRef.keyNum) If invalid  ResultFlag

InValidKey   Output ResultFlag   Return EndIf #Generate message forpassing into GenerateSignature function data

(RWSense|MSelect|KeyIdSelect|ChipId|WordSelect|M0|M1)     # Refer toFigure 382. #Generate Signature SIG_(L)

GenerateSignature(KeyRef,data,R_(E),R_(L)) # Check input signatureSIG_(E) If(SIG_(L) = SIG_(E))   Update R_(L) to R_(L2) Else   ResultFlag

Bad Signature   Output ResultFlag   Return EndIf27.1.4.2 GenerateFieldSelectAndFieldVal (FieldNumE, FieldDataE,XferSEQ_(—)1FieldNum, XferSEQ_(—)1DataToDevice, XferSEQ_(—)2FieldNum,XferSEQ_(—)2DataToDevice, FieldSelect, FieldVal)

This functions generates the FieldSelect and FieldVal for output fromFieldNumE and its final data, and data to be written to Seq fieldsSEQ_(—)1 and SEQ_(—)2.

27.1.4.3 PresentFlag GetFieldPresent(M1,FieldNum)

This function checks whether FieldNum is a valid. FieldSize[16]

0 # Array to hold FieldSize assuming there are 16 fields NumFields

FindNumberOfFieldsInM0(M1,FieldSize) #Refer to Section 19.4.1If(FieldNum< NumFields)   PresentFlag

1 Else   PresentFlag

0 EndIf Return PresentFlag27.1.4.4 NumFields FindNumOfFieldsInM0(M1,FieldSize

)

Refer to Figure 19.4.1 for details.

27.1.4.5 FieldNum GetFieldNum(M1, Type)

This function returns the field number based on the Type. FieldSize[16]

0 # Array to hold FieldSize assuming there are 16 fields NumFields

FindNumberOfFieldsInM0(M1,FieldSize) #Refer to Section 19.4.1 For i = 0to NumFields   If(M1[i].Type = Type)     Return i # This is field Numfor matching field EndFor i = 255 # If XferSession field was not foundthen return an invalid value Return i27.1.4.6 PermOK CheckFieldNumEPerm(M1,FieldNumE)

This function checks authenticated write permission for FieldNum whichholds the upgraded value. AuthRW

M1[FieldNum].AuthRW NonAuthRW

M1[FieldNum].NonAuthRW If(AuthRW = 1)

(NonAuthRW = 0)   PermOK

1 Else   PermOK

0 EndIf Return PermOK27.1.4.7 PermOK CheckSeqDataFieldPerms(M1, XferSEQ_(—)1FieldNum,XferSEQ_(—)2FieldNum, FieldNumE)

This function checks that both SeqData fields have Decrement-Onlypermission with the same key that has write permission on FieldNumE.KeyNumForFieldNumE

M1[Field.NumE].KeyNum # Isolate KeyNum for the field that will                  # be upgraded # Isolate KeyNum for both SeqData fieldsand check that they can be written using the same key KeyNumForSEQ_1

M1[XferSEQ_1FieldNum].KeyNum KeyNumForSEQ_2

M1[XferSEQ_2FieldNum].KeyNum If(KeyNumForSEQ_1 ≠KeyNumForSEQ_2)   PermOK

0   Return PermOK EndIf # Check that the write key for FieldNumE andSeqData field is not the same If (KeyNumForSEQ_1 = KeyNumForFieldNumE)  PermOK

0   Return PermOK EndIf #Isolate Decrement-Only permissions with thewrite key of FieldNumE KeyPermsSEQ_1

M1[XferSEQ_1FieldNum].KeyPerms[KeyNumForFieldNumE] KeyPermsSEQ_2

M1[XferSEQ_2FieldNum].KeyPerms[KeyNumForFieldNumE] # Check that bothsequence fields have Decrement-Only permission for this keyIf(KeyPermsSEQ_1 = 0)

(KeyPermsSEQ_2 = 0)   PermOK

0   Return PermOK EndIf PermOK

1 Return PermOK27.1.4.8 AddDataSetToXferEntryCache (ChipID, FieldNumE, FieldNumL,XferVa/, SEQ_(—)1Data, SEQ_(—)2Data)

This function adds a new dataset to the Xfer Entry cache. Dataset is asingle record in the Xfer Entrycache. Refer to Section 27 for details. #Search for matching ChipId FieldNumE is Cache DataSet

SearchDataSetInCache (ChipId, FieldNumE) # If found If(DataSet is valid)  DeleteDataSetInCache(DataSet) # This creates a vacant dataset  AddRecordToCache(ChipId, FieldNumE,FieldDataL,XferVal,SEQ_1Data,SEQ_2Data) EndIf # Searches the cache for XferStatecomplete/deleted Found

SearchRecordsInCache(complete/deleted) If(Found =1)  AddRecordToCache(ChipId, FieldNumE,FieldDataL,XferVal,SEQ_1Data,SEQ_2Data) Else   # This will overwrite the oldest DataSet incache   AddRecordToCache(ChipId, FieldNumE,FieldDataL,XferVal,SEQ_1Data,SEQ_2Data)   Return Endif Set XferState in record to XferReturn27.1.4.9 FieldType FindFieldNumType(M1,FieldNum)

This function gets the Type attribute for a given field.

-   -   FieldType←M1[FieldNum].Type    -   Return FieldType        27.1.4.10 PermOK CheckFieldNumLPerm(M1, FieldNumL, KeyRef)

This function checks authenticated write permissions using KeyRef forFieldNumL in the refill device. AuthRW

_(M1)[FieldNumL].AuthRW KeyNumAtt

_(M1)[FieldNumL].KeyNum DOForKeys

_(M1)[FieldNumL].DOForKeys[KeyNum] # Authenticated write allowed #ReadWrite key for field is the same as Input KeyRef.keyNum # Key hasboth ReadWrite and DecrementOnly Permission If(AuthRW = 1)

(KeyRef.keyNum = KeyNumAtt)

(DOForKeys = 1   PermOK

1 Else   PermOK

0 EndIf Return PermOK27.1.4.11 CheckOK UpgradeValCheck(FieldNum1, M0OfFieldNum1,M1OfFieldNum1, FieldNum2, M0OfFieldNum2, M1OfFieldNum2,KeyRef)

This function checks the upgrade value corresponding to the countremaining. The upgrade value corresponding to the count remaining fieldis stored in the lower adjoining field. To upgrade the count remainingfield, the upgrade value in refill device and the device being upgradedmust match. #Check authenticated write permissions is allowed to thefield #Check that only one key has ReadWrite access, #and all other keysare ReadOnly access PermCheckOKFieldNum1

CheckUpgradeKeyForField(FieldNum1,M1OfFieldNum1,KeyRef)If(PermCheckOKFieldNum1 ≠ 1)   CheckOK

0   Return CheckOK EndIf PermCheckOKFieldNum2

CheckUpgradeKeyForField(FieldNum2,M1OfFieldNum2,KeyRef)If(PermCheckOKFieldNum2 ≠ 1)   CheckOK

0   Return CheckOK EndIf #Get the upgrade value associated with fieldGetFieldDataWords(FieldNum1,UpgradeValueFieldNum1,M0OfFieldNum1,M1OfFieldNum1) #Get the upgrade value associated withfield GetFieldDataWords(FieldNum2,UpgradeValueFieldNum2,M0OfFieldNum2,M1OfFieldNum2) If(UpgradeValueFieldNum1 ≠UpgradeValueFieldNum2)   CheckOK

0   Return CheckOK EndIf # Get the type attribute for the fieldUpgradeTypeFieldNum1

GetupgradeType(FieldNum1, M1OfFieldNum1) UpgradeTypeFieldNum2

GetupgradeType(FieldNum2, M1OfFieldNum2) If(UpgradeTypeFieldNum1 ≠UpgradeTypeFieldNum2)   CheckOK

0   Return CheckOK EndIf CheckOK

1 Return CheckOK27.1.4.12 CheckOK CheckUpgradeKeyForField(FieldNum,M1,KeyRef)

This function checks that authenticated write permissions is allowed tothe field. It also checks that only one key has ReadWrite access and allother keys have ReadOnly access. KeyRef which updates count remainingmust not have write access to the upgarde value field. KeyNum

M1[FieldNum].KeyNum AuthRW

M1[FieldNum].AuthRW NonAuthRW

M1[FieldNum].NonAuthRW DOForKeys

M1[FieldNum].DOForKeys #Check that KeyRef doesn't have write permissionsto the field If(KeyRef.keyNum = KeyNum)   CheckOK

0   Return CheckOK EndIf #AuthRW access allowed or NonAuthRW not allowedIf(AuthRW = 0)

(NonAuthRW =1)   CheckOK

0   Return CheckOK EndIf For i

0 to 7   # Keys other than KeyNum are allowed ReadOnly access,   #DecrementOnly access not allowed for other keys(not KeyNum)   If (i≠KeyNum)

(DOForKeys[i] = 1)     CheckOK

0     Return CheckOK   EndIf   #ReadWrite access allowed for KeyNum,  #ReadWrite and DecrementOnly access not allowed for KeyNum.   If (i =KeyNum)

(DOForKeys[i] = 1)     CheckOK

0     Return CheckOK   EndIf EndFor CheckOK

1 Return CheckOK27.1.4.13 Upgrade Type GetUpgrade Type(FieldNum, M1)

This function gets the type attribute for the upgrade field.

-   -   UpgradeType GetUpgradeType(FieldNum)    -   UpgradeType←M1[FieldNum].Type    -   Return UpgradeType        27.1.4.14 GetFieldDataWords(FieldNum,FieldData        , M0, M1)

This function gets the words corresponding to a given field. CurrPos

MaxWordInM If FieldNum = 0  CurrPos

MaxWordInM Else  CurrPos

(M1[FieldNum −1].EndPos) −1 # Next lower word after last word of the                  # previous field EndIf EndPos

(M1[FieldNum].Endpos) For i

EndPos to CurrPos j

0  FieldData[j]

M0[i] #Copy M0 word to FieldData array EndFor

27.2 StartRollBack Input: KeyRef, _(M0)OfExternal, _(M1)OfExternal,ChipId, FieldNumL, FieldNumE, InputParameterCheck (optional), R_(E),SIG_(E), R_(E2) Output: ResultFlag, FieldSelect, Field Val, R_(L2),SIG_(out) Changes: _(M0) and R_(L) Availability Ink refill QA Device andParameter Upgrader QA Device

-   -   Availability Ink refill QA Device and Parameter Upgrader QA        Device        27.2.1 Function Description

StartRollBack function is used to start a rollback sequence if the QADevice being upgraded didn't receive the transfer message correctly andhence didn't receive the transfer.

The system calls the function on the upgrading QA Device, passing inFieldNumE and ChipId of the QA Device being upgraded, and FieldNumL ofthe upgrading QA Device. The upgrading QA Device checks that the QADevice being upgraded didn't actually receive the message correctly, bycomparing the values read from the device with the values stored in theXfer Entry cache. The values compared is the value of the sequencefields. After all checks are fulfilled, the upgrading QA Device producesthe new data for the sequence fields and a signature. This issubsequently applied to the QA Device being upgraded (using theWriteFieldAuth function), which updates the sequence fields SEQ_(—)1 andSEQ_(—)2 to the pre-rollback values. However, the new data for thesequence fields and signature can only be applied if the previous datafor the sequence fields produced by Xfer function has not been written.

The output from the StartRollBack function consists only of the fielddata of the two sequence fields, and a signature using the refill key.When a pre-rollback output is produced, then sequence field data inSEQ_(—)1 (as stored in the Xfer Entry cache, which is what is passed into the XferAmount function) is decremented by 1 and the sequence fielddata in SEQ_(—)2 (as stored in the Xfer Entry cache, which is what ispassed in to the XferAmount function) is decremented by 2.

Additional InputParameterCheck value must be provided for the parametersnot included in the SIG_(E), if the transmission between the System andInk Refill QA Device is error prone, and these errors are not correctedby the transimission protocol itself. InputParameterCheck isSHA-1[FieldNumL|FieldNumE], and is required to ensure the integrity ofthese parameters, when these inputs are received by the Ink Refill QADevice.

The StartRollBack function must first calculate theSHA-1[FieldNumL|FieldNumE], compare the calculated value to the valuereceived (InputParameterCheck) and only if the values match act upon theinputs.

27.2.2 Input Parameters

Table 293 describes each of the input parameters for StartRollbackfunction. Parameter Description KeyRef For common key input signature:KeyRef.keyNum = Slot number of the key to be used for testing inputsignature. SIG_(E) produced using K_(KeyRef.keyNum) by the QA Devicebeing upgraded. KeyRef.useChipId = 0 For variant key input signature:KeyRef.keyNum = Slot number of the key to be used for generating thevariant key for testing input signature. SIG_(E) produced using avariant of K_(KeyRef.keyNum) by the QA Device being upgraded.KeyRef.useChipId = 1 KeyRef.chipId = ChipId of the device whichgenerated SIG_(E.) _(M0)OfExternal All 16 words of _(M0) of the QADevice being upgraded which failed to upgrade. _(M1)OfExternal All 16words of _(M1) of the QA Device being upgraded which failed to upgrade.ChipId ChipId of the QA Device being upgraded which failed to upgrade.FieldNumL _(M0) field number of the local (refill) device from which thevalue was supposed to transferred. FleidNumE _(M0) field number of theQA Device being upgraded to which the value couldn't be transferred.R_(E) External random value used to verify input signature. This will bethe R from the input signature generator (i.e device generatingSIG_(E)). The input signal generator in this case, is the device whichfailed to upgrade or a translation device. SIG_(E) External signaturerequired for authenticating input data. The input data in this case, isthe output from the Read function performed on the device which failedto upgrade. A correct SIG_(E) = SIG_(KeyRef)(Data|R_(E)|R_(L)).27.2.2.1 Input Signature Verification Data Format

Refer to Section 27.1.2.1.

27.2.3 Output Parameters

Table 294 describes each of the output parameters for StartRollbackfunction. Parameter Description ResultFlag Indicates whether thefunction completed successfully or not. If it did not completesuccessfully, the reason for the failure is returned here. See Section12.1, Table 292 and Table 295. FieldSelect Selection of fields to bewritten In this case the bits corresponding to SEQ_1 and SEQ_2 are setto 1. All other bits are set to 0. FieldVal Updated data for sequencedatat field for QA Device being upgraded. This must be passed as inputto the WriteFieldsAuth function of the QA Device being upgraded. R_(L2)Internal random value required to generate output signature. This mustbe passed as input to the WriteFieldsAuth function or Translate functionof the QA Device being upgraded. SIG_(out) Output signature which mustbe passed as an input to the WriteFieldsAuth function of the QA Devicebeing upgraded. SIG_(out) = SIG_(KeyRef)(data|R_(L2)|R_(E2)) as per FIG.373.

TABLE 295 Result definition for StartRollBack ResultFlag DefinitionDescription RollBackInvalid RollBack cannot be performed on the requestbecause parameters for rollback is incorrect.27.2.3.1 SIG_(out)

Refer to Section 20.2.1 for details.

27.2.4 Function Sequence

The StartRollBack command is illustrated by the following pseudocode:Accept input parameters-KeyRef, M0OfExternal, M1OfExternal, ChipId,FieldNumL, FieldNumE, R_(E), SIG_(E), R_(E2) Accept R_(E), SIG_(E),R_(E2) #Generate message for passing into ValidateKeyRefAndSignaturefunction data

(RWSense|MSelect|KeyIdSelect|ChipId|WordSelect|M0|M1)    # Refer toFigure 382.---------------------------------------------------------------- #Validate KeyRef, and then verify signature ResultFlag =ValidateKeyRefAndSignature(KeyRef,data,R_(E),R_(L)) If (ResultFlag ≠Pass)  Output ResultFlag  Return EndIf----------------------------------------------------------------# CheckSeq Fields Exist and get their Field Num # Get Seqdata field SEQ_1 numfor the device being upgraded XferSEQ_1FieldNum

GetFieldNum(M1OfExternal, SEQ_1) # Check if the Seqdata field SEQ_1 isvalid If(XferSEQ_1FieldNum invalid)  ResultFlag

SeqFieldInvalid  Output ResultFlag  Return EndIf # Get Seqdata fieldSEQ_2 num for the device being upgraded XferSEQ_2FieldNum

GetFieldNum(M1OfExternal, SEQ_2) # Check if the Seqdata field SEQ_2 isvalid If(XferSEQ_2FieldNum invalid)  ResultFlag

SeqFieldInvalid  Output ResultFlag  Return EndIf---------------------------------------------------------------- # GetSeqData SEQ_1 data from device being upgradedGetFieldDataWords(XferSEQ_1FieldNum, XferSEQ_1DataFromDevice,M0OfExternal,M1OfExternal) # Get SeqData SEQ_2data from device being upgraded GetFieldDataWords(XferSEQ_2FieldNum,       XferSEQ_2DataFromDevice, M0OfExternal,M1OfExternal)---------------------------------------------------------------- # CheckXfer Entry in cache is correct - dataset exists, Field data # andsequence field data matches and Xfer State is correct XferEntryOK

CheckEntry(ChipId, FieldNumE, FieldNumL,        XferSEQ_1DataFromdevice,       XferSEQ_2DataFromDevice) If( XferEntryOK= 0)  ResultFlag

RollBackInvalid  Output ResultFlag  Return EndIf # Generate Seqdata forSEQ_1 and SEQ_2 fields XferSEQ_1DataToDevice = XferSEQ_1DataFromDevice −1 XferSEQ_2DataToDevice = XferSEQ_2DataFromDevice − 2 # GenerateFieldSelect and FieldVal for sequence fields SEQ_1 and SEQ_2CurrentFieldSelect

0 FieldVal

0 GenerateFieldSelectAndFieldVal(XferSEQ_1FieldNum,XferSEQ_1DataToDevice, XferSEQ_2FieldNum, XferSEQ_2DataToDevice,FieldSelect, FieldVal) #Generate message for passing intoGenerateSignature function data

(RWSense|FieldSelect|ChipId|FieldVal)# Refer to Figure 373. #Createoutput signature for FieldNumE SIG_(out)

GenerateSignature(KeyRef,data,R_(L2),R_(E2)) Update R_(L2) to R_(L3)ResultFlag

Pass Output ResultFlag, FieldData, R_(L2) ,SIG_(out) Return EndIf

27.3 RollBackAmount Input: KeyRef, _(M0)OfExternal, _(M1)OfExternal,ChipId, FieldNumL, FieldNumE, InputParameterCheck (optional), R_(E),SIG_(E) Output: ResultFlag Changes: _(M0) and R_(L) Availablity: Inkrefill QA Device27.3.1 Function Description

RollBackAmount function finally adjusts the value of the FieldNumL ofthe upgarding QA Device to a previous value before the transfer request,if the QA Device being upgraded didn't receive the transfer messagecorrectly (and hence was not upgraded).

The upgrading QA Device checks that the QA Device being upgraded didn'tactually receive the transfer message correctly, by comparing thesequence data field values read from the device with the values storedin the Xfer Entry cache. The sequence data field values read must matchwhat was previously written using the StartRollBack function. After allchecks are fulfilled, the upgrading QA Device adjusts its FieldNumL.

Additional InputParameterCheck value must be provided for the parametersnot included in the SIG_(E), if the transmission between the System andInk Refill QA Device is error prone, and these errors are not correctedby the transimission protocol itself. InputParameterCheck isSHA-1[FieldNumL|FieldNumE], and is required to ensure the integrity ofthese parameters, when these inputs are received by the Ink Refill QADevice.

The RollBackAmount function must first calculate theSHA-1[FieldNumL|FieldNumE], compare the calculated value to the valuereceived (InputParameterCheck) and only if the values match act upon theinputs.

27.3.2 Input Parameters

Table 296 describes each of the intput parameters for RollbackAmountfunction. Parameter Description KeyRef For common key input signature:KeyRef.keyNum = Slot number of the key to be used for testing inputsignature. SIG_(E) produced using K_(KeyRef.keyNum) by the QA Devicebeing upgraded. KeyRef.useChipId = 0 For variant key input signature:KeyRef.keyNum = Slot number of the key to be used for generating thevariant key for testing input signature. SIG_(E) produced using avariant of K_(KeyRef.keyNum) by the QA Device being upgraded.KeyRef.useChipId = 1 KeyRef.chipId = ChipId of the device whichgenerated SIG_(E.) _(M0)OfExternal All 16 words of _(M0) of the QADevice being upgraded which failed to upgrade. _(M1)OfExternal All 16words of _(M1) of the QA Device being upgraded which failed to upgrade.ChipId ChipId of the QA Device being upgraded which failed to upgrade.FieldNumL _(M0) field number of the local (refill) device from which thevalue was supposed to transferred. FieldNumE _(M0) field number of theQA Device being upgraded to which the value was not transferred. R_(E)External random value used to verify input signature. This will be the Rfrom the input signature generator (i.e device generating SIG_(E)). Theinput signal generator in this case, is the device which failed toupgrade or a translation device. SIG_(E) External signature required forauthenticating input data. The input data in this case, is the outputfrom the Read function performed on the device which failed to upgrade.A correct SIG_(E) = SIG_(KeyRef)(Data|R_(E)|R_(L)).27.3.2.1 Input Signature Generation Data Format

Refer to Section 27.1.2.1 for details.

27.3.3 Output Parameters

Table 297 describes each of the output parameters for RollbackAmount.Parameter Description ResultFlag Indicates whether the functioncompleted successfully or not. If it did not complete successfully, thereason for the failure is returned here. See Section 12.1, Table 292 andTable 295.27.3.4 Function Sequence

The RollBackAmount command is illustrated by the following pseudocode:Accept input parameters-KeyRef, M0OfExternal, M1OfExternal, ChipId,FieldNumL, FieldNumE, R_(E),SIG_(E) #Generate message for passing intoValidateKeyRefAndSignature function data

(RWSense|MSelect|KeyIdSelect|ChipId|WordSelect|M0|M1)    # Refer toFigure 382.---------------------------------------------------------------- #Validate KeyRef, and then verify signature ResultFlag =ValidateKeyRefAndSignature(KeyRef,data,R_(E),R_(L)) If (ResultFlag ≠Pass)  Output ResultFlag  Return EndIf---------------------------------------------------------------- # CheckSeq Fields Exist and get their Field Num # Get Seqdata field SEQ_1 numfor the device being upgraded XferSEQ_1FieldNum

GetFieldNum(M1OfExternal, SEQ_1) # Check if the Seqdata field SEQ_1 isvalid If(XferSEQ_1FieldNum invalid)  ResultFlag

SeqFieldInvalid  Output ResultFlag  Return EndIf # Get Seqdata fieldSEQ_2 num for the device being upgraded XferSEQ_2FieldNum

GetFieldNum(M1OfExternal, SEQ_2) # Check if the Seqdata field SEQ_2 isvalid If(XferSEQ_2FieldNum invalid)  ResultFlag

SeqFieldInvalid  Output ResultFlag  Return EndIf---------------------------------------------------------------- # GetSeqData SEQ_1 data from device being upgradedGetFieldDataWords(XferSEQ_1FieldNum, XferSEQ_1DataFromDevice,M0OfExternal,M1OfExternal) # Get SeqData SEQ_2data from device being upgraded GetFieldDataWords(XferSEQ_2FieldNum,     XferSEQ_2DataFromDevice, M0OfExternal,M1OfExternal)--------------------------------------------------------------- #Generate Seqdata for SEQ_1 and SEQ_2 fields with the data that is readXferSEQ_1Data = XferSEQ_1DataFromDevice + 1 XferSEQ_2Data =XferSEQ_2DataFromDevice + 2 # Check Xfer Entry in cache is correct -dataset exists, Field data # and sequence field data matches and XferState is correct XferEntryOK

CheckEntry(ChipId, FieldNumE, FieldNumL,      XferSEQ_1Data,XferSEQ_2Data) If( XferEntryOK= 0)  ResultFlag

RollBackInvalid  Output ResultFlag  Return EndIf # Get ΔFieldDataL fromDataSet GetVal (ChipId, FieldNumE,ΔFieldDataL) # Add ΔFieldDataL toFieldNumL AddValToField(FieldNumL,ΔFieldDataL) # Update XferState inDataSet to complete/deleted UpdateXferStateToComplete(ChipId,FieldNumE)ResultFlag

Pass Output ResultFlag ReturnFunctionsUpgrade Device(Printer Upgrade)28 Concepts

This section is very similar to Section 26. The differences between thissection and Section 26 have been summarised and underlined, whererequired.

28.1 Purpose

In a printing application, a printer contains a Printer QA Device, whichstores details of the various operating parameters of a printer, some ofwhich may be upgradeable. The upgradeable parameters must be written(initially) and changed in an authorised manner.

The authorisation for the write or change is achieved by using aParameter Upgrader QA Device which contains the necessary functions toallow a write or a change of a parameter value (e.g. a print speed) intoanother QA Device, typically a printer QA Device. This QA Device is alsoreferred to as an upgrading QA Device.

A parameter upgrader QA Device is able to perform a fixed number ofupgrades, and this number is effectively a consumable value. The numberof upgrades remaining is also referred to as count-remaining. With eachwrite/change of an operating parameter in a Printer QA Device, thecount-remaining decreases by 1, and can be replenished by a valueupgrader QA Device.

The Parameter Upgrader QA Device can also be referred to as theUpgrading QA Device, and the Printer QA Device can also be referred toas the QA Device being upgraded.

The writing or changing of the parameter can also be referred to as atransfer of a parameter.

The Parameter Upgrader QA Device copies its parameter value field to theparameter value field of Printer QA Device, and decrements thecount-remaining field associated with the parameter value field by 1.

28.2 Requirements

The transfer of a parameter has two basic requirements:

-   -   The transfer can only be performed if the transfer request is        valid. The validity of the transfer request must be completely        checked by the Parameter Upgrader QA Device, before it produces        the required output for the transfer. It must not be possible to        apply the transfer output to the Printer QA Device, if the        Parameter Upgrader QA Device has been already been rolled back        for that particular transfer.    -   A process of rollback is available if the transfer was not        received by the Printer QA Device.

A rollback is performed only if the rollback request is valid. Thevalidity of the rollback request must be completely checked by theParameter Upgrader QA Device, before the count-remaining value isincremented by 1. It must not be possible to rollback an ParameterUpgrader QA Device for a transfer, which has already been applied to thePrinter QA Device i.e the Parameter Upgrader QA Device must only berolled back for transfers that have actually failed.

28.3 Basic Scheme

The transfer and rollback process is shown in FIG. 383.

Following is a sequential description of the transfer and rollbackprocess:

1. The System Reads the memory vectors M0 and M1 of the Printer QADevice. The output from the read which includes the M0 and M1 words ofthe Printer QA Device, and a signature, is passed as an input to theTransfer Request. It is essential that M0 and M1 are read together. Thisensures that the field information for M0 fields are correct, and havenot been modified, or substituted from another device. Entire M0 and M1must be read to verify the correctness of the subsequent TransferRequest by the Parameter Upgrader QA Device.

2. The System makes a Transfer Request to the Parameter Upgrader QADevice with the field in the Parameter Upgrader QA Device whose datawill be copied to the Printer QA Device, and the field in Printer QADevice to which this data will be copied to. The Transfer Request alsoincludes the output from Read of the Printer QA Device. The ParameterUpgrader QA Device validates the Transfer Request based on the Readoutput, checks that it has enough count-remaining for a successfultransfer, and then produces the necessary Transfer output. The TransferOutput typically consists of new field data for the field being refilledor upgraded, additional field data required to ensure the correctness oftransfer/rollback, along with a signature.

3. The System then applies the Transfer Output on the Printer QA Device,by calling an authenticated Write on it, passing in the Transfer Output.The Write is either successful or not. If the Write is not successful,then the System will repeat calling the Write function using the sametransfer output, which may be successful or not. If unsuccessful theSystem will initiate a rollback of the transfer. The rollback must beperformed on the Parameter Upgrader QA Device, so that it can adjust itsvalue to a previous value before the current Transfer Request wasinitiated.

4. The System starts a rollback by Reading the memory vectors M0 and M1of the Printer QA Device.

5. The System makes a StartRollBack Request to the Parameter Upgrader QADevice with same input parameters as the Transfer Request, and theoutput from Read in (4). The Parameter Upgrader QA Device validates theStartRollBack Request based on the Read output, and then produces thenecessary Pre-rollback output. The Pre-rollback output typicallyconsists only of additional field data along with a signature.

6. The System then applies the Pre-rollback output on the ParameterUpgrader QA Device, by calling an authenticated Write on it, passing inthe Pre-rollback output. The Write is either successful or not. If theWrite is not successful, then either (6), or (5) and (6) must berepeated.

7. The System then Reads the memory vectors M0 and M1 of the Printer QADevice.

8. The System makes a RollBack Request to the Parameter Upgrader QADevice with same input parameters as the Transfer Request, and theoutput from Read (7). The Parameter Upgrader QA Device validates theRollBack Request based on the Read output, and then rolls back itscount-remaining field by incrementing it by 1.

28.3.1 Transfer

The Printer QA Device stores upgradeable operating parameter values inM0 fields, and its corresponding M₁ words contains field information forits operating parameter fields. The field information consists of thesize of the field, the Type of data stored in field and the accesspermission to the field. See Section 8.1.1 for details.

The Parameter Upgrader QA Device also stores the new operating parametervalues (which will be written to the Printer QA Device) in its M0fields, and its coressponding M₁ words contains field information forthe new operating parameter fields. Additionally, the Parameter UpgraderQA Device has a count-remaining field associated with the new operatingparameter value field. The count-remaining field occupies the higherfield position when compared to its associated operating parameter valuefield.

28.3.1.1 Authorisation

The basic authorisation for a transfer comes from a key, which hasauthenticated ReadWrite permission (stored in field information asKeyNum) to the operating parameter field in the Printer QA Device. Wewill refer to this key as the upgrade key. The same upgrade key mustalso have authenticated decrement-only permission to the count-remainingfield (which decrements by 1 with every transfer) in the ParameterUpgrader QA Device.

After validating the input upgrade request, the Parameter Upgrader QADevice will decrement the value of the count-remaining field by 1, andproduce data (by copying the data stored from its operating parameterfield) and signature for the new operating parameter using the upgradekey. Note that the Parameter Upgrader QA Device can decrement itscount-remaining field only if the upgrade key has the permission todecrement it.

The data and signature produced by the Parameter Upgrader QA Device issubsequently applied to the Printer QA Device. The Printer QA Devicewill accept the new transferred operating parameter, only if thesignature is valid. Note that the signature will only be valid if it wasproduced using the upgrade key which has write permission to theoperating parameter field being written.

The upgrade key has authenticated ReadWrite permission to the operatingparameter field (which will change) in the Printer QA Device. Theupgrade key has decrement-only permission to the the count-remainingfield (which decrements by 1 with every transfer of field) in theParameter Upgrader QA Device.

28.3.1.2 Data Type Matching

The Parameter Upgrader QA Device validates the transfer request bymatching the Type of the data in the field information of operatingparameter field (stored in M1) of Printer QA Device to the Type of datain the field information of operating parameter field of the ParameterUpgrader QA Device. This ensures that equivalent data types are beingtransferred i.e Network_OEM1_printspeed_(—)1500 is not transferred toNetwork_OEM1_printspeed_(—)2000.

28.3.1.3 Addition Validation

Additional validation of the transfer request must be performed before atransfer output is generated by the Parameter Upgrader QA Device. Theseare as follows:

-   -   For the Printer QA Device    -   1. Whether the field being upgraded is actually present.

2. Whether the field being upgraded can hold the changed value.

-   -   For the Parameter Upgrader QA Device:    -   1. Whether the new operating parameter field and its associated        count-remaining is actually present.

2. Whether the count-remaining field has an upgrade left for thetransfer to succeed.

28.3.1.4 Rollback Facilitation

To facilitate a rollback, the Parameter Upgrade QA Device will store alist of transfer requests processed by it. This list is referred to asthe Xfer Entry cache. Each record in the list consists of the transferparameters corresponding to the transfer request.

28.3.2 Rollback

A rollback request will be validated by looking through the Xfer Entrycache of the Parameter Upgrader QA Device. After the right transferrequest is found the Parameter Upgrade QA Device checks that the outputfrom the transfer request was not applied to the Printer QA Device bycomparing the current Read of the Printer QA Device to the values in theXfer Entry cache, and finally rolling back the Parameter Upgrader QADevice count-remaining field by incrementing it by 1. The ParameterUpgrader QA Device must be absolutely sure that the Printer QA Devicedidn't receive the transfer. This factor determines the additionalfields that must be written along with new operating parameter data, andalso the parameters of the transfer request that must be stored in theXfer Entry cache to facilitate a rollback, to prove that the Printer QADevice didn't actually receive the transfer.

The rollback process increments the count-remaining field by 1 in theParameter Upgrader QA Device.

28.3.2.1 Sequence Fields

The rollback process must ensure that the transfer output (which waspreviously produced) for which the rollback is being performed, cannotbe applied after the rollback has been performed. How do we achievethis? There are two separate decrement-only sequence fields (SEQ_(—)1and SEQ_(—)2) in the Printer QA Device which can only be decremented bythe Parameter Upgrader QA Device using the upgrade key. The nature ofdata to be written to the sequence fields is such that either thetransfer output or the pre-rollback output can be applied to the PrinterQA Device, but not both i.e they must be mutually exclusive. Refer toTable 285 for details.

The two sequence fields are initialised to 1xFFFFFFFF using sequencekey. The sequence key is different to the upgrade key, and hasauthenticated ReadWrite permission to both the sequence fields.

The transfer output consists of the new data for the field beingupgraded, field data of the two sequence fields, and a signature usingthe upgrade key. The field data for SEQ_(—)1 is decremented by 2 fromthe original value that was passed in with the transfer request. Thefield data for SEQ_(—)2 is decremented by 1 from the original value thatwas passed in with the transfer request.

The pre-rollback output consists only of the field data for the twosequence fields, and a signature using the upgrade key. The field datafor SEQ_(—)1 is decremented by 1 from the original value that was passedin with the transfer request. The field data for SEQ_(—)2 is decrementedby 2 from the original value that was passed in with the transferrequest.

Since the two sequence fields are decrement-only fields, the writing ofthe transfer output to QA Device being upgraded will prevent the writingof the pre-rollback output to QA Device being upgraded, since thesequence fields are decrement-only fields, and only one possible set canbe written. If the writing of the transfer output fails, thenpre-rollback can be written. However, the transfer output cannot bewritten after the pre-rollback output has been written.

Before a rollback is performed, the Parameter Upgrader QA Device mustconfirm that the sequence fields was successfully written to thepre-rollback values in the Printer QA Device. Because the sequencefields are decrement-only fields, the Printer QA Device will allowpre-rollback output to be written only if the transfer output has notbeen written.

28.3.2.1.1 Field Information of the Sequence Data Field

For a device to be upgradeable the device must have two sequence fieldsSEQ_(—)1 and SEQ_(—)2 which are written with sequence data during thetransfer sequence. Thus all upgrading QA Devices, ink QA Devices andprinter QA Devices must have two sequence fields. The upgrading QADevices must have these fields because they can be upgraded as well. Thesequence field information are defined in Table 298. Attribute NameValue Explanation Type TYPE_SEQ_1 or TYPE_SEQ_2. See Appendix A forexact data. KeyNum Slot number of the sequence key. Only the sequencekey has authenticated ReadWrite access to this field. Non Auth RW 0 Nonauthenticated ReadWrite Perm^(b) is not allowed to the field. Auth RWPerm^(c) 1 Authenticated (key based) ReadWrite access is allowed to thefield. KeyPerm KeyPerms[KeyNum] = 0 KeyNum is the slot number of thesequence key, which has ReadWrite permission to the field. KeyPerms[Slotnumber of upgrade key] = 1 Upgrade key can decrement the sequence field.KeyPerms[others = 0 ..7(except upgrade All other keys have ReadOnlyaccess. key)] = 0 End Pos Set as required. Size is typically 1 word.a. This is a sample type only and is not included in the Type Map inAppendix A.^(b)Non authenticated Read Write permission.^(c)Authenticated Read Write permission.28.3.3 Upgrade States

There are three states in an transfer sequence, the first state isinitiated for every transfer, while the next two states are initiatedonly when the transfer fails. The states are—Xfer, StartRollback, andRollback.

28.3.3.1 Upgrade Flow

FIG. 384 shows a typical upgrade flow.

28.3.3.2 Xfer

This state indicates the start of the transfer process, and is the onlystate required if the transfer is successful. During this state, theParameter Upgrader QA Device adds a new record to its Xfer Entry cache,decrements its count-remaining by 1, produces new operating parameterfield, new sequence data (as described in Section 28.3.2.1) and asignature based on the upgrade key.

The Printer QA Device will subsequently write the new operatingparameter field and new sequence data, after verifying the signature. Ifthe new operating parameter field can be successfully written to thePrinter QA Device, then this will finish a successful transfer.

If the writing of the new amount is unsuccessful (result returned is BADSIG), the System will re-transmit the transfer output to the Printer QADevice, by calling the authenticated Write function on it again, usingthe same transfer output.

If retrying to write the same transfer output fails repeatedly, theSystem will start the rollback process on Parameter Upgrader QA Device,by calling the Read function on the Printer QA Device, and subsequentlycalling the StartRollBack function on the Parameter Upgrader QA Device.After a successful rollback is performed, the System will invoke thetransfer sequence again.

28.3.3.3 StartRollBack

This state indicates the start of the rollback process. During thisstate, the Parameter Upgrade QA Device produces the next sequence dataand a signature based on the upgrade key. This is also called apre-rollback, as described in Section 26.3.2.

The pre-rollback output can only be written to the Printer QA Device, ifthe previous transfer output has not been written. The writing of thepre-rollback sequence data also ensures, that if the previous transferoutput was captured and not applied, then it cannot be applied to thePrinter QA Device in the future.

If the writing of the pre-rollback output is unsuccessful (resultreturned is BAD SIG), the System will re-transmit the pre-rollbackoutput to the Printer QA Device, by calling the authenticated Writefunction on it again, using the same pre-rollback output.

If retrying to write the same pre-rollback output fails repeatedly, theSystem will call the StartRollback on the Parameter Upgrade QA Deviceagain, and subsequently calling the authenticated Write function on thePrinter QA Device using this output.

28.3.3.4 Rollback

This state indicates a successful deletion (completion) of a transfersequence. During this state, the Parameter Upgrader QA Device verifiesthe sequence data produced from StartRollBack has been correctly writtento Printer QA Device, then rolls its count-remaining field to a previousvalue before the transfer request was issued.

28.3.4 Xfer Entry Cache

The Xfer Entry data structure must allow for the following:

-   -   Stores the transfer state and sequence data for a given transfer        sequence.    -   Store all data corresponding to a given transfer, to facilitate        a rollback to the previous value before the transfer output was        generated.

The Xfer Entry cache depth will depend on the QA Chip Logical Interfaceimplementation. For some implementations a single Xfer Entry value willbe saved. If the Parameter Upgrader QA Device has no powersafe storageof Xfer Entry cache, a power down will cause the erasure of the XferEntry cache and the Parameter Upgrader QA Device will not be able torollback to a pre-power-down value.

A dataset in the Xfer Entry cache will consist of the following:

-   -   Information about the Printer QA Device:    -   a. ChipId of the device.    -   b. FieldNum of the M0 field (i.e what was being upgraded).    -   Information about the Parameter Upgrader QA Device:    -   a. FieldNum of the M0 field used to transfer the count-remaining        from.    -   Xfer State—indicating at which state the transfer sequence is.        This will consist of:    -   a. State definition which could be one of the following:—Xfer,        StartRollBack and deleted (completed).    -   b. The value of sequence data fields SEQ_(—)1 and SEQ_(—)2.

The Xfer Entry cache stores the FieldNum of the count-remaining field ofthe Parameter Upgrader QA Device.

28.3.4.1 Adding New Dataset

A new dataset is added to Xfer Entry cache by the Xfer function.

There are three methods which can be used to add new dataset to the XferEntry cache. The methods have been listed below in the order of theirpriority:

-   1. Replacing existing dataset in Xfer Entry cache with new dataset    based on ChipId and FieldNum of the Ink QA Device in the new    dataset. A matching ChipId and FieldNum could be found because a    previous transfer output corresponding to the dataset stored in the    Xfer Entry cache has been correctly received and processed by the    Parameter Upgrader QA Device, and a new transfer request for the    same Printer QA Device, same field, has come through to the    Parameter Upgrader QA Device.-   2. Replace existing dataset cache with new dataset based on the Xfer    State. If the Xfer State for a dataset indicates deleted (complete),    then such a dataset will not be used for any further functions, and    can be overwritten by a new dataset.-   3. Add new dataset to the end of the cache. This will automatically    delete the oldest dataset from the cache regardless of the Xfer    State.    28.4 Upgrading the Count-Remaining Field

This section is only applicable to the Parameter Upgrader QA Device.

The transfer of count-remaining is similar to transfer ink-remainingbecause both involve transferring of amounts. Therefore, this transferuses the XferAmount function.

The XferAmount function performs additional checks when transferringcount-remaining. This includes checking of the operating parameterfield, associated with the count-remaining. They are as follows:

-   -   The operating parameter value of the upgrading QA Device and the        QA Device being upgraded must match.    -   The operating parameter field (in both devices) must be        upgradeable by one key only, and all other keys must have        ReadOnly access. This key which has authenticated ReadWrite        permission to the operating parameter field, must be different        to the key that has authenticated Read Write permission to the        count-remaining field.    -   The data Type for the operating parameter field in the upgrading        QA Device must match the data Type for the operating parameter        field in the QA Device being upgraded.        28.5 New Operating Parameter Field Information

This section is only applicable to the Parameter Upgrader QA Device.

This field stores the operating parameter value that is copied from theParameter Upgrader QA Device to the operating parameter field beingupdated in the Printer QA Device.

This field has a single key associated with it. This key hasauthenticated ReadWrite permission to this field and will be referred toas write-parameter key.

Table 299 shows the field information for the new operating parameterfield in the Parameter Upgrader QA Device. Attribute Name ValueExplanation Type For e.g - Type describing the upgrade.TYPE_UPGRADE_PRINTSPEED_15^(a) KeyNum Slot number of the write-parameterkey. Only the write-parameter key has authenticated ReadWrite access tothis field. Non Auth RW 0 Non authenticated ReadWrite Perm^(b) is notallowed to the field. Auth RW Perm^(c) 1 Authenticated (key based)ReadWrite access is allowed to the field. KeyPerm KeyPerms[KeyNum] = 0KeyNum is the slot number of the write- parameter key which hasReadWrite permission to the field. KeyPerms[others = 0 ..7] = 0 Allother keys have ReadOnly access. End Pos Set as required.^(a)This is a sample type only and is not included in the Type Map inAppendix A.^(b)Non authenticated Read Write permission.^(c)Authenticated Read Write permission.

-   a. This is a sample type only and is not included in the Type Map in    Appendix A.-   b. Non authenticated Read Write permission.-   c. Authenticated Read Write permission.    28.6 Different Types of Transfer

There can be three types of transfer:

-   -   Parameter Transfer—This is transfer of an operating parameter        value from a Parameter Upgrader QA Device to a Printer QA        Device. This is performed when an upgradeable operating        parameter is written (for the first time) or changed.    -   Hierarchical refill—This is a transfer of count-remaining value        from one Parameter Upgrader Refill QA Device to a Parameter        Upgrader QA Device, where both QA Devices belong to the same        OEM. This is typically performed when OEM divides the number of        upgrades from one of its Parameter Upgrader QA Device to many of        its Parameter Upgrader QA Devices.    -   Peer to Peer refill—This is a transfer of count-remaining value        from one Parameter Upgrader Refill QA Device to Parameter        Upgrader Refill QA Device, where the QA Devices belong to        different organisations, say ComCo and OEM. This is typically        performed when ComCo divides number of upgrades from its        Parameter Upgrader QA Device to several Parameter Upgrader QA        Device belonging to several OEMs.

Transfer of count-remaining between peers, and hierarchical transfer ofcount-remaining, is similar to an ink transfer, but additional checks onthe transfer request is performed when transferring count-remainingamounts. This is described in Section 28.4.1.

Transfer of an operating parameter value decrements the count-remainingby 1, hence is different to a ink-transfer.

FIG. 385 is a representation of various authorised upgrade paths in theprinting system.

28.6.1 Hierarchical Transfers

Referring to FIG. 385, this transfer is typically performed whencount-remaining amount is transferred from ComCo's Parameter UpgraderRefill QA Device to OEM's Parameter Upgrader Refill QA Device, or fromQACo's Parameter Upgrader Refill QA Device to ComCo's Parameter UpgraderRefill QA Device.

This transfers are made using the XferAmount function (and not with theXferField described in Section 29.1). because count-remaining transferis similar to fill/refilling of ink amounts, where ink amount isreplaced by count-remaining amount.

28.6.1.1 Keys and Access Permission

We will explain this using a transfer from ComCo to OEM.

There is a count-remaining field associated with the ComCo's ParameterUpgrader Refill QA Device. This count-remaining field has two keysassociated with:

-   -   The first key transfers count-remaining to the device from        another Parameter Upgrader Refill QA device(device is higher in        the heirachy), fills/refills the device itself.    -   The second key transfers count-remaining from it to other        devices (which are lower in the heirachy), fills/refills other        devices from it.

There is a count-remaining field associated with the OEM's ParameterUpgrader Refill QA Device.

-   -   This count-remaining field has a single key associated with:    -   This key transfers count-remaining to the device from another        Parameter Upgrader Refill QA device (which is higher or at the        same level in the heirachy), fills/refills (upgrades) the device        itself, and additionally transfers count-remaining from it to        other devices (which are lower in the heirachy), fills/refills        (upgrades) other devices from it.

For a successful transfer of count-remaining from ComCo's refill deviceto an OEM's refill device, the ComCo's refill device and the OEM'srefill device must share a common key or a variant key.

This key is fill/refill key with respect to the OEM's refill device andit is the transfer key with respect to the ComCo's refill device.

For a ComCo to successfully fill/refill its refill device from anotherrefill device (which is higher in the heirachy possibly belonging to theQACo), the ComCo's refill device and the QACo's refill device must sharea common key or a variant key. This key is fill/refill key with respectto the ComCo's refill device and it is the transfer key with respect tothe QACo's refill device.

28.6.1.1.1 Count-Remaining Field Information

Table 300 shows the field information for an _(M0) field storing logicalcount-remaining amounts in the refill device, which has the ability totransfer down the heirachy. Attribute Name Value Explanation TypeTYPE_COUNT_REMAINING^(a) Type describes that the field is a count-remaining field. KeyNum Slot number of the refill key. Only the refillkey has authenticated ReadWrite access to this field. Non Auth RW 0 Nonauthenticated ReadWrite Perm^(b) is not allowed to the field. Auth RWPerm^(c) 1 Authenticated (key based) ReadWrite access is allowed to thefield. KeyPerm KeyPerms[KeyNum] = 0 KeyNum is the slot number of therefill key, which has ReadWrite permission to the field. KeyPerms[SlotNum of transfer key] = 1 Transfer key can decrement the field.KeyPerms[others = 0 ..7(except transfer All other keys have ReadOnlyaccess. key)] = 0 End Pos Set as required. Depends on the amount oflogical ink the device can store and storage resolution - i.e inpicolitres or in microlitres.^(a)Refer to Type Map in Appendix A for exact value.^(b)Non authenticated Read Write permission.^(c)Authenticated Read Write permission.28.6.2 Peer to Peer Transfer

Referring to FIG. 385, this transfer is typically performed whencount-remaining amount is transferred from OEM's Parameter UpgraderRefill QA Device to another Parameter Device Refill QA Device belongingto the same OEM.

28.6.2.1 Keys and Access Permission

There is an count-remaining field associated with the refill device.This count-remaining field has a single key associated with:

-   -   This key transfers count-remaining amount to the device from        another refill device (which is higher or at the same level in        the heirachy), fills/refills (upgrades) the device itself, and        additionally transfers ink from it to other devices (which are        lower in the heirachy), fills/refills (upgrades) other devices        from it.

This key is referred to as the fill/refill key and is used for bothfill/refill and transfer. Hence, this key has both ReadWrite andDecrement-Only permission to the count-remaining field in the refilldevice.

28.6.2.1.1 Count-Remaining Field Information

Table 301 shows the field information for an _(M0) field storing logicalcount-remaining amounts in the refill device with the ability totransfer between peers. TABLE 301 Field information for ink-remainingfield for refill devices transferring between peers Attribute Name ValueExplanation Type TYPE_COUNT_REMAINING^(a) Type describes that the fieldis a count-remaining field. KeyNum Slot number of the refill key. Onlythe refill key has authenticated ReadWrite access to this field. NonAuth 0 Non authenticated ReadWrite is not allowed to the field. RWPerm^(b) Auth RW 1 Authenticated (key based) ReadWrite access Perm^(c)is allowed to the field. KeyPerm KeyPerms[KeyNum] = 1 KeyNum is the slotnumber of the refill key, which has ReadWrite and Decrement permissionto the field. KeyPerms[others = 0 ..7(except All other keys haveReadOnly access. KeyNum)] = 0 End Pos Set as required. Depends on theamount of logical ink the device can store and storage resolution - i.ein picolitres or in microlitres.^(a)Refer to Type Map in Appendix A for exact value.^(b)Non authenticated Read Write permission.^(c)Authenticated Read Write permission.29 Functions

29.1 XferField Input: KeyRef, _(M0)OfExternal, _(M1)OfExternal, ChipId,FieldNumL, FieldNumE, InputParameterCheck (Optional), R_(E), SIG_(E),R_(E2) Output: ResultFlag, Field data, R_(L2), SIG_(OUT) Changes: _(M0)and R_(L) Availablity: Parameter Upgrader QA Device29.1.1 Function Description

The XferField is similar to the XferAmount function in that it producesdata and signature for updating a given _(M0) field. This data andsignature when applied to the appropriate device through theWriteFieldsAuth function, will upgrade the FieldNumE (_(M0) field) of adevice to the same value as FieldNumL of the upgrading device.

The system calls the XferField function on the upgrade device with acertain FieldNumL to be transferred to the device being upgraded TheFieldNumE is validated by the XferField function according to variousrules as described in Section 29.1.4. If validation succeeds theXferField function produces the data and signature for subsequentpassing into the WriteFieldsAuth function for the device being upgraded.

The transfer field output consists of the new data for the field beingupgraded, field data of the two sequence fields, and a signature. When atransfer output is produced, the sequence field data in SEQ_(—)1 isdecremented by 2 from the previous value (as passed in with the input),and the sequence field data in SEQ_(—)2 is decremented by 1 from theprevious value (as passed in with the input).

Additional InputParameterCheck value must be provided for the parametersnot included in the SIG_(E), if the transmission between the System andParameter Upgrader QA Device is error prone, and these errors are notcorrected by the transimission protocol itself. InputParameterCheck isSHA-1[FieldNumL|FieldNumE|XferValLength|XferVal], and is required toensure the integrity of these parameters, when these inputs are receivedby the Parameter Upgrader QA Device.

The XferField function must first calculate theSHA-1[FieldNumL|FieldNumE], compare the calculated value to the valuereceived (InputParameterCheck) and only if the values match act upon theinputs.

29.1.2 Input Parameters

Table 302 describes each of the input parameters for XferField function.Parameter Description KeyRef For common key input and output signature:KeyRef.keyNum = Slot number of the key to be used for testing inputsignature and producing the output signature. SIG_(E) produced usingK_(KeyRef.keyNum) by the QA Device being upgraded. SIGout produced usingK_(KeyRef.keyNum) for delivery to the QA Device being upgraded.KeyRef.useChipId = 0 For variant key input and output signatures:KeyRef.keyNum = Slot number of the key to be used for generating thevariant key. SIG_(E) produced using a variant of K_(KeyRef.keyNum) bythe QA Device being upgraded. SIGout produced using a variant ofK_(KeyRef.keyNum) for delivery to the QA Device being upgraded.KeyRef.useChipId = 1 KeyRef.chipId = ChipId of the device whichgenerated SIG_(E) and will receive SIGout. _(M0)OfExternal All 16 wordsof _(M0) of the QA Device being upgraded _(M1)OfExternal All 16 words of_(M1) of the QA Device being upgraded. ChipId ChipId of the QA Devicebeing upgraded. FieldNumL _(M0) field number of the local (updating)device. The data stored in this field will be copied from the upgradingdevice. FieldNumE _(M0) field number of the QA Device being upgraded.This field will be updated to the value stored in FieldNumL within theupgrading device. R_(E) External random value used to verify inputsignature. This will be the R from the input signature generator (i.edevice generating SIG_(E)). The input signal generator in this case, isthe device being upgraded or a translation device. R_(E2) Externalrandom value used to produce output signature. This will be the Robtained by calling the Random function on the device which will receivethe SIG_(out) from the XferField function. The device receiving theSIG_(out) in this case, is the device being upgraded or a translationdevice. SIG_(E) External signature required for authenticating inputdata. The input data in this case, is the output from the Read functionperformed on the device being upgraded. A correct SIG_(E) =SIG_(KeyRef)(Data|R_(E)|R_(L)).29.1.2.1 Input Signature Verification Data Format

Refer to Section 27.1.2.1.

29.1.3 Output Parameters

Table 303 describes each of the output parameters for XferFieldfunction. Parameter Description ResultFlag Indicates whether thefunction completed successfully or not. If it did not completesuccessfully, the reason for the failure is returned here. See Section12.1, Table 292 and Table 303. FieldSelect Selection of fields to bewritten In this case the bit corresponding to SEQ_1, SEQ_2 and toFieldNumE are set to 1. All other bits are set to 0. FieldVal Updateddata words for sequence data field and FieldNumE for QA Device beingupgraded. Starts with LSW of lower field. This must be passed as inputto the WriteFieldsAuth function of the QA Device being upgraded. R_(L2)Internal random value required to generate output signature This must bepassed as input to the WriteFieldsAuth function or Translate function ofthe QA Device being upgraded. SIG_(out) Output signature which must bepassed as an input to the WriteFieldsAuth function or Translate functionof the QA Device being upgraded. SIG_(out) =SIG_(KeyRef)(data|R_(L2)|R_(E2)) as per FIG. 37329.1.3.1 Output Signature Generation Data Format

Refer to Section 27.1.3.1.

29.1.4 Function Sequence

The XferField command is illustrated by the following pseudocode: Acceptinput parameters-KeyRef, M0OfExternal, M1OfExternal, ChipId, FieldNumL,FieldNumE, R_(E), SIG_(E), R_(E2) #Generate message for passing intoValidateKeyRefAndSignature function data

(RWSense|MSelect|KeyIdSelect|ChipId|WordSelect|M0|M1)    # Refer toFigure 382.---------------------------------------------------------------- #Validate KeyRef, and then verify signature ResultFlag =ValidateKeyRefAndSignature (KeyRef,data,R_(E),R_(L)) If (ResultFlag ≠Pass)  Output ResultFlag  Return EndIf---------------------------------------------------------------- #Validatate FieldNumE # FieldNumE is present in the device being upgradedPresentFlagFieldNumE

GetFieldPresent(M1OfExternal,FieldNumE) # Check FieldNumE present flagIf(PresentFlagFieldNumE ≠ 1)  ResultFlag

FieldNumEInvalid  Output ResultFlag  Return EndIf---------------------------------------------------------------- # CheckSeq fields exist and get their Field Number # Get Seqdata field SEQ_1for the device being upgraded XferSEQ_1FieldNum

GetFieldNum(M1OfExternal, SEQ_1) # Check if the Seqdata field SEQ_1 isvalid If(XferSEQ_1FieldNum invalid)  ResultFlag

SeqFieldInvalid  Output ResultFlag  Return EndIf # Get Seqdata fieldSEQ_2 for the device being upgraded XferSEQ_2FieldNum

GetFieldNum(M1OfExternal, SEQ_2) # Check if the Seqdata field SEQ_2 isvalid If(XferSEQ_2FieldNum invalid)  ResultFlag

SeqFieldInvalid  Output ResultFlag  Return EndIf--------------------------------------------------------------------------------- #Check write permission for FieldNumE PermOKFieldNumE

CheckFieldNumEPerm(M1OfExternal, FieldNumE) If(PermOKFieldNumE ≠ 1) ResultFlag

FieldNumEWritePermInvalid  Output ResultFlag  Return EndIf--------------------------------------------------------------------------------- #Check that both SeqData fields have Decrement-Onlypermission with the same key #that has write permission on FieldNumEPermOKXferSeqData

CheckSeqDataFieldPerms(M1OfExternal,         XferSEQ_1FieldNum,XferSEQ_2FieldNum,FieldNumE) If(PermOKXferSeqData ≠ 1)  ResultFlag

SeqWritePermInvalid  Output ResultFlag  Return EndIf--------------------------------------------------------------------------------- # Get SeqData SEQ_1 data from device being upgradedGetFieldDataWords(XferSEQ_1FieldNum, XferSEQ_1DataFromDevice,M0OfExternal,M1OfExternal) # Get SeqData SEQ_2data from device being upgraded GetFieldDataWords(XferSEQ_2FieldNum,        XferSEQ_2DataFromDevice, M0OfExternal,M1OfExternal)---------------------------------------------------------------- #FieldNumL(upgrade value)is a valid field in the upgrading devicePresentFlagFieldNumL

GetFieldPresent(M1,FieldNumL) If(PresentFlagFieldNumL ≠ 1)  ResultFlag

FieldNumLInvalid  Output ResultFlag  Return EndIf---------------------------------------------------------------- #Getthe CountRemaining field associated with the upgrade value field # TheCountRemaining field is the next higher field from the upgrade valuefield FieldNumCountRemaining

FieldNumL + 1 # FieldNumCountRemaining is a valid field in the upgradingdevice PresentFlagFieldNumCountRemaining

GetFieldPresent(M1,FieldNumCountRemaining)If(PresentFlagFieldNumCountRemaining ≠ 1)  ResultFlag

CountRemainingFieldInvalid  Output ResultFlag  Return EndIf------------------------------------------------------------------#Check permission for upgrade value field. Only one key (different #from KeRef.keyNum) has write permissions to the field and no key hasdecrement permissions. CheckOK

CheckUpgradeKeyForField(FieldNumL,M1,KeyRef) If(CheckOK ≠ 1)  ResultFlag

FieldNumEKeyPermInvalid  Output ResultFlag  Return EndIf------------------------------------------------------------------ #Findthe type attribute for FieldNumE TypeFieldNumE

FindFieldNumType(M1OfExternal,FieldNumE) #Find the type attribute forFieldNumL (upgrade value) TypeFieldNumL

FindFieldNumType(M1,FieldNumL) If(TypeFieldNumE ≠ TypeFieldNumL) ResultFlag

TypeMismatch  Output ResultFlag  Return EndIf------------------------------------------------------------------ #Check permissions for CountRemaining field # Check upgrades areavailable in the CountRemaining field of the # upgrading device i.evalue of CountRemaining is non-zero positive number CountRemainingOK

CheckCountRemaining (FieldNumCountRemaining, M0, M1) If(CountRemainingOK≠ 1)  ResultFlag

NoUpgradesRemaining  Output ResultFlag  Return EndIf---------------------------------------------------------------- #Getthe size of the FieldNumL (upgrade value) If(FieldNumL = 0) FieldSizeOfFieldNumL

MaxWordInM− M1[FieldNumL].EndPos Else  FieldSizeOfFieldNumL

M1[FieldNumL−1].EndPos− M1[FieldNumL].EndPos EndIf #Get the size of theFieldNumE (field being updated) If(FieldNumL = 0)  FieldSizeOfFieldNumE

MaxWordInM− M1OfExternal [FieldNumE − 1].EndPos Else FieldSizeOfFieldNumE

M1OfExternal[FieldNumE−1].EndPos −        M1OfExternal[FieldNumL].EndPosEndIf # Check whether the device being upgraded can hold the upgradevalue from # FieldNumL If(FieldSizeOfFieldNumE < FieldSizeOfFieldNumL) ResultFlag

FieldNumESizeInsufficient  Output ResultFlag  Return EndIf------------------------------------------------------------------ # Allchecks complete ..... # Generate Seqdata for SEQ_1 and SEQ_2 fieldsXferSEQ_1DataToDevice = XferSEQ_1DataFromDevice − 2XferSEQ_2DataToDevice = XferSEQ_2DataFromDevice − 1 # Add DataSet toXfer Entry Cache AddDataSetToXferEntryCache(ChipId, FieldNumE,FieldNumL, XferSEQ_1DataFromDevice, XferSEQ_2DataFromDevice) #DecrementCountRemaining field by one DecrementField(FieldNumCountRemaining,M0)#Get the upgrade value words from FieldNumE of the upgrading deviceGetFieldDataWords(FieldNumL, UpgradeValue,M0,M1) #Generate new fielddata words for FieldNumE. The upgrade value is copied to FieldDataEFieldDataE

UpgradeValue # Generate FieldSelect and FieldVal for SeqData fieldSEQ_1, SEQ_2 and # FieldDataE... CurrentFieldSelect

0 FieldVal

0 GenerateFieldSelectAndFieldVal(FieldNumE, FieldDataE,XferSEQ_1FieldNum, XferSEQ_1DataToDevice,XferSEQ_2FieldNum,XferSEQ_2DataToDevice, FieldSelect,FieldVal) #Generate message forpassing into GenerateSignature function data

(RWSense|Fieldselect|ChipId|FieldVal)# Refer to Figure 373. #Createoutput signature for FieldNumE SIG_(out)

GenerateSignature(KeyRef,data,R_(L2),R_(E2)) Update R_(L2) to R_(L3)ResultFlag

Pass Output ResultFlag, FieldSelect,FieldVal, R_(L2 ,)SIG_(out) ReturnEndIf29.1.4.1 CountRemainingOKCheckCountRemainingFieldNumL(FieldNumCountRemaining, M1, M0)

This functions checks permissions for CountRemaining field and alsochecks that upgrades are available in the CountRemaining field of theupgrading device. AuthRW

M1[FieldNumCountRemaining].AuthRW NonAuthRW

M1[FieldNumCountRemaining].NonAuthRW DOForKeys

_(M1)[FieldNumCountRemaining].DOForKeys[KeyNum] Type

_(M1)[FieldNumCountRemaining].Type

(Type = TYPE_COUNT_REMAINING)  PermOK

1 Else  PermOK

0  Return PermOK EndIf #Get the count-remaining value from the upgradingdevice GetFieldDataWords(FieldNumCountRemaining,CountRemainingValue,M0,M1) If(CountRemainingValue <= 0)  PermOK

0  Return PermOK EndIf PermOK

1 Return PermOK29.2 RollBackField

Table 305 describes each of the input parameters for RollBackFieldfunction. Input: KeyRef, _(M0)OfExternal, _(M1)OfExternal, ChipId,FieldNumL, FieldNumE, InputParameterCheck (optional), R_(E), SIG_(E)Output: ResultFlag Changes: _(M0) and R_(L) Availablity: ParameterUpgrader QA Device29.2.1 Function Description

The RollBackField function is very similar to the RollBackAmountfunction, the only difference being that the RollBackField functionadjusts the value of the count-remaining field associated with theupgrade value field of the upgrading device, instead of the upgradevalue field itself. A successful rollback, increments thecount-remaining by 1.

The Parameter Upgrader QA Device checks that the Printer QA Devicedidn't actually receive the transfer message correctly, by comparing thesequence data field values read from the device with the values storedin the Xfer Entry cache. The sequence data field values read must matchwhat was previously written using the StartRollBack function. After allchecks are fulfilled, the Parameter Upgrader QA Device adjusts itsFieldNumL.

Additional InputParameterCheck value must be provided for the parametersnot included in the SIG_(E), if the transmission between the System andParameter Upgrader QA Device is error prone, and these errors are notcorrected by the transimission protocol itself. InputParameterCheck isSHA-1[FieldNumL|FieldNumE], and is required to ensure the integrity ofthese parameters, when these inputs are received by the ParameterUpgrader QA Device.

The RollBackField function must first calculate theSHA-1[FieldNumL|FieldNumE], compare the calculated value to the valuereceived (InputParameterCheck) and only if the values match act upon theinputs.

29.2.2 Input Parameters Parameter Description KeyRef For common keyinput signature: KeyRef.keyNum = Slot number of the key to be used fortesting input signature. SIG_(E) produced using K_(KeyRef.keyNum) by theQA Device being upgraded. KeyRef.useChipId = 0 For variant key inputsignature: KeyRef.keyNum = Slot number of the key to be used forgenerating the variant key. SIG_(E) produced using a variant ofK_(KeyRef.keyNum) by the QA Device being upgraded. KeyRef.useChipId = 1KeyRef.chipId = ChipId of the device which generated SIG_(E.)_(M0)OfExternal 16 words of _(M0) of the QA Device being upgraded whichfailed to upgrade. _(M1)OfExternal 16 words of _(M1) of the QA Devicebeing upgraded which failed to upgrade. ChipId ChipId of the QA Devicebeing upgraded which failed to upgrade. FieldNumL _(M0) field number ofthe local (upgrading) device whose value could not be copied to thedevice being upgraded. FieldNumE _(M0) field number of the QA Devicebeing upgraded to which the upgrade value in FieldNumL couldn't becopied. R_(E) External random value used to verify input signature. Thiswill be the R from the input signature generator (i.e device generatingSIG_(E)). The input signal generator in this case, is the device whichfailed to upgrade or a translation device. SIG_(E) External signaturerequired for authenticating input data. The input data in this case, isthe output from the Read function performed on the device which failedto upgrade. A correct SIG_(E) = SIG_(KeyRef)(Data| R_(E)|R_(L)).29.2.2.1 Input Signature Generation Data Format

Refer to Section 27.1.2.1 for details.

29.2.3 Output Parameters

Table 306 describes each of the output parameters for RollBackField.Parameter Description ResultFlag Indicates whether the functioncompleted successfully or not. If it did not complete successfully, thereason for the failure is returned here. See Section 12.1, Table 292,Table 304 and Table 295.

29.2.4 Function Sequence

The RollBackField command is illustrated by the following pseudocode:Accept input parameters-KeyRef, M0OfExternal, M1OfExternal, ChipId,FieldNumL, FieldNumE, R_(E),SIG_(E) #Generate message for passing intoGenerateSignature function data

(RWSense|MSelect|KeyIdSelect|ChipId|WordSelect|M0|M1)    # Refer toFigure 382.---------------------------------------------------------------- #Validate KeyRef, and then verify signature ResultFlag =ValidateKeyRefAndSignature(KeyRef,data,R_(E),R_(L)) If (ResultFlag ≠Pass)  Output ResultFlag  Return EndIf---------------------------------------------------------------- # CheckSeq fields exist and get their Field Number # Get Seqdata field SEQ_1num for the device being upgraded XferSEQ_1FieldNum

GetFieldNum(M1OfExternal, SEQ_1) # Check if the Seqdata field SEQ_1 isvalid If(XferSEQ_1FieldNum invalid)  ResultFlag

SeqFieldInvalid  Output ResultFlag  Return EndIf # Get Seqdata fieldSEQ_2 num for the device being upgraded XferSEQ_2FieldNum

GetFieldNum(M1OfExternal, SEQ_2) # Check if the Seqdata field SEQ_2 isvalid If(XferSEQ_2FieldNum invalid)  ResultFlag

SeqFieldInvalid  Output ResultFlag  Return EndIf----------------------------------------------------------------- # GetSeqData SEQ_1 data from device being upgradedGetFieldDataWords(XferSEQ_1FieldNum,  XferSEQ_1DataFromDevice,M0OfExternal,M1OfExternal) # Get SeqData SEQ_2 data from device beingupgraded GetFieldDataWords(XferSEQ_2FieldNum,        XferSEQ_2DataFromDevice, M0OfExternal,M1OfExternal) # GenerateSeqdata for SEQ_1 and SEQ_2 fields with the data that is readXferSEQ_1Data = XferSEQ_1DataFromDevice + 1 XferSEQ_2Data =XferSEQ_2DataFromDevice + 2 # Check Xfer Entry in cache is correct -dataset exists, Field data # and sequence field data matches and XferState is correct XferEntryOK

CheckEntry(ChipId, FieldNumE, FieldNumL,         XferSEQ_1Data,XferSEQ_2Data) If( XferEntryOK= 0)  ResultFlag

RollBackInvalid  Output ResultFlag  Return EndIf # Increment associatedCountRemaining by 1 IncrementCountRemaining(FieldNumCountRemaining) #Update XferState in DataSet to complete/deletedUpdateXferStateToComplete(ChipId,FieldNumE) ResultFlag

Pass Output ResultFlag ReturnExample Sequence of Operations30 Concepts

The QA Chip Logical Interface interface devices do not initiate anyactivities themselves. Instead the System reads data and signature fromvarious untrusted devices, and sends the data and signature to a trusteddevice for validation of signature, and then uses the data to performoperations required for printing, refilling, upgrading and keyreplacement. The system will therefore be responsible for performing thefunctional sequences required for printing, refilling, upgrading and keyreplacement. It formats all input parameters required for a particularfunction, then calls the function with the input parameters on theappropriate QA Chip Logical Interface instance, and thenprocesses/stores the output parameters from the function appropriately.

Validation of signatures is achieved by either of the following schemes:

-   -   Direct—the signature produced by an untrusted device is directly        passed in for validation to the trusted device. The direct        validation requires the untrusted device to share a common key        or a variant key with the trusted device. Refer to Section 7 for        further details on common and variant keys.    -   Translation—the signature produced by an untrusted is first        validated by the translating device, and a new signature of the        read data is produced by the translation device for validation        by the trusted device. Several translation device may be chained        together—the first translation device validates the signature        from the untrusted device, and the last translation device        produces the final signature for validation by the trusted        device. The translation device must share a common key or a        variant key with the trusted/untrusted device and among        themselves, if several translation devices are chained together        for signature validation.        30.1 Representation

Each functional sequence consists of the following devices (refer toSection 4.3):

-   -   System.    -   A trusted QA Device—which may be a system trusted QA Device, or        an Parameter Upgrader QA Device, or a Ink Refill QA Device, or a        Key Programmer QA Device depending on the function performed.        This device is referred to as device A.    -   An untrusted QA Device—which may be a Printer QA Device, or an        Ink QA Device. This device is referred to as device B.    -   A translation QA Device will be used if a translation scheme is        used to validate signatures. This device is referred to as        device C.

The command sequence produced by the system for further sequences willbe documented as shown in Table 307. TABLE 307 Command sequencerepresentation Sequence No Function Parameters Sequence orderDevice.FunctionName Input Parameters and their values. Output parametersand their description.

Therefore, a typical direct signature validation sequence can berepresented by FIG. 386 and Table 308.

For a direct signature to be used, A and B must share a common or avariant key i.e B.K_(n1)=A.K_(n2) or B.K_(n1)=FormKeyVariant(A.K_(n2),B.ChipID). TABLE 308 Command sequence for direct signature validationSequence No Function Parameters 1 A.Random None R_(A) =RL 2 B.ReadKeyRef = n1, SigOnly = 0, MSelect = Any one M, KeyIdSelect = 0,WordSelectForDesiredM = Any one word in the selected M, RE = R_(A) IfResultFlag = Pass then MWords = SelectedWordsOfSelectedMs as per input[MSelect] and [WordSelectForDesiredM], R_(B) = R_(L), SIG_(B) = SIGoutRefer to Section 15.3.1. 3 A.Test KeyRef = n2, DataLength = Length ofMWords in words preformatted as per Section 16.1, Data = MWordspreformatted as per Section 16.1, RE =R_(B), SIGE = SIG_(B) ResultFlag =Pass/Fail

A typical signature validation using translation can be represented byFIG. 387 and Table 309.

For validating signatures using translation:

-   -   A and C must share a common or a variant key        -   i.e C.K_(n3)=A.K_(n2) or C.K_(n3)=FormKeyVariant(A.K₂,            C.ChipID).    -   B and C must share a common or a variant key

i.e C.K_(n2)=B.K_(n1) or B.K_(n1)=Form KeyVariant(C.K_(n2), B.ChipID).TABLE 309 Command sequence for signature validation using translationSequence No Function Parameters 1 C.Random None R_(C) = RL 2 B.ReadKeyRef = n1, SigOnly = 1 or 0, MSelect = any, KeyIdSelect = any,WordSelectForDesiredM = any, RE = R_(C) If ResultFlag = Pass then MWords= SelectedWordsOfSelectedMs as per input [MSelect] and[WordSelectForDesiredM], R_(B) = R_(L), SIG_(B) = SIGout Refer toSection 15.3.1. 3 A.Random None R_(A) = RL 4 C.Translate InputKeyRef=n2, DataLength = Length of MWords in words preformatted as per Section17.1, Data = MWords preformatted as per Section 17.1, RE= R_(B), SIGE =SIG_(B), OutputKeyRef = n3, RE2 = R_(A) If ResultFlag = Pass thenR_(C1)= R_(L2), SIG_(C)= SIGOut Refer to Section 15.3.1 5 A.Test KeyRef= n2, DataLength = Length of MWords in words preformatted as per Section16.1, Data = MWords preformatted as per Section 16.1, RE =R_(C1), SIGE =SIG_(C) ResultFlag = Pass/Fail31 In Field Use

This section covers functional sequences for printer and ink QA Devices,as they perform their usual function of printing.

31.1 Startup Sequence

At startup of any operation (a printer startup or an upgrade startup),the system determines the properties of each QA Device it is going tocommunicate with. These properties are:

-   -   Software version of the QA Device. This includes        SoftwareReleaseIdMajor and SoftwareReleaseIdMinor. The        SoftwareReleaseIdMajor identifies the functions available in the        QA Device. Refer to Section 13.2 for details.    -   The number of memory vectors in the QA Device.    -   The number of keys in the QA Device.    -   The ChipId of the QA Device.

The properties allow the system to determine which functions areavailable in a given QA Device, as well as the value of input parametersrequired to communicate with the QA Device.

Table 310 shows the startup sequence. TABLE 310 Startup command sequenceSequence No Function Command 1 B.GetInfo None Major release identifierof the QA Device = SoftwareReleaseIdMajor, Minor release identifier ofthe QA Device= SoftwareReleaseIdMinor, Number of memory vectors in theQA Device= NumVectors, Number of keys in the QA Device= NumKeys, Id ofthe QA Device = ChipId 0 = VarDataLen No VarData in case of an ink orprinter QA Device31.1.1 Clearing the Preauthorisation Field

Preauthorisation of ink is one of the schemes that a printer may use todecrement logical ink as physical ink is used. This is discussed indetails in Section 31.4.3.

If the printer uses preauthorisation, the system must read thepreauthorisation field at startup. If the preauthorisation field is notclear, then the system must apply (decrement) the preauth amount to thecorresponding ink field, by performing a non-authenticated write of thedecremented amount to the appropriate ink field, and then clear thepreauthorisation field by performing an authenticated write to thepreauthorisation field.

31.2 Presence Only Authentication

The purpose of presence only authentication is to determine whether theprinter should or shouldn't work with the ink cartridge.

31.2.1 Without Data Interpretation

This sequence is performed when the printer authenticates the inkcartridge. The authentication consists of verifying a signaturegenerated by the untrusted ink QA Device (in the ink cartridge) usingthe system's trusted QA Device.

For signature to be valID, the trusted QA Device (A) and the untrustedink QA Device (B) must share a common or a variant key i.eB.K_(n1)=A.K_(n2) or B.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID).

A single word of a single M is read because the system is onlyinterested in the validity of signature for a given data.

If the printer wants to verify the signature and doesn't require anydata from the ink cartridge (because it is cached in the printer), thenthe printer calls the Read function with SigOnly set to 1. The Readreturns only the signature of the data as requested by the inputparameters. The printer then sends its cached data and signature (fromthe Read function) to its trusted QA Device for verification. Theprinter may use this signature verification scheme if it has read thedata previously from the ink QA Device, and the printer knows that thedata in the ink QA Device has not changed from value that was readearlier by the printer.

Table 311 shows the command sequence for performing presence onlyauthentication requiring both data and signature. Seq No FunctionParameters 1 A.Random None R_(A) = RL 2 B.Read KeyRef = n1, SigOnly = 0,MSelect = Any one M, KeyIdSelect = 0, WordSelectForDesiredM = Any oneword in the selected M, RE= R_(A) If ResultFlag = Pass then MWords =SelectedWordsOfSelectedMs as per input [MSelect] and[WordSelectForDesiredM], R_(B) = R_(L), SIG_(B) = SIGout Refer toSection 15.3.1. 3 A.Test KeyRef = n2, DataLength = Length of MWords inwords preformatted as per Section 16.1, Data = MWords preformatted asper Section 16.1, RE =R_(B), SIGE = SIG_(B) ResultFlag = Pass/Fail31.2.2 With Data Interpretation

This sequence is performed when the printer reads the relevant data fromthe untrusted QA Device in the ink cartridge. The system validates thesignature from the external ink QA Device, and then uses this data forfurther processing.

For signature to be valID, the trusted QA Device (A) and the untrustedQA Device (B) must share a common or a variant key i.e B.K_(n1)=A.K_(n2)or B.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID).

The data read assists the printer to determine the following beforeprinting can commence:

-   -   Which fields in _(M0) store logical ink amounts in the ink QA        Device.    -   The size of the ink fields in the ink QA Device. Refer to        Section 8.1.1.1.    -   The type of ink.    -   The amount of ink in the field.

Table 312 shows the command sequence for performing presence onlyauthentication (with data interpretation). Seq No Function Parameters 1A.Random None R_(A) = RL 2 B.Read KeyRef = n1, SigOnly = 0, MSelect =0x03(indicates M0 and M1), KeyIdSelect = 0xFF (Read all KeyIds),WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all 16 _(M0)words),WordSelectForDesiredM (for _(M1)) =0xFFFF (Read all 16 _(M1)words), RE=R_(A) If ResultFlag = Pass then MWords = SelectedWordsOfSelectedMs asper input [MSelect] and [WordSelectForDesiredM], All 16 words of _(M0)and _(M1). R_(B) = RL SIG_(B) = SIGout Refer to Section 15.3.1 3 A.TestInput Key = n2, DataLength = Length of MWords in words preformatted asper Section 16.1, Data = MWords preformatted as per Section 16.1, RE=R_(B), SIGE = SIG_(B) ResultFlag = Pass/Fail31.2.2.1 Locating Ink Fields and Determining Ink Amounts Remaining

Before printing can commence, the printer must determine the ink fieldsin the ink cartridge so that it can decrement these fields with thephysical use of ink. The printer must also verify that the ink in theink cartridge is suitable for use by the printer.

This process requires reading data from the ink QA Device and thencomparing the data to what is required. To perform the comparison theprinter must store a list for each ink it uses.

The ink list must consist of the following:

-   -   Ink Id—A identifier for the ink    -   KeyId—The KeyId of the key used to fill/refill this ink.    -   Type—This is the type attribute of the ink.

The ink list stored in the printer is shown in Table 313. Ink Id KeyIdType 1- represents 1- represents KeyId of 0x55 black inkNetwork_OEM_InkFill/ TYPE_REGULAR_(—) RefillKey^(b) BLACK_INK^(a) 2-represents 1- represents KeyId of 0x9F cyan ink Network_OEM_InkFill/TYPE_HIGHQUALITY_(—) RefillKey^(b) CYAN_INK^(a) 3- represents 1-represents KeyId of 0x9A magenta ink Network_OEM_InkFill/TYPE_HIGHQUALITY_(—) RefillKey^(b) MAGENTA_INK^(a) 4- represents 1-represents KeyId of 0x9C yellow ink Network_OEM_InkFill/TYPE_HIGHQUALITY_(—) RefillKey^(b) YELLOW_INK^(a)^(a)These Types are only used as an example.^(b)These KeyIds are only used as an example.

The printer will perform a Read of the ink QA Device's M0, M1 and KeyIdsto determine the following:

-   -   The correct ink field (_(M0) field) in the ink QA Device.    -   The amount of ink-remaining in the field.

The ink QA Device's M1 and KeyId helps the printer determine thelocation of the ink field and ink QA Device's M0 and M1 helps determinethe amount of ink-remaining in the field.

31.2.2.2 FieldNum FindFieldNum(keyIdRequired, typeRequired)

This function returns a FieldNum of an M0 field, whose authenticatedReadWrite access key's KeyId is keyIdRequired, and whose Type attributematches typeRequired. If no matching field is found it returns aFieldNum=255. This function must be available in the printer system sothat it can determine the ink field required by it.

The function sequence is described below. # Get total number of fieldsin the ink QA Device FieldSize[16]

0 # Array to hold FieldSize assuming there are 16 fields NumFields

FindNumberOfFieldsInM0(M1,FieldSize) # Refer to Section 19.4.1. # Loopthrough KeyIds read assuming all KeyIds have been read from ink QADevice For i

0 to 7  #Check if KeyId read matches  If(KeyId_(t) = keyIdRequired #Matching keyId found   KeyNum

i     # Get the KeyNum of the matching keyId   # Now look through thefield to check which field has   #write permissions with this KeyNum  For j

0 to NumOfFields    AuthRW

_(M1)[j].AuthRW # Isolate AuthRW for field    # Check authenticatedwrite is allowed to the field    If(AuthRW = 1)     KeyNum_(j)

_(M1)[j].KeyNum # Isolate KeyNum of the field     Typej

_(M1)[j].Type #Islotate Type attribute of the field     # Check if Keyis write key for the field and type of Ink Id#2     If(KeyNum =KeyNum_(j))

(Type_(j) = typeRequired)      FieldNum

j      return FieldNum     EndIf    EndIf   EndFor # Loop through tonext field   FieldNum

255 # Error - no field found   return FieldNum  EndIf EndFor # Loopthrough to next keyId   For e.g if the printer wants to find an inkfield that matches Ink Id#2 (from Table   313) in the ink QA Device, itmust call the function FindFieldNum with   keyIdRequired = keyId ofNetwork_OEM_InkFill/Refill Key and typeRequired =  TYPE_HIGHQUALITY_CYAN_INK.31.2.2.3 Ink-Remaining Amount

This can be determined by using the functionGetFieldDataWords(FieldNum,FieldData

, M0,M1) described in Section 27.1.4.14. FieldNum must be set to thevalue returned from function in Section 31.2.2.2. FieldData returns theink-remaining amount.

The function GetFieldDataWords(FieldNum,FieldData

, M0,M1) must be implemented in the printer system.

31.3 Presence Only Authentication Through the Translate Function

This sequence is performed when the printer reads the data from theuntrusted ink QA Device in the ink cartridge but uses a translating QADevice to indirectly validate the read data. The translating QA Devicevalidates the signature using the key it shares with the untrusted QADevice, and then signs the data using the key it shares with the trustedQA Device. The trusted QA Device then validates the signature producedby the translating QA Device.

For validating signatures using translation:

-   -   A and C must share a common or a variant key        -   i.e C.K_(n3)=A.K₂ or C.K_(n3)=FormKeyVariant(A.K_(n2),            C.ChipID).    -   B and C must share a common or a variant key        -   i.e C.K_(n2)=B.K_(n1) or B.K_(n1)=FormKeyVariant(C.K_(n2),            B.ChipID).

Table 314 shows a command sequence for presence only authenticationusing translation TABLE 314 Seq No Function Parameters 1 C.Random NoneR_(C)= RL 2 B.Read KeyRef = n1, SigOnly = 1 or 0, MSelect = any M,KeyIdSelect = 0, WordSelectForDesiredM = any, RE = R_(C) If ResultFlag =Pass then MWords = Selected WordsOfSelectedMs as per input [MSelect] and[WordSelectForDesiredM], R_(B) = R_(L), SIG_(B) = SIGout Refer toSection 15.3.1 3 A.Random None R_(A) = RL 4 C.Translate InputKeyRef =n2,DataLength = Length of MWords in words preformatted as per Section 17.1,Data = MWords preformatted as per Section 17.1, RE= R_(B), SIGE =SIG_(B), OutputKeyRef = n3, RE2 = R_(A) If ResultFlag = Pass thenR_(C1)=RL1, SIG_(C)= SIGOut Refer to Section 15.3.1 5 A.Test KeyRef =n2, DataLength = Length of MWords in words preformatted as per Section16.1, Data = MWords preformatted as per Section 16.1, RE =R_(C1), SIGE =SIG_(C) ResultFlag = Pass/Fail31.4 Updating the Ink-Remaining

This sequence is performed when the printer is printing. The ink QADevice holds the logical amount of ink-remaining corresponding to thephysical ink left in the cartridge. This logical ink amount mustdecrease, as physical ink from the ink cartridge is used for printing.

31.4.1 Sequence of Update

The primary question is when to deduct the logical ink amount—before orafter the physical ink is used.

a. Print first (use physical ink) and then update the logical ink. Ifthe power is cut off after a physical print and before a logical update,then the logical update is not performed. Therefore, the logicalink-remaining is more than the physical ink-remaining. Performingrepeated power cuts will increase the differential amount, and finallyany physical ink could be used to refill the QA Device.

b. Update the logical ink and then print (use physical ink). This isbetter than (a) because other physical inks cannot be used. However, ifa problem occurs during printing, after the logical amount has alreadybeen deducted, there will be a disparity between logical and physicalamounts. This might result in the printer not printing even if physicalink is present in the ink cartridge. The amount of disparity can bereduced by increasing the frequency of updating logical ink i.e updateafter each line instead of after each page.

c. Preauthorise logical ink. Preauthorise certain amount of ink (dependson the frequency of logical updates) before print and clear it at theend of printing. If power is cut off after a page is printed, then onstart up, the printer reads the preauthorisation field, if it has notbeen cleared, it applies the preauth amount to the ink-remaining amount,and then clears the preauthorisation field.

31.4.2 Basic Update

Some printers may use one of methods described in Section 31.4.1 (a) or(b) to update logical ink amounts in the ink QA Device. This method ofupdating the ink is termed as a basic update. The decremented amount iswritten to the appropriate ink field (which has been previouslydetermined using Section 31.2.2) in _(M0) The printer verifies thewrite, by reading the signature of the written data, then passing it tothe Test function of the trusted QA Device.

For signature to be valID, the trusted QA Device (A) and ink QA Device(B) must share a common or a variant key i.e B.K_(n1)=A.K_(n2) orB.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID). TABLE 315 Command sequencefor updating the ink-remaining (basic) Seq No Function Parameter 1B.WriteFields VectNum = 0, FieldSelect =Select bits corresponding to theInk fields, The ink field locations should have been determined beforeby using the method in Section ′31.2.2.1 FieldVal= Decrementedink-remaining amount ResultFlag = Pass/Fail 2 A.Random None R_(A) = RL 3B.Read KeyRef = n1, SigOnly = 1, (We only need the signature because wealready know the data) MSelect = _(M0), KeyIdSelect = 0,WordSelectForDesiredM = corresponds to the ink fields written in Seq No1, RE= R_(A) If ResultFlag = Pass then SelectedWordsOfSelectedMs notreturned because [SigOnly] = 1 in Seq 3, R_(B) = R_(L), SIG_(B) = SIGoutRefer to Section 15.3.1. 4 A.Test KeyRef = n2, DataLength = length inwords as per Seq No 1 [MVal] preformatted as per Section 16.1, Data = asper Seq No 1 [MVal] preformatted as per Section 16.1, RE =R_(B), SIGE =SIG_(B) ResultFlag = Pass/Fail31.4.3 Preauthorisation

This section describes the update of logical ink amounts usingpreauthorisation.

The basic preauthorisation sequence is as follows:

-   a. Preauthorise before the first print. Preauthorisation amount    depends on the printer model. Example amounts could be the ink    required for an fully covered A4 page or an A3 page. Value    corresponding to the preauth amount is written to the preauth field    in the ink QA Device.

Note: The preauth value must be correctly interpreted on differentprinter models i.e if a preauthorisation amount of A4 page is set in theink cartridge in printer1(model1), and later the ink cartridge is placedin printer2(model2) with its preauth still set, printer2 must deduct anA4 page worth of ink from ink-remaining amount.

-   b. Print the page.-   c. Write the deducted logical amount to the ink field of the ink QA    Device and validate the write by reading the signature of the ink    field.-   d. Repeat b to c till the last page has been printed.-   e. Clear the preauth amount.-   f. If the power is cut off before the preauth is applied, on startup    apply the preauth amount to the corresponding ink field, by    performing a non authenticated write of the decremented amount and    clear the preauth amount by performing an authenticated write of the    preauth field.    31.4.3.1 Set Up of the Preauth Field

Only a single preauth gield must exist in an Ink QA Device.

Preauth field will consist of a single _(M0) word but can be optionallyextended to two _(M0) words by using a different value of typeattribute. FIG. 388 shows the setup of preauth field's attributes in_(M1).

The preauth field has authenticated ReadWrite access using theINK_USAGE_KEY i.e INK_USAGE_KEY can perform authenticated writes to thisfield. This key or its variant is shared between the ink QA Device andthe printer QA Device to validate any data read from the ink cartridge.For signature to be valID, B.K_(n1)=A.K_(n2) orB.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID), where K_(n1)=INK_USAGE_KEY.The system performs a WriteAuth to the preauth field using this key, toset up the preauth amount, and to clear the preauth amount.

The preauth field is identified by two attributes:

-   -   Type attribute—TYPE_PREAUTH. Refer to Appendix A.    -   KeyId of KeyNum attribute must be the same as the KeyId of the        INK_USAGE_KEY which the printer uses to validate the any data        read from the ink QA Device.

The Preauth field can be applied to a single ink field or multiple inkfields.

31.4.3.2 Preauth Applied to a Single Ink Field

In this case the entire preauth field is used to store the preauthamount and is only linked to one ink field.

31.4.3.3 Preauth Applied to Multiple Ink Fields

Multiple preauth fields can be accommodated in a single M₀ field by ascheme shown in FIG. 388A.

This scheme supports a maximum of 8 ink fields being present in the InkQA Device.

The field in _(M0) is divided into two parts— preauth field select andpreauth amount. Each bit in preauth field select corresponds to a singleink field, and the preauth amount for each ink field is the same. If anink cartridge uses multiple inks which are preauthorised, then each ofthe inks will have a corresponding preauth field bit. Before aparticular ink is used for printing the corresponding preauth field bitis set. The preauth amount field is also set if the previous amount iszero. At finish, the preauth field bit is cleared. If more than one inkis used, the preauth bit for each ink field is set, and at finish eachbit is cleared with last bit clearing the preauth amount as well.

31.4.3.4 Locating Preauth Fields and Determining Preauth Field Value

The preauth field can be located in the same manner as the ink field. Ifthe printer wants to find the preauth field in the ink QA Device, itmust call the function FindFieldNum (see Section 31.2.2.2) withkeyIdRequired=KeyId of Network_OEM_Ink_Usage_Key andtypeRequired=TYPE_PREAUTH. The preauth field value can be read in thesame manner as the ink-remaining amount. This requires using of thefunction GetFieldDataWords(FieldNum,FieldData

, M0,M1) described in Section 27.1.4.14. FieldNum must be set to thevalue returned from function FindFieldNum, which in this case is thefield number of the preauth field. FieldData returns the value of thepreauth field.

31.4.3.5 Command Sequence

The command sequence can be broken up into three parts:

-   -   Start of print sequence.    -   During print sequence.    -   End of print sequence.        31.4.3.5.1 Start of Print Sequence

This sets up the preauth amount before the start of printing.

Table 316 shows the command sequence for start of print sequence. Thefirst Random-Read-Test sequence determines the preauth field in the inkQA Device and its value. The Random-SignM-WriteFieldsAuth sequence, thenwrites to the preauth field the new preauth value. TABLE 316 Updatingthe consumable remaining (preauth) start of print sequence Seq NoFunction Parameters Random-Read-Test sequence to determine the locationof the preauth field in the ink QA Device and its value 1 A.Random NoneR_(A) = RL 2 B.Read KeyRef = n1, SigOnly = 0, WordSelectForDesiredM (for_(M0)) = all 16 words of M0 and all 16 words of M1 MSelect =0x03(indicates M0 and M1), KeyIdSelect = 0xFF (Read all KeyIds),WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all 16 _(M0)words),WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all 16 _(M1)words), RE =R_(A) If ResultFlag = Pass then MWords = SelectedWordsOfSelectedMs asper input [MSelect] and [WordSelectForDesiredM], R_(B) = R_(L), SIG_(B)= SIGout Refer to Section 15.3.1 3 A.Test KeyRef = n2, DataLength =length of MWords in words preformatted as per Section 16.1, Data =MWords as per Seq No 2 preformatted as per Section 16.1, RE =R_(B), SIGE= SIG_(B) ResultFlag = Pass/Fail Random-SignM-Write FieldsAuth sequenceto write the new preauth value 4 B.Random None R_(B1)= RL 5 A.SignMKeyRef = n2, FieldSelect = Select bit corresponding to the Preauthfield, FieldVal = new preauth value, ChipId = ChipId of B, R_(E)= R_(B1)If ResultFlag = Pass then R_(A1) = R_(L) SIG_(A)= SIGout Refer toSection 27.1.3.1 6 B.WriteFieldsAuth KeyRef = n1, FieldSelect= same asSeq 5 [FieldSelect], Field Val= same as Seq 5 [Field Val], RE = R_(A1),SIGE = SIG_(A) ResultFlag = Pass/Fail31.4.3.5.2During Print Sequence

This set of commands are repeated at equal intervals to update logicalink amounts to the ink QA Device during printing.

Table 317 shows the command sequence for the print sequence. TheWriteFields writes the updated value to the ink field. Random-Read-Testreads back the value written and tests whether the value read matchesthe value written. TABLE 317 Updating the consumable remaining (preauth)during print sequence Seq No Function Parameters Write the decrementedink-remaining account. 7 B.WriteFields FieldSelect = Select bitscorresponding to the Ink fields, FieldVal= Decremented ink-remainingamount for a single ink or multiple ink fields as per FieldSelect.ResultFlag = Pass/Fail Random-Read-Test sequence to read and verify theink-remaining amount written 8 A.Random None R_(A) = RL 9 B.Read KeyRef= n1, SigOnly = 1 —(We only need the signature because we already knowthe data), MSelect = 0x01 (only _(M0)), KeyIdSelect = 0,WordSelectForDesiredM = corresponds to the ink fields witten in Seq No7, RE = R_(A) If ResultFlag = Pass then SelectedWordsOfSelectedMs notreturned because [SigOnly] = 1 in Seq 9 R_(B) = R_(L), SIG_(B) = SIGoutRefer to Section 15.3.1. 10 A.Test KeyRef = n2, DataLength = length inwords as per Seq No 7 [MVal] preformatted as per Section 16.1, Data = asper Seq No 7 [MVal] preformatted as per Section 16.1, RE =R_(B), SIGE =SIG_(B) ResultFlag = Pass/Fail31.4.3.5.3 End of Print Sequence

This sequence clears preauth amount before the print sequence iscompleted.

Table 318 shows the command sequence for the end of print sequence.

The preauth field is read using the Random-Read-Test sequence. And thepreauth field is cleared using the Random-SignM-WriteFieldsAuthsequence. TABLE 318 Updating the consumable remaining (preauth) end ofprint sequence Seq No Function Parameters Random-Read-Test sequence toread the preauth field and verify the preauth data 11 A.Random NoneR_(A =) R_(L) 12 B.Read KeyRef = n1, SigOnly = 1, MSelect = 0x01(onlyM0), KeyIdSelect = 0, WordSelectForDesiredM (for _(M0))= Wordscorresponding to the Preauthfield that has been written to in Seq 5[FieldSelect] in Table 317. RE = R_(A) If ResultFlag = Pass then MWords= SelectedWordsOfSelectedMs as per Seq No 12 [MSelect] and[WordSelectForDesiredM], R_(B) = R_(L), SIG_(B) = SIGout Refer toSection 15.3.1 13 A.Test KeyRef = n2, DataLength = length of MWords inwords as per Seq No 12 preformatted as per Section 16.1, Data = MWordsas per Seq No 12 preformatted as per Section 16.1, RE =R_(B), SIGE =SIG_(B) ResultFlag = Pass/Fail Random-SignM-WriteFieldsAuth sequenceclears the preauth field 14 B.Random None R_(B1) =R_(L) 15 A.SignMKeyRef = n2, FieldSelect = Select bit corresponding to Pre authfield,FieldVal = Clear the preauth field, ChipId = ChipId of B, R_(E)= R_(B1)If ResultFlag = Pass then R_(A1)= R_(L) SIG_(A) =SIGout Refer to Section27.1.3.1 16 B.WriteFieldsAuth KeyRef = n1, FieldNum = same as Seq 5[FieldSelect], FieldData = same as Seq 5 [FieldVal], RE= R_(B1), SIGE =SIG_(A) ResultFlag = Pass/Fail31.4.4 Preauthorisation Through the Translate Function

This is performed when the system trusted QA Device doesn't share a keywith the ink QA Device, and uses a translating QA Device to Translate aRead from the ink QA Device, and to Translate a SignM to the ink QADevice.

The basic translate principle involves translating the Read data fromthe untrusted QA Device, to the Test data of the trusted QA Device, andtranslating the SignM data from the trusted QA Device, to theWriteFieldsAuth data of the untrusted QA Device.

For validating signatures using translation:

-   -   The trusted QA Device (A) and the translating QA Device (C) must        share a common or a variant key i.e C.K_(n3)=A.K_(n2) or        C.K₃=FormKeyVariant(A.K_(n2), C.ChipID).    -   The ink QA Device (B) and the translating QA Device (C) must        share a common or a variant key i.e C.K_(m2)=B.K_(n1) or        B.K_(n1)=FormKeyVariant(C.K_(n2), B.ChipID).

Only the start of print sequence is described using Translate. The restof the sequences in preauthorisation can be modified to applytranslation using this example.

Table 319 shows the command sequence for preauth (start of printsequence) using translation. TABLE 319 Preauth(start of print sequence)using translate command Seq No Function ParameterRandom-Read-Random-Translate-Test sequence reads the location of thepreauth field and its value using the translating QA Device C 1 C.RandomNone R_(C) = RL 2 B.Read KeyRef = n1, SigOnly = 0, MSelect =0x03(indicates M0 and M1), KeyIdSelect = 0xFF (Read all KeyIds),WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all 16 _(M0) words),WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all 16 _(M1)words), RE =R_(A) If ResultFlag = Pass then MWords = SelectedWordsOfSelectedMs asper input [MSelect] and [WordSelectForDesiredM], R_(B) = R_(L), SIG_(B)= SIGout Refer to Section 15.3.1 3 A.Random None R_(A)= RL 4 C.TranslateInputKeyRef = n2, DataLength (in words) = length of MWords in words asper Seq No 2 preformatted as per Section n 17.1, Data = MWords asreturned from Seq No 2 preformatted as per Section 17.1, RE= R_(B), SIGE= SIG_(B) OutputKeyRef = n3, RE2 = R_(A) If ResultFlag = Pass thenR_(C1)= RL2, SIG_(C) = SIGOut Refer to FIG. 15.3.1 5 A.Test KeyRef = n2,DataLength = length of MWords in words as per Seq No 2 preformatted asper Section 16.1, Data = MWords as returned from Seq No 2 parameterpreformatted as per Section 16.1, RE =R_(C1), SIGE = SIG_(C) ResultFlag= Pass/Fail Random-SignM-Random-Translate-WriteFieldAuth sequence towrite the new preauth value using the translating QA Device C 6 C.RandomNone R_(C2=) R_(L) 7 A.SignM KeyRef = n2, FieldSelect = Select bitcorresponding to Pre authfield, FieldVal = new value of preauth field,ChipId = ChipId of B, R_(E)= R_(C2) If ResultFlag = Pass then R_(A1 =)R_(L) SIG_(A) = SIGout Refer to Section 27.1.3.1 8 B.Random NoneR_(B1 =) R_(L) 9 C.Translate InputKeyRef = n3, DataLength (in words) =length in words as per Seq 7 [FieldSelect] preformatted as per Section17.1, Data = same as Seq 7 [FieldVal] preformatted as per Section 17.1,RE= R_(A1), SIGE = SIG_(A), OutputKeyRef = n2, RE2 = R_(B1) IfResultFlag = Pass then R_(C3)= R_(L2), SIG_(C) = SIGOut Refer to FIG.15.3.1 10  B.WriteFieldsAuth KeyRef = n1, FieldNum = same as Seq 7[FieldSelect], FieldData = same as Seq 7 [FieldVal], RE= R_(C3), SIGE =SIG_(C) ResultFlag = Pass/Fail,31.5 Upgrading the Printer Parameters

This sequence is performed when a printer's operating parameter isupgraded.

The Parameter Upgrader QA Device stores the upgrade value which iscopied to the operating parameter field of the Printer QA Device, andthe count-remaining associated with upgrade value is decremented by 1 inthe Parameter Upgrader QA Device.

The Parameter Upgrader QA Device output the data and signature onlyafter completing all necessary checks for the upgrade.

31.5.1 Basic

The basic upgrade is used when the Parameter Upgrader QA Device andPrinter QA Device being upgraded share a common key or a variant key i.eB.K_(n1)=A.K_(n2) or B.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID), whereB is the Printer QA Device and A is the Parameter Upgrader QA Device.

Therefore, the messages and their signatures, generated by each of themcan be correctly interpreted by the other.

The transfer sequence is performed usingRandom-Read-Random-XferField-WriteFieldsAuth. Table 320 shows thecommand sequence for a basic upgrade. TABLE 320 Basic upgrade commandsequence Seq No Function ParameterRandom-Read-Random-XferField-WriteFieldsAuth reads M0 and M1of the QADevice being upgraded, Parameter Upgrader QA Device produces the upgradevalue for FieldNumE and Sequence data fields SEQ_1 and SEQ_2, then thesevalues are written to the Printer QA Device. 1 A.Random None R_(A) =R_(L) 2 B.Read KeyRef = n1, SigOnly = 0, MSelect = 3 (indicates _(M0)and _(M1)) KeyIdSelect = 0x00 (no KeyIds required),WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all _(M0)words),WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all _(M1)words), RE =R_(A) If ResultFlag = Pass then MWords = SelectedWordsOfSelectedMs, asper input [MSelect] and [WordSelectForDesiredM], R_(B) = RL,. SIG_(B) =SIGout Refer to Section 15.3.1 3 B.Random None R_(B1) = R_(L) 4A.XferField KeyRef = n2, _(M0)OfExternal = First 16 words of MWords,_(M1)OfExternal = Last 16 words of MWords, ChipId = ChipId of B,FieldNumL= The field storing the upgrade value in the Parameter UpgraderQA Device. The value of this field will be copied to FieldNumE.FieldNumE = The field which will be upgraded in the Printer QA Device.R_(E=) R_(B), R_(E2 =) R_(B1), SIG_(E)= SIG_(B) If ResultFlag = Passthen FieldSelectB1 = FieldSelect − Select bits for FieldNumE and Seqdata fields SEQ_1 and SEQ_2 field, FieldValB1 = FieldVal −New Value forFieldNumE (Copied from FieldNumL of the Parameter Upgrader QA Device)and sequence data fields R_(A1)= R_(L2), SIG_(A) = SIGout = Refer toSection 27.1.3.1. 5 B.WriteFieldsAuth KeyRef = n1, FieldSelect=FieldSelectB1, FieldData = FieldValB1, RE = R_(A1), SIGE = SIG_(A)ResultFlag = Pass/Fail31.5.2 Using the Translate Function

The upgrade through the Translate function is used when the ParameterUpgrader QA Device and the Printer QA Device don't share a key betweenthem. The translating QA Device shares a key with the Parameter UpgraderQA Device and a second key with the Printer QA Device. Therefore themessages and their signatures, generated by the Parameter Upgrader QADevice and the Printer QA Device are translated appropriately by thetranslating QA Device. The translating QA Device validates the Read fromthe Printer QA Device, and translates it for input to the XferFieldfunction. The translating QA Device will validate the output from theXferField function, and then translate it for input to WriteFieldsAuthmessage of the Printer QA Device.

For validating signatures using translation:

-   -   The Parameter Upgrader QA Device (A) and the translating QA        Device (C) must share a common or a variant key i.e        C.K_(n3)=A.K_(n2) or C.K_(n3)=FormKeyVariant(A.K_(n2),        C.ChipID).    -   The Printer QA Device (B) and the translating QA Device (C) must        share a common or a variant key i.e C.K_(n2)=B.K_(n1) or        B.K_(n1)=FormKeyVariant(C.K_(n2), B.ChipID).

Table 321 shows the command sequence for a basic refill usingtranslation. TABLE 321 An upgrade with translate command sequence Seq NoFunction CommandRandom-Read-Random-Translate-Random-XferField-Random-Translate-Random-WriteFieldsAuthreads M0 and M1of the Printer QA Device using the translating QA DeviceC and then does a write of the upgrade value to FieldNumE and newsequence data to the seq data fields SEQ_1 and SEQ_2 field of thePrinter QA Device using the translating QA Device C. 1 C.Random NoneR_(C) = R_(L) 2 B.Read KeyRef = n1, SigOnly = 0, MSelect =0x03(indicates_(M0) and _(M1)), KeyIdSelect = 0x00 (no KeyIds required),WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all _(M0)words),WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all _(M1) words), R_(E) =R_(C) If ResultFlag = Pass then MWords = SelectedWordsOfSelectedMs asper input [MSelect] and [WordSelectForDesiredM], R_(B) = RL, SIG_(B) =SIGout Refer to Section 15.3.1 3 A.Random None R_(A) = R_(L) 4C.Translate InputKeyRef = n2, DataLength = MWords length in words as perSeq No 2 preformatted as per Section 17.1, Data = MWords as returnedfrom Seq No 2 preformatted as per Section 17.1, RE= R_(B), SIGE =SIG_(B), OutputKeyRef = n3, RE2 = R_(A) If ResultFlag = Pass then R_(C1)= RL2, SIG_(C)= SIGOut Refer to Section 17.3.1 5 C.Random None R_(C2)=R_(L) 6 A.XferField KeyRef = n2, _(M0)OfExternal = First 16 words ofMWords, _(M1)OfExternal= Last 16 words of MWords, ChipId = ChipId of B,FieldNumL= The field storing the upgrade value in the Parameter UpgraderQA Device. FieldNumE= The field which will be upgraded in the Printer QADevice. R_(E=) R_(C1), R_(E2 =) R_(C2), SIG_(E)= SIG_(C) If ResultFlag =Pass then FieldSelectB1 = FieldSelect − Select bits for FieldNumE andsequence fields, FieldValB1 = FieldVal − New Value for FieldNumE (Copiedfrom FieldNumL of the Parameter Upgrader QA Device) and sequence fieldsSEQ_1 and SEQ_2, R_(A1)= R_(L2), SIG_(A) = SIGout Refer to Section27.1.3.1 7 B.Random None R_(B1) = R_(L) 8 C.Translate InputKeyRef =n3,DataLength = FieldValB1 length in words as per Seq No 6 preformatted asper Section 17.1, Data = FieldValB1 as returned from Seq No 6preformatted as per Section 17.1, RE= R_(A1), SIGE = SIG_(A),OutputKeyRef= n2, RE2 = R_(B1) If ResultFlag = Pass then R_(C3) =R_(L2), SIG_(C)= SIGOut Refer to Section 17.3.1 19 B.WriteFieldsAuthKeyRef = n1, FieldSelect = FieldSelectB1, FieldVal = FieldValB1, RE =R_(C3), SIGE = SIG_(C) 10 ResultFlag = Pass/Fail31.6 Recovering From a Failed Upgrade

This sequence is performed if the upgrade failed (for e.g Printer QADevice didn't receive the upgrade message correctly and hence didn'tupgrade successfully). The Parameter Upgrader QA Device therefore needsto be rolled back to the previous value before the upgrade. In thiscase, the count-remaining associated with the upgrade value in theParameter Upgrader QA Device is increased by one.

The Parameter Upgrader QA Device checks that the Printer QA Devicedidn't actually receive the message correctly using the StartRollBackfunction. The RollBackField performs further comparisons on sequencefields and FieldNumE of the Printer QA Device to values stored in theXferEntry cache. After performing all checks, the Parameter Upgrader QADevice increments the count remaining field associated with the upgradevalue field by one. Refer to Section 26 and Section 28 for details.

The rollback is started using theRandom-Read-Random-StartRollBack-WriteFieldsAuth and the rollback of theParameter Upgrader QA Device is performed usingRandom-Read-RollBackField sequence.

Table 322 shows the command sequence for a rollback upgrade. Seq NoFunction Command Random-Read-Random-StartRollBack-WriteFieldsAuth startsthe rollback and updates data for the sequence fields. 1 A.Random NoneR_(A) = RL 2 B.Read KeyRef = n1, SigOnly = 0, MSelect =0x03(indicates_(M0) and _(M1)), KeyIdSelect = 0x00 (no KeyIds required),WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all _(M0)words),WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all _(M1)words), R_(E)=R_(A) If ResultFlag = Pass then MWords = SelectedWordsOfSelectedMs asper input [MSelect] and [WordSelectForDesiredM], R_(B) = R_(L), SIG_(B)= SIGout Refer to Section 15.3.1 3 B.Random None R_(B1) = R_(L) 4A.StartRollBack KeyRef = n2, _(M0)OfExternal = First 16 words of MWords,_(M1)OfExternal= Last 16 words of MWords, ChipId = ChipId of B,FieldNumE= The field which was not upgraded in the Printer QA Device,FieldNumL = The upgrade value in the Parameter Upgrader QA Device whichcouldn't be copied to FieldNumE of the Printer QA Device, R_(E)= R_(B),R_(E2) = R_(B1), SIG_(E)= SIG_(B) If ResultFlag = Pass then FieldSelectB= FieldSelect − Select bits for sequence data fields SEQ_1 and SEQ_2,FieldValB = FieldVal − New values for SEQ_1 and SEEQ_2 fields R_(A1) =R_(L2) SIG_(A) = SIGout Refer to Section 27.1.3.1 5 B.WriteFieldsAuthKeyRef = n1, FieldSelect= FieldSelectB, FieldData = FieldValB, RE =R_(A1), SIGE = SIG_(A) ResultFlag = Pass/Fail Random-Read-RollBackFieldperforms a read of the QA Device being upgraded, checks its values areas per Xfer Entry cache, and then adjusts its count-remaining field. 6A.Random None R_(A2) = RL 7 B.Read KeyRef = n1, SigOnly = 0, MSelect=0x03(indicates _(M0) and _(M1)), KeyIdSelect = 0x00 (no KeyIdsrequired), WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all_(M0)words), WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all_(M1)words), R_(E)= R_(A2) If ResultFlag = Pass then MWords =SelectedWordsOfSelectedMs as per input [MSelect] and[WordSelectForDesiredM], R_(B2) = RL, SIG_(B) = SIGout Refer to Section15.3.1 8 A.RollBackField KeyRef = n2, _(M0)OfExternal = First 16 wordsof MWords, _(M1)OfExternal= Last 16 words of MWords, ChipId = ChipId ofB, FieldNumE= The field which was not upgraded in the Printer QA Device,FieldNumL = The upgrade value in the Parameter Upgrader QA Device whichcouldn't be copied to FieldNumE of the Printer QA Device, R_(E) =R_(B2), SIG_(E)= SIG_(B) ResultFlag = Pass/Fail31.7 Re/Filling the Consumable (INK)

This sequence is performed when an ink cartridge is first manufacturedor after all the physical ink has been used, it can be filled orrefilled. The re/fill protocol is used to transfer the logical ink fromthe Ink Refill QA Device to the Ink QA Device in the ink cartridge.

The Ink Refill QA Device stores the amount of logical ink correspondingto the physical ink in the refill station. During the refill, therequired logical amount (corresponding to the physical transfer amount)is transferred from the Ink Refill QA Device to the Ink QA Device.

The Ink Refill QA Device output the transfer data only after completingall necessary checks to ensure that correct logical ink type is beingtransferred e.g Network_OEM1_infrared ink is not transferred toNetwork_OEM2_cyan ink. Refer to the XferAmount command in Section 27.1.

31.7.1 Basic Refill

The basic refill is used when the Ink Refill QA Device and the Ink QADevice share a common key or a variant key i.e B.K_(n1)=A.K_(n2) orB.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID) where B is the Ink QA Deviceand A is the Ink Refill QA Device. Therefore, the messages and theirsignatures, generated by each of them can be correctly interpreted bythe other.

The Xfer Sequence is started usingRandom-Read-Random-StartXfer-WriteAuth and the the Xfer Amount iswritten to the QA Device being refilled usingRandom-Read-Random-XferAmount-WriteFieldsAuth sequence. TABLE 323 thecommand sequence for a basic refill. Seq No Function ParameterRandom-Read-Random-XferAmount-WriteFieldsAuth reads M0 and M1 of the InkQA Device being refilled, produce updated amount for FieldNumE andsequence datat field by calling XferAmount on Ink Refill QA Device, andfinally writing the updated value to Ink QA Device usingWriteFieldsAuth. 1 A.Random None R_(A) = R_(L) 2 B.Read KeyRef = n1,SigOnly = 0, MSelect = 0x03(indicates _(M0) and _(M1)), KeyIdSelect =0x00 (no KeyIds required), WordSelectForDesiredM (for _(M0))= 0xFFFF(Read all _(M0)words), WordSelectForDesiredM (for _(M1))= 0xFFFF(Readall _(M1)words), RE= R_(A) If ResultFlag = Pass then MWords =SelectedWordsOfSelectedMs as per input [MSelect] and[WordSelectForDesiredM], R_(B) = RL, SIG_(B) = SIGout Refer to Section15.3.1 3 B.Random None R_(B1)= R_(L) 4 AxferAmount KeyRef = n2,_(M0)OfExternal = First 16 words of MWords, _(M1)OfExternal= Last 16words of MWords, ChipId = ChipId of B, FieldNumL= ink-remaining field ofthe Ink Refill QA Device, FieldNumE= ink-remaining field of the Ink QADevice, XferValLength = length in words of XferVal XferVal = Value to betransferred from Ink Refill QA Device to Ink QA Device being refilled,R_(E=) R_(B), R_(E2 =) R_(B1), SIG_(E)= SIG_(B) If ResultFlag = Passthen FieldSelectB1 = FieldSelect − Select bits for FieldNumE andsequence data field SEQ_1 and SEQ_2 FieldValB1 = FieldVal − New Valuefor FieldNumE (transferred from FieldNumL of the Ink Refill QA Device)and sequence data fields SEQ_1 and SEQ_2, R_(A1) = R_(L2), SIG_(A)=SIGout Refer to Section 27.1.3.1. 5 B.WriteFieldsAuth KeyRef = n1,FieldSelect= FieldSelectB, FieldData = FieldValB, RE = R_(A1), SIGE =SIG_(A) ResultFlag = Pass/Fail31.7.2 Using the Translate Function

The refill through the Translate function is used when the Ink Refill QADevice and the Ink QA Device don't share a key between them. Thetranslating QA Device shares a key with the Ink Refill QA Device and asecond key with the Ink QA Device. Therefore the messages and theirsignatures, generated by the Ink Refill QA Device and the Ink QA Device,are translated appropriately by the translating QA Device. Thetranslating QA Device validates the Read from the Ink QA Device, andtranslates it for input to the XferAmount function. The translating QADevice will validate the output from the XferAmount function, and thentranslate it for input to WriteFieldsAuth message of the Ink QA Device.

For validating signatures using translation:

-   -   The Ink Refill QA Device (A) and the translating QA Device (C)        must share a common or a variant key i.e C.K_(n3)=A.K_(n2) or        C.K_(n3)=FormKeyVariant(A.K_(n2), C.ChipID).

The Ink Refill QA Device being refilled (B) and the translating QADevice (C) must share a common or a variant key i.e C.K_(n2)=B.K_(n1) orB.K_(n1)=FormKeyVariant(C.K_(n2), B.ChipID). TABLE 324 A basic refillusing translation command sequence Seq No Function CommandRandom-Read-Random-Translate-Random-XferAmount-Random-Translate-Random-WriteFieldsAuth -reads M0 and M1 of the Ink QA Device being refilled using thetranslating QA Device C, produce updated amount for FieldNumE andsequence data field by calling XferAmount on Ink Refill QA Device, andfinally writing the updated value to Ink QA Device using the translatingQA Device. 1 C.Random None R_(C)= R_(L) 2 B.Read KeyRef = n1, SigOnly =0, MSelect =0x03(indicates _(M0) and _(M1)), KeyIdSelect = 0x00 (noKeyIds required), WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all_(M0)words), WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all_(M1)words), R_(E)= R_(C) If ResultFlag = Pass then MWords = SelectedWordsOfSelectedMs as per input [MSelect] and [WordSelectForDesiredM],R_(B) = R_(L), SIG_(B) = SIGout Refer to Section 15.3.1 3 A.Random NoneR_(A) = R_(L) 4 C.Translate InputKeyRef =n2, DataLength = MWords lengthin words as per Seq No 2 preformatted as per Section 17.1, Data = MWordsas returned from Seq No 2 preformatted as per Section 17.1, RE= R_(B),SIGE= SIG_(B), OutputKeyRef = n3, RE2 = R_(A) If ResultFlag = Pass thenR_(C1)= R_(L2), SIG_(C)= SIGOut Refer to Section 17.3.1 5 C.Random NoneR_(L) = R_(C2) 6 A.XferAmount KeyRef = n2, _(M0)OfExternal = First 16words of MWords, _(M1)OfExternal= Last 16 words of MWords, ChipId =ChipId of B, FieldNumL= ink-remaining field of the Ink Refill QA Device,FieldNumE= ink-remaining field of the Ink QA Device, XferValLength =length in words of XferVal XferVal = Value to be transferred from InkRefill QA Device to Ink QA Device being refilled, R_(E)= R_(C1), R_(E2)= R_(C2), SIG_(E)= SIG_(C) If ResultFlag = Pass then FieldSelectB1 =FieldSelect − Select bits for FieldNumE and sequence data field SEQ_1and SEQ_2, FieldValB1 = Field Val −New Value for FieldNumE (transferredfrom FieldNumL of the Ink Refill QA Device) and sequence data fieldsSEQ_1 and SEQ_2, R_(A1)= R_(L2), SIG_(A) = SIGout Refer to Section27.1.3.1 7 B.Random None R_(B1) = R_(L) 8 C.Translate InputKeyRef =n3,DataLength = FieldValB length in words as per Seq No 6 preformatted asper Section 17.1, Data = FieldValB as returned from Seq No 6preformatted as per Section 17.1, RE= R_(A1), SIGE = SIG_(A),OutputKeyRef= n2, RE2 = R_(B1) If ResultFlag = Pass then R_(C3) = RL2,SIG_(C)= SIGOut Refer to Section 17.3.1 9 B.WriteFieldsAuth KeyRef = n1,FieldSelect= FieldSelectB, FieldData = FieldValB, RE = R_(C3), SIGE =SIG_(C) ResultFlag = Pass/Fail31.8 Recovering From a Failed Refill

This sequence is performed if the refill failed (for e.g Ink QA Devicedidn't receive the refill message correctly and hence didn't refillsuccessfully). The Ink Refill QA Device therefore needs to be rolledback to the previous value before the refill.

The Ink Refill QA Device checks that the Ink QA Device didn't actuallyreceive the message correctly using the StartRollBack function. TheRollBackAmount performs further comparisons on sequence data field andFieldNumE of the Ink QA Device, to values stored in the XferEntry cache.After performing all checks, the Ink Refill QA Device adjusts its inkfield to a previous value before the transfer request was processed byit. Refer to Section 26 and Section 28 for details.

The rollback is started using theRandom-Read-Random-StartRollBack-WriteFieldsAuth and the rollback of theInk Refill QA Device is performed using Random-Read-RollBackAmountsequence. TABLE 325 Rollback amount command sequence Seq No FunctionCommand Random-Read-Random-StartRollBack-WriteAuth starts the rollbackand updates data for the sequence data fields SEQ_1 and SEQ_2. 1A.Random None R_(A) = RL 2 B.Read KeyRef = n1, SigOnly = 0, MSelect=0x03(indicates _(M0) and _(M1)), KeyIdSelect = 0x00 (no KeyIdsrequired), WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all_(M0)words), WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all_(M1)words), R_(E)= R_(A) If ResultFlag = Pass then MWords =SelectedWordsOfSelectedMs as per input [MSelect] and[WordSelectForDesiredM], R_(B) = RL, SIG_(B) = SIGout Refer to Section15.3.1 3 B.Random None R_(B1)= R_(L) 4 A.StartRollBack KeyRef = n2,_(M0)OfExternal = First 16 words of MWords, _(M1)OfExternal= Last 16words of MWords, ChipId = ChipId of B, FieldNumL= ink-remaining field ofthe Ink Refill QA Device which will be adjusted to the value before thefailed refill, FieldNumE= ink-remaining field of the Ink QA Device whichfailed to refill, R_(E) = R_(B), R_(E2) = R_(B1) SIG_(E)= SIG_(B) IfResultFlag = Pass then FieldSelectB = FieldSelect − Select bits forsequence data fields- SEQ_1 and SEQ_2, FieldValB = FieldVal − New valuefor sequence data fields SEQ_1 and SEQ_2 R_(A1) = R_(L2), SIG_(A) =SIGout Refer to Section 27.1.3.1. 5 B.WriteFieldsAuth KeyRef = n1,FieldSelect= FieldSelectB in Seq No 4, FieldData = FieldValB in Seq No 4RE = R_(A1), SIGE = SIG_(A) 10 ResultFlag = Pass/FailRandom-Read-RollBackAmount performs a read of the Ink QA Device, checksits values are as per Xfer Entry cache, and then adjusts itsink-remaining field. 11 A.Random None R_(A2) = RL 12 B.Read KeyRef = n1,SigOnly = 0, MSelect =0x03(indicates _(M0) and _(M1)), KeyIdReq = 0 (notrequired), KeyIdSelect = 0x00 (no KeyIds required),WordSelectForDesiredM (for _(M0))= 0xFFFF (Read all _(M0)words),WordSelectForDesiredM (for _(M1))= 0xFFFF(Read all _(M1)words), RE=R_(A2) If ResultFlag = Pass then MWords = SelectedWordsOfSelectedMs asper input [MSelect] and [WordSelectForDesiredM], R_(B2) = R_(L), SIG_(B)= SIGout Refer to Section 15.3.1 13 A.RollBackAmount KeyRef = n2,_(M0)OfExternal = First 16 words of MWords, _(M1)OfExternal= Last 16words of MWords, ChipId = ChipId of B, FieldNumL= ink-remaining field ofInk Refill QA Device which will be adjusted to the value before thefailed refill, FieldNumE= ink-remaining field of Ink QA Device whichfailed to refill, R_(E)= R_(B2), SIG_(E)= SIG_(B) ResultFlag = Pass/Fail31.9 Upgrading/Refilling/Filling the Upgrader

This sequence is performed when a count-remaining field in the ParameterQA Device must be updated or when the ink-remaining field in the InkRefill QA Device requires re/filling.

In case of the Parameter QA Device, another Parameter Upgrader Refill QADevice transfers its count-remaining value to the Parameter QA Deviceusing the transfer sequence described in Section 31.4. Also refer toSection 28.6. This means the count-remaining in the Paramater UpgraderRefill QA Device must be decremented by the same amount that ParameterUpgrader QA Device is incremented by i.e a credit transfer occurs.

In case of the Ink Refill QA Device, another Ink Refill QA Devicetransfers its ink-remaining value to the Ink Refill QA Device using thetransfer sequence described in Section 31.4. Also refer to Section 26.4.This means the logical ink-remaining in the Ink Refill QA Device must bedecremented by the same amount that QA Device being refilled isincremented by i.e a credit transfer occurs.

32 Setting Up for Field Use

This section consists of setting up the data structures in the QA Devicecorrectly for field use. All data structures are first programmed tofactory values. Some of the data structures can then be changed toapplication specific values at the ComCo or the OEM, while others areset to fixed values.

32.1 Instantiating the QA Chip Logical Interface

This sequence is performed when the QA Device is first created. Table326 shows the data structure on final program load. TABLE 326 Datastructure set up during final program load Data Structure Fixed or NameValue Set to Updatable ChipId Unique Identifier for QA Device FixedNumKey Number of keys the QA Device Fixed can hold K_(n) All K_(n) =K_(batch). The K_(batch) is unique Updateable if for a productionbatch^(a). previous value is known KeyId All KeyIds = KeyId ofK_(batch). Updateable along with K_(n). KeyLock All KeyLock = unlockedUpdateable NumVectors Number of memory vectors in the Fixed QA Device._(M0) Set to zeros Updateable _(M0) Set to zeros Updateable M₂₊ Set tozeros Updateable P_(n) Set to ones Updateable R Set to an initial randomvalue Updateable

Each key slot has the same K_(batch). If each key slot had a differentK_(batch), and any one of the K_(batch) was compromised then the entirebatch would be compromised till the K_(batch) was replaced to anotherkey. Hence, each key slot having a different K_(batch) doesn't have anysecurity advantages but requires more keys to be managed.

32.2 Setting Up Application Specific Data

The section defines the sequences for configuring the data structures inthe QA Device to application specific data.

32.2.1 Replacing Keys

The QA Devices are programmed with production batch keys at finalprogram load. The COMCO keys replace the production batch keys beforethe QA Devices are shipped to the ComCo. The ComCo replaces the COMCOkeys to COMCO_OEM when shipping QA Devices to its OEMs. The OEM replacesthe COMCO_OEM to COMCO_OEM app as the QA Devices are placed in inkcartridges or printers.

The replacement occurs without the ComCo or the OEM knowing the actualvalue of the key. The actual value of the keys is only to known to QACo.The ComCo or the OEM is able to perform these replacements because theQACo provides them with a key programming QA Device with keysappropriately set which can generate the necessary messages andsignatures to replace the old key with the new key.

Table 327 shows the command sequence for ReplaceKey. The GetProgramKeygets the new encrypted key from the key programming QA Device, and theencrypted new key is passed into the QA Device whose key is beingreplaced through the ReplaceKey function. Depending on the OldKeyRef andNewKeyRef objects a common encrypted key or a variant encrypted key canbe produced for the ReplaceKey function TABLE 327 ReplaceKey commandsequence Seq No Function Command 1 B.Random None R_(B) = R_(L) 2A.GetProgramKey OldKeyRef = Key Num of the old key. This key must bechanged to the NewKeyRef in the QA Device whose key s being replaced.ChipId = Chip identifier of the QA Device whose key is being replaced.RE= R_(B) KeyLock = Set depending on whether the new key is the finalkey for the key slot or it will be replaced further. NewKeyRef = Key Numof the new key. This key will change the OldKeyRef in the QA Devicewhose key is being replaced. If ResultFlag = Pass then R_(A =) RL,KeyId_(new) = KeyIdOfNewKey EncryptedNewKey = EncryptedKey, SIGA =SIGout Refer to Section 22.2.1. 3 B.ReplaceKey KeyNumToBeReplaced = Oldkey number, the old key could be a common key or a variant key, KeyId =KeyId_(new), EncryptedKey= EncryptedNewKey, RE = RA, SIGE = SIGAResultFlag = Pass/Fail32.2.2 Setting up ReadOnly Data

This sets the permanent functional parameters of the application wherethe QA Device has been placed. These parameters remain unchanged for thelifetime of the QA Device. In case of the ink cartridge such parametersare colour and viscosity of the ink. These values are written to M₂₊memory vectors using the WriteM1+ function, and its permissions are setto ReadOnly by SetPerm function. These values are typically set at theOEM.

Table 328 shows the command sequence for setting up ReadOnly data. TABLE328 ReadOnly data setup command sequence Seq No Function Command 1B.WriteM1+ VectNum = 2 or 3, WordSelect = the selected words to bewritten, MVal = words corresponding to word select starting from LSWResultFlag = Pass/Fail 2 B.SetPerm (VectNum =same as Seq No 1parameter[VectNum], PermVal =same as Seq No 1 parameter [WordSelect]) IfResultFlag = Pass then CurrPerm = NewPerm Current permission value afterapplying PermVal

In case of the SBR4320, the values written to M₂₊ memory vectors iswrite-once only i.e they are set to ReadOnly as soon as they are writtento once, therefore the command sequence consists only of Seq No 1 inTable 329.

32.2.3 Defining Fields in _(M0)

The QACo must determine the field definitions for M0 depending on theapplication of the QA Device. These field definitions will consist ofthe following:

-   -   Number of fields and the size of each field.    -   The Type attribute of each field.    -   The access permission for each field.

Following fields have been presently defined in an ink QA Device:

-   -   ink-remaining field. See Section 26 for details.

-   Preauthorisation field. See Section 31.4.3 for details.    -   Sequence data fields SEQ_(—)1 and SEQ_(—)2. See Section 26 for        details.

Following fields have been presently defined in a printer QA Device:

-   -   Operating parameter field. See Section 28 for details.    -   Sequence data fields SEQ_(—)1 and SEQ_(—)2. See Section 26 for        details.

After the field definitions are determined, they are formatted as perSection 8.1.1.4. These formatted values are then written to _(M1) usinga WriteM1+ function. TABLE 329 Defining M0 fields command sequenceSequence No Function Command 1 B.WriteM1+ VectNum = 1, WordSelect = Theselected words corresponding to the attribute field/fields of _(M0),MVal = words corresponding to word select starting from LSW) ResultFlag= Pass/Fail32.2.4 Writing Values to Fields in _(M0)

The writing of _(M0) fields for an Ink QA Device will typically occurwhen the ink cartridge is filled with physical ink for the first time,and the equivalent logical ink is written to the Ink QA Device. Refer toSection 31.7 for details.

The writing of _(M0) fields for a Printer QA Device will typically occurwhen the printer parameters are written for the first time. Theprocedure for writing of a printer parameter for the first time orupgrading a printer parameters is exactly the same. Refer to Section31.5 for details.

Before any value is written to a field, the key slot containing the keywhich has authenticated ReadWrite access to the field must be locked.

Both Ink QA Device and Printer QA Device has a sequence data fieldsSEQ_(—)1 and SEQ_(—)2 as described in Section 27. These two fields mustbe initialised to 1xFFFFFFFF, refer to Section 27 for details.

The Ink QA Device/Printer QA Device and the trusted QA Device writing toit, share the sequence key or a variant sequence key between them i.eB.K_(n1)=A.K_(n2) or B.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID), whereB is the Ink QA Device/Printer QA Device and A is the trusted QA Device.The command sequence used is described in Table 330. TABLE 330 Commandsequence for writing sequence data fields to the QA Devices. Sequence NoFunction Parameters 1 B.Random R_(B) = RL 2 A.SignM KeyRef = n2,FieldSelect =Select bit correponding to SEQ_1 and SEQ-2 FieldVal = bothfields set 0xFFFFFFFF. Refer to Section 31.4.3.3 ChipId = ChipId of B,R_(E) = R_(B) If ResultFlag = Pass then R_(A) = R_(L) SIG_(A) =SIGoutRefer to Section 27.1.3.1 3 B.WriteFieldsAuth KeyRef = n1, FieldSelect =same as Seq 2[FieldSelect], FieldVal = same as Seq 2[FieldVal], RE=R_(A), SIGE = SIG_(A) ResultFlag = Pass/Fail32.3 Setting Up the Upgrading QA Device

The upgrading QA Device must be set up either as an Ink Refill QA Deviceor as a Parameter Upgrader QA Device.

Each upgrading QA Device must go through the following set up:

-   -   The upgrading QA Device must be set to factory defaults. Refer        to Section 32.1. At the end of this process the upgrading QA        Device is either an Ink Refill QA Device or a Parameter Upgrader        QA Device with production batch keys and M0 fields set to        deafult.    -   The upgrading QA Device must be programmed with the appropriate        keys and upgrade data before it can start upgrading other QA        Devices. Following must be performed on each upgrade QA Device:    -   a. The upgrading QA Device must be programmed with the        appropriate keys required to upgrade other QA Devices and to        upgrade itself when necessary.    -   b. The M0 fields must be correctly defined and set in M1.        -   For a Ink Refill QA Device the ink-remaining field must be            defined and set. For a printer upgrade QA Device the upgrade            value field and the count-remaining field must be defined            and set. All upgrade QA Devices must also have a sequence            datat fields SEQ_(—)1 and SEQ_(—)2 which are used to upgrade            the upgrading QA Device itself.    -   c. Finally, M0 fields defined in b must be written with        appropriate values so that the upgrade QA Device can perform        upgrades.        -   An Ink Refill QA Device will typically store the logical ink            equivalent to the physical ink in a refill station, hence            the Ink Refill QA Device's ink-remaining field must be            written with the equivalent logical ink amount.

For a Parameter Upgrader QA Device the upgrade value field and thecount-remaining field must be written. The upgrade value depends on thetype of upgrade the Parameter Upgrader QA Device can perform i.e oneParameter Upgrader QA Device can upgrade to 10 ppm (pages per minute)while another Parameter Upgrader QA Device can upgrade to 5 ppm. Thecount-remaining is the number of times the Parameter Upgrader QA Deviceis permitted to write the associated upgrade value to other QA Devices.The count-remaining field must be written to a positive non-zero valuefor the Parameter Upgrader QA Device to perform successful upgrades.Refer to Section 32.3.1 and Section 32.3.2 for details.

32.3.1 Setting Up the Ink Refill QA Device

32.3.1.1 Setting Up the Keys

The Ink Refill QA DeviceQA Device could be transferring ink betweenpeers or transferring ink down the heirachy, accordingly the peer topeer Ink Refill QA Device has two keys (fill/refill key and sequencekey) as described in Section 27, and a Ink Refill QA Device transferringdown the heirachy has three keys (fill/refill key, transfer key andsequence key). These keys must be programmed into the Ink Refill QADevice using the sequence described in Section 32.2.1.

The Key Programming QA Device must be programmed with the appropriateproduction batch keys, and the fill/refill, transfer key and sequencekey

The GetProgramKey function is called on the Key Programming QA Devicewith OldKeyRef (OldKeyRef—refer to Section 32.2.1) pointing to aproduction batch key, and the NewKeyRef (NewKeyRef—refer to Section32.2.1) pointing to either a fill/refill key or a transfer key or asequence key. The outputs from the GetProgramKey (signature andencrypted New Key) is passed in to ReplaceKey function of the Ink RefillQA Device.

The GetProgramKey function must be called (on the Key Programming QADevice) for replacing each of the production batch keys in the InkRefill QA Device. The output of the GetProgramKey will be passed in tothe ReplaceKey function called on the Ink Refill QA Device. Thesuccessful processing of the ReplaceKey function will replace an oldkey(production keys) to a corresponding new key (either a fill/refillkey or a transfer key or a sequence key).

32.3.1.2 Setting Up the M0 Field Information in _(M1)

The ink-remaining field and the sequence data fields SEQ_(—)1 andSEQ_(—)2 must be defined and set in the Ink Refill QA Device using thesequence described in Section 32.2.3.

32.3.1.3 Transferring Ink Amounts

Finally, the logical ink amounts are transferred to the ink-remainingfield using the sequence described in Section 31.7.

The QACo will transfer to the ComCo Ink Refill QA Device at the top ofthe heirachy using the command sequence in Table 331.

For a successful transfer from QACo to ComCo, ComCo and QACo must sharea common key or a variant key be i.e ComCo.K_(n1)=QACo.K_(n2) orComCo.K_(n1)=FormKeyVariant(QACo.K_(n2), ComCo.ChipID)K_(n1) is thefill/refill key for the ComCo refill QA Device. TABLE 331 Commandsequence for writing ink-remaining amounts to the highest QA Device inthe heirachy. Sequence No Function Parameters 1 B.Random R_(B) = RL 2A.SignM KeyRef = n2, FieldSelect =Select bit correponding to theink-remaining field, FieldVal = Ink amount to be transferred, Refer toSection 31.4.3.3 ChipId = ChipId of B, R_(E) = R_(B) If ResultFlag =Pass then R_(A)= R_(L) SIG_(A) =SIGout Refer to Section 27.1.3.1 3B.WriteFieldsAuth KeyRef = n1, FieldSelect = same as Seq 2[FieldSelect],FieldVal = same as Seq 2[FieldVal], RE= R_(A), SIGE = SIG_(A) ResultFlag= Pass/Fail32.3.1.4 Setting Up Sequence Data Fields

The Ink Refill QA Device has sequence data fields SEQ_(—)1 and SEQ_(—)2(as described in Section 27) because its ink-remaining fields can berefilled as well. These two fields must be initialised to 1xFFFFFFFF,refer to Section 27 for details.

The Ink Refill QA Device and the trusted QA Device writing to it, sharethe sequence key or a variant sequence key between them i.eB.K_(n1)=A.K_(n2) or B.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID), whereB is the Ink Refill QA Device and A is the trusted QA Device. Thecommand sequence used is described in Table 331.

32.3.2 Setting Up the Parameter Upgrader QA Device

32.3.2.1 Setting Up the Keys

The Parameter Upgrader QA Device could be transferring upgrades betweenpeers or transferring upgrades down the heirachy, accordingly the peerto peer Parameter Upgrader QA Device has three keys (write-parameterkey, fill/refill key and sequence key) as described in Section 28.6 andSection 26, and a Parameter Upgrader QA Device transferring down theheirachy has four keys (write-parameter key, fill/refill key, transferkey and sequence Key). These keys must be programmed into the ParameterUpgrader QA Device using the sequence described in Section 32.2.1.

The Key Programming QA Device must be programmed with the appropriateproduction batch keys, and write-parameter key, fill/refill key,transfer key and sequence key

The GetProgramKey function is called on the Key Programming QA Devicewith OldKeyRef (OldKeyRef—refer to Section 32.2.1) pointing to aproduction batch key, and the NewKeyRef (NewKeyRef—refer to Section32.2.1) pointing to either a write-parameter key, or a fill/refill key,or a transfer key, or a sequence key. The outputs from the GetProgramKey(signature and encrypted New Key) is passed in to ReplaceKey function ofthe Parameter Upgrader QA Device.

32.3.2.2 Setting Up the M0 Field in _(M1)

The upgrade value field and the count-remaining field must be definedand set in the upgrade QA Device using the sequence described in Section32.2.3.

32.3.2.3 Writing Upgrade Value to the Upgrade Field

The upgrade value is written to upgrade field using the write-parameterkey. The upgrade QA Device and the trusted QA Device writing to it,share the write-parameter key or a variant write-parameter key betweenthem i.e B.K_(n1)=A.K_(n2) or B.K_(n1)=FormKeyVariant(A.K_(n2),B.ChipID), where B is the upgrade QA Device and A is the trusted QADevice. The command sequence used is described in Table 331.

32.3.2.4 Transferring Count-Remaining Amounts

Finally, the logical count-remaining amounts are transferred to thecount-remaining field using the sequence described in Section 31.7.

The QACo will also transfer to the ComCo's upgrade QA Device using thecommand sequence in Table 331.

For a successful transfer from QACo to ComCo, ComCo and QACo must sharea common key or a variant key be i.e ComCo.K_(n1)=QACo.K_(n2) orComCo.K_(n1)=FormKeyVariant(QACo.K_(n2),ComCo.ChipID). K_(n1) is thefill/refill key for the ComCo upgrade QA Device.

32.3.2.5 Setting Up Sequence Data Fields

The Parameter Upgrader QA Device has sequence data fields SEQ_(—)1 andSEQ_(—)2 (as described in Section 27) because its count-remaining fieldscan be refilled as well. These two fields must be initialised to1xFFFFFFFF, refer to Section 27 for details.

The Parameter Upgrader QA Device and the trusted QA Device writing toit, share the sequence key or a variant sequence key between them i.eB.K_(n1)=A.K_(n2) or B.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID), whereB is the Parameter Upgrader QA Device and A is the trusted QA Device.The command sequence used is described in Table 331.

32.4 Setting Up the Key Programmer

The key programming QA Device is set up to replace keys in other QADevices.

Each key programming QA Device must go through the following set up:

-   -   The key programming QA Device must be instantiated to factory        defaults. Refer to Section 32.1. At the end of instantiation the        key programming QA Device has production batch keys and no key        replacement data.    -   The key programming QA Device must be programmed with the        appropriate keys and key replacement map before it can start to        replace keys in other QA Devices.        32.4.1 Setting Up the Keys

The key programming QA Device must be programmed with the keyreplacement map key. The key replacement map key is described in detailsin Section 24.

The key programming QA Device must programmed with the old and new keysfor the QA Devices it is going to perform key replacement on.

Each of the keys is set in the key programming QA Device using thesequence described in Section 32.2.1.

32.4.2 Setting Up Key Replacement Map Field Information

First the key replacement map field information is worked out as perSection 24.1. This field information is set in M1 as per the sequencedescribed Section 32.2.3.

32.4.3 Setting Up Key Replacement Map

Finally, the key replacement map field must be written with the validmapping using the key replacement map key. The key programming QA Deviceand the trusted QA Device writing to it must share the key replacementmap key or a variant of the key replacement map key between them.

For a successful write of the key replacement map B.K_(n1)=A.K_(n2) orB.K_(n1)=FormKeyVariant(A.K_(n2), B.ChipID), where B is the keyreplacement QA Device and A is the trusted QA Device. The commandsequence used is described in Table 331.

Appendix A: Field Types

Table 332 lists the field types that are specifically required by the QAChip Logical Interface and therefore apply across all applications.Additional field types are application specific, and are defined in therelevant application documentation. TABLE 332 Predefined Field TypesValue Type Description 0x0000 0 Non-initialised (default value afterfinal program load) 0x0001 TYPE_PREAUTH Defines a preauth field in anInk QA Device 0x0002 TYPE_COUNT_REMAINING Defines a countRemaining fieldin an Parameter Upgrader QA Device 0x0003 TYPE_SEQ_1 Defines a sequencedata field SEQ_1 in an Ink QA Device or in a Printer QA Device or in anupgrader QA Device 0x0004 TYPE_SEQ_2 Defines a sequence data fieldsSEQ_2 in an Ink QA Device or in a Printer QA Device or in an upgrader QADevice 0x0005 TYPE_KEY_MAP Defines a key replacement map in a KeyProgrammer QA Device 0x0006 reserved reserved for future use and above

Appendix B: Key and field definition for different QA Devices

B.1 Parameter Upgrader QA Device

B.1.1 Peer to Peer QA Device TABLE 333 Key definitions for a peer topeer Parameter Upgrader QA Device Key Name Purpose Fill/refill This keyhas is used for upgrading Key count-remaining values when the upgrade QADevice is upgraded by another upgrade QA Device and is also used todecrement the count-remaining when upgrading other QA Devices. SequenceThis key is used to initialise sequence Key data fields SEQ_1 and SEQ_2to 0xFFFFFFF. Write This key is used to write the upgrade Parametervalue to the Parameter Upgrader QA Device. Key

TABLE 334 Field definitions for a peer to peer Parameter Upgrader QADevice Field Attrinutes Field A^(a) NA^(b) EndPos Name Purpose TypeKeyNum RW RW KPerms^(c) (Size) Count The field storesTYPE_COUNT_REMAINING SN^(f) fill/refill key 1 0 KPerms[KN^(e)] = 1Depends Remaining the number of Rest are 0 on the times the maximumParameter number Upgrader QA of Device is upgrades permitted to thatupgrade a printer can be QA Device. stored. Upgrade This stores the Mustdefine the type of the SN^(f) write-parameter 1 0 KPerms[KN^(e)] = 0 Setas per Value value that is upgrade value key Rest are 0 upgrade copiedfrom the i.e TYPE_PRINT_SPEED^(d) as well value. Parameter Upgrader QADevice to the field being upgraded on the printer QA Device during theupgrade SEQ_1 This field holds TYPE_SEQ_1 SN^(f) sequence key 1 0KPerms[KN^(e)] = 0 Typically the data for KPerms[fill/ 32 bit. sequencedata refill^(g)] = 1 field SEQ_1 Rest are 0 when the as well. ParameterUpgrader QA Device is being upgraded by another Parameter UpgraderRefill QA Device. SEQ_2 This field holds TYPE_SEQ_2 SN^(f) sequence key1 0 KPerms[KN^(e)] = 0 Typically the data for KPerms[fill/ 32 bit.sequence data refill^(g)] = 1 fieldsSEQ_2 Rest are 0 when the as well.Parameter Upgrader QA Device is being upgraded by another ParameterUpgrader Refill QA Device.^(a)Authenticated ReadWrite permission^(b)Non-authenticated ReadWrite permission^(c)KeyPerms^(d)This is a sample type only^(e)KeyNum^(f)Key Slot Number^(g)Fill/Refill key has authenticated decrement-only permission to thesequence data fieldsB.1.2 Heirarchical Transfer QA Device

Key Definitions TABLE 335 Key definitions for a Parameter Upgrader QADevice (transferring down the heirachy) Key Name Purpose Transfer Thiskey is used to decrement the count-remaining when Key upgrading other QADevices. Fill/refill This key has is used for upgrading count-remainingvalues Key when the Parameter Upgrader QA Device is upgraded by anotherParameter Upgrader QA Device Refill QA Device. Sequence This key is usedto initialise sequence data fields SEQ_1 and Key SEQ_2 to 0xFFFFFFF.Write This key is used to write the upgrade value to the ParameterParameter Upgrader QA Device. Key

Field Definitions TABLE 336 Field definitions for Parameter Upgrader QADevice transferring down the hierachy Field Attrinutes Field A^(a)NA^(b) EndPos Name Purpose Type KeyNum RW RW KPerms^(c) (Size) Count Thefield stores the TYPE_COUNT_REMAINING SN^(f) fill/refill 1 0KPerms[KN^(e)] = 0 Depends Remaining number of times key KPerms[Transferon the Parameter Key] = 1 the Upgrader QA Rest are 0 maximum Device ispermitted number to upgrade a printer of QA Device. upgrades that can bestored. Upgrade This stores the Must define the type of SN^(f) write- 10 KeyPerms[KN^(e)] = 0 Set Value value that is the parameter Rest are 0as copied from the upgrade value key per Parameter i.e upgrade UpgraderQA TYPE_PRINT_SPEED^(d) value. Device to the field being upgraded on theprinter QA Device during the upgrade SEQ_1 This field holds TYPE_SEQ_1SN^(f) sequence 1 0 KPerms[KN^(e)] = 0 Typically the data for keyKPerms[fill/refill^(g)] = 1 32 bit. sequence data Rest are 0 as fieldsSEQ_1 well. when the Parameter Upgrader QA Device is being upgraded byanother Parameter Upgrader Refill QA Device. SEQ_2 This field holdsTYPE_SEQ_2 SN^(f) sequence 1 0 KPerms[KN^(e)] = 0 Typically the data forkey KPerms[fill/refill^(g)] = 1 32 bit. sequence data Rest are 0 asfields SEQ_2 well. when the Parameter Upgrader QA Device is beingupgraded by another Parameter Upgrader Refill QA Device.^(a)Authenticated ReadWrite permission^(b)Non-authenticated ReadWrite permission^(c)KeyPerms^(d)This is a sample type only^(e)KeyNum^(f)Key Slot Number^(g)Fill/Refill key has authenticated decrement-only permission to thesequence data fieldsB.2 Ink Refill QA DeviceB.2.1 Peer to Peer QA Device

Key Definitions TABLE 337 Key definitions for a peer to peer Ink RefillQA Device Key Name Purpose Fill/refill This key has is used forfilling/refilling ink-remaining values Key when the Ink Refill QA Deviceis upgraded by another Ink Refill QA Device and is also used todecrement from the ink-remaining when transferring ink to other QADevices (typically Ink QA Device). Sequence This key is used toinitialise sequence data fields SEQ_1 and Key SEQ_2 to 0xFFFFFFF.

Field Definitions TABLE 338 Field definitions for a peer to peer InkRefill QA Device Field Attrinutes Field Key A^(a) NA^(b) Name PurposeType Num RW RW KeyPerms^(c) EndPos(Size) Ink The field stores the Mustdefine the SN^(f) fill/refill 1 1 KeyPerms[KN^(e)] = 1 Depends onRemaining amount of type of Ink key Rest are 0 the logical ink-remainingin e.g maximum the TYPE_HIGHQUALITY_BLACK_INK^(d) amount ink refill QADevice. of ink that can be stored and the storage resolution i.e in picolitres or in micro litres. SEQ_1 This field holds the data TYPE_SEQ_1SN^(f) sequence 1 0 KPerms[KN^(e)] = 0 Typically 32 for keyKPerms[fill/refill^(g)] = 1 bit. sequence data field well. SEQ_1 whenthe Ink Refill QA Device is being filled/refilled by another Ink RefillQA Device. SEQ_2 This field holds the data TYPE_SEQ_2 SN^(f) sequence 10 KPerms[KN^(e)] = 0 Typically 32 for key KPerms[fill/refill^(g)] = 1bit. sequence data field Rest are 0 as SEQ_2 well. when the Ink RefillQA Device is being filled/refilled by another Ink Refill QA Device.^(a)Authenticated ReadWrite permission^(b)Non-authenticated ReadWrite permission^(c)Decrement-Only For Keys^(d)This is a sample type only^(e)KeyNum^(f)Key Slot Number^(g)Fill/Refill key has authenticated decrement-only permission to thesequence data fieldsB.2.2 Heirarchical Transfer QA Device

Key Definitions TABLE 339 Key definitions for a ink refill QA Device(transferring down the heirachy) Key Name Purpose Transfer This key isused to decrement from the ink-remaining when Key transferring ink toother QA Devices. Fill/refill This key has is used for filling/refillingink-remaining values Key when the Ink Refill QA Device is upgraded byanother Ink Refill QA Device. Sequence This key is used to initialisesequence data fields SEQ_1 and Key SEQ_2 to 0xFFFFFFF.

Field Definitions TABLE 340 Field definitions for a Ink Refill QA Device(transferring down the heirachy) Field Attrinutes Field A^(a) NA^(b)EndPos Name Purpose Type KeyNum RW RW KeyPerms^(c) (Size) Ink The fieldstores the Must define the type SN^(f) fill/ 1 0 KPerms[KN^(e)] = 0Depends Remaining amount of Ink refill key KPerms[Transfer on the oflogical ink- e.g- Key] = 1 maximum remaining in theTYPE_HIGHQUALITY_BLACK_INK^(d) Rest are 0 amount Ink Refill QA of inkDevice. that can be stored and the storage resolution i.e in pico litresor in micro litres. SEQ_1 This field holds the TYPE_SEQ_1 SN^(f) 1 0KPerms[KN^(e)] = 0 Typically data for sequence KPerms[fill/refill^(g)] =1 32 bit. sequence data field key Rest are 0. SEQ_1 when the Ink RefillQA Device is being filled/refilled by another Ink Refill QA Device.SEQ_2 This field holds the TYPE_SEQ_2 SN^(f) 1 0 KPerms[KN^(e)] = 0Typically data for sequence KPerms[fill/refill^(g)] = 1 32 bit. sequencedata field key Rest are 0. SEQ_2 when the Ink Refill QA Device is beingfilled/refilled by another Ink Refill QA Device.^(a)Authenticated ReadWrite permission^(b)Non-authenticated ReadWrite permission^(c)KeyPerms^(d)This is a sample type only^(e)KeyNum^(f)Key Slot Number^(g)Fill/Refill key has authenticated decrement-only permission to thesequence data fieldsB.3 Key Programming QA Device

B.3.1 Key Definitions TABLE 341 Key definitions for a Key Programming QADevice Key Name Purpose Key This key is used to write the keyreplacement map. replacement map Key Old Keys These are the old keys ofthe QA Device whose keys will be replaced by The Key Programming QADevice. New Keys These are the new keys of the QA Device whose old keyswill be replaced by the Key Programming QA Device.

B.3.2 Field Definitions TABLE 342 Field definitions for a keyreplacement QA Device Field Attrinutes Field A^(a) NA^(b) EndPos NamePurpose Type KeyNum RW RW KPerms^(c) (Size) Key This defines theTYPE_KEY_MAP Key Replacement 1 0 KPerms[KN^(d)] = 0 2 replacementmapping Map key Rest are 0 words map between the old (64 key and the newbits) key for the QA Device whose old key will be replaced by the newkey.^(a)Authenticated ReadWrite permission^(b)Non-authenticated ReadWrite permission^(c)KeyPerms^(d)KeyNumB.4 Ink QA Device

B.4.1 Key Definitions TABLE 343 Key definitions for a Ink QA Device KeyName Purpose Fill/refill This key is used for fill/refillingink-remaining amount in the Key ink QA Device. Ink usage This key isverifying the data read from the ink QA Device Key and for writingpreauth data. Sequence This key is used to initialise sequence datafields SEQ_1 and Key SEQ_2 to 0xFFFFFFF.

B.4.2 Field Definitions TABLE 344 Field definitions for a Ink QA DeviceField Attrinutes Field Key A^(a) NA^(b) EndPos Name Purpose Type Num RWRW KPerms^(c) (Size) Ink The amount of logical Must define the typeSN^(f) 1 1 KPerms[KN^(e)] = 1 Depends Remaining ink-remaining in the ofInk fill/refill Rest are 0 on the ink QA Device. i.e key maximum Morethan one ink- TYPE_HQ_BLACK_INK^(d) amount remaining field may be of inkthat present depending on can be the number of physical stored inksstored in the ink and cartridge. the storage resolution i.e in picolitres or in micro litres. Preauth This field defines the TYPE_PREAUTHSN^(f) ink 0 1 KPerms[KN^(e)] = 0 Depends preauth value. usage key Restare 0 on preauth amount. Typically 32 bits, may be 64 bits to accomodatelarger preauth amounts. SEQ_1 This field holds the TYPE_SEQ_1 SN^(f) 1 0KPerms[KN^(e)] = 0 Typically data for sequence KPerms[fill/refill^(g)] =1 32 bit. sequence data field key Rest are 0. SEQ_1 when the Ink QADevice is being filled/refilled by a Ink Refill QA Device. SEQ_2 Thisfield holds the TYPE_SEQ_2 SN^(f) 1 0 KPerms[KN^(e)] = 0 Typically datafor sequence KPerms[fill/refill^(g)] = 1 32 bit. sequence data field keyRest are 0. SEQ_2 when the Ink QA Device is being filled/refilled byanother Ink Refill QA Device.^(a)Authenticated ReadWrite permission^(b)Non-authenticated ReadWrite permission^(c)KeyPerms^(d)This is a sample type only^(e)KeyNum^(f)Key Slot Number^(g)Fill/Refill key has authenticated decrement-only permission to thesequence data fieldsB.5 Printer QA Device

B.5.1 Key Definition TABLE 345 Key definitions for a Printer QA DeviceKey Name Purpose Upgrade key This key is used for writing/upgrading thefunctional (fill/refill parameter. key) Ink usage This key is verifyingthe data read from the Ink QA Device. Key Sequence This key is used toinitialise sequence data fields SEQ_1 Key and SEQ_2 to 0xFFFFFFF. PECID/This key is used to verify the data read from the printer QA SOPECIDDevice. This key is unique to each printer. Also used to Key translatedata from the ink QA Device to the trusted printer system QA Device.

B.5.2 Field Definition TABLE 346 Field definitions for a Printer QADevice Field Attrinutes Field Key A^(a) NA^(b) EndPos Name Purpose TypeNum RW RW KPerms^(c) (Size) Functional The field stores an Must definethe type of SN^(f) 1 0 KPerms[KN^(e)] = 0 Set as parameter upgradeablefunctional print speed fill/refill Rest are 0 per parameter. i.e keyfunctional More than one TYPE_PRINT_SPEED^(d) parameter. functionalparameter can be stored in the printer QA Device. SEQ_1 This field holdsthe TYPE_SEQ_1 SN^(f) 1 0 KPerms[KN^(e)] = 0 Typically data for sequenceKPerms[fill/refill^(g)] = 1 32 sequence data field key Rest are 0. bit.SEQ_1 when the Printer QA Device is being filled/refilled by a ParameterUpgrader QA Device. SEQ_2 This field holds the TYPE_SEQ_2 SN^(f) 1 0KPerms[KN^(e)] = 0 Typically data for sequence KPerms[fill/refill^(g)] =1 32 sequence data field key Rest are 0. bit. SEQ_2 when the Printer QADevice is being filled/refilled by another Parameter Upgrader QA Device.^(a)Authenticated ReadWrite permission^(b)Non-authenticated ReadWrite permission^(c)KeyPerms^(d)This is a sample type only^(e)KeyNum^(f)Key Slot Number^(g)Fill/Refill key has authenticated decrement-only permission to thesequence data fieldsB.6 Trusted Printer System QA Device

B.6.1 Key Definition TABLE 347 Key Name Purpose PECID/SOPECID This keyis used to verify the data read from Key the printer QA Device. This keyis unique to each printer. This key is also used for verifyingtranslated data from the ink QA Device.Introduction1 Background

This document describes a QA Chip that can be used to hold containsauthentication keys together with circuitry specially designed toprevent copying. The chip is manufactured using a standard Flash memorymanufacturing process, and is low cost enough to be included inconsumables such as ink and toner cartridges. The implementation isapproximately 1 mm² in a 0.25 micron flash process, and has an expecteddie manufacturing cost of approximately 10 cents in 2003.

Once programmed, the QA Chips as described here are compliant with theNSA export guidelines since they do not constitute a strong encryptiondevice. They can therefore be practically manufactured in the USA (andexported) or anywhere else in the world.

Note that although the QA Chip is designed for use in authenticationsystems, it is microcoded, and can therefore be programmed for a varietyof applications.

2 Nomenclature

The following symbolic nomenclature is used throughout this document:TABLE 348 Summary of symbolic nomenclature Symbol Description F[X]Function F, taking a single parameter X F[X, Y] Function F, taking twoparameters, X and Y X|Y X concatenated with Y X

Y Bitwise X AND Y X

Y Bitwise X OR Y (inclusive-OR) X ⊕ Y Bitwise X XOR Y (exclusive-OR)

X Bitwise NOT X (complement) X

Y X is assigned the value Y X

{Y, Z} The domain of assignment inputs to X is Y and Z X = Y X is equalto Y X ≠ Y X is not equal to Y

X Decrement X by 1 (floor 0)

X Increment X by 1 (modulo register length) Erase X Erase Flash memoryregister X SetBits[X, Y] Set the bits of the Flash memory register Xbased on Y Z

ShiftRight[X, Shift register X right one bit position, taking input Y]bit from Y and placing the output bit in Z3 Pseudocode3.1 Asynchronous

The following pseudocode:

var=expression

means the var signal or output is equal to the evaluation of theexpression.

3.2 Synchronous

The following pseudocode:

var←expression

means the var register is assigned the result of evaluating theexpression during this cycle.

3.3 Expression

Expressions are defined using the nomenclature in Table 348 above.Therefore:

var=(a=b)

is interpreted as the var signal is 1 if a is equal to b, and 0otherwise.

4 Diagrams

Black lines are used to denote data, while red lines are used to denote1-bit control-signal lines.

Logical Interface

5 Introduction

The QA Chip has a physical and a logical external interface. Thephysical interface defines how the QA Chip can be connected to aphysical System, while the logical interface determines how that Systemcan communicate with the QA ChIP. This section deals with the logicalinterface.

5.1 Operating Modes

The QA Chip has four operating modes—Idle Mode, Program Mode, Trim Modeand Active Mode.

-   -   Active Mode is entered on power-on Reset when the fuse has been        blown, and whenever a specific authentication command arrives        from the System. Program code is only executed in Active Mode.        When the reset program code has finished, or the results of the        command have been returned to the System, the chip enters Idle        Mode to wait for the next instruction.    -   Idle Mode is used to allow the chip to wait for the next        instruction from the System.    -   Trim Mode is used to determine the clock speed of the chip and        to trim the frequency during the initial programming stage of        the chip (when Flash memory is garbage). The clock frequency        must be trimmed via Trim Mode before Program Mode is used to        store the program code.    -   Program Mode is used to load up the operating program code, and        is required because the operating program code is stored in        Flash memory instead of ROM (for security reasons).

Apart from while the QA Chip is executing Reset program code, it isalways possible to interrupt the QA Chip and change from one mode toanother.

5.1.1 Active Mode

Active Mode is entered in any of the following three situations:

-   -   power-on Reset when the fuse has been blown    -   receiving a command consisting of a global id write byte (0x00)        followed by the ActiveMode command byte (0x06)    -   receiving a command consisting of a local id byte write followed        by some number of bytes representing opcode and data.

In all cases, Active Mode causes execution of program code previouslystored in the flash memory via Program Mode.

If Active Mode is entered by power-on Reset or the global id mechanism,the QA Chip executes specific reset startup code, typically setting upthe local id and other IO specific data. The reset startup code cannotbe interrupted except by a power-down condition. The power-on resetstartup mechanism cannot be used before the fuse has been blown sincethe QA Chip cannot tell whether the flash memory is valid or not. Inthis case the globalid mechanism must be used instead.

If Active Mode is entered by the local id mechanism, the QA Chipexecutes specific code depending on the following bytes, which functionas opcode plus data. The interpretation of the following bytes dependson whatever software happens to be stored in the QA ChIP.

5.1.2 Idle Mode

The QA Chip starts up in Idle Mode when the fuse has not yet been blown,and returns to Idle Mode after the completion of another mode. When theQA Chip is in Idle Mode, it waits for a command from the master bywatching the low speed serial line for an id that matches either theglobal id (0x00), or the chip's local id.

-   -   If the primary id matches the global id (0x00, common to all QA        Chips), and the following byte from the master is the Trim Mode        id byte, and the fuse has not yet been blown, the QA Chip enters        Trim Mode and starts counting the number of internal clock        cycles until the next byte is received. Trim Mode cannot be        entered if the fuse has been blown.    -   If the primary id matches the global id (0x00, common to all QA        Chips), and the following byte from the master is the Program        Mode id byte, and the fuse has not yet been blown, the QA Chip        enters Program Mode. Program Mode cannot be entered if the fuse        has been blown.    -   If the primary id matches the global id (0x00, common to all QA        Chips), and the following byte from the master is the Active        Mode id bytes, the QA Chip enters Active Mode and executes        startup code, allowing the chip to set itself into a state to        subsequently receive authentication commands (includes setting a        local id and a trim value).    -   If the primary id matches the chip's local ID, the QA Chip        enters Active Mode, allowing the subsequent command to be        executed.

The valid 8-bit serial mode values sent after a global id are as shownin Table 349: TABLE 349 Command byte values to place chip in specificmode Value Interpretation 10101011 Trim Mode (only functions when thefuse has not been blown) (0xAB) 10001101 Program Mode (only functionswhen the fuse has not (0xAD) been blown) 00000110 Active Mode (resetsthe chip & loads the localId) (0x06)5.1.3 Trim Mode

Trim Mode is enabled by sending a global id byte (0x00) followed by theTrim Mode command byte (1xAB). Trim Mode can only be entered while thefuse has not yet been blown.

The purpose of Trim Mode is to set the trim value (an internal registersetting) of the internal ring oscillator so that Flash erasures andwrites are of the correct duration. This is necessary due to the 2:1variation of the clock speed due to process variations. If writes anerasures are too long, the Flash memory will wear out faster thandesired, and in some cases can even be damaged. Note that the 2:1variation due to temperature still remains, so the effective operatingspeed of the chip is 7-14 MHz around a nominal 10 MHz.

Trim Mode works by measuring the number of system clock cycles thatoccur inside the chip from the receipt of the Trim Mode command byteuntil the receipt of a data byte. When the data byte is received, thedata byte is copied to the trim register and the current value of thecount is transmitted to the outside world.

Once the count has been transmitted, the QA Chip returns to Idle Mode.

At reset, the internal trim register setting is set to a known value r.The external user can now perform the following operations:

-   -   send the global id+write followed by the Trim Mode command byte    -   send the 8-bit value v over a specified time t    -   send a stop bit to signify no more data    -   send the global id+read followed by the Trim Mode command byte    -   receive the count c    -   send a stop bit to signify no more data

At the end of this procedure, the trim register will be v, and theexternal user will know the relationship between external time t andinternal time c. Therefore a new value for v can be calculated.

The Trim Mode procedure can be repeated a number of times, varying botht and v in known ways, measuring the resultant c. At the end of theprocess, the final value for v is established (and stored in the trimregister for subsequent use in Program Mode). This value v must also bewritten to the flash for later use (every time the chip is placed inActive Mode for the first time after power-up). For more informationabout the internal workings of Trim Mode and the accuracy of trim in theQA Chip, see Section 11.2 on page 967.

5.1.4 Program Mode

Program Mode is enabled by sending a global id byte (0x00) followed bythe Program Mode command byte.

If the QA Chip knows already that the fuse has been blown, it simplydoes not enter Program Mode. If the QA Chip does not know the state ofthe fuse, it determines whether or not the internal fuse has been blownby reading 32-bit word 0 of the information block of flash memory. Ifthe fuse has been blown the remainder of data from the Program Modecommand is ignored, and the QA Chip returns to Idle Mode.

If the fuse is still intact, the chip enters Program Mode and erases theentire contents of Flash memory. The QA Chip then validates the erasure.If the erasure was successful, the QA Chip receives up to 4096 bytes ofdata corresponding to the new program code and variable data. The bytesare transferred in order byte₀ to byte₄₀₉₅.

Once all bytes of data have been loaded into Flash, the QA Chip returnsto Idle Mode.

Note that Trim Mode functionality must be performed before a chip entersProgram Mode for the first time. Otherwise the erasure and writedurations could be incorrect.

Once the desired number of bytes have been downloaded in Program Mode,the LSS Master must wait for 80 μs (the time taken to write two bytes toflash at nybble rates) before sending the new transaction (e.g. ActiveMode). Otherwise the last nybbles may not be written to flash.

5.1.5 After Manufacture

Directly after manufacture the flash memory will be invalid and the fusewill not have been blown. Therefore power-on-reset will not cause ActiveMode. Trim Mode must therefore be entered first, and only after asuitable trim value is found, should Program Mode be entered to store aprogram. Active Mode can be entered if the program is known to be valid.

Logical View of CPU

6 Introduction

The QA Chip is a 32-bit microprocessor with on-board RAM for scratchstorage, on-board flash for program storage, a serial interface, andspecific security enhancements.

The high level commands that a user of an QA Chip sees are allimplemented as small programs written in the CPU instruction set.

The following sections describe the memory model, the various registers,and the instruction set of the CPU.

7 Memory Model

The QA Chip has its own internal memory, broken into the followingconceptual regions:

-   -   RAM variables (3 Kbits=96 entries at 32-bits wide), used for        scratch storage (e.g. HMAC-SHA1processing).    -   Flash memory (8 Kbytes main block(+)128 bytes info block) used        to hold the non-volatile authentication variables (including        program keys etc), and program code. Only 4 KBytes(+)64 bytes is        visible to the program addressing space due to shadowing.        Shadowing is where half of each byte is used to validate and        verify the other half, thus protecting against certain forms of        physical and logical attacks. As a result, two bytes are read to        obtain a single byte of data (this happens transparently).        7.1 RAM

The RAM region consists of 96×32-bit words required for the generalfunctioning of the QA Chip, but only during the operation of the chIP.RAM is volatile memory: once power is removed, the values are lost. Notethat in actual fact memory retains its value for some period of timeafter power-down, but cannot be considered to be available uponpower-up. This has issues for security that are addressed in othersections of this document.

RAM is typically used for temporary storage of variables during chipoperation. Short programs can also be stored and executed from the RAM.

RAM is addressed from 0 to 5F. Since RAM is in an unknown state upon aRESET (RstL), program code should not assume the contents to be 0.Program code can, however, set the RAM to be a particular known stateduring execution of the reset command (guaranteed to be received beforeany other commands).

7.2 Flash Variables

The flash memory region contains the non-volatile information in the QAChIP. Flash memory retains its value after a RESET or if power isremoved, and can be expected to be unchanged when the power is nextturned on.

Byte 0 of main memory is the first byte of the program run for thecommand dispatcher. Note that the command dispatcher is always run withshadows enabled.

Bytes 0-7 of the information block flash memory is reserved as follows:

-   -   byte 0-3=fuse. A value of 0x5555AAAA indicates that the fuse has        been blown (think of a physical fuse whose wire is no longer        intact).    -   bytes 4-7=random number used to XOR all data for RAM and flash        memory accesses

After power-on reset (when the fuse is blown) or upon receipt of aglobalId Active command, the 32-bit data from bytes 4-7 in theinformation block of Flash memory is loaded into an internal ChipMaskregister. In Active Mode (the chip is executing program code), all dataread from the flash and RAM is XORed with the ChipMask register, and alldata written to the flash and RAM is XORed with the ChipMask registerbefore being written out. This XORing happens completely transparentlyto the program code. Main flash memory byte 0 onward is the start ofprogram code. Note that byte 0 onward needs to be valid after beingXORed with the appropriate bytes of ChipMask.

Even though CPU access is in 8-bit and 32-bit quantities, the data isactually stored in flash a nybble-at-a-time. Each nybble write iswritten as a byte containing 4 sets of b/

b pairs. Thus every byte write to flash is writing a nybble to real andshadow. A write mask allows the individual targetting ofnybble-at-a-time writes.

The checking of flash vs shadow flash is automatically carried out eachread (each byte contains both flash and shadow flash). If all 8 bits are1, the byte is considered to be in its erased form¹, and returns 0 asthe nybble. Otherwise, the value returned for the nybble depends on thesize of the overall access and the setting of bit 0 of the 8-bitWriteMask.¹TSMC's flash memory has an erased state of all 1s

-   -   All 8-bit accesses (i.e. instruction and program code fetches)        are checked to ensure that each byte read from flash is 4 sets        of b/        b pairs. If the data is not of this form, the chip hangs until a        new command is issued over the serial interface.    -   With 32-bit accesses (i.e. data used by program code), each byte        read from flash is checked to ensure that it is 4 sets of b/        b pairs. A setting of WriteMask₀=0 means that if the data is not        valID, then the chip will hang until a new command is issued        over the serial interface. A setting of WriteMask₀=1 means that        each invalid nybble is replaced by the upper nybble of the        WriteMask. This allows recovery after a write or erasure is        interrupted by a power-down.        8 Registers

A number of registers are defined for use by the CPU. They are used forcontrol, temporary storage, arithmetic functions, counting and indexing,and for I/O.

These registers do not need to be kept in non-volatile (Flash) memory.They can be read or written without the need for an erase cycle (unlikeFlash memory). Temporary storage registers that contain secretinformation still need to be protected from physical attack by TamperPrevention and Detection circuitry and parity checks.

All registers are cleared to 0 on a RESET. However, program code shouldnot assume any RAM contents have any particular state, and should set upregister values appropriately. In particular, at the startup entrypoint, the various address registers need to be set up from unknownstates.

8.1 GO

A 1-bit GO register is 1 when the program is executing, and 0 when it isnot. Programs can clear the GO register to halt execution of programcode once the command has finished executing.

8.2 Accumulator and Z Flag

The Accumulator is a 32-bit general-purpose register that can be thoughtof as the single data register. It is used as one of the inputs to allarithmetic operations, and is the register used for transferringinformation between memory registers.

The Z register is a 1-bit flag, and is updated each time the Accumulatoris written to. The Z register contains the zero-ness of the Accumulator.Z=1 if the last value written to the Accumulator was 0, and 0 if thelast value written was non-0.

Both the Accumulator and Z registers are directly accessible from theinstruction set.

8.3 Address Registers

8.3.1 Program Counter Array and Stack Pointer

A 12-level deep 12-bit Program Counter Array (PCA) is defined. It isindexed by a 4-bit Stack Pointer (SP). The current Program Counter (PC),containing the address of the currently executing instruction, iseffectively PCA[SP]. A single register bit, PCRamSel determines whetherthe program is executing from flash or RAM (0=flash, 1=RAM).

The PC is affected by calling subroutines or returning from them, and byexecuting branching instructions. The SP is affected by callingsubroutines or returning from them. There is no bounds checking oncalling too many subroutines: the oldest entry in the execution stackwill be lost.

The entry point for program code is defined to be address 0 in Flash.This entry point is used whenever the master signals a new transaction.

8.3.2 A0-A3

There are 4 8-bit address registers Each register has an associatedmemory mode bit designating the address as in Flash (0) or RAM (1).

When an An register is pointing to an address in RAM, it holds the wordnumber. When it is pointing to an address in Flash, it points to a setof 32-bit words that start at a 128-bit (16 byte) alignment. The A0register has a special use of direct offset e.g. access is possible to(A0),0-7 which is the 32-bit word pointed to by A0 offset by thespecified number of words.

8.3.3 WriteMask

The WriteMask register is used to determine how many nybbles will bewritten during a 32-bit write to Flash, and whether or not an invalidnybble will be replaced during a read from Flash.

During writes to flash, bit n (of 8) determines whether nybble n iswritten. The unit of writing is a nybble since half of each byte is usedfor shadow data. A setting of 0xFF means that all 32-bits will bewritten to flash (as 8 sets of nybble writes).

During 32-bit reads from flash (occurs as 8 reads), the value ofWriteMask₀ is used to determine whether a read of invalid data isreplaced by the upper nybble of WriteMask. If 0, a read of invalid datais not replaced, and the chip hangs until a new command is issued overthe serial interface. If 1, a read of invalid data is replaced by theupper nybble of the WriteMask.

Thus a WriteMask setting of 0 (reset setting) means that no writes willoccur to flash, and all reads are not replaced (causing the program tohang if an invalid value is encountered).

8.4 Counters

A number of special purpose counters/index registers are defined: TABLE350 Counter/Index registers Register Name Size Bits Description C1 1 × 33 Counter used to index arrays and general purpose counter C2 1 × 6 6General purpose counter and can be used to index arrays

All these counter registers are directly accessible from the instructionset. Special instructions exist to load them with specific values, andother instructions exist to decrement or increment them, or to branchdepending on the whether or not the specific counter is zero.

There are also 2 special flags (not registers) associated with C1 andC2, and these flags hold the zero-ness of C1 or C2. The flags are usedfor loop control, and are listed here, for although they are notregisters, they can be tested like registers. TABLE 351 Flags fortesting C1 and C2 Name Description C1Z 1 = C1 is current zero, 0 = C1 iscurrently non-zero. C2Z 1 = C2 is current zero, 0 = C2 is currentlynon-zero.8.5 RTMP

The single bit register RTMP allows the implementation of LFSRs andmultiple precision shift registers.

During a rotate right (ROR) instruction with operand of RB, the bitshifted out (formally bit 0) is written to the RTMP register. The bitcurrently in the RTMP register becomes the new bit 31 of theAccumulator. Performing multiple ROR RB commands over several 32-bitvalues implements a multiple precision rotate/shift right.

The XRB operand operates in the same way as RB, in that the currentvalue in the RTMP register becomes the new bit 31 of the Accumulator.However with the XRB instruction, the bit formally known as bit 0 doesnot simply replace RTMP (as in the RB instruction). Instead, it is XORedwith RTMP, and the result stored in RTMP, thereby allowing theimplementation of long LFSRs.

8.6 Registers Used for I/O

Several registers are defined for communication between the master andthe QA ChIP. These registers are LocalID, InByte and OutByte.

LocalId (7 bits) defines the chip-specific id that this particular QAChip will accept commands for.

InByte (8 bits) provides the means for the QA Chip to obtain the nextbyte from the master. OutByte (8 bits) provides the means for the QAChip to send a byte of data to the master.

From the QA Chip's point of view:

-   -   Reads from InByte will hang until there is 1 byte of data        present from the master.    -   Writes to OutByte will hang if the master has not already        consumed the last OutByte.

When the master begins a new command transaction, any existing data inInByte and OutByte is lost, and the PC is reset to the entry point inthe code, thus ensuring correct framing of data.

8.7 Registers Used for Trimming Clock Speed

A single 8-bit Trim register is used to trim the ring oscillaor clockspeed. The register has a known value of 0x00 during reset to ensurethat reads from flash will succeed at the fastest process corners, andcan be set in one of two ways:

-   -   via Trim Mode, which is necessary before the QA Chip is        programmed for the first time; or    -   via the CPU, which is necessary every time the QA Chip is        powered up before any flash write or erasure accesses can be        carried out.        8.8 Registers Used for Testing Flash

There are a number of registers specifically for testing the flashimplementation. A single 32-bit write to an appropriate RAM addressallows the setting of any combination of these flash test registers.

RAM consists of 96×32-bit words, and can be pointed to by any of thestandard An address registers. A write to a RAM address in the range97-127 does nothing with the RAM (reads return 0), but a write to a RAMaddress in the range 0x80-0x87 will write to specific groupings ofregisters according to the low 3 bits of the RAM address. A 1 in theaddress bit means the appropriate part of the 32-bit Accumulator valuewill be written to the appropriate flash test registers. A 0 in theaddress bit means the register bits will be unaffected.

The registers and address bit groupings are listed in Table 352: TABLE352 Flash test registers settable from CPU in RAM address range0x80-0x87² adr bitSuperscriptparanumonly data bits name description 0 0ShadowsOff 0 = shadowing applies (nybble based flash access) 1 =shadowing disabled, 8-bit direct accesses to flash. 1 hiFlashAdr Onlyvalid when shadowsOff = 1 0 = accesses are to lower 4 Kbytes of flash 1= accesses are to upper 4 Kbytes of flash 2 1 3 enableFlashTest 0 = keepflash test register within the TSMC flash IP in its reset state 1 =enable flash test register to take on non- reset values. 8-4 flashTestInternal 5-bit flash test register within the TSMC flash IP(SFC008_08B9_HE). If this is written with 0x1E, then subsequent writeswill be according to the TSMC write test mode. You must write a non-0x1Evalue or reset the register to exit this mode. 2 28-9  flashTime WhentimerSel is 1, this value is used for the duration of the program cyclewithin a standard flash write or erasure. 1 unit = 16 clock cycles (16 ×100 ns typical). Regardless of timerSel, this value is also used for thetimeout following power down detection before the QA Chip resets itself.1 unit = 1 clock cycle (=100 ns typical). Note that this means theprogrammer should set this to an appropriate value (e.g. 5 μs), just asthe localId needs to be set. 29  timerSel 0 = use internal (default)timings for flash writes & erasures 1 = use flashTime for flash writesand erasures²This is from the programmer's perspective. Addresses sent from the CPUare byte aligned, so the MRU needs to test bit n+2. Similarly, checkingDRAM address >128 means testing bit 7 of the CPU, and bit 9 in the MRU.³unshadowed⁴shadowed

When none of the address register bits 0-2 are set (e.g. a write to RAMaddress 0x80), then invalid writes will clear the illChip and retryCountregisters.

For example, set the A0 register to be 0x80 in RAM. A write to (A0),0will write to none of the flash test registers, but will clear theillChip and retryCount registers. A write to (A0),7 will write to all ofthe flash test registers. A write to (A0),2 will write to theenableFlashTest and flashTest registers only. A write to (A0),4 willwrite to the flashTime and bmerSel registers etc.

Finally, a write to address 0x88 in RAM will cause a device erasure. IfinfoBlockSel is 0, then the device erasure will only be of main memory.If infoBlockSel is 1, then the device erasure is of both main memory andthe information block (which will also clear the ChipMask and the Fuse).

Reads of invalid RAM areas will reveal information as follows:

-   -   all invalid addresses in RAM (e.g. 0x80) will return the illChip        flag in the low bit (illChip is set whenever 16 consecutive bad        reads occur for a single byte in memory)    -   all invalid addresses in RAM with the low address bit set (e.g.        0x81, or (A0),1 when A0 holds 0x80), will additionally return        the most recent retryCount setting (only updated by the chip        when a bad read occurs). i.e. bit 0=illChip, bits        4-1=retryCount.        8.9 Register Summary

Table 353 provides a summary of the registers used in the CPU. TABLE 353Register summary Register name Description #bits A[0-3] addressregisters 49 = 36 Acc Accumulator 32 C1 general purpose counter andindex 3 C2 general purpose counter and index 6 IIIChip gets set whenevermore than 15 1 consecutive bad reads from flash occurred (and anyprogram executing has hung) InByte input byte from outside world 8 Godetermines whether CPU is executing 1 LocalId determines id for thischip's IO 7 OutByte output byte to outside world 8 Z zero flag for lastxfer to Acc 1 PCA program counter array 1212 = 144 PCRamSel Program codeis executing in flash 1 (0) or ram (1) RetryCount counts the number ofretries 4 for bad reads RTMP bit used to alow multi-word rotations 1 SPstack pointer into PCA 4 Trim trims ring oscillator frequency 8 fashtest registers various registers in the 30 embedded flash and flashaccess logic specifically for testing the flash memory TOTAL (bits) 2958.10 Startup

Whenever the chip is powered up, or receives a ‘write’ command over theserial interface, the PC and PCRamSel get set to 0 and execution beginsat 0 in Flash memory. The program (starting at 0) needs to determine howthe program was started by reading the InByte register.

If the first byte read is 0xFF, the chip is being requested to performsoftware reset tasks. Execution of software reset can only beinterrupted by a power down. The reset tasks include setting up RAM tocontain known startup state information, setting up Trim and localIDregisters etc. The CPU signals that it is now ready to receive commandsfrom an external device by writing to the OutByte register.

An external Master is able to read the OutByte (and any further outbytesthat the CPU decides to send) if it so wishes by a read using thelocalId.

Otherwise the first byte read will be of the form where the leastsignificant bit is 0, and bits 7-1 contain the localId of the device asread over the serial interface. This byte is usually discarded since itnominally only has a value of differentiation against a software resetrequest. The second and subsequent bytes contain the data message of awrite using the localId. The CPU can prevent interruption duringexecution by writing 0 to the localId and then restoring the desiredlocalId at the later stage.

9 Instruction Set

The CPU operates on 8-bit instructions and typically on 32-bit dataitems. Each instruction typically consists of an opcode and operand,although the number of bits allocated to opcode and operand variesbetween instructions.

9.1 Basic Opcodes (Summary)

The opcodes are summarized in Table 354: TABLE 354 Opcode bit patternmap Opcode Mnemonic Simple Description 0000xxxx JMP Jump 0001xxxx JSRJump subroutine 0010xxxx TBR Test and branch 0011xxxx DBR Decrement andbranch 0100xxxx SC Set counter to a value 0101xxxx ST Store Accumulatorin specified location 0110000x — reserved 01100010 JPZ Jump to 001100011 JPI Jump indirect 011001xx — reserved 01101xxx — reserved01110000 — reserved 01110001 ERA Erase page of flash memory pointed toby Accumulator 01110010 JSZ Jump to subroutine at at 0 01110011 JSI Jumpsubroutine indirect 01110100 RTS Return from subroutine 01110101 HALTStop the CPU 0111011x — reserved 01111xxx LIA Load immediate value intoaddress register 10000xxx AND Bitwise AND Accumulator 10001xxx ORBitwise OR Accumulator 1001xxxx XOR Exclusive-OR Accumulator 1010xxxxADD Add a 32 bit value to the Accumulator 1011xxxx LD Load Accumulator1100xxxx ROR Rotate Accumulator right 11010xxx AND Bitwise ANDAccumulator⁵ 11011xxx OR Bitwise OR Accumulator^(Superscriptparanumonly)11100xxx XOR Bitwise XOR Accumulator^(Superscriptparanumonly) 11101xxxADD Add a 32 bit value to the Accumulator^(Superscriptparanumonly)11110xxx LD Load Accumulator^(Superscriptparanumonly) 11111xxx RIARotate Accumulator into address register⁵immediate form of instruction

Table 355 is a summary of valid operands for each opcode. The table isordered alphabetically by opcode mnemonic. The binary value for eachoperand can be found in the subsequent sections. Opcode Valid operandsADD immediate value (A0), offset (An), {C1, C2} [where n = 0-3] ANDimmediate value (A0), offset DBR {C1, C2}, offset ERA HALT JMP addressJPI JPZ JSI JSR address JSZ LIA {Flash, Ram}, An [where n = 0-3],{immediate value} LD immediate value (A0), offset (An), {C1, C2} [wheren = 0-3] OR immediate value (A0), offset RIA {Flash, Ram}, An [where n =0-3] ROR {InByte, OutByte, WriteMask, ID, C1, C2, RB, XRB, 1, 3, 8, 24,31} RTS SC {C1, C2}, {immediate value} ST (A0), offset (An), {C1, C2}[where n = 0-3] TBR {0, 1}, offset XOR immediate value (A0), offset(An), {C1, C2} [where n = 0-3]

Additional pseduo-opcodes (for programming convenience) are as follows:

-   -   DEC=ADD 0xFF..    -   INC=ADD 0x01    -   NOT=XOR 0xFF..    -   LDZ=LD0    -   SC {C1, C2}, Acc=ROR {C1, C2}    -   RD=ROR Inbyte    -   WR=ROR OutByte    -   LDMASK=ROR WriteMask    -   LDID=ROR Id    -   NOP=XOR 0        9.2 Addressing Modes

The CPU supports a set of addressing modes as follows:

-   -   immediate    -   accumulator indirect    -   indirect fixed    -   indirect indexed        9.2.1 Immediate

In this form of addressing, the operand itself supplies the 32-bit data.

Immediate addressing relies on 3 bits of operand, plus an optional 8bits at PC+1 to determine an 8-bit base value. Bits 0 to 1 of the opcodebyte determine whether the base value comes from the opcode byte itself,or from PC+1, as shown in Table 356. TABLE 356 Selection for base valuein immediate mode Opcode₁₋₀ Base value 00 00000000 01 00000001 10 FromPC+1 (i.e. MIUData₇₋₀) 11 11111111

The base value is computed by using CMD₀ as bit 0, and copying CMD₁ intothe upper 7 bits.

The resultant 8 bit base value is then used as a 32-bit value, with 0sin the upper 24 bits, or the 8-bit value is replicated into the upper 32bits. The selection is determined by bit 2 of the opcode byte, asfollows: TABLE 357 Replicate bits selection Opcode₂ Data 0 Noreplication. Data has 0 in upper 24 bits and baseVal in lower 8 bits 1Replicated. Data is 32-bit value formed by replicating baseVal.

Opcodes that support immediate addressing are LD, ADD, XOR, AND, OR. TheSC and LIA instructions are also immediate in that they store the datawith the opcode, but they are not in the same form as that describedhere. See the detail on the individual instructions for moreinformation. Single byte examples include:

-   -   LD 0    -   ADD 1    -   ADD 0xFF...# this subtracts 1 from the acc    -   XOR 0xFF...# this performs an effective logical NOT operation

Double byte examples include:

-   -   LD 0x05 # a constant    -   AND 0x0F # isolates the lower nybble    -   LD 0x36...# useful for HMAC processing        9.2.2 Accumulator Indirect

In this form of addressing, the Accumulator holds the effective address.

Opcodes that support Accumulator indirect addressing are JPI, JSI andERA. In the case of JPI and JSI, the Accumulator holds the address tojump to. In the case of ERA, the Accumulator holds the address of thepage in flash memory to be erased.

Examples include:

-   -   JPI    -   JSI    -   ERA        9.2.3 Indirect Fixed

In this form of addressing, address register A0 is used as a baseaddress, and then a specific fixed offset is added to the base addressto give the effective address.

Bits 2-0 of the opcode byte specify the fixed offset from A0, whichmeans the fixed offset has a range of 0 to 7.

Opcodes that support indirect indexed addressing are LD, ST, ADD, XOR,AND, OR.

Examples include:

-   -   LD (A0),2    -   ADD (A0), 3    -   AND (A0), 4    -   ST (A0), 7        9.2.4 Indirect Indexed

In this form of addressing, an address register is used as a baseaddress, and then an index register is used to offset from that baseaddress to give the effective address.

The address register is one of 4, and is selected via bits 2-1 of theopcode byte as follows: TABLE 358 Address register selection addressregister Opcode₂₋₁ selected 00 A0 01 A1 10 A2 11 A3

Bit 0 of the opcode byte selects whether index register C1 or C2 isused:

The counter is selected as follows: TABLE 359 Interpretation of counterfor DBR Opcode₀ interpretion 0 C1 1 C2

Opcodes that support indirect indexed addressing are LD, ST, ADD, XOR.

Examples include:

-   -   LD (A2), C1    -   ADD (A1), C1    -   ST (A3), C2

Since C1 and C2 can only decement, processing of data structurestypically works by loading Cn with some number n and decrementing to 0.Thus (Ax),n is the first word accessed, and (Ax),0 is the last 32-bitword accessed in the loop.

9.3 ADD—Add to Accumulator

-   -   Mnemonic: ADD    -   Opcode: 1010xxxx, and 11101xxx    -   Usage: ADD effective-address, or ADD immediate-value

The ADD instruction adds the specified 32-bit value to the Accumulatorvia modulo 2³² addition.

The 11101xxx form of the opcode follows the immediate addressing rules(see Section 9.2.1 on page 946). The 1010xxxx form of the opcode definesan effective address as follows: TABLE 360 Interpretation of operand forADD (1010xxxx) bit 3 interpretion comment 0 (A0), offset indirect fixedaddressing (see Section 9.2.3 on page 948) 1 (An), Cn indirect indexedaddressing (see Section 9.2.4 on page 948)

The Z flag is also set during this operation, depending on whether theresult (loaded into the Accumulator) is zero or not.

9.4 AND—Bitwise AND

-   -   Mnemonic: AND    -   Opcode: 10000xxx, and 11010xxx    -   Usage: AND effective-address, or AND immediate-value

The AND instruction performs a 32-bit bitwise AND operation on theAccumulator.

The 11010xxx form of the opcode follows the immediate addressing rules(see Section 9.2.1 on page 946). The 10000xxx form of the opcode followsthe indirect fixed addressing rules (see Section 9.2.3 on page 948).

The Z flag is also set during this operation, depending on whether theresultant 32-bit value (loaded into the Accumulator) is zero or not.

9.5 DBR-Decrement and Branch Mnemonic: DBR Opcode: 0011xxxx Usage: DBRCounter, Offset

This instruction provides the mechanism for building simple loops.

The counter is selected from bit 0 of the opcode byte as follows: TABLE361 Interpretation of counter for DBR bit 0 interpretion 0 C1 1 C2

If the specified counter is non-zero, then the counter is decrementedand the designated offset is added to the current instruction address(PC for 1-byte instructions, PC+1 for 2-byte instructions). If thespecified counter is zero, it is decremented (all bits in the counterbecome set) and processing continues at the next instruction (PC+1 orPC+2). The designated offset will typically be negative for use inloops.

The instruction is either 1 or two bytes, as determined by bits 3-1 ofthe opcode byte:

-   -   If bits 3-1=000, the instruction consumes 2 bytes. The 8 bits at        PC+1 are treated as a signed number and used as the offset        amount. Thus 0xFF is treated as −1, and 0x01 is treated as +1.    -   If bits 3-1≠000, the instruction consumes 1 byte. Bits 3-1 are        treated as a negative number (the sign bit is implied) and used        as the offset amount. Thus 111 is treated as −1, and 001 is        treated as −7. This is useful for small loops.

The effect is that if the branch is back 1-7 bytes (1 byte is notparticularly useful), then the single byte form of the instruction canbe used. If the branch is forward, or backward more than 7 bytes, thenthe 2-byte instruction is required.

9.6 ERA-Erase Mnemonic: ERA Opcode: 01110001 Usage: ERA

This instruction causes an erasure of the 256-byte page of flash memorypointed to by the Accumulator. The Accumulator is assumed to contain an8-bit pointer to a 128-bit (16 byte) aligned structure (same structureas the address registers). The page number to be erased comes from bits7-4, and the lower 4 bits are ignored.

Note that the size of the flash memory page being erased is actually 512bytes, but in terms of data storage and addressing from the point ofview of the CPU, there is only 256 bytes in the page.

9.7 HALT—Halt CPU Operation Mnemonic: HALT Opcode: 01110101 Usage: HALT

The HALT instruction writes a 0 to the internal GO register, therebycausing the CPU to terminate the currently executing program. The CPUwill only be restarted with a new localId transaction from the Master orby a globalId plus Active Mode byte.

9.8 JMP—Jump Mnemonic: JMP Opcode: 0000xxxx Usage: JMP effective-address

The JMP instruction provides for a method of branching to a specifiedaddress. The instruction loads the PC with the effective address.

The new PC is loaded as follows: bits 11-8 are obtained from bits 3-0 ofthe JMP opcode byte, and bits 7-0 are obtained from PC+1.

9.9 JPI—Jump Indirect Mnemonic: JPI Opcode: 01100011 Usage: JPI

The JPI instruction loads the PC with the lower 12 bits of theAccumulator, and sets the PCRamSel register with bit 15 of theAccumulator. Note that the stack is unaffected (unlike JSI).

9.10 JPZ—Jump to Zero Mnemonic: JPZ Opcode: 01100010 Usage: JPZ

The JPZ instruction loads the PC and PCRamSel with 0, thereby causing ajump to address 0 in Flash memory.

Programmers will not typically use the JPZ command. However the CPUexecutes this instruction whenever a new command arrives over the serialinterface, so that the code entry point is known i.e. every time thechip receives a new command, execution begins at address 0 in flash.This does not change the status of any other internal register settings(e.g. the flash test registers).

9.11 JSI—Jump Subroutine Indirect Mnemonic: JSI Opcode: 01110011 Usage:JSI

The JSI instruction allows the jumping to a subroutine whose address isobtained from the Accumulator. The instruction pushes the current PConto the stack, loads the PC with the lower 12 bits of the Accumulator,and sets the PCRamSel register with bit 15 of the Accumulator.

The stack provides for 12 levels of execution (11 subroutines deep). Itis the responsibility of the programmer to ensure that this depth is notexceeded or the deepest return value will be overwritten (since thestack wraps). Programs can take advantage of the fact that the stackwraps.

9.12 JSR—JUMP SUBROUTINE Mnemonic: JSR Opcode: 0001xxxx Usage: JSReffective-address

The JSR instruction provides for the most common usage of the subroutineconstruct. The instruction pushes the current PC onto the stack, andloads the PC with the effective address.

The new PC is loaded as follows: bits 11-8 are obtained from bits 3-0 ofthe JSR opcode byte, and bits 7-0 are obtained from PC+1.

The stack provides for 12 levels of execution (11 subroutines deep). Itis the responsibility of the programmer to ensure that this depth is notexceeded or the return value will be overwritten (since the stackwraps). Programs can take advantage of the fact that the stack wraps.

9.13 JSZ—Jump to Subroutine at Zero Mnemonic: JSZ Opcode: 01110010Usage: JSZ

The JSZ instruction jumps to the subroutine at flash address 0 (i.e. itpushes the current PC onto the stack, and loads the PC and PCRamSel with0).

Programmers will not typically use the JSZ command. It exists merely asa result of opcode decoding minimization and can be used to assist withthe testing of the chIP.

9.14 LD—LOAD ACCUMULATOR Mnemonic: LD Opcode: 1011xxxx, and 11110xxxUsage: LD effective-address, or LD immediate-value

The LD instruction loads the Accumulator with the 32-bit value.

The 11110xxx form of the opcode follows the immediate addressing rules(see Section 9.2.1 on page 946). The 1011xxxx form of the opcode definesan effective address as follows: TABLE 362 Interpretation of operand forLD (1011xxxx) bit 3 interpretion comment 0 (A0), offset indirect fixedaddressing (see Section 9.2.3 on page 948) 1 (An), Cn indirect indexedaddressing (see Section 9.2.4 on page 948)

The Z flag is also set during this operation, depending on whether thevalue loaded into the Accumulator is zero or not.

9.15 LIA—LOAD IMMEDIATE ADDRESS Mnemonic: LIA Opcode: 01111xxx Usage:LIAF AddressRegister, Value # for flash addresses LIAR AddressRegister,Value # for ram addresses

The LIA instruction transfers the data from PC+1 into the designatedaddress register (A0-A3), and sets the memory mode bit for that addressregister.

Bit 0 specifies whether the address is in flash or ram, as follows:TABLE 363 Interpretation of memory mode for LIA bit 0 interpretion 0Flash 1 Ram

The address register to be targetted is selected via bits 2-1 of theinstruction.

9.16 OR—BITWISE OR Mnemonic: OR Opcode: 10001xxx, and 11011xxx Usage: OReffective-address, or OR immediate-value

The OR instruction performs a 32-bit bitwise OR operation on theAccumulator.

The 11011xxx form of the opcode follows the immediate addressing rules(see Section 9.2.1 on page 946). The 10001xxx form of the opcode followsthe indirect fixed addressing rules (see Section 9.2.3 on page 948).

The Z flag is also set during this operation, depending on whether theresultant 32-bit value (loaded into the Accumulator) is zero or not.

9.17 RIA—ROTATE IN ADDRESS Mnemonic: RIA Opcode: 11111xxx Usage: RIAFAddressRegister # for flash addresses RIAR AddressRegister # for ramaddresses

-   -   -   RIAR AddressRegister # for ram addresses

The RIA instruction transfers the lower 8 bits of the Accumulator intothe designated address register (A0-A3), sets the memory mode bit forthat address register, and rotates the Accumulator right by 8 bits.

Bit 0 specifies whether the address is in flash or ram, as follows:TABLE 364 Interpretation of memory mode for RIA bit 0 interpretion 0Flash 1 Ram

The address register to be targetted is selected via bits 2-1 of theinstruction.

9.18 ROR—Rotate Right ROR—ROTATE RIGHT Mnemonic: ROR Opcode: 1100xxxxUsage: ROR Value

The ROR instruction provides a way of rotating the Accumulator right aset number of bits. The bit(s) coming in at the top of the Accumulator(to become bit 31) can either come from the previous lower bits of theAccumulator, from the serial connection, or from external flags. Thebit(s) rotated out can also be output from the serial connection, orcombined with an external flag.

The allowed operands are as follows: TABLE 365 Interpretation of operandfor ROR bits 3-0 interpretion 0000 RB 0001 XRB 0010 WriteMask 0011  10100 — (reserved) 0101  3 0110 31 0111 24 1000 C1 1001 C2 1010 —(reserved) 1011 — (reserved) 1100  8 1101 ID 1110 InByte 1111 OutByte

The Z flag is also set during this operation, depending on whetherresultant 32-bit value (loaded into the Accumulator) is zero or not.

In its simplest form, the operand for the ROR instruction is one of 1,3, 8, 24, 31, indicating how many bit positions the Accumulator shouldbe rotated. For these operands, there is no external input or output—thebits of the Accumulator are merely rotated right. Note that these valuesare the equivalent to rotating left 31, 29, 24, 8, 1 bit positions.

With operand WriteMask, the lower 8 bits of the Accumulator aretransferred to the WriteMask register, and the Accumulator is rotatedright by 1 bit. This conveniently allows successive nybbles to be maskedduring Flash writes if the Accumulator has been preloaded with anappropriate value (eg 1x01).

With operands C1 and C2, the lower appropriate number of bits of theAccumulator (3 for C1, 6 for C2) are transferred to the C1 or C2register and the lower 6 bits of the Accumulator are loaded with theprevious value of the Cn register. The remaining upper bits of theAccumulator are set as follows: bit 31-24 are copied from previous bits7-0, and bits 23-6 are copied from previous bits 31-14 (effectivelyjunk). As a result, the Accumulator should be subsequently masked if theprogrammer wants to compare for specific values).

With operand ID, the 7 low-order bits are transferred from theAccumulator to the LocalId register, the low-order 8 bits of theAccumulator are copied to the Trim register if the Trim register has notalready been written to after power-on reset, and the Accumulator isrotated right by 8 bits. This means that the ROR ID instruction needs tobe performed twice, typically during Global Active Mode—once to setTrim, and once to set LocalId. Note there is no way to read the contentsof the localId or Trim registers directly. However the LocalId sent tothe program for a command is available as bits 7-1 of the first byteobtained from InByte after program startup.

With operand InByte, the next serial input byte is transferred to thehighest 8 bits of the Accumulator. The InByteValid bit is also cleared.If there is no input byte available from the client yet, execution issuspended until there is one. The remainder of the Accumulator isshifted right 8 bit positions (bit 31 becomes bit 23 etc.), with lowestbits of the Accumulator shifted out.

With operand OutByte, the Accumulator is shifted right 8 bit positions.The byte shifted out from bits 7-0 is stored in the OutByte register andthe OutByteValid flag is set. It is therefore ready for a client toread. If the OutByteValid flag is already set, execution of theinstruction stalls until the OutByteValid flag cleared (when the OutBytebyte has been read by the client). The new data shifted in to the upper8 bits of the Accumulator is what was transferred to the OutByteregister (i.e. from the Accumulator). Finally, the RB and XRB operandsallow the implementation of LFSRs and multiple precision shiftregisters. With RB, the bit shifted out (formally bit 0) is written tothe RTMP register. The register currently in the RTMP register becomesthe new bit 31 of the Accumulator. Performing multiple ROR RB commandsover several 32-bit values implements a multiple precision rotate/shiftright. The XRB operates in the same way as RB, in that the current valuein the RTMP register becomes the new bit 31 of the Accumulator. Howeverwith the XRB instruction, the bit formally known as bit 0 does notsimply replace RTMP (as in the RB instruction). Instead, it is XORedwith RTMP, and the result stored in RTMP. This allows the implementationof long LFSR_(S), as required by the authentication protocol.

9.19 RTS—Return From Subroutine Mnemonic: RTS Opcode: 01110100 Usage:RTS

The RTS instruction pulls the saved PC from the stack, adds 1, andresumes execution at the resultant address. The effect is to causeexecution to resume at the instruction after the most recently executedJSR or JSI instruction.

Although 12 levels of execution are provided for (11 subroutines), it isthe responsibility of the programmer to balance each JSR and JSIinstruction with an RTS. A RTS executed with no previous JSR will causeexecution to begin at whatever address happens to be pulled from thestack. Of course this may be desired behaviour in specificcircumstances.

9.20 SC—Set Counter Mnemonic: SC Opcode: 0100xxxx Usage: SC CounterValue

The SC instruction is used to transfer a 3-bit Value into the specifiedcounter. The operand determines which of counters C1 and C2 is to beloaded as well as the value to be loaded. Value is stored in bits 3-1 ofthe 8-bit opcode, and the counter is specified by bit 0 as follows:TABLE 366 Interpretation of counter for SC bit 0 interpretion 0 C1 1 C2

Since counter C1 is 3 bits, Value is copied directly into C1.

For counter C2, C2₂₋₀ are copied to C2₅₋₃, and Value is copied to C2₂₋₀.Two SC C2 instructions are therefore required to load C2 with a given6-bit value. For example, to load C2 with 0x0C, we would have SC C2 1followed by SC C2 4.

9.21 ST—Store Accumulator Mnemonic: ST Opcode: 0101xxxx Usage: STeffective-address

The ST instruction stores the 32-bit Accumulator at the effectiveaddress. The effective address is determined as follows: TABLE 367Interpretation of operand for ST (0101xxxx) bit 3 interpretion comment 0(A0), offset indirect fixed addressing (see Section 9.2.3 on page 948) 1(An), Cn indirect indexed addressing (see Section 9.2.4 on page 948)

If the effective address in Flash memory, only those nybbles whosecorresponding WriteMask bit is set will be written to Flash. Programmersshould be very aware of flash characteristics (write time, longevity,page size etc. when storing data in flash).

There is always the possibility that power could be removed during awrite to Flash. If this occurs, the flash will be in an indeterminatestate. If the QA Chip is warned by the external system that power isabout to be removed (via the master causing a transition to Idle Mode),the write will be aborted cleanly at the nearest nybble boundary (writesoccur in the order of least significant to most significant).

9.22 TBR—Test and Branch Mnemonic: TBR Opcode: 0010xxxx Usage: TBR ValueOffset

The Test and Branch instruction tests the status of the Z flag (thezero-ness of the Accumulator), and then branches if a match ocurs.

The zero-ness is selected from bit 0 of the opcode byte as follows:TABLE 368 Interpretation of zero-ness for TBR bit 0 interpretion 0 trueif Acc is zero (Z = 1) 1 true if Acc is non-zero (Z = 0)

If the specified zero-test matches, then the designated offset is addedto the current instruction address (PC for 1-byte instructions, PC+1 for2-byte instructions). If the zero-test does not match, processingcontinues at the next instruction (PC+1 or PC+2). The instruction iseither 1 or two bytes, as determined by bits 3-1 of the opcode byte:

-   -   If bits 3-1=000, the instruction consumes 2 bytes. The 8 bits at        PC+1 are treated as a signed number and used as the offset        amount to be added to PC+1. Thus 0xFF is treated as −1, and 0x01        is treated as +1.    -   If bits 3-1≠000, the instruction consumes 1 byte. Bits 3-1 are        treated as a positive number (the sign bit is implied) and used        as the offset amount to be added to PC. Thus 111 is treated as        7, and 001 is treated as 1. This is useful for skipping over a        small number of instructions.

The effect is that if the branch is forward 1-7 bytes (1 byte is notparticularly useful), then the single byte form of the instruction canbe used. If the branch is backward, or forward more than 7 bytes, thenthe 2-byte instruction is required.

9.23 XOR—Bitwise Exclusive OR Mnemonic: XOR Opcode: 1001xxxx, and11100xxx Usage: XOR effective-address, or XOR immediate-value

The XOR instruction performs a 32-bit bitwise XOR operation on theAccumulator.

The 11100xxx form of the opcode follows the immediate addressing rules(see Section 9.2.1 on page 946). The 1001xxxx form of the opcode has aneffective address as follows: TABLE 369 Interpretation of operand forXOR (1001xxxx) bit 3 interpretion comment 0 (A0), offset indirect fixedaddressing (see Section 9.2.3 on page 948) 1 (An), Cn indirect indexedaddressing (see Section 9.2.4 on page 948)

The Z flag is also set during this operation, depending on whether theresult (loaded into the Accumulator) is zero or not.

Implementation

10 Introduction

This chapter provides the high-level definition of a CPU capable ofimplementing the functionality required of an QA ChIP.

10.1 Physical Interface

10.1.1 Pin Connections

The pin connections are described in Table 370. TABLE 370 Pinconnections to QA Chip pin direction description Vdd In Nominal voltage.If the voltage deviates from this by more than a fixed amount, the chipwill RESET. GND In SClk In Serial clock SDa In/Out Serial data

The system operating clock SysClk is different to SClk. SysClk isderived from an internal ring oscillator based on the processtechnology. In the FPGA implementation SysClk is obtained via a 5th pin.

10.1.2 Size and Cost

The QA Chip uses a 0.25 μm CMOS Flash process for an area of 1 mm²yielding a 10 cent manufacturing cost in 2002. A breakdown of area islisted in Table 371. TABLE 371 Breakdown of Area for QA Chip approximatearea (mm²) description 0.49 8 KByte flash memory TSMC: SFC0008_08B9_HE(8K × 8-bits, erase page size = 512 bytes) Area = 724.688 μm × 682.05μm. 0.08 3072 bits of static RAM 0.38 General logic 0.05 Analogcircuitry 1 TOTAL (approximate)

Note that there is no specific test circuitry (scan chains or BIST)within the QA Chip (see Section 10.3.10 on page 965), so the totaltransistor count is as shown in Table 371.

10.1.3 Reset

The chip performs a RESET upon power-up. In addition, tamper detectionand prevention circuitry in the chip will cause the chip to either RESETor erase Flash memory (depending on the attack detected) if an attack isdetected.

10.2 Operating Speed

The base operating system clock SysClk is generated internally from aring oscillator (process dependant). Since the frequency varies withoperating temperature and voltage, the clock is passed through atemperature-based clock filter before use (see Section 10.3.3 on page961). The frequency is built into the chip during manufacture, andcannot be changed. The frequency is in the range 7-14 MHz.

10.3 General Manufacturing Comments

Manufacturing comments are not normally made when normally describingthe architecture of a chIP. However, in the case of the QA Chip, thephysical implementation of the chip is very much tied to the security ofthe key. Consequently a number of specialized circuits and componentsare necessary for implementation of the QA ChIP. They are listed here.

-   -   Flash process    -   Internal randomized clock    -   Temperature based clock filter    -   Noise generator    -   Tamper Prevention and Detection circuitry    -   Protected memory with tamper detection    -   Boot-strap circuitry for loading program code    -   Data connections in polysilicon layers where possible    -   OverUnderPower Detection Unit    -   No scan-chains or BIST        10.3.1 Flash Process

The QA Chip is implemented with a standard Flash manufacturing process.It is important that a Flash process be used to ensure that goodendurance is achieved (parts of the Flash memory can be erased/writtenmany times).

10.3.2 Internal Randomized Clock

To prevent clock glitching and external clock-based attacks, theoperating clock of the chip should be generated internally. This can beconveniently accomplished by an internal ring oscillator. The length ofthe ring depends on the process used for manufacturing the chIP.

Due to process and temperature variations, the clock needs to be trimmedto bring it into a range usable for timing of Flash memory writes anderases.

The internal clock should also contain a small amount of randomizationto prevent attacks where light emissions from switching events arecaptured, as described below.

Finally, the generated clock must be passed through a temperature-basedclock filter before being used by the rest of the chip (see Section10.3.3 on page 961).

The normal situation for FET implementation for the case of a CMOSinverter (which involves a pMOS transistor combined with an nMOStransistor) as shown in FIG. 353.

During the transition, there is a small period of time where both thenMOS transistor and the pMOS transistor have an intermediate resistance.The resultant power-ground short circuit causes a temporary increase inthe current, and in fact accounts for around 20% of current consumed bya CMOS device. A small amount of infrared light is emitted during theshort circuit, and can be viewed through the silicon substrate (siliconis transparent to infrared light). A small amount of light is alsoemitted during the charging and discharging of the transistor gatecapacitance and transmission line capacitance.

For circuitry that manipulates secret key information, such informationmust be kept hidden.

Fortunately, IBM's PICA system and LVP (laser voltage probe) both have arequirement for repeatability due to the fact that the photo emissionsare extremely weak (one photon requires more than 10⁵ switching events).PICA requires around 10⁹ pases to build a picture of the opticalwaveform. Similarly the LVP requires multiple passes to ensure anadequate SNR.

Randomizing the clock stops repeatability (from the point of view ofcollecting information about the same position in time), and thereforereduces the possibility of this attack.

10.3.3 Temperature Based Clock Filter

The QA Chip circuitry is designed to operate within a specific clockspeed range. Although the clock is generated by an internal ringoscillator, the speed varies with temperature and power. Since the usersupplies the temperature and power, it is possible for an attacker toattempt to introduce race-conditions in the circuitry at specific timesduring processing. An example of this is where a low temperature causesa clock speed higher than the circuitry is designed for, and this mayprevent an XOR from working properly, and of the two inputs, the firstmay always be returned. These styles of transient fault attacks aredocumented further in [1]. The lesson to be learned from this is thatthe input power and operating temperature cannot be trusted.

Since the chip contains a specific power filter, we must also filter theclock. This can be achieved with a temperature sensor that allows theclock pulses through only when the temperature range is such that thechip can function correctly.

The filtered clock signal would be further divided internally asrequired.

10.3.4 Noise Generator

Each QA Chip should contain a noise generator that generates continuouscircuit noise. The noise will interfere with other electromagneticemissions from the chip's regular activities and add noise to the I_(dd)signal. Placement of the noise generator is not an issue on an QA Chipdue to the length of the emission wavelengths.

The noise generator is used to generate electronic noise, multiple statechanges each clock cycle, and as a source of pseudo-random bits for theTamper Prevention and Detection circuitry (see Section 10.3.5 on page962).

A simple implementation of a noise generator is a 64-bit maximal periodLFSR seeded with a non-zero number.

10.3.5 Tamper Prevention and Detection Circuitry

A set of circuits is required to test for and prevent physical attackson the QA ChIP. However what is actually detected as an attack may notbe an intentional physical attack. It is therefore important todistinguish between these two types of attacks in an QA Chip:

-   -   where you can be certain that a physical attack has occurred.    -   where you cannot be certain that a physical attack has occurred.

The two types of detection differ in what is performed as a result ofthe detection. In the first case, where the circuitry can be certainthat a true physical attack has occurred, erasure of flash memory keyinformation is a sensible action. In the second case, where thecircuitry cannot be sure if an attack has occurred, there is stillcertainly something wrong. Action must be taken, but the action shouldnot be the erasure of secret key information. A suitable action to takein the second case is a chip RESET. If what was detected was an attackthat has permanently damaged the chip, the same conditions will occurnext time and the chip will RESET again. If, on the other hand, what wasdetected was part of the normal operating environment of the chip, aRESET will not harm the key.

A good example of an event that circuitry cannot have knowledge about,is a power glitch. The glitch may be an intentional attack, attemptingto reveal information about the key. It may, however, be the result of afaulty connection, or simply the start of a power-down sequence. It istherefore best to only RESET the chip, and not erase the key. If thechip was powering down, nothing is lost.

If the System is faulty, repeated RESETs will cause the consumer to getthe System repaired. In both cases the consumable is still intact.

A good example of an event that circuitry can have knowledge about, isthe cutting of a data line within the chIP. If this attack is somehowdetected, it could only be a result of a faulty chip (manufacturingdefect) or an attack. In either case, the erasure of the secretinformation is a sensible step to take.

Consequently each QA Chip should have 2 Tamper Detection Lines—one fordefinite attacks, and one for possible attacks. Connected to theseTamper Detection Lines would be a number of Tamper Detection test units,each testing for different forms of tampering. In addition, we want toensure that the Tamper Detection Lines and Circuits themselves cannotalso be tampered with.

At one end of the Tamper Detection Line is a source of pseudo-randombits (clocking at high speed compared to the general operatingcircuitry). The Noise Generator circuit described above is an adequatesource. The generated bits pass through two different paths—one carriesthe original data, and the other carries the inverse of the data. Thewires carrying these bits are in the layer above the general chipcircuitry (for example, the memory, the key manipulation circuitryetc.). The wires must also cover the random bit generator. The bits arerecombined at a number of places via an XOR gate. If the bits aredifferent (they should be), a 1 is output, and used by the particularunit (for example, each output bit from a memory read should be ANDedwith this bit value). The lines finally come together at the Flashmemory Erase circuit, where a complete erasure is triggered by a 0 fromthe XOR. Attached to the line is a number of triggers, each detecting aphysical attack on the chIP. Each trigger has an oversize nMOStransistor attached to GND. The Tamper Detection Line physically goesthrough this nMOS transistor. If the test fails, the trigger causes theTamper Detect Line to become 0. The XOR test will therefore fail oneither this clock cycle or the next one (on average), thus RESETing orerasing the chIP.

FIG. 349 illustrates the basic principle of a Tamper Detection Line interms of tests and the XOR connected to either the Erase or RESETcircuitry.

The Tamper Detection Line must go through the drain of an outputtransistor for each test, as illustrated by FIG. 350.

It is not possible to break the Tamper Detect Line since this would stopthe flow of 1 s and 0s from the random source. The XOR tests wouldtherefore fail. As the Tamper Detect Line physically passes through eachtest, it is not possible to eliminate any particular test withoutbreaking the Tamper Detect Line.

It is important that the XORs take values from a variety of places alongthe Tamper Detect Lines in order to reduce the chances of an attack.FIG. 351 illustrates the taking of multiple XORs from the Tamper DetectLine to be used in the different parts of the chIP. Each of these XORscan be considered to be generating a ChipOK bit that can be used withineach unit or sub-unit.

A typical usage would be to have an OK bit in each unit that is ANDedwith a given ChipOK bit each cycle. The OK bit is loaded with 1 on aRESET. If OK is 0, that unit will fail until the next RESET. If theTamper Detect Line is functioning correctly, the chip will either RESETor erase all key information. If the RESET or erase circuitry has beendestroyed, then this unit will not function, thus thwarting an attacker.

The destination of the RESET and Erase line and associated circuitry isvery context sensitive. It needs to be protected in much the same way asthe individual tamper tests. There is no point generating a RESET pulseif the attacker can simply cut the wire leading to the RESET circuitry.

The actual implementation will depend very much on what is to be clearedat RESET, and how those items are cleared.

Finally, FIG. 352 shows how the Tamper Lines cover the noise generatorcircuitry of the chIP. The generator and NOT gate are on one level,while the Tamper Detect Lines run on a level above the generator.

10.3.6 Protected Memory with Tamper Detection

It is not enough to simply store secret information or program code inflash memory. The Flash memory and RAM must be protected from anattacker who would attempt to modify (or set) a particular bit ofprogram code or key information. The mechanism used must conform tobeing used in the Tamper Detection Circuitry (described above).

The first part of the solution is to ensure that the Tamper DetectionLine passes directly above each flash or RAM bit. This ensures that anattacker cannot probe the contents of flash or RAM. A breach of thecovering wire is a break in the Tamper Detection Line. The breach causesthe Erase signal to be set, thus deleting any contents of the memory.The high frequency noise on the Tamper Detection Line also obscurespassive observation.

The second part of the solution for flash is to always store the datawith its inverse. In each byte, 4 bits contains the data, and 4 bits(the shadow) contains the inverse of the data. If both are 0, this is avalid erase state, and the value is 0. Otherwise, the memory is onlyvalid if the 4 bits of shadow are the inverse of the main 4 bits. Thereasoning is that it is possible to add electrons to flash via a FIB,but not take electrons away. If it is possible to change a 0 to 1 forexample, it is not possible to do the same to its inverse, and thereforeregardless of the sense of flash, an attack can be detected.

The second part of the solution for RAM is to use a parity bit. The datapart of the register can be checked against the parity bit (which willnot match after an attack).

The bits coming from Flash and RAM can therefore be validated by anumber of test units (one per bit) connected to the common TamperDetection Line. The Tamper Detection circuitry would be the firstcircuitry the data passes through (thus stopping an attacker fromcutting the data lines).

In addition, the data and program code should be stored in differentlocations for each chip, so an attacker does not know where to launch anattack. Finally, XORing the data coming in and going to Flash with arandom number that varies for each chip means that the attacker cannotlearn anything about the key by setting or clearing an individual bitthat has a probability of being the key (the inverse of the key mustalso be stored somewhere in flash).

Finally, each time the chip is called, every flash location is readbefore performing any program code. This allows the flash tamperdetection to be activated in a common spot instead of when the data isactually used or program code executed. This reduces the ability of anattacker to know exactly what was written to.

10.3.7 Boot-Strap Circuitry for Loading Program Code

Program code should be kept in protected flash instead of ROM, since ROMis subject to being altered in a non-testable way. A boot-strapmechanism is therefore required to load the program code into flashmemory (flash memory is in an indeterminate state after manufacture).

The boot-strap circuitry must not be in a ROM—a small state-machinesuffices. Otherwise the boot code could be trivially modified in anundetectable way.

The boot-strap circuitry must erase all flash memory, check to ensurethe erasure worked, and then load the program code.

The program code should only be executed once the flash program memoryhas been validated via Program Mode.

Once the final program has been loaded, a fuse can be blown to preventfurther programming of the chIP.

10.3.8 Connections in Polysilicon Layers Where Possible

Wherever possible, the connections along which the key or secret dataflows, should be made in the polysilicon layers. Where necessary, theycan be in metal 1, but must never be in the top metal layer (containingthe Tamper Detection Lines).

10.3.9 OverUnder Power Detection Unit

Each QA Chip requires an OverUnder Power Detection Unit (PDU) to preventPower Supply Attacks. A PDU detects power glitches and tests the powerlevel against a Voltage Reference to ensure it is within a certaintolerance. The Unit contains a single Voltage Reference and twocomparators. The PDU would be connected into the RESET Tamper DetectionLine, thus causing a RESET when triggered.

A side effect of the PDU is that as the voltage drops during apower-down, a RESET is triggered, thus erasing any work registers.

10.3.10 No Scan Chains or BIST

Test hardware on an QA Chip could very easily introduce vulnerabilities.In addition, due to the small size of the QA Chip logic, test hardwaresuch as scan paths and BIST units could in fact take a sizeable chunk ofthe final chip, lowering yield and causing a situation where an error inthe test hardware causes the chip to be unusable. As a result, the QAChip should not contain any BIST or scan paths. Instead, the programmemory must first be validated via the Program Mode mechanism, and thena series of program tests run to verify the remaining parts of the chIP.

11 Architecture

FIG. 389 shows a high level block diagram of the QA ChIP. Note that thetamper prevention and detection circuitry is not shown.

11.1 Analogue Unit

FIG. 390 shows a block diagram of the Analogue Unit. Blocks shown inyellow provide additional protection against physical and electricalattack and, depending on the level of security required, may optionallybe implemented.

11.1.1 Ring Oscillator

The operating clock of the chip (SysClk) is generated by an internalring oscillator whose frequency can be trimmed to reduce the variationfrom 4:1 (due to process and temperature) down to 2:1 (temperaturevariations only) in order to satisfy the timing requirements of theFlash memory.

The length of the ring depends on the process used for manufacturing thechIP. A nominal operating frequency range of 10 MHz is sufficient. Thisclock should contain a small amount of randomization to prevent attackswhere light emissions from switching events are captured.

Note that this is different to the input SClk which is the serial clockfor external communication.

The ring oscillator is covered by both Tamper Detection and Preventionlines so that if an attacker attempts to tamper with the unit, the chipwill either RESET or erase all secret information.

FPGA Note: the FPGA does not have an internal ring oscillator. Anadditional pin (SysClk) is used instead. This is replaced by an internalring oscillator in the final ASIC.

11.1.2 Voltage Reference

The voltage reference block maintains an output which is substantiallyindependent of process, supply voltage and temperature. It provides areference voltage which is used by the PDU and a reference current tostabilise the ring oscillator. It may also be used as part of thetemperature based clock filter described in Section 10.3.3 on page 961.

11.1.3 OverUnder Power Detection Unit

The OverUnder Power Detection Unit (PDU) is the same as that describedin Section 10.3.9 on page 965.

The Under Voltage Detection Unit provides the signal PwrFailing which,if asserted, indicates that the power supply may be turning off. Thissignal is used to rapidly terminate any Flash write that may be inprogress to avoid accidentally writing to an indeterminate memorylocation.

Note that the PDU triggers the RESET Tamper Detection Line only. It doesnot trigger the Erase Tamper Detection Line.

The PDU can be implemented with regular CMOS, since the key does notpass through this unit. It does not have to be implemented withnon-flashing CMOS.

The PDU is covered by both Tamper Detection and Prevention lines so thatif an attacker attempts to tamper with the unit, the chip will eitherRESET or erase all secret information.

11.1.4 Power-On Reset and Tamper Detect Unit

The Power-on Reset unit (POR) detects a power-on condition and generatesthe PORstL signal that is fed to all the validation units, including thetwo inside the Tamper Detect Unit (TDU).

All other logic is connected to RstL, which is the PORstL gated by theVAL unit attached to the Reset tamper detection lines (see Section10.3.5 on page 962) within the TDU. Therefore, if the Reset tamper lineis asserted, the validation will drive RstL low, and can only be clearedby a power-down. If the tamper line is not asserted, then RstL=PORstL.

The TDU contains a second VAL unit attached to the Erase tamperdetection lines (see Section 10.3.5 on page 962) within the TDU. Itproduces a TamperEraseOK signal that is output to the MIU (1=the tamperlines are all OK, 0=force an erasure of Flash).

11.1.5 Noise Generator

The Noise Generator (NG) is the same as that described in Section 10.3.4on page 961. It is based on a 64-bit maximal period LFSR loaded with aset non-zero bit pattern on RESET.

The NG must be protected by both Tamper Detection and Prevention linesso that if an attacker attempts to tamper with the unit, the chip willeither RESET or erase all secret information.

In addition, the bits in the LFSR must be validated to ensure they havenot been tampered with (i.e. a parity check). If the parity check fails,the Erase Tamper Detection Line is triggered.

Finally, all 64 bits of the NG are ORed into a single bit. If this bitis 0, the Erase Tamper Detection Line is triggered. This is because 0 isan invalid state for an LFSR.

11.2 Trim Unit

The 8-bit Trim register within the Trim Unit has a reset value of0x00(to enable the flash reads to succeed even in the fastest processcorners), and is written to either by the PMU during Trim Mode or by theCPU in Active Mode. Note that the CPU is only able to write once to theTrim register between power-on-reset due to the TrimDone flag whichprovides overloading of LocalidWE.

The reset value of Trim (0) means that the chip has a nominal frequencyof 2.7 MHz-10 MHz. The upper of the range is when we cannot trim itlower than this (or we could allow some spread on the acceptable trimmedfrequency but this will reduce our tolerance to ageing, voltage andtemperature which is the range 7 MHz to 14 MHz). The 2.7 MHz value isdetermined by a chip whose oscillator runs at 10 MHz when the trimregister is set to its maximum value, so then it must run at 2.7 MHzwhen trim=0. This is based on the non-linear frequency-currentcharacteristic of the oscillator.

Chips found outside of these limits will be rejected.

The frequency of the ring oscillator is measured by counting cycles⁶, inthe PMU, over the byte period of the serial interface. The frequency ofthe serial clock, SClk, and therefore the byte period will be accuratelycontrolled during the measurement. The cycle count (Fineas) at the endof the period is read over the serial bus and the Trim register updated(Trimval) from its power on default (POD) value. The steps are shown inFIG. 391. Multiple measure—read—trim cycles are possible to improve theaccuracy of the trim procedure.6Note that the PMU counts using 12-bits, saturates at 0xFFF, and returnsthe cycle count divided by 2 as an 8-bit value. This means that multiplemeasure-read-trim cycles may be necessary to resolve any amibguity. Inany case, multiple cycles are necessary to test the correctness of thetrim circuitry during manufacture test.

A single byte for both Fineas and Trimval provide sufficient accuracyfor measurement and trimming of the frequency. If the bus operates at400 kHz, a byte (8 bits) can be sent in 20 μs. By dividing the maximumoscillator frequency, expected to be 20 MHz, by 2 results in a cyclecount of 200 and 50 for the minimum frequency of 5 MHz resulting in aworst case accuracy of 2%.

FIG. 392 shows a block diagram of the Trim Unit:

The 8-bit Trim value is used in the analog Trim Block to adjust thefrequency of the ring oscillator by controlling its bias current. Thetwo lsbs are used as a voltage trim, and the 6 msbs are used as afrequency trim.

The analog Trim Clock circuit also contains a Temperature filter asdescribed in Section 10.3.3 on page 961.

11.310 Unit

The QA Chip acts as a slave device, accepting serial data from anexternal master via the IO Unit (IOU). Although the IOU actuallytransmits data over a 1-bit line, the data is always transmitted andreceived in 1-byte chunks.

The IOU receives commands from the master to place it in a specificoperating mode, which is one of:

-   -   Idle Mode: is the startup mode for the IOU if the fuse has not        yet been blown. Idle Mode is the mode where the QA Chip is        waiting for the next command from the master. Input signals from        the CPU are ignored.    -   Program Mode: is where the QA Chip erases all currently stored        data in the Flash memory (program and secret key information)        and then allows new data to be written to the Flash. The IOU        stays in Program Mode until told to enter another mode.    -   Active Mode: is the startup mode for the IOU if the fuse has        been blown (the program is safe to run). Active Mode is where        the QA Chip allows the program code to be executed to process        the master's specific command. The IOU returns to Idle Mode        automatically when the command has been processed, or if the        time taken between consuming input bytes (while the master is        writing the data) or generating output bytes (while the master        is reading the results) is too great.    -   Trim Mode: is where the QA Chip allows the generation and        setting of a trim value to be used on the internal ring        oscillator clock value. This must be done for safety reasons        before a program can be stored in the Flash memory.

See Section 12 on page 970 for detailed information about the IOU.

11.4 Central Processing Unit

The Central Processing Unit (CPU) block provides the majority of thecircuitry of the 4-bit microprocessor. FIG. 393 shows a high level viewof the block.

11.5 Memory Interface Unit

The Memory Interface Unit (MIU) provides the interface to flash and RAM.The MIU contains a Program Mode Unit that allows flash memory to beloaded via the IOU, a Memory Request Unit that maps 8-bit and 32-bitrequests into multiple byte based requests, and a Memory Access Unitthat generates read/write strobes for individual accesses to the memory.

FIG. 394 shows a high level view of the MIU block.

11.6 Memory Components

The Memory Components block isolates the memory implementation from therest of the QA ChIP. The entire contents of the Memory Components blockmust be protected from tampering. Therefore the logic must be covered byboth Tamper Detection Lines. This is to ensure that program code, keys,and intermediate data values cannot be changed by an attacker. The 8-bitwide RAM also needs to be parity-checked.

FIG. 395 shows a high level view of the Memory Components block. Itconsists of 8 KBytes of flash memory and 3072 bits of parity checkedRAM.

11.6.1 RAM

The RAM block is shown here as a simple 96×32-bit RAM (plus parityincluded for verification).

The parity bit is generated during the write.

The RAM is in an unknown state after RESET, so program code cannot relyon RAM being 0 at startup.

The initial version of the ASIC has the RAM implemented by Artisancomponent RA1SH (96×32-bit RAM without parity). Note that the RAMOutEnport is active low i.e. when 0, the RAM is enabled, and when 1, the RAMis disabled.

11.6.2 Flash Memory

A single Flash memory block is used to hold all non-volatile data. Thisincludes program code and variables. The Flash memory block isimplemented by TSMC component SFC0008_(—)08B9_HE [4], which has thefollowing characteristics:

-   -   8 K×8-bit main memory, plus 128×8-bit information memory    -   512 byte page erase    -   Endurance of 20,000 cycles (min)    -   Greater than 100 years data retention at room temperature    -   Access time: 20 ns (max)    -   Byte write time: 20 μs (min)    -   Page erase time: 20 ms (min)    -   Device erase time: 200 ms (min)    -   Area of 0.494 mm² (724.66 μm×682.05 μm)

The FlashCtrl line are the various inputs on the SFC0008_(—)08B9_HErequired to read and write bytes, erase pages and erase the device. Atotal of 9 bits are required (see [4] for more information).

Flash values are unchanged by a RESET. After manufacture, the Flashcontents must be considered to be garbage. After an erasure, the Flashcontents in the SFC0008_(—)08B9_HE is all 1 s.

11.6.3 VAL Blocks

The two VAL units are validation units connected to the TamperPrevention and Detection circuitry (described in Section 10.3.5 on page962), each with an OK bit. The OK bit is set to 1 on PORstL, and ORedwith the ChipOK values from both Tamper Detection Lines each cycle. TheOK bit is ANDed with each data bit that passes through the unit.

In the case of VAL₁, the effective byte output from the flash willalways be 0 if the chip has been tampered with. This will cause shadowtests to fail, program code will not execute, and the chip will hang.

In the case of VAL₂, the effective byte from RAM will always be 0 if thechip has been tampered with, thus resulting in no temporary storage foruse by an attacker.

12 IO Unit

The I/O Unit (IOU) is responsible for providing the physicalimplementation of the logical interface described in Section 5.1 on page933, moving between the various modes (Idle, Program, Trim and Active)according to commands sent by the master.

The IOU therefore contains the circuitry for communicating externallywith the external world via the SClk and SDa pins. The IOU sends andreceives data in 8-bit chunks. Data is sent serially, most significantbit (bit 7) first through to least significant bit (bit 0) last. When amaster sends a command to an QA Chip, the command commences with asingle byte containing an id in bits 7-1, and a read/write sense in bit0, as shown in FIG. 396.

The IOU recognizes a global id of 0x00 and a local id of LocalId (setafter the CPU has executed program code at reset or due to a globalid/ActiveMode command on the serial bus). Subsequent bytes contain modalinformation in the case of global ID, and command/data bytes in the caseof a match with the local id.

If the master sends data too fast, then the IOU will miss data, sincethe IOU never holds the bus.

The meaning of too fast depends on what is running. In Program Mode, themaster must send data a little slower than the time it takes to writethe byte to flash (actually written as 2×8-bit writes, or 40 μs). InActiveMode, the master is permitted to send and request data at rates upto 500 KHz.

None of the latches in the IOU need to be parity checked since there isno advantage for an attacker to destroy or modify them.

The IOU outputs 0s and inputs 0s if either of the Tamper Detection Linesis broken. This will only come into effect if an attacker has disabledthe RESET and/or erase circuitry, since breaking either Tamper DetectionLines should result in a RESET or the erasure of all Flash memory.

The IOU's InByte, InByteValID, OutByte, and OutByteValid registers areused for communication between the master and the QA ChIP. InByte andInByteValid provide the means for clients to pass commands and data tothe QA ChIP. OutByte and OutByteValid provide the means for the masterto read data from the QA ChIP.

-   -   Reads from InByte should wait until InByteValid is set.        InByteValid will remain clear until the master has written the        next input byte to the QA ChIP. When the IOU is told (by the FEU        or MU) that InByte has been read, the IOU clears the InByteValid        bit to allow the next byte to be read from the client.    -   Writes to OutByte should wait until OutByteValid is clear.        Writing OutByte sets the OutByteValid bit to signify that data        is available to be transmitted to the master. OutByteValid will        then remain set until the master has read the data from OutByte.        If the master requests a byte but OutByteValid is clear, the IOU        sends a NAck to indicate the data is not yet ready.

When the chip is reset via RstL, the IOU enters ActiveMode to allow thePMU to run to load the fuse. Once the fuse has been loaded (whenMlUAvail transitions from 0 to 1) the IOU checks to see if the programis known to be safe. If it is not safe, the IOU reverts to IdleMode. Ifit is safe (FuseBlown=1), the IOU stays in ActiveMode to allow theprogram to load up the localId and do any other reset initialization,and will not process any further serial commands until the CPU haswritten a byte to the OutByte register (which may be read or not at thediscretion of the master using a localId read). In both cases the masteris then able to send commands to the QA Chip as described in Section 5.1on page 933.

FIG. 397 shows a block diagram of the IOU.

With regards to InByteValid inputs, set has priority over reset,although both set and reset in correct operation should never beasserted at the same time. With regards to IOSetInByte and IOLoadInByte,if IOSetInByte is asserted, it will set InByte to be 0xFF regardless ofthe setting of IOLoadInByte.

The two VAL units are validation units connected to the TamperPrevention and Detection circuitry (described in Section 10.3.5 of theArchitecture Overview chapter), each with an OK bit. The OK bit is setto 1 on PORstL, and ORed with the ChipOK values from both TamperDetection Lines each cycle. The OK bit is ANDed with each data bit thatpasses through the unit.

In the case of VAL₁, the effective byte output from the chip will alwaysbe 0 if the chip has been tampered with. Thus no useful output can begenerated by an attacker. In the case of VAL2, the effective byte inputto the chip will always be 0 if the chip has been tampered with. Thus nouseful input can be chosen by an attacker.

There is no need to verify the registers in the IOU since an attackerdoes not gain anything by destroying or modifying them.

The current mode of the IOU is output as a 2-bit IOMode to allow theother units within the QA Chip to take correct action. IOMode is definedas shown in Table 372: TABLE 372 IOMode values Value Interpretation 00Idle Mode 01 Program Mode 10 Active Mode 11 Trim Mode

The Logic blocks generate a 1 if the current IOMode is in Program Mode,Active Mode or Trim Mode respectively. The logic blocks are: Logic₁IOMode = 01 (Program) Logic₂ IOMode = 10 (Active) Logic₃ IOMode = 11(Trim)12.1 State Machine

There are two state machines in the IOU running in parallel. The firstis a byte-oriented state machine, the second is a bit-oriented statemachine. The byte-oriented state machine keeps track of the operatingmode of the QA Chip while the bit-oriented state machine keeps track ofthe low-level bit Rx/Tx protocol.

The SDa and SClk lines are connected to the respective pads on the QAChIP. The IOU passes each of the signals from the pads through 2 D-typesto compensate for metastability on input, and then a further latch andcomparitor to ensure that signals are only used if stable for 2consecutive internal clock cycles. The circuit is shown in Section12.1.1 below.

12.1.1 Start/Stop Control Signals

The StartDetected and StopDetected control signals are generated basedupon monitoring SDa synchronized to SClk. The StartDetected condition isasserted on the falling edge of SDa synchronized to SClk, and theStopDetected condition is asserted on the rising edge of SDasynchronized to SClk.

In addition we generate feSClk which is asserted on the falling edge ofSClk, and reSClk which is asserted on the rising edge of SClk. Finally,feSclkPrev is the value of feSClk delayed by a single cycle. FIG. 398shows the relationship of inputs and the generation of SDaReg, reSClk,feSClk, feSclkPrev, StartDetected and StopDetected.

The SDaRegSelect logic compensates for the 2:1 variation in clockfrequency. It uses the length of the high period of the SClk (from thesaturating counter) to select between sda5, sda6 and sda7 as the validdata from 300 ns before the falling edge of SClk as follows.

The minimum time for the high period of SClk is 600 ns. If the counter<=4 (i.e. 5 or fewer cycles with SClk=1) then SDaReg output=sda5 (samplepoint is equidistant from rising and falling edges). If the counter=5 or6 (i.e. 6 or 7 samples where SClk=1), then SDaReg output=sda6. If thecounter=7 (the counter saturates when there are 8 samples of SClk=1),then SDaReg output=sda7. This is shown in pseducode below: If ((counter₂= 0)

(counter = 4))    SDaReg = sda5   ElseIf (counter = 7)    SDaReg = sda7)  Else    SDaReg = sda6   EndIf

The counter also provides a means of enabling start and stop detection.There is a minimum of a 600 ns setup and 600 ns hold time for start andstop conditions. At 14 MHz this means samples 4 and 5 after the risingedge (sample 1 is considered to be the first sample where SClk=1) couldpotentially include a valid start or stop condition. At 7 MHz samples 4and 5 represent 284 and 355 ns respectively, although this is after therising edge of SClk, which itself is 100 ns after the setup of data(i.e. 384 and 455 ns respectively and therefore safe for sampling). Thusthe data will be stable (although not a start or stop). Since we detectstops and starts using sda5 and sda6, we can only validly detect startsand stops 6 cycles after a rising edge, and we need to not-detect startsand stops 4 cycles before the falling edge. We therefore only detectstarts and stops when the counter is >=6 (i.e. when sclk3 and scik2 are0 and 1 respectively, sda2 holds sample 1 coincident with the risingedge, sdal holds sample 2, sda0 holds sample 3, we load the counter with0 and sample SDa to obtain the new sda0 which will hold sample 4 at theend of the cycle. Thus while the counter is incrementing from 0 to 1,sda0 will hold sample 4. Therefore sample 4 will be in sda6 when thecounter is 6.

12.1.2 Control of SDa and SClk Pins

The SClk line is always driven by the master. The SDa line is driven lowwhenever we want to transmit an ACK (SDa is active low) or a 0-bit fromOutByte. The generation of the SDa pin is shown in the followingpseudocode: TxAck = (bitSM_state = ack)

((byteSM_state = doWrite)

  (((byteSM_state = getGlobalCmd)

(byteSM_state = checkId))

AckCmd)) TxBit

(byteSM_state = doRead)

(bitSM_state = xferBit)

OutByte_(bitCount) SDa =

(TxAck

TxBit) # only drive the line when we are xmitting a 0

The slew rate of the SDa line should be restricted to minimise groundbounce. The pad must guarantee a fall time >20 ns. The rise time will becontrolled by the external pull up resistor and bus capacitance.

12.1.3 Bit-Oriented State Machine

The bit-oriented state machine keeps track of the general flow of serialtransmission including start/data/ack/stop as shown in the followingpseudocode: idle  EndByte = FALSE  EndAck = FALSE  If (StartDetected)  state

starting  Else   state

idle  EndIf starting  EndByte = FALSE  EndAck = FALSE  NAck

0  If (StopDetected)   state

idle  ElseIf (feSClkPrev)   bitCount

0   state

xferBit  Else   state

starting# includes StartDetected  EndIf xferBit  EndAck = FALSE  EndByte= (feSclkPrev

(bitCount = 0)) # after feSclk bitCount must be 1..8  If (feSClk)  shiftLeft[ioByte, SDaReg] # capture the bit in the ioByte shiftregister   bitCount

bitCount + 1# modulo count due to 3 bit bitCount  EndIf  If(StopDetected)   state

idle  ElseIf (StartDetected)   state

starting  ElseIf (EndByte)   state

ack  Else   state

xferBit  EndIf ack  EndByte = FALSE  EndAck = feSclkPrev  If(StopDetected)   state

idle  ElseIf (StartDetected)   state

starting  ElseIf (EndAck)   state

xferBit # bitCount is already 0  Else   If (feSClk)    NAck

SDaReg    # active low, so 0 = ACK, 1 = NACK   EndIf   state

ack  EndIf12.1.4 Byte-Oriented State Machine

The following pseudocode illustrates the general startup state of theIOU and the receipt of a transmission from the master. rstL # setupstate of registers on reset  IOMode

ActiveMode # to force the fuse to be loaded  OutByteValid

0  OutByte

0  InByteValid

1 # required  InByte

0xFF   # byte = FF = the ‘reset’ command  localId

0  # loads localId with the globalId so no localId exists  state

wait4fuse wait4fuse  If (MIUAvail)   If (FuseBlown)# this must be donesame cycle as seeing MIUAvail go high    state

wait4cpu   Else    IOMode

IdleMode # CPU will now require an external ActiveMode to start    state

idle  Else   state

wait4fuse  EndIf wait4cpu  If (CPUOutByteWE)  # wait for CPU resetactivities to finish   state

idle      # note: we're still in ActiveMode  Else   state

wait4cpu  EndIf idle  If (StartDetected)   state

checkId  Else   state

idle  EndIf

The first byte received must be checked to ensure it is meant foreveryone (globaild of 0) or specifically for us (localid matches). Weonly send an ACK to a read when there is data available to send. Inaddition, writes to the general call address (0) are always ACKed, butreads from the general call address are only ACKed before the fuse hasbeen blown. checkId  isWrite = (ioByte₀ = 0)  isRead = (ioByte₀ = 1) isGlobal = (ioByte₇₋₁ = 0)  globalW = isGlobal

isWrite  localW = (ioByte₇₋₁ = localID)

isWrite

isGlobal  localR = (ioByte₇₋₁ = localID)

isRead

(

GlobalW

FuseBlown)  If (StopDetected)   state

idle  ElseIf (EndByte)   AckCmd_in = (globalW

localW)

(localR

OutByteValid)   AckCmd

AckCmd_in   If (localW)    IOMode

IdleMode # jic - any output was pending    IOOutByteUsed = 1  IOClearInByte = 1 # ensure there is nothing hanging around from before  EndIf  ElseIf (EndAck)   If (globalW) # globalW and localW aremutually exclusive    state

getGlobalCmd  ElseIf (localW)    IOMode

ActiveMode    IOLoadInByte = 1 # will set inByte to localW (lsb will be0)    state

doWrite   ElseIf (localR

IOMode₁

AckCmd) # Active mode (or Trim when fuse intact)    state

doRead   Else    state

idle # ignore reads unless first in active or trim mode   EndIf  Else  state

checkId  EndIf

With a new global command the IOU waits for the mode byte (see Tablepage6 on page 934) to determine the new operating mode: getGlobalCmd wantProg = ((ioByte = ProgramModeId)

FuseBlown)  wantTrim = ((ioByte = TrimModeId)

FuseBlown)  wantActive = (ioByte = ActiveModeId)  If (StopDetected)  state

idle  ElseIf (StartDetected)   state

checkId  ElseIf (EndByte)   AckCmd_in = wantActive

wantProg

wantTrim # only ACK cmds we can do   AckCmd

AckCmd_in   If (AckCmd_in)    IOMode

IdleMode # jic - any output was pending    IOOutByteUsed = 1   IOClearInByte = 1 # ensure there is nothing hanging around frombefore   EndIf  ElseIf (EndAck)   If (wantProg)    IOMode

ProgramMode # don't load inByte (we only want the data)    state

doWrite   ElseIf (wantTrim)    IOMode

TrimMode # don't load InByte (we only want the next byte)    state

doWrite   ElseIf (wantActive) # must be Active    IOMode

ActiveMode    IOSetInByte = 1 # 0 for all other cases & states. 1 = setsinByte to 0xFF    IOLoadInByte = 1 # sets InByteValid (InByte is set to0xFF (‘reset’ cmd))    state

wait4cpu# don't do anything til the cpu has completed this task   Else   state

idle # unknown id, so ignore remainder   EndIf  Else   state

getGlobalCmd  EndIf

When the master writes bytes to the QA Chip (e.g. parameters for acommand), the program must consume the byte fast enough (i.e. during thesending of the ACK) or subsequent bits may be lost.

The process of receiving bytes is shown in the following pseudocode:doWrite  If (StopDetected)   state

idle    # stay in whatever IOMode we were in  ElseIf (StartDetected)  state

checkId  Else   If (EndByte)    IOLoadInByte =

InByteValid   EndIf   If (EndByte

InByteValid) # will only be when master sends data too quickly    state

idle          # ACK will not be sent when in idle state   Else    state

doWrite # ACK will be sent automatically after byte is Rxed   EndIf EndIf

When the master wants to read, the IOU sends one byte at a time asrequested. The process is shown in the following pseudocode: doRead If(StopDetected)   state

idle ElseIf (StartDetected)   state

checkId ElseIf (EndAck)   If (NAck

OutByteValid)     state

idle   Else     state

doRead   EndIf Else   If (EndByte)     IOOutByteUsed = 1   EndIf   state

doRead  EndIf13 Fetch and Execute Unit13.1 Introduction

The QA Chip does not require the high speeds and throughput of a generalpurpose CPU. It must operate fast enough to perform the authenticationprotocols, but not faster. Rather than have specialized circuitry foroptimizing branch control or executing opcodes while fetching the nextone (and all the complexity associated with that), the state machineadopts a simplistic view of the world. This helps to minimize designtime as well as reducing the possibility of error in implementation.

The FEU is responsible for generating the operating cycles of the CPU,stalling appropriately during long command operations due to memorylatency.

When a new transaction begins, the FEU will generate a JPZ (jump tozero) instruction.

The general operation of the FEU is to generate sets of cycles:

-   -   Cycle 0: fetch cycles. This is where the opcode is fetched from        the program memory, and the effective address from the fetched        opcode is generated. The Fetch output flag is set during the        final cycle 0 (i.e. when the opcode is finally valID).    -   Cycle 1: execute cycle. This is where the operand is        (potentially) looked up via the generated effective address        (from Cycle 0) and the operation itself is executed. The Exec        output flag is set during the final cycle 1 (i.e. when the        operand is finally valID).

Under normal conditions, the state machine generates multiple Cycle=0followed by multiple Cycle=1. This is because the program is stored inflash memory, and may take multiple cycles to read. In addition, writesto and erasures of flash memory take differing numbers of cycles toperform. The FEU will stall, generating multiple instances of the sameCycle value with Fetch and Exec both 0 until the input MIURdy=1,whereupon a Fetch or Exec pulse will be generated in that same cycle.

There are also two cases for stalling due to serial I/O operations:

-   -   The opcode is ROR OutByte, and OutByteValid=1. This means that        the current operation requires outputting a byte to the master,        but the master hasn't read the last byte yet.    -   The operation is ROR InByte, and InByteValid=0. This means that        the current operation requires reading a byte from the master,        but the master hasn't supplied the byte yet.

In both these cases, the FEU must stall until the stalling condition hasfinished.

Finally, the FEU must stop executing code if the IOU exits Active Mode.

The local Cmd opcode/operand latch needs to be parity-checked. The logicand registers contained in the FEU must be covered by both TamperDetection Lines. This is to ensure that the instructions to be executedare not changed by an attacker.

13.2 State Machine

The Fetch and Execute Unit (FEU) is combinatorial logic with thefollowing registers: TABLE 373 FEU Registers Name #bits DescriptionOutput registers (visible outside the FEU) Cycle 1 0 if the FEU iscurrently fetching an opcode, 1 if the FEU is currently executing theopcode. NewMemTrans 1 Is asserted during the start of a potential newmemory access. 0 = this is not the first cycle of a set of Cycle 0 orCycle 1 1 = this is the first cycle of a set of Cycle 0 or Cycle 1(previous cycle must have been a Fetch or an Exec). Go 1 1 if the FEU iscurrently fetching and executing program code (i.e. a program iscurrently running), 0 if it is not. Local registers (not visible outsidethe FEU) CurrCmd 8 + p Holds the currently executing instruction (paritychecked). PendingKill 1 The currently executing program is waiting to behalted (waiting due to memory access) PendingStart 1 A new transactionis waiting to be started (waiting due to memory access or an existingtransaction not yet stopped) WasIdle 1 The previous cycle had an IOModeof IdleMode.

In addition, the following externally visible outputs are generatedasynchronously: TABLE 374 Externally visible asynchronous FEU outputsName #bits Description Fetch 1 1 if the FEU is performing the finalcycle of a fetch (i.e. Cycle will also be 0). It is set when the NextCmdoutput is valid. The local Cmd register is latched during the Fetchcycle with either the incoming MIU8Data or an FEU-generated command.Exec 1 1 if the FEU is performing the final cycle of an execute (i.e.Cycle will also be 1). It is set when the data required by the opcodefrom the MIU is valid. Other units can execute the Cmd and latch datafrom the MIU (e.g. from MIUData) during the Exec cycle. Cmd 8 When Cycle= 0, this holds the next instruction to be executed (during the nextCycle = 1). Is generated based on incoming MIU8Data or substituted FEUcommand (e.g. JSR 0). When Cycle = 1, this holds the current instructionbeing executed (based on theCmd).

The Cycle and currCmd registers are not used directly. Instead, theiroutputs are passed through a VAL unit before use. The VAL units aredesigned to validate the data that passes through them. Each contains anOK bit connected to both Tamper Prevention and Detection Lines. The OKbit is set to 1 on PORstL, and ORed with the ChipOK values from bothTamper Detection Lines each cycle. The OK bit is ANDed with each databit that passes through the unit.

In the case of VAL₁, the effective Cycle will always be 0 if the chiphas been tampered with. Thus no program code will execute.

In the case of VAL₂, the effective 8-bit currCmd value will always be 0if the chip has been tampered with. Multiple 0s will be interpreted asthe JSR 0 instruction, and this will effectively hang the CPU. VAL₂ alsoperforms a parity check on the bits from currCmd to ensure that currCmdhas not been tampered with. If the parity check fails, the Erase TamperDetection Line is triggered. For more information on Tamper Preventionand Detection circuitry, see Section 10.3.5 on page 962.

13.2.1 Pseudocode

reset conditions:  Fetch = 0  Exec = 0  Cycle

0  currCmd

0  Go

0  pendingKill

0  pendingStart

0  newMemTrans

0  wasIdle

1# required to detect if IOU starts in a non-idle state

The cycle by cycle combinatorial logic behaviour is shown in thefollowing pseudocode: isActive = (IOMode = ActiveMode) wasIdle

(IOMode = IdleMode) wantToStart = (pendingStart

wasIdle)

isActive newTrans = wantToStart

Go

MIUAvail pendingStart

wantToStart

newTrans killTrans = Go

(

isActive

pendingKill) Fetch = newTrans

(Go

Cycle

MIURdy

killTrans) inDelay = (currCmd = ROR InByte)

InByteValid outDelay = (currCmd = ROR OutByte)

OutByteValid ioDelay = inDelay

outDelay Exec = Go

Cycle

MIURdy

ioDelay If (Cycle)  Cmd = currCmd ElseIf (newTrans)  Cmd = JPZ # jump to0 Else  Cmd = MIU8Data EndIf resetGo = (MIURdy

killTrans)

(Fetch

(Cmd = HALT)) pendingKill

killTrans

resetGo changeCycle = Fetch

Exec    # will only be 1 when Go = 1 Cycle

newTrans

((Cycle ⊕ changeCycle)

resetGo) newMemTrans

newTrans

(changeCycle

resetGo) If (Fetch)  currCmd

Cmd EndIf If (resetGo)  Go

0 ElseIf (newTrans)  Go

1 EndIf14 ALU

The Arithmetic Logic Unit (ALU) contains a 32-bit Acc (Accumulator)register as well as the circuitry for simple arithmetic and logicaloperations.

The logic and registers contained in the ALU must be covered by bothTamper Detection Lines. This is to ensure that keys and intermediatecalculation values cannot be changed by an attacker. In addition, theAccumulator must be parity-checked.

A 1-bit Z signal represents the state of zero-ness of the Accumulator.The Accumulator is cleared to 0 upon a RstL, and the Z signal is setto 1. The Accumulator is updated for any of the commands: AND, OR, XOR,ADD, ROR, and RIA, and the Z signal is updated whenever the Accumulatoris updated. Note that the Z signal is actually implemented as a nonZregister whose output is passed through an inverter and used as Z.

Each arithmetic and logical block operates on two 32-bit inputs: thecurrent value of the Accumulator, and the current 32-bit output of theDataSel block (either the 32 bit value from MIUData or an immediatevalue). The AND, OR, XOR and ADD blocks perform the standard 32-bitoperations. The remaining blocks are outlined below.

FIG. 399 shows a block diagram of the ALU:

The Accumulator is updated for all instructions where the high bit ofthe opcode is set: Logic₁ Exec

Cmd₇

Since the WriteEnables of Acc and nonZ takes Cmd7 and Exec into account(due to Logic₁), these two bits are not required by the multiplexor MX₁in order to select the output. The output selection for MX₁ onlyrequires bits 6-3 of the Cmd and is therefore simpler as a result (asshown in Table 375). TABLE 375 Selection for multiplexor MX₁ OutputCmd₆₋₃ MX₁ immOut 011x

1110 (LD) rorOut 100x

1111 (RIA, ROR) from XOR 001x

1100 (XOR) from ADD 010x

1101 (ADD) from AND 0000

1010 (AND) from OR 0001

1011 (OR)

The two VAL units are validation units connected to the TamperPrevention and Detection circuitry (described in Section 10.3.5 on page962), each with an OK bit. The OK bit is set to 1 on PORstL, and ORedwith the ChipOK values from both Tamper Detection Lines each cycle. TheOK bit is ANDed with each data bit that passes through the unit.

In the case of VAL₁, the effective bit output from the Accumulator willalways be 0 if the chip has been tampered with. This prevents anattacker from processing anything involving the Accumulator. VAL₁ alsoperforms a parity check on the Accumulator, setting the Erase TamperDetection Line if the check fails.

In the case of VAL₂, the effective Z status of the Accumulator willalways be true if the chip has been tampered with. Thus no loopingconstructs can be created by an attacker.

14.1 DataSel Block

The DataSel block is designed to implement the selection between theMIU32Data and the immediate addressing mode for logical commands.

Immediate addressing relies on 3 bits of operand, plus an optional 8bits at PC+1 to determine an 8-bit base value. Bits 0 to 1 determinewhether the base value comes from the opcode byte itself, or from PC+1,as shown in Table 376. TABLE 376 Selection for base value in immediatemode Cmd₁₋₀ Base value 00 00000000 01 00000001 10 From PC+1 (i.e.MIUData₃₁₋₂₄) 11 11111111

The base value is computed by using CMD₀ as bit 0, and copying CMD₁ intothe upper 7 bits.

The 8-bit base value forms the lower 8 bits of output. These 8 bits arealso ANDed with the sense of whether the data is replicated in the upperbits or not (i.e. CMD₂). The resultant bits are copied in 3 times toform the upper 24 bits of the output.

FIG. 400 shows a block diagram of the ALU's DataSel block:

14.2 ROR Block

The ROR block implements the ROR and RIA functionality of the ALU.

A 1-bit register named RTMP is contained within the ROR unit. RTMP iscleared to 0 on a RstL, and set during the ROR RB and ROR XRB commands.The RTMP register allows implementation of Linear Feedback ShiftRegisters with any tap configuration.

FIG. 401 shows a block diagram of the ALU's ROR block:

The ROR n, blocks are shown for clarity, but in fact would be hardwiredinto multiplexor MX₃, since each block is simply a rewiring of the32-bits, rotated right n bits.

Logic₁ is used to provide the WriteEnable signal to RTMP. The RTMPregister should only be written to during ROR RB and ROR XRB commands.The combinatorial logic block is: Logic₁ Exec

(Cmd₇₋₄ = ROR)

(Cmd₃₋₁ = 000)

Multiplexor MX₁ performs the task of selecting the 6-bit value from Cninstead of bits 13-8 (6 bits) from Acc (the selection is based on thevalue of Logic₂). Bit 5 is required to distinguish ROR from RIA. Logic₂Cmd₅₋₂ = 0x10

TABLE 377 Selection for multiplexor MX₁ Output Logic₂ MX₁ Cn 1 Acc₁₃₋₈ 0

Multiplexor MX₂ performs the task of selecting the 8-bit value fromInByte instead of the lower 8 bits from the ANDed Acc based on the CMD.TABLE 378 Selection for multiplexor MX₂ Output Cmd₄₋₀ MX₂ InByte 0x110Acc₇₋₀

(0x110)

Multiplexor MX₃ does the final rotating of the 32-bit value. The bitpatterns of the CMD operand are taken advantage of: TABLE 379 Selectionfor multiplexor MX₃ Output Cmd₃₋₀ Comments MX₃ ROR 1 00xx RB, XRB,WriteMask, 1 ROR 3 010x  3 ROR 31 0110 31 ROR 24 0111 24 ROR 8 1xxx RIA,InByte, 8, OutByte, C1, C2, ID14.3 IO Block

The IO block within the ALU implements the logic for communicating withthe IOU during instructions that involve the Accumulator. This includesgenerating appropriate control signals and for generating the correctdata for sending during writes to the IOU's OutByte and LocalIdregisters.

FIG. 402 shows a block diagram of the IO block:

Logic₁ is used to provide the LocalIdWE signal to the IOU. The localIdregister should only be written to during the ROR ID command. Only thelower 7 bits of the Accumulator are written to the localId register.

Logic₂ is used to provide the ALUOutByteWE signal to the IOU. TheOutByte register should only be written to during the ROR OutBytecommand. Only the lower 8 bits of the Accumulator are written to theOutByte register.

In both cases we output the lower 8 bits of the Accumulator. TheALUIOData value is ANDed with the output of Logic₂ to ensure thatALUIOData is only valid when it is safe to do so (thus the IOU logicnever sees the key passing by in ALUIOData). The combinatorial logicblocks are: Logic₁ Exec

(Cmd₇₋₀ = ROR ID) Logic₂ Exec

(Cmd₇₋₀ = ROR OutByte)

Logic₃ is used to provide the ALUInByteUsed signal to the IOU. TheInByte is only used during the ROR InByte command. The combinatoriallogic is: Logic₃ Exec

(Cmd₇₋₀ = ROR InByte)15 Program Counter Unit

The Program Counter Unit (PCU) includes the 12 bit PC (Program Counter),as well as logic for branching and subroutine control.

The PCU latches need to be parity-checked. In addition, the logic andregisters contained in the PCU must be covered by both Tamper DetectionLines to ensure that the PC cannot be changed by an attacker.

The PC is implemented as a 12 entry by 12-bit PCA (PC Array), indexed bya 4-bit SP (Stack Pointer) register. The PC, PCRamSel and SP registersare all cleared to 0 on a RstL, and updated during the flow of programcontrol according to the opcodes.

The current value for the PC is normally updated during the Executecycle according to the command being executed. However it is alsoincremented by 1 during the Fetch cycle for two byte instructions suchas JMP, JSR, DBR, TBR, and instructions that require an additional bytefor immediate addressing. The mechanism for calculating the new PC valuedepends upon the opcode being processed.

FIG. 403 shows a block diagram of the PCU:

The ADD block is a simple adder modulo 2¹² with two inputs: an unsigned12 bit number and an 8-bit signed number (high bit=sign). The signedinput is either a constant of 0x01, or an 8-bit offset (the 8 bits fromthe MIU).

The “+1.” block takes a 4-bit input and increments it by 1 (modulo 12).The “−1.” block takes a 4-bit input and decrements it by 1 (modulo 12).

Table 380 lists the different forms of PC control: TABLE 381 Differentforms of PC control during the Exec cycle Command Action JMP The PC isloaded with the current 12-bit value as passed in from the MIU. JPI ThePC is loaded with the current 12-bit value as passed in from the Acc.PCRamSel is loaded with the value from bit 15 of the Acc. JPZ The PC isloaded with 0. PCRamSel is loaded with 0 (program in flash) JSZ Save oldvalue of PC onto stack for later. The PC is loaded with 0. PCRamSel isloaded with 0 (program in flash). JSR, JSI Save old value of PC ontostack for later. The PC is loaded with the current 12-bit value aspassed in from either the MIU or the Acc. With JSI, PCRamSel is loadedfrom the value in bit 15 of the Accumulator. RTS Pop old value of PCfrom stack and increment by 1 to get new PC. TBR If the Z flag matchesthe TBR test, add 8-bit signed number (MIU8Data) to current PC.Otherwise increment current PC by 1. DBR If the CZ flag is set, add8-bit signed offset (MIU8Data) to current PC. Otherwise incrementcurrent PC by 1. All others Increment current PC by 1

The updating of PCRamSel only occurs during JPI, JSI, JPZ and JSZinstructions, detected via Logic₀.

The same action for the Exec takes place for JMP, JSR, JPI, JSI, JPZ andJSZ, so we specifically detect that case in Logic₁. In the same way, wetest for the RTS case in Logic₂. Logic₀ Cmd₇₋₁ = 011x001 Logic₁ (Cmd₇₋₅= 000)

Logic₀ Logic₂ Cmd₇₋₀ = RTS

When updating the PC, we must decide if the PC is to be replaced by acompletely new value (as in the case of the JMP, JSR, JPI, JSI, JPZ andJSZ instructions), or by the result of the adder (all otherinstructions). The output from Logic₁ ANDed with Cycle can therefore besafely used by the multiplexor to obtain the new PC value (we need toalways select PC+1 when Cycle is 0, even though we don't always write itto the PCA).

Note that the JPZ and JSZ instructions are implemented as 12 AND gatesthat cause the Accumulator value to be ignored, and the new PC to be setto 0. Likewise, the PCRamSel bit is cleared via these two instructionsusing the same AND mechanism.

The input to the 12-bit adder depends on whether we are incrementing by1 (the usual case), or adding the offset as read from the MIU (when abranch is taken by the DBR and TBR instructions). Logic₃ generates thetest. Logic₃ Cycle

(((Cmd₇₋₄ = DBR)

CZ)

((Cmd₇₋₄ = TBR)

(Cmd₀ ⊕ Z)))

The actual offset to be added in the case of the DBR and TBRinstructions is either the 8-bit value read from the MIU, or an 8-bitvalue generated by bits 3-1 of the opcode and treating bit 4 of theopcode as the sign (thereby making DBR immediate branching negative, andTBR immediate branching positive). The former is selected when bits 3-1of the opcode is 0, as shown by Logic₄. Logic₄ If (Cmd₃₋₁ = 000) outputMIU8Data Else output Cmd₄|Cmd₄|Cmd₄|Cmd₄|Cmd₄|Cmd₃₋₁

Finally, the selection of which PC entry to use depends on the currentvalue for SP. As we enter a subroutine, the SP index value mustincrement, and as we return from a subroutine, the SP index value mustdecrement. Logic₁ tells us when a subroutine is being entered, andLogic₂ tells us when the subroutine is being returned from. We useLogic₂ to select the altered SP value, but only write to the SP registerwhen Exec and Cmd₄ are also set (to prevent JMP and JPZ from adjustingSP).

The two VAL units are validation units connected to the TamperPrevention and Detection circuitry (described in Section 10.3.5 on page962), each with an OK bit. The OK bit is set to 1 on PORstL, and ORedwith the ChipOK values from both Tamper Detection Lines each cycle. TheOK bit is ANDed with each data bit that passes through the unit. BothVAL units also parity-check the data bits to ensure that they are valid.If the parity-check fails, the Erase Tamper Detection Line is triggered.

In the case of VAL₁, the effective output from the SP register willalways be 0. If the chip has been tampered with. This prevents anattacker from executing any subroutines.

In the case of VAL₂, the effective PC output will always be 0 if thechip has been tampered with. This prevents an attacker from executingany program code.

16 Address Generator Unit

The Address Generator Unit (AGU) generates effective addresses foraccessing the Memory Unit (MU). In Cycle 0, the PC is passed through tothe MU in order to fetch the next opcode. The AGU interprets thereturned opcode in order to generate the effective address for Cycle 1.In Cycle 1, the generated address is passed to the MU.

The logic and registers contained in the AGU must be covered by bothTamper Detection Lines. This is to ensure that an attacker cannot alterany generated address. The latches for the counters and calculatedaddress should also be parity-checked.

If either of the Tamper Detection Lines is broken, the AGU will generateaddress 0 each cycle and all counters will be fixed at 0. This will onlycome into effect if an attacker has disabled the RESET and/or erasecircuitry, since under normal circumstances, breaking a Tamper DetectionLine will result in a RESET or the erasure of all Flash memory.

16.1 Implementation

The block diagram for the AGU is shown in FIG. 404:

The accessMode and WriteMask registers must be cleared to 0 on reset toensure that no access to memory occurs at startup of the CPU.

The Adr and accessMode registers are written to during the final cycleof cycle 0 (Fetch) and cycle 1 (Exec) with the address to use during thefollowing cycle phase. For example, when cycle=1, the PC is selected sothat it can be written to Adr during Exec. During cycle 0, while the PCis being output from Adr, the address to be used in the following cycle1 is calculated (based on the fetched opcode seen as Cmd) and finallystored in Adr when Fetch is 1. The accessMode register is also updatedin the same way.

It is important to distinguish between the value of Cmd during differentvalues for Cycle:

-   -   During Cycle 0, when Fetch is 1, the 8-bit input Cmd holds the        instruction to be executed in the following Cycle 1. This 8-bit        value is used to decode the effective address for the operand of        the instruction.    -   During Cycle 1, when Exec is 1, Cmd holds the currently        executing instruction.

The WriteMask register is only ever written to during execution of anappropriate ROR instruction. Logic₁ sets the WriteMask and MMRWriteEnables respectively based on this condition: Logic₁ Exec

(Cmd₇₋₀ = ROR WriteMask)

The data written to the WriteMask register is the lower 8 bits of theAccumulator.

The Address Register Unit is only updated by an RIA or LIA instruction,so the writeEnable is generated by Logic₂ as follows: Logic₂ Exec

(Cmd₆₋₃ = 1111)

The Counter Unit (CU) generates counters C1, C2 and the selected Nindex. In addition, the CU outputs a CZ flag for use by the PCU. The CUis described in more detail below.

The VAL₁ unit is a validation unit connected to the Tamper Preventionand Detection circuitry (described in Section 10.3.5 on page 962). Itcontains an OK bit that is set to 1 on PORstL, and ORed with the ChipOKvalues from both Tamper Detection Lines each cycle. The OK bit is ANDedwith the 12 bits of Adr before they can be used. If the chip has beentampered with, the address output will be always 0, thereby preventingan attacker from accessing other parts of memory. The VAL₁ unit alsoperforms a parity check on the Adr Address bits to ensure it has notbeen tampered with. If the parity-check fails, the Erase TamperDetection Line is triggered.

16.1.1 Counter Unit

The Counter Unit (CU) generates counters C1 and C2 (used internally). Inaddition, the CU outputs Cn and flag CZ for use externally. The blockdiagram for the CU is shown in FIG. 405: Registers C1 and C2 are updatedwhen they are the targets of a DBR, SC or ROR instruction. Logic₁generates the control signals for the write enables as shown in thefollowing pseudocode. isDbrSc = (Cmd₇₋₄ = DBR)

(Cmd₇₋₄ = SC) isRorCn = (Cmd₇₋₄ = ROR)

(Cmd₃₋₂ = 10) CnWE = Exec

(isDbrSc

isRorCn) C1we = CnWE

Cmd₀ C2we = CnWE

Cmd₀

The single bit flag CZ is produced by the NOR of the appropriate C1 orC2 register for use during a DBR instruction. Thus CZ is 1 if theappropriate Cn value=0.

The actual value written to C1 or C2 depends on whether the ROR, DBR orSC instruction is being executed. During a DBR instruction, the value ofeither C1 or C2 is decremented by 1 (with wrap). One multiplexor selectsbetween the lower 6 bits of the Accumulator (for ROR instructions), anda 6-bit value for an SC instruction where the upper 3 bits=the low 3bits from C2, and low 3 bits=low 3 bits from Cmd. Note that only thelowest 3 bits of the operand are written to C1.

The two VAL units are validation units connected to the TamperPrevention and Detection circuitry (described in Section 10.3.5 on page962), each with an OK bit. The OK bit is set to 1 on PORstL, and ORedwith the ChipOK values from both Tamper Detection Lines each cycle. TheOK bit is ANDed with each data bit that passes through the unit. All VALunits also parity check the data to ensure the counters have not beentampered with. If a parity check fails, the Erase Tamper Detection Lineis triggered.

In the case of VAL₁, the effective output from the counter C1 willalways be 0 if the chip has been tampered with. This prevents anattacker from executing any looping constructs.

In the case of VAL₂, the effective output from the counter C2 willalways be 0 if the chip has been tampered with. This prevents anattacker from executing any looping constructs.

16.1.2 Calculate Next Address

This unit generates the address of the operand for the next instructionto be executed. It makes use of the Address Register Unit and PC toobtain base addresses, and the counters from the Counter Unit to assistin generating offsets from the base address.

This unit consists of some simple combinatorial logic, including anadder that adds a 6-bit number to a 10-bit number. The logic is shown inthe following pseudocode. isErase = (Cmd₇₋₀ = ERA) isSt = (Cmd₇₋₄ = ST)isAccRead = (Cmd₇₋₆ = 10) # First determine whether this is an immediatemode requiring PC+1 isJmpJsrDbrTbrImmed = (Cmd₇₋₆ =00)

(

Cmd₅

(Cmd₅₋₁ = 1x000)) isLia = (Cmd₇₋₃ = LIA) isLogImmed = ((Cmd₇₋₆ = 11)

((Cmd₅

Cmd₄)

(Cmd₅₋₃ ≠ 111)))

(Cmd₁₋₀ = 10) pcSel = Cycle

(

Cycle

(isJmpJsrDbrTbrImmed

isLogImmed

isLia)) # Generate AnSel signal for the Address Register Unit A0Sel =(isAccRead

isSt)

(

Cmd₃

(Cmd₅₋₃ = 001)) AnSel₁₋₀ =

A0Sel

Cmd₂₋₁ # The next address is either the new PC or must be generated #(we require the base address from Address Register Unit) nextRAMSel =AnDataOut₈

isErase If (nextRAMSel)  baseAdr = 00 | AnDataOut₇₋₀# ram addresses arealready word aligned Else  baseAdr = AnDataOut₇₋₀ | 00# flash addressesare 4-byte aligned EndIf # Base address is now word (4-byte) aligned #Now generate the offset amount to be added to the base address selCn =(isAccRead

isSt)

(Cmd₅

Cmd₄)

Cmd₃ offset₀ = (A0Sel

Cmd₀)

(selCn

Cn₀) offset₁ = (A0Sel

Cmd₁)

(selCn

Cn₁) offset₂ = (A0Sel

Cmd₂)

(selCn

Cn₂) offset₅₋₃ = selCn

Cn₅₋₃ If (isErase)  nextEffAdr₁₁₋₄ = Acc₇₋₀  nextEffAdr₃₋₀ = don't careElse  # now we can simply add the offset to the base address to get theeffective adr  nextEffAdr₁₁₋₂ = baseAdr + offset # 10 bit plus 6 bit,with wrap = 10 bits out  nextEffAdr₁₋₀ = 0 # word access, so lower bitsof effadr are 0 EndIf # Now generate the various signals for use duringCycle=1 # Note that these are only valid when pcSel is 0 (otherwise willread PC) nextAccessMode₀ = 1 # want 32-bit access nextAccessMode₁ =nextRAMSel # ram or flash access (only valid if rd/wr/erase set)nextAccessMode₂ = isAccRead # pcSel takes care of LIA instructionnextAccessMode₃ = isSt # write access nextAccessMode₄ = isErase # erasepage access16.1.3 Address Register Unit

This unit contains 4×9-bit registers that are optionally cleared to 0 onPORstL. The 2-bit input AnSel selects which of the 4 registers to outputon DataOut. When the writeEnable is set, the AnSel selects which of the4 registers is written to with the 9-bit DataIn.

17 Program Mode Unit

The Program Mode Unit (PMU) is responsible for Program Mode and TrimMode operations:

-   -   Program Mode involves erasing the existing flash memory and        loading the new program/data into the flash. The program that is        loaded can be a bootstrap program if desired, and may contain        additional program code to produce a digital signature of the        final program to verify that the program was written correctly        (e.g. by producing a SHA-1 signature of the entire flash        memory).    -   Trim Mode involves counting the number of internal cycles that        have elapsed between the entry of Trim Mode (at the falling edge        of the ack) and the receipt of the next byte (at the falling        edge of the last bit before the ack) from the Master. When the        byte is received, the current count value divided by 2 is        transmitted to the Master.

The PMU relies on a fuse (implemented as the value of word 0 of theflash information block) to determine whether it is allowed to performProgram Mode operations. The purpose of this fuse is to prevent easy (oraccidental) reprogramming of QA Chips once their purpose has been set.For example, an attacker may want to reuse chips from old consumables.If an attacker somehow bypasses the fuse check, the PMU will still eraseall of flash before storing the desired program. Even if the attackersomehow disconnects the erasure logic, they will be unable to store aprogram in the flash due to the shadow nybbles.

The PMU contains an 8-bit buff register that is used to hold the bytebeing written to flash and a 12-bit adr register that is used to holdthe byte address currently being written to.

The PMU is also used to load word 1 of the information block into a32-bit register (combined from 8-bits of buff, 12-bits of adr, and afurther 12-bit register) so it can be used to XOR all data to and frommemory (both Flash and RAM) for future CPU accesses. This logic isactivated only when the chip enters ActiveMode (so as not to accessflash and possibly cause an erasure directly after manufacture sinceshadows will not be correct). The logic and 32-bit mask register is inthe PMU to minimize chip area.

The PMU therefore has an asymmetric access to flash memory:

-   -   writes are to main memory    -   reads are from information block memory

The reads and writes are automatically directed appropriately in theMRU.

A block diagram of the PMU is shown in FIG. 406.

17.1 Local Storage and Counters

The PMU keeps a 1-cycle delayed version of MRURdy, called prevMRURdy. Itis used to generate PMNewTrans. Therefore each cycle the PMU performsthe following task:

-   -   prevMRURdy←MRURdy v(state=loadByte)

The PMU also requires 1-bit maskLoaded, idlePending and idlePendingregisters, all of which are cleared to 0 on RstL. The 1-bit fuseBlownregister is set to 1 on RstL for security.

17.2 State Machine

The state machine for the PMU is shown in FIG. 407, with the pseudocodefor the various states outlined below. rstl prevMRURdy, maskLoaded,idlePending, adr

0 #clear most regs fuseBlown

1 # for security sake assume the worst state

idle

The idle state, entered after reset, simply waits for the IOMode toenter ProgramMode, ActiveMode, or TrimMode. Note that the reset valuefor fuseBlown means that ProgramMode and TrimMode cannot be entereduntil after a successful entry into ActiveMode that also clears thefuseBlown register. In state idle, PMEn=

maskLoaded, and in state wait4Mode PMEn=0. In all other states, PMEn=1.idle  idlePending

0  PMEn =

maskLoaded  PMNewTrans = 0  If ((IOMode = ActiveMode)

MRURdy)   If (maskLoaded)    state

wait4mode # no need to reload mask once loaded   Else    adr

0 # the location of the fuse is within 32-bit word 0    state

loadFuse   EndIf  ElseIf ((IOMode = ProgramMode)

MRURdy

fuseBlown) # wait 4 access 2 finish   maskLoaded

0 # the mask is now invalid   adr

0 # the location of the fuse is within 32-bit word 0   state

loadFuse  ElseIf ((IOMode = TrimMode)

MRURdy

fuseBlown)# wait 4 access 2 finish   maskLoaded

0 # the mask is now invalid   adr

0 # start the counter on entering TrimMode   state

trim  Else   state

idle  EndIf

The wait4mode state simply waits until for the current mode to finishand returns to idle. wait4mode PMEn = 0 PMNewTrans = 0 If (IOMode =IdleMode)  state

idle Else  state

wait4mode EndIf

The trim state is where we count the number of cycles between the entryof the Trim Mode and the arrival of a byte from the Master. When thebyte arrives from the Master, we send the resultant count: trim  # Wesaturate the adder at all 1s to make external trim control easier lastOne = adr₀

adr₁

... adr₁₁  If (

lastOne)   adr = adr + 1 # 12 bit incrementor  EndIf  # This logicsimply causes the current adder value to be written to the  # outBytewhen the inByte is received. The inByte is cleared when received  #although it is not strictly necessary to do so  PMOutByteWE =InByteValid # 0 in all other states  PMInByteUsed = InByteValid# same asin loadByte state, 0 in all other states  If (IOMode ≠ TrimMode)   state

idle  ElseIf (InByteValid)   state

wait4mode  Else   state

trim  EndIf

The loadFuse state is called whenever there is an attempt to program thedevice or we are entering ActiveMode and the mask is invalid (i.e. afterpower up or after a ProgramMode or TrimMode command). We load the 32-bitfuse value from word 0 of information memory in flash and compare itagainst the FuseSig constant (0x5555AAAA) to obtain the fuse value. Thenext state depends on IOMode and the Fuse. loadFuse  PMEn = 1 PMNewTrans = prevMRURdy  idlePending_in = idlePending

(IOMode = IdleMode)  idlePending

idlePending_in  If (MRURdy)   If (idlePending_in)# don't change stateuntil the memory access is complete    state

idle   Else    fuseBlown_in = (MRUData₃₁₋₀ = FuseSig)    fuseBlown

fuseBlown_in    If (IOMode = ProgramMode)     If (fuseBlown_in)     state

wait4mode # not allowed to program anymore     Else      state

erase     EndIf    Elsif (IOMode = ActiveMode)     adr

4 # byte 4 is word 1 (the location of the XORMask)     state

getMask    Else     state

idle    EndIf   EndIf  Else   state

loadFuse  EndIf

The erase state erases the flash memory and then leads into the mainprogramming states: erase  PMNewTrans = prevMRURdy  PMEraseDevice = 1 #is 0 in all other states  adr

0  idlePending_in = idlePending

(IOMode ≠ ProgramMode)  idlePending

idlePending_in  If (MRURdy)   If (idlePending_in)    state

idle   Else    state

loadByte   EndIf  Else   state

erase  EndIf

Program Mode involves loading a series of 8-bit data values into theFlash. The PMU reads bytes via the IOU's InByte and InByteValID, settingMUInByteUsed as it loads data. The Master must send data slightly slowerthan the speed it takes to write to Flash to ensure that data is notlost. loadByte    # Load in 1 byte (1 word) from IO Unit  PMNewTrans = 0 PMInByteUsed = InByteValid# same as in TrimIn state, and 0 in all otherstates  If (IOMode ≠ ProgramMode)   state

idle  Else   If (InByteValid)    buff

InByte    state

writeByte   Else    state

loadByte   EndIf  EndIf writeByte  PMNewTrans = prevMRURdy  PMRW = 0   #write. In all other states, PMRW = 1 (read)  PM32Out₇₋₀ = buff # data(can be tied to this)  PM32Out₁₉₋₈ = adr # can be tied to this PM32Out₃₁₋₂₀ = 12bitReg# is always this (is don't care during a write) idlePending_in = idlePending

(IOMode ≠ ProgramMode)  idlePending

idlePending_in  If (MRURdy)   lastOne = adr₀

adr₁

... adr₁₁   adr

adr + 1 # 12 bit incrementor   If (idlePending_in)    state

idle   ElseIf (lastOne)    state

wait4Mode   Else    state

loadByte   EndIf  Else   state

writeByte  EndIf

The getMask state loads up word 1 of the flash information block (bytes4-7) into the 32-bit buffer so it can be used to XOR all data to andfrom memory (both Flash and RAM) for future CPU accesses. getMask PMNewTrans = prevMRURdy  PM32Out₁₉₋₈ = adr # adr should = 4, i.e. word1 which holds the CPU's mask  PMRW = 1    # read (MUST be 1 in thisstate)  idlePending_in = idlePending

(IOMode ≠ ActiveMode)  idlePending

idlePending_in  If (MRURdy)   buff

MRUData₇₋₀   adr

MRUData₁₉₋₈   12bitReg

MRUData₃₁₋₂₀   maskLoaded

1   If (idlePending_in)    state

idle   Else    state

wait4mode   EndIf  Else    state

getMask  EndIf18 Memory Request Unit

The Memory Request Unit (MRU) provides arbitration between PMU memoryrequests and CPU-based memory requests.

The arbitration is straightforward: if the input PMEn is asserted, thenPMU inputs are processed and CPU inputs are ignored. If PMEn isdeasserted, the reverse is true.

A block diagram of the MRU is shown in FIG. 408.

18.1 Arbitration Logic

The arbitration logic block provides arbitration between the accesses ofthe PM and the 8/32-bit accesses of the CPU via a simple multiplexingmechanism based on PMEn:  ReqDataOut₃₁₋₈ = CPUDataOut₃₁₋₈  If (PMEn)  NewTrans = PMNewTrans   AccessMode₀ = PMRW # maps to 1 for reads (32bits), 0 for writes (8 bits)   AccessMode₁ = 0 # flash accesses only  AccessMode₂ = PMRW

$$PMEraseDevice # read has lower priority than erase   AccessMode₃ =

PMRW

$$PMEraseDevice # write has lower priority than erase   AccessMode₄ = 0# pageErase   AccessMode₅ = PMEraseDevice # erase everything (main &info block)   WriteMask = 0xFF   Adr = PM32Out₁₉₋₈   ReqDataOut₇₋₀ =PM32Out₇₋₀  Else   NewTrans = CPUNewTrans

(CPUAccessMode₄₋₂ ≠ 000)   AccessMode₄₋₀ = CPUAccessMode   AccessMode₅ =0 # cpu cannot ever erase entire chip   WriteMask = CPUWriteMask   Adr =CPUAdr   ReqDataOut₇₋₀ = CPUDataOut₇₋₀  EndIf18.2 Memory Request Logic

The Memory Request Logic in the MRU implements the memory requests fromthe selected input.

An individual request may involve outputting multiple sub-requests e.g.an 8-bit read consists of 2×4-bit reads (each flash byte contains anybble plus its inverse).

The input accessMode bits are interpreted as follows: TABLE 382Interpretation of accessMode bits Bit Description 0 0 = 8-bit access 1 =32-bit access 1 0 = flash access 1 = RAM access this bit is only validif bit 2, 3 or 4 is set 2 1 = read access 3 1 = write access 4 1 = erasepage access 5 1 = erase entire (info and main) flash (only used withinthe MRU)

The MRU contains the following registers for general purpose flowcontrol: TABLE 383 Description of register settings name #bitsDescription ActiveTrans 1 Is there a transaction still running? If so,then extraTrans and nextToXfer can be considered valid. badUntilRestart1 0 = memory (flash and ram) reads work correctly 1 = memory (flash andram) reads return 0 Gets set whenever illChip gets set, and remains setuntil a soft restart occurs i.e. IOMode passes through Idle. extraTrans1 Determines whether there is an additional sub- transaction to perform.e.g. a 32 bit read from flash involves 4 sub-transactions in the case of8-bit accesses, and 8 sub-transactions in the case of 4-bit accesses.IIIChip 1 0 = 15 consecutive bad reads have not occurred 1 = 15consecutive bad reads have occurred nextToXfer 3 The next element (byteor nybble) number to transfer to/from memory restartPending 1 1 = IOModepassed through Idle while a transaction was being processed 0 = Thetransaction completed without IOMode passing through Idle retryCount 4Number of times that a byte has been read badly from flash. When a bytehas been read badly 15 consecutive times illChip will be set.retryStarted 1 0 = no retries encountered yet for this read 1 = retrieshave been encountered - retryCount holds the number of retries TheretryStarted register is used to stop retryCount being cleared on goodreads - thus keeping a record of the last number of retries on a badread.

Table 383 lists the registers specifically for testing flash. Althoughthe complete set of flash test registers is in both the MRU and MAU(group 0 is in the MRU, groups 1 and 2 are in the MAU), all the decodingtakes place from the MRU. TABLE 383 Flash test registers settable fromCPU when the RAM address is >128⁷ adr bitSuperscriptparanumonly bitsname description 0 0 shadowsOff 0 = regular shadowing (nybble basedaccess to flash) 1 = shadowing disabled, 8-bit direct accesses to flash.1 hiFlashAdr Only valid when shadowsOff = 1 0 = accesses are to lower 4Kbytes of flash 1 = accesses are to upper 4 Kbytes of flash 2 1 3enableFlashTest 0 = keep flash test register within the TSMC flash IP inits reset state 1 = enable flash test register to take on non-resetvalues.  8-4 flashTest Internal 5-bit flash test register within theTSMC flash IP (SFC008_08B9_HE). If this is written with 0x1E, thensubsequent writes will be according to the TSMC write test mode. Youmust write a non-0x1E value or reset the register to exit this mode. 228-9 flashTime When timerSel is 1, this value is used for the durationof the program cycle within a standard flash write or erasure. 1 unit =16 clock cycles (16 × 100 ns typical). Regardless of timerSel, thisvalue is also used for the timeout following power down detection beforethe QA Chip resets itself. 1 unit = 1 clock cycle (= 100 ns typical).Note that this means the programmer should set this to an appropriatevalue (e.g. 5 μs), just as the localId needs to be set. 29  timerSel 0 =use internal (default) timings for flash writes & erasures 1 = useflashTime for flash writes and erasures⁷This is from the programmer's perspective. Addresses sent from the CPUare byte aligned, so the MRU needs to test bit n+2. Similarly, checkingDRAM address >128 means testing bit 7 of the address in the CPU, and bit9 in the MRU.

Initialization on reset involves clearing all the flags: MRURdy = 0 #can't process anything at this point activeTrans

0 extraTrans

0 illChip

0 badUntilRestart

0 restartPending

0 retryCount

0 retryStarted

0 nextToXfer

0 # don't care shadowsOff

0 hiFlashAdr

0 infoBlockSel

0# used to generate MRUMode₂18.2.2 Main Logic

The main logic consists of waiting for a new transaction, and startingan appropriate sub-transaction accordingly, as shown in the followingpseudocode: #  Generate some basic signals for use in determiningaccessPatterns Is32Bit = AccessMode₀ Is8Bit =

AccessMode₀ IsFlash =

AccessMode₁ IsRAM = AccessMode₁ IsRead = AccessMode₂ IsWrite =AccessMode₃ noShadows = shadowsOff doShadows = IsFlash

noShadows continueRequest = (IOMode ≠ IdleMode) okForTrans =

restartPending

continueRequest startOfSubTrans = (NewTrans

extraTrans)

okForTrans doingTrans = startOfSubTrans

(activeTrans

extraTrans) IsInvalidRAM = doingTrans

IsRAM

(Adr₉

(Adr₈

Adr₇)) IsTestModeWE = doingTrans

IsRAM

IsWrite

Adr₉ IsTestReg₀ = IsTestModeWE

Adr₃  #write to flash test register - bit 1 of word adr IsTestReg₁ =IsTestModeWE

Adr₄  #write to flash test register - bit 2 of word adr MRUTestWE =IsTestReg₀

IsTestReg₁ IsPageErase = AccessMode₄ IsDeviceErase = AccessMode₅

(IsTestModeWE

(Adr₈₋₂ = 0001000)) # bit 9 not req IsErase = IsDeviceErase

IsPageErase MRURAMSel = IsRAM

MRUTestWE

IsDeviceErase IsInfBlock = (PMEn

(IsDeviceErase

IsRead))

  (

PMEn

infoBlockSel

   (IsDeviceErase

(IsFlash

(Adr₁₁₋₇ = 0)

(Adr₆

doShadows)))) # Which element (byte or nybble) are we up to xferring

If (NewTrans)  toXfer = 0 Else  toXfer = nextToXfer EndIf # Form theaddress that goes to the outside world If (IsFlash

noShadows)  byteCount = toXfer₁₋₀  MRUAdr₁₂ = hiFlashAdr # upper orlower block of 4Kbytes of flash  MRUAdr₁₁₋₂ = Adr₁₁₋₂ # word # MRUAdr₁₋₀ = (Adr₁₋₀

(

Is32Bit|

Is32Bit))

byteCount # byte Else  byteCount = toXfer₂₋₁  MRUAdr₁₂₋₃ = Adr₁₁₋₂ #word #  MRUAdr₂₋₁ = (Adr₁₋₀

(

Is32Bit|

Is32Bit))

byteCount # byte  MRUAdr₀ = toXfer₀ #nybble EndIf # Assuming a write,are we allowed to write to this address

writeEn = SelectBit[WriteMask, ((MRUAdr₂

doShadows)| MRUAdr₁₋₀)] # mux: 1 from 8 # Generate the 4-bit mask to beused for XORing during CPU access to flash baseMask =SelectNybble(PM32Out, MRUAdr₂₋₀) # mux selects 4 bits of 32 If (PMEn) theMask = 0 Else  theMask = baseMask # we only use mask for CPUaccesses to flash EndIf # Select a byte (and nybble) from the data forwrites baseByte = SelectByte[ReqDataOut, byteCount] # mux: 8 bits from32 baseNybble = SelectNybble[baseByte, toXfer₀] # mux: 4 bits from 8outNybble = baseNybble ⊕ theMask # only used when nybble writing #Generate the data on the output lines (doesn't matter for reads orerasures) MRUDataOut₃₁₋₈ = ReqDataOut₃₁₋₈ # effectively don't care forflash writes If (doShadows)  MRUDataOut₇ =

outNybble₃  MRUDataOut₆ = outNybble₃  MRUDataOut₅ =

outNybble₂  MRUDataOut₄ = outNybble₂  MRUDataOut₃ =

outNybble₁  MRUDataOut₂ = outNybble₁  MRUDataOut₁ =

outNybble₀  MRUDataOut₀ = outNybble₀ Else  MRUDataOut₇₋₀ = baseByteEndIf # Setup MRUMode allowTrans = IsRAM

IsRead

(IsWrite

writeEn)

IsErase If (doingTrans)  MRUMode₂ = TsInfBlock  MRUMode₁ = IsErase

IsTestReg₁  MRUMode₀ = IsDeviceErase

(

IsWrite

IsPageErase)

IsTestReg₀  MRUNewTrans = startOfSubTrans

allowTrans

    (

IsInvalidRAM

MRUTestWE

IsDeviceErase) Else  MRUMode₂₋₀ = 001 # read (safe)  MRUNewTrans = 0EndIf # Generate the effective nybble read from flash (this may not beused). # When there is a shadowFault (non-erased memory and invalidshadows) we consider # it a bad read when an 8-bit read, or whenwriteMask₀ is 0. # Note: we always substitute the upper nybble ofWriteMask for the non-valid data, # but only flag a read error ifWriteMask₀ is also 1. When the data is erased, # we return 0 regardlessof WriteMask₀. finishedTrans = doingTrans

MAURdy finishedFlashSubTrans = finishedTrans

IsFlash

IsErase isWrittenFlash = (FlashData₇₋₀ ≠ 11111111) # flash is erased toall 1s If (isWrittenFlash

((FlashData_(7,5,3,1) ⊕ FlashData_(6,4,2,0)) ≠ 1111))  inNybble₃₋₀ =WriteMask₇₋₄  badRead = finishedFlashSubTrans

IsRead

(Is8Bit

WriteMask₀)

doShadows Else  inNybble_(3,2,1,0) = (theMask_(3,2,1,0) ⊕FlashData_(6,4,2,0))

isWrittenFlash  badRead = 0 EndIf # Present the resultant data to theoutside world MaskTheData = IsInvalidRAM

badRead

(badUntilRestart

IsRAM) NoData = IsErase

IsWrite

doingTrans If (NoData

MaskTheData)  MRUData₀ = IsInvalidRAM

illChip  MRUData₄₋₁ = retryCount

(IsInvalidRAM

Adr₂) # mask all 4 count bits  MRUData₃₁₋₅ = 0 # also ensures a readthat is bad returns 0 ElseIf (IsRAM)  MRUData₃₁₋₂₄ = SelectByte[RAMData,(Adr₁₋₀

Is32Bit|Is32Bit)]  # mux: 8 from 32  MRUData₂₃₋₀ = RAMData₂₃₋₀ # lsbsremain unchanged from RAM ElseIf (doShadows)  MRUData₃₁₋₂₈ = inNybble MRUData₂₇₋₀ = buff₂₇₋₀ Else  MRUData₃₁₋₂₄ = FlashData  MRUData₂₃₋₀ =buff₂₇₋₄ EndIf # Shift in the data for the good reads - either 4 or 8bits (writes = don't care) If (finishedFlashSubTrans

badRead)   buff₃₋₀

buff₇₋₄ # shift right 4 bits  If (doShadows)   buff₂₃₋₄

buff₂₇₋₈       # shift right 4 bits   buff₂₇₋₂₄

inNybble Else   buff₁₉₋₄

buff₂₇₋₁₂ # shift right 8 bits, buff₃₋₀ is don't care   buff₂₇₋₂₀

FlashData  EndIf EndIf # Determine whether or not we need a newsub-transaction. We only need one if: # * there hasn't been a transitionto IdleMode during this transaction # * we're doing 8 bit reads that areshadowed # * we're doing 32 bit reads and we've done less than 4 or 8(sh vs non-sh) # * we got a bad read from flash and we need to retry theread (jic was a glitch) moreAdrsToGo = (

toXfer₀

((Is8Bit

doShadows)

Is32Bit))

   (

toXfer₁

Is32Bit)

(

toXfer₂

Is32Bit

doShadows) needToRetryRead = badRead

(

retryStarted

(retryCount ≠ 1111)) extraTrans_in = finishedFlashSubTrans

(moreAdrsToGo

needToRetryRead)       

okForTrans nextToXfer

toXfer + (finishedFlashSubTrans

(IsWrite

needToRetryRead)) # generate our rdy signal and state values for nextcycle MRURdy =

doingTrans

(doingTrans

MAURdy

extraTrans_in) extraTrans

extraTrans_in activeTrans

MRURdy # all complete only when MRURdy is set # Take account of badreads triedEnough = badRead

retryStarted

(retrycount = 1111) If (MAURdy)  If (IsTestModeWE

(Adr₅₋₂ = 0000)) # capture writes to local regs   illChip

0   retryCount

0  Else   illChip

illChip

triedEnough   If (badRead)    retryCount

(retryCount

retryStarted) + 1 # AND all 4 bits    retryStarted

1   Else    retryStarted

0# clear flag so will be ok for the next read   EndIf  EndIf EndIf #Ensure that we won't have problems restarting a program If (MRURdy

okForTrans) # note MRURdy (may not be running a transaction

)  shadowsOff,  hiFlashAdr,  infoBlockSel,  restartPending, badUntilRestart

0  Else   badUntilRestart

badUntilRestart

triedEnough  If (doingTrans

continueRequest)   restartPending

1 # record for later use  EndIf  If (IsTestModeWE

Adr₂) # the other writes are taken care of by the MAU   shadowsOff

ReqDataOut₀   hiFlashAdr

ReqDataOut₁   infoBlockSel

ReqDataOut₂  EndIf EndIf19 Memory Access Unit

The Memory Access Unit (MAU) takes memory access control signals andturns them into RAM accesses and flash access strobed signals withappropriate duration.

A new transaction is given by MRUNewTrans. The address to be read fromor written to is on MRUAdr, which is a nybble-based address. The MRUAdr(13-bits) is used as-is for Flash addressing. When MRURAMSel=1, then theRAM address (RAMAdr) is taken from bits 9-3 of MRUAdr. The data to bewritten is on MRUData.

The return value MAURdy is set when the MAU is capable of receiving anew transaction the following cycle. Thus MAURdy will be 1 during thefinal cycle of a flash or ram access, and should be 1 when the MAU isidle. MAURdy should only be 0 during startup or when a transaction hasyet to finish. TABLE 384 Interpretation of MRUMode¹⁰ _(for RAM accesses)bits action xx0 doWrite xx1 doRead¹⁰MRUMode₂₋₁ is ignored for RAM accesses

-   -   When ^(MRURAMSel)=0, the access is to flash. If ^(MRUTestWE)=0,        then the access is to regular flash memory, as given by        ^(MRUMode):

Table 385. lnterpretaton of MRUMode for regular flash accesses¹¹¹¹ MRUMode₂ can be directly interpreted by the MAU as the IFREN signalrequired for embedded flash block SFC008_(—)08B9_HEbits1-0 action when MRUMode₂ = 0 action when MRUMode₂ = 1 00 doWrite(main memory) doWrite (info block) 01 doRead (main memory) doRead (infoblock) 10 doErasePage (main doErasePage (info block) memory) 11doEraseDevice (main doEraseDevice (both memory) blocks)

If MRUTestWE is 1, then MRUMode₂ will also be 0, and the access is to aflash test register, as given by MRUMode: TABLE 386 Interpretation ofMRUMode for flash test register write accesses bits¹² action xx1 If(MRUData₃ = 0), tie the flash IP test register to its reset state If(MRUData₃ = 1), take the flash IP test register out of reset state, andwrite MRUData₈₋₄ to the 5-bit flash test register within the flash IP(SFC008_08B9_HE) x1x Write MRUData₂₈₋₉ to the internal 20-bitalternate-counter-source register flashTime, and MRUData₂₉ to thecorresponding 1-bit test register timerSel.¹²MRUMode₂ will always be 0 when MRUTestWE = 1.19.1 Implementation

The MAU consists of logic that calculates MAURdy, and additional logicthat produces the various strobed signals according to the TSMC Flashmemory SFC0008_(—)08B9_HE; refer to this datasheet [4] for detailedtiming diagrams. Both main memory and information blocks can be accessedin the Flash. The Flash test modes are also supported as described in[5] and general application information is given in [6].

The MAU can be considered to be a RAM control block and a flash controlblock, with appropriate action selected by MRURAMSel. For all modesexcept read, the Flash requires wait states (which are implemented witha single counter) during which it is possible to access the RAM. Only 1transaction may be pending while waiting for the wait states to expire.Multiple bytes may be written to Flash without exiting the write mode.

The MAU ensures that only valid control sequences meeting the timingrequirements of the Flash memory are provided. A write time-out isincluded which ensures the Flash cannot be left in write modeindefinitely; this is used when the Flash is programmed via the IO Unitto ensure the X address does not change while in write mode. Otherwise,other units should ensure that when writing bytes to Flash, the Xaddress does not change. The X address is held constant by the MAUduring write and page erase modes to protect the Flash. If an X addresschange is detected by the MAU during a Flash write sequence, it willexit write mode allowing the X address to change and re-enter writemode. Thus, the data will still be written to Flash but it will takelonger.

When either the Flash or RAM is not being used, the MAU sets the controlsignals to put the particular memory type into standby to minimise powerconsumption.

The MAU assumes no new transactions can start while one is in progressand all inputs must remain constant until MAU is ready.

19.2 Flash Test Mode

MAU also enables the Flash test mode register to be programmed whichallows various production tests to be carried out. If MRUTestWE=1,transactions are directed towards the test mode register. Most of thetests use the same control sequences that are used for normal operationexcept that one time value needs to be changed. This is provided by theflashTime register that can be written to by the CPU allowing the timerto be set to a range of values up to more than 1 second. A specialcontrol sequence is generated when the test mode register is set to 0x1Eand is initiated by writing to the Flash.

Note that on reset, timeSel and flashTime are both cleared to 0. The5-bit flash test register within the TSMC flash IP is also reset bysetting TMR=1. When MRUTestWE=1, any open write sequence is closed evenif the write is not to the 5-bit flash test register within the TSMCflash IP.

19.3 Flash Power Failure Protection

Power could fail at any time; the most serious consequence would be ifthis occurred during writing to the Flash and data became corrupted inanother location to that being written to. The MAU will protect theFlash by switching off the charge pump (high voltage supply used forprogramming and erasing) as soon as the power starts to fail. After atime delay of about 5 μs (programmable), to allow the discharge of thecharge pump, the QA chip will be reset whether or not the power supplyrecovers.

19.4 Flash Access State Machine

19.5 Interface TABLE 387 MAU interface description Signal name I/ODescription Clk In System clock. RstL In System reset (active low).MAURAMEn In Flag indicating whether the external user needs access tothe RAM at a gross level (e.g. the CPU is active and therefore may wantRAM access). 1 = wants access available, 0 = don't want. MRUNewTrans InFlag indicating MRU wishes to start a new transaction. May only beasserted (=1) when MAURdy = 1. All inputs below must be held constantuntil MAU is ready. MRURAMSel In 1 = RAM, 0 = Flash. MRUMode2-0 In Typeof transaction to be performed. MRUAdr12-0 In Memory address from theMRU. MRUDataOut31-0 In Data used to control and set test modes andtiming. MRUTestWE In Flag indicating test mode transactions. PwrFailingIn Flag indicating possible power failure in progress. MAURdy Out TheMAU is ready when MAURdy = 1. It is always set for RAM transactions andheld low during Flash wait states. RAMOutEn Out 0 = enable the RAM toread or write this cycle (i.e. active low) 1 = disable the RAM thiscycle (saves power, memory is intact) RAMWE Out RAM write when RAMWE = 0(Artisan Synchronous SRAM). MemClk Out Inverted system clock to the RAM(required to meet timing). FlashCtrl8-0 Out Control signals to theFlash. IFREN = information block enable, not used always = 0 XE = Xaddress enable YE = Y address enable SE = sense amplifier enable (readonly) OE = output enable (read only), hi-Z when OE = 0 PROG = program(write bytes) NVSTR = enables all write and erase modes ERASE = pageerase mode MAS1 = mass erase mode TMR Out TMR = Register reset for testmode RAMAdr6-0 Out RAM address in the range 0 to 95. FlashAdr12-0 OutFlash address, full range. MAURstOutL Out Activates the global reset,RstL.19.6 Calculation of Timer Values

Set and calculate timer initialisation values based on Flash data sheetvalues, clock period and clock range. # Note: Flash data sheet givesminimum timings # Delays greater than 1 clock cycle clock_per = 100 # nsFlash_Tnvs = 7500 # ns Flash_Tnvh = 7500 # ns Flash_Tnvh1 = 150 # usFlash_Tpgs = 15        # us Flash_Tpgh = 100 # ns Flash_Tprog = 30 # usFlash_Tads = 100 # ns Flash_Tadh = 30 # us # Byte write timeoutFlash_Trcv = 1500 # ns Flash_Thv = 6 # ms # Not currently usedFlash_Terase = 30 # ms Flash_Tme = 300 # ms # Derive maximum counts (−1since state machine is synchronous) FLASH_NVS = Flash_Tnvs/clock_per − 1FLASH_NVH = Flash_Tnvh/clock_per − 1 FLASH_NVH1 =Flash_Tnvh1*1000/clock_per − 1 FLASH_PGS = Flash_Tpgs*1000/clock_per − 1FLASH_PGH = Flash_Tpgh/clock_per − 1 FLASH_PROG =Flash_Tprog*1000/clock_per − 1 FLASH_ADS = Flash_Tads/clock_per − 1FLASH_ADH = Flash_Tadh*1000/clock_per − 1 FLASH_ADH_AND_WRITE_PGH =FLASH_ADH + FLASH_PGH + 1 # note is +1 FLASH_RCV = Flash_Trcv/clock_per− 1 FLASH_HV = Flash_Thv*1000000/clock_per − 1 FLASH_ERASE =Flash_Terase*1000000/clock_per − 1 FLASH_ME =Flash_Tme*1000000/clock_per − 1 count_size = 24 # Number of bits intimer counter (newCount) determined by Tme DEFAULTS   Defaults to usewhen no action is specified.  FlashTransPendingSet = 0 FlashTransPendingReset = 0  TMRSet = 0  TMRRst = 0  STLESet = 0 STLERst = 0  TestTimeEn = 0  IFREN = FlashXadr₇  XE = 0  YE = 0  SE = 0 OE = 0  PROG = 0  NVSTR = 0  ERASE = 0  MAS1 = 0  MAURstOutL = 1  If(accessCount ≠ 0)   newCount =accessCount − 1 # decrement unlessinstructed otherwise  Else   newCount =0  EndIf RESET  Initialise stateand counter registers. # asynchronous reset (active low)  state

idle  accessCount

1  countZ

0  XadrReg

0  FlashTransPending

0  TestTime

0  TMR

1  STLEFlag

019.9 State Machine

The state machine generates sequences of timed waveforms to control theoperation of the Flash memory. idle  FlashTransPendingReset = 1  If(somethingToDo) # Flash starting conditions   If (MRUTestWE)   nextState =TM0   Else    Switch (MRUModeint)    Case doWrite:    nextState =writeNVS     newCount = FLASH_NVS    Case doRead:     YE= 1     SE = 1     OE = 1     XE = 1     nextState = idle    CasedoErasePage:     nextState =pageErase     newCount = FLASH_NVS    CasedoEraseDevice:     nextState =massErase     newCount = FLASH_NVS   EndSwitch   EndIf  EndIf19.9.1 Flash Page Erase

The following pseducocode illustrates the Flash page erase sequence.pageErase   ERASE = 1   XE = 1   If (

PwrFailing)     If (countZ)       newCount = FLASH_ERASE       nextState=pageEraseERASE     EndIf   Else     newCount = TestTime₁₉₋₀    nextState =Help1   EndIf pageEraseERASE   ERASE = 1   NVSTR = 1   XE= 1   If (

PwrFailing)     If (countZ)       newCount = FLASH_NVH       nextState =pageEraseNVH     EndIf   Else     newCount = TestTime₁₉₋₀     nextState=Help1   EndIf pageEraseNVH   NVSTR = 1   XE = 1   If (

PwrFailing)     If (countZ)       newCount = FLASH_RCV       nextState=RCVPM     EndIf   Else     newCount = TestTime₁₉₋₀     nextState =Help1    EndIf RCVPM   If (countZ)     nextState =idle # exit   EndIf19.9.2 Flash Mass Erase

The following pseducocode illustrates the Flash mass erase sequence.massErase   MAS1 = 1   ERASE = 1   XE = 1   If (countZ)     If (

TestTime₂₀)       newCount = FLASH_ME     Else       newCount =TestTime₁₉₋₀ | 0000     EndIf     nextState =massEraseME   EndIfmassEraseME   MAS1 = 1   ERASE = 1   NVSTR = 1   XE = 1   If (countZ)    newCount = FLASH_NVH1     nextState =massEraseNVH1   EndIfmassEraseNVH1   MAS1 = 1   NVSTR = 1   XE = 1   If (countZ)     newCount= FLASH_RCV     nextState =RCVPM   EndIf19.9.3 Flash Byte Write

The following pseducocode illustrates the Flash byte write sequence.writeNVS   PROG = 1   XE = 1   If (

PwrFailing)     If (countZ)       If (

STLEFlag)         newCount = FLASH_PGS         nextState =writePGS      Else         newCount = TestTime₁₉₋₀ | 0000         nextState=STLE0       EndIf     EndIf   Else     newCount = TestTime₁₉₋₀    nextState =Help1   EndIf writePGS   PROG = 1   NVSTR = 1   XE = 1  If (

PwrFailing)     If (countZ)       newCount = FLASH_ADS       nextState=writeADS     EndIf   Else     newCount = TestTime₁₉₋₀     nextState=Help1   EndIf writeADS # Add Tads to Tpgs   PROG = 1   NVSTR = 1   XE =1   FlashTransPendingReset = 1   If (

PwrFailing)     If (countZ)       If (

TestTime₂₀)         newCount = FLASH_PROG       Else         newCount =TestTime₁₉₋₀ | 0000       EndIf       nextState =writePROG     EndIf  Else     newCount = TestTime₁₉₋₀     nextState =Help1   EndIfwritePROG   PROG = 1   NVSTR = 1   YE = 1   XE = 1   If (

PwrFailing)     If (countZ)       newCount = FLASH_ADH_AND_WRITE_PGH      nextState =writeADH     EndIf   Else     newCount = TestTime₁₉₋₀    nextState =Help2   EndIf writeADH   PROG = 1   NVSTR = 1   XE = 1  FlashTransPendingSet = somethingToDo   If (

PwrFailing)     If (

FlashNewTrans)       If (countZ)-- Gracefull exit after timeout        newCount = FLASH_NVH         nextState =writeNVH       EndIf    Else # -- Do something as there is a new transaction       If((MRUModeint = doWrite)

(

XadrCh))         newCount = FLASH_ADS -- Write another byte        nextState =writeADS       Else         newCount = FLASH_NVH --Exit as new trans is not Flash write         nextState =writeNVH      EndIf     EndIf   Else     newCount = TestTime₁₉₋₀     nextState=Help1   EndIf writeNVH   NVSTR = 1   XE = 1   FlashTransPendingSet =somethingToDo   If (

PwrFailing)     If (countZ)       newCount = FLASH_RCV       nextState=RCV     EndIf   Else     newCount = TestTime₁₉₋₀     nextState =Help1  EndIf RCV      # wait til we're allowed to do another transaction  FlashTransPendingSet = somethingToDo   If (countZ)     nextState =idle   EndIf19.9.4 Test Mode Sequence

The following pseducocode illustrates the test mode sequence. TM0 #Needed this due to delay on TMR   IFREN = 0   nextState = idle # default  If ( MRUModeint₁)     TestTimeEn = 1   EndIf   If (MRUModeint₀)     If(

MRUDataOut₃)       TMRSet = 1       STLERst = 1 # Reset flag as leavingtest mode     Else       If (MRUDataOut₈₋₄ = 11110)         STLESet = 1      Else         STLERst = 1       EndIf       TMRRst = 1      nextState = TM1 # Will get priority     EndIf   EndIf TM1   IFREN= 0   nextState = TM2 TM2   NVSTR = 1   SE = 1   IFREN = 0   nextState =TM3 TM3   NVSTR = 1   SE = 1   MAS1 = MRUDataOut₄   IFREN = MRUDataOut₅  XE = MRUDataOut₆   YE = MRUDataOut₇   ERASE = MRUDataOut₈   TMRSet = 1  nextState = TM4 TM4   NVSTR = 1   SE = 1   MAS1 = MRUDataOut₄   IFREN= MRUDataOut₅   XE = MRUDataOut₆   YE = MRUDataOut₇   ERASE =MRUDataOut₈   TMRRst = 1   nextState = TM5 TM5   NVSTR = 1   SE = 1  MAS1 = MRUDataOut₄   IFREN = MRUDataOut₅   XE = MRUDataOut₆   YE =MRUDataOut₇   ERASE = MRUDataOut₈   nextState = TM6 TM6   NVSTR = 1   SE= 1   nextState = idle19.9.5 Reverse Tunneling and Thin Oxide Leak Test

The following pseducocode shows the reverse tunneling and thin oxideleak test sequence. STLE0   XE = 1   PROG = 1   NVSTR = 1   If (countZ)    newCount = FLASH_NVH     nextState = STLE1   EndIf STLE1   XE = 1  NVSTR = 1   If (countZ)     newCount = FLASH_RCV     nextState = STLE2  EndIf STLE2   If (countZ)     nextState = idle   EndIf19.9.6 Emergency Instructions

The following pseducocode shows the states used for emergency situationssuch as when power is failing. Help1 # MAURdy -> 0 to hold MAU inputsconstant, if not too late   XE = 1   If (countZ)     nextState =Goodbye  EndIf Help2 # MAURdy -> 0 to hold MAU inputs constant, if not too late  XE = 1   YE = 1   If (countZ)     nextState =Goodbye   EndIf Goodbye  XE = 1 # Prevents Flash timing violation   MAURstOutL = 0 # Resetwhole chip whether power fails         # nothing else to do or recovers20 Analogue Unit

This section specifies the mandatory blocks of Section 11.1 on page 965in a way which allows some freedom in the detailed implementation.

Circuits need to operate over the temperature range −40° C. to +125° C.

The unit provides power on reset, protection of the Flash memory againsterroneous writes during power down (in conjunction with the MAU) and thesystem clock SysClk.

20.1 Voltage Budget

The table below shows the key thresholds for V_(DD) which define therequirements for power on reset and normal operation. TABLE 388 V_(DD)limits VDD parameter Description Voltage VDDFTmax Flash test maximum3.6¹³ VDDFTtyp Flash test typical 3.3 VDDFTmin Flash test minimum 3.0VDDmax Normal operation maximum (typ + 10%) 2.75¹⁴ VDDtyp Normaloperation typical 2.5 VDDmin Normal operation minimum (typ − 5%) 2.375VDDPORmax Power on reset maximum 2.0¹⁵¹³The voltage VDDFT may only be applied for the times specified in theTSMC Flash memory test document.¹⁴Voltage regulators used to derive VDD will typically have symmetrictolerance limits¹⁵The minimum allowable voltage for Flash memory operation.20.2 Voltage Reference

This circuit generates a stable voltage that is approximatelyindependent of PVT (process, voltage, temperature) and will typically beimplemented as a bandgap. Usually, a startup circuit is required toavoid the stable V_(bg)=0 condition. The design should aim to minimisethe additional voltage above V_(bg) required for the circuit to operate.An additional output, BGOn, will be provided and asserted when thebandgap has started and indicates to other blocks that the outputvoltage is stable and may be used. TABLE 389 Bandgap target performanceParameter Conditions Min Typ Max Units Vbg¹⁶ typical 1.2 1.23 1.26 V IDDtypical 50 μA Vstart worst case 1.6 V Iout 10 nA Vtemp +0.1 mV/° C.¹⁶Over PVT, not including offsets20.3 Power Detection Unit

Only under voltage detection will be described and is required toprovide two outputs:

-   -   underL controls the power on reset; and    -   PwrFailing indicates possible failure of the power supply.

Both signals are derived by comparing scaled versions of V_(DD) againstthe reference voltage V_(bg).

20.3.1 V_(DD) Monotonicity

The rising and falling edges of V_(DD) (from the external power supply)shall be monotonic in order to guarantee correct operation of power onreset and power failing detection. Random noise may be present butshould have a peak to peak amplitude of less than the hysteresis of thecomparators used for detection in the PDU.

20.3.2 Under Voltage Detection Unit

The underL signal generates the global reset to the logic which shouldbe de-asserted when the supply voltage is high enough for the logic andanalogue circuits to operate. Since the logic reset is asynchronous, itis not necessary to ensure the clock is active before releasing thereset or to include any delay.

The QA chip logic will start immediately the power on reset is releasedso this should only be done when the conditions of supply voltage andclock frequency are within limits for the correct operation of thelogic.

The power on reset signal shall not be triggered by narrow spikes (<100ns) on the power supply. Some immunity should be provided to powersupply glitches although since the QA chip may be under attack, anyreset delay should be kept short. The unit should not be triggered bylogic dynamic current spikes resulting in short voltage spikes due tobond wire and package inductance. On the rising edge of V_(DD), themaximum threshold for de-asserting the signal shall be whenV_(DD)>V_(DDmin). On the falling edge of V_(DD), the minimum thresholdfor asserting the signal shall be V_(DD)<V_(DDPORmax).

The reset signal must be held low long enough (T_(pwmin)) to ensure allflip-flops are reset. The standard cell data sheet [7] gives a figure of0.73 ns for the minimum width of the reset pulse for all flip-floptypes.

2 bits of trimming (trim₁₋₀) will be provided to take up all of theerror in the bandgap voltage. This will only affect the assertion of thereset during power down since the power on default setting must be usedduring power up.

Although the reference voltage cannot be directly measured, it iscompared against V_(DD) in the PDU. The state of the power on resetsignal can be inferred by trying to communicate through the serial buswith the chIP. By polling the chip and slowly increasing V_(DD), a pointwill be reached where the power on reset is released allowing the serialbus to operate; this voltage should be recorded. As V_(DD) is lowered,it will cross the threshold which asserts the reset signal. The power ondefault is set to the lowest voltage that can be trimmed (which givesthe maximum hysterisis). This voltage should be recorded (or it may besufficient to estimate it from the reset release voltage recordedabove). V_(DD) is then increased above the reset release threshold andthe PDU trim adjusted to the setting the closest to V_(DDPORmax). V_(DD)should then be lowered and the threshold at which the reset isre-asserted confirmed. TABLE 390 Power on reset target performanceParameter Conditions Min Typ Max Units Vthrup T = 27° C. 2.0 2.375 VVthrdn T = 27° C. 2.0 2.1 V Vhystmin 16 mV IDD 5 μA Tspike 100 ns Vminr0.5 V Tpwmin 1 nsPower on Reset Behaviour

The signal PwrFailing will be used to protect the Flash memory byturning off the charge pump during a write or page erase if the supplyvoltage drops below a certain threshold. The charge pump is expected totake about 5 us to discharge. The PwrFailing signal shall be protectedagainst narrow spikes (<100 ns) on the power supply.

The nominal threshold for asserting the signal needs to be in the rangeV_(PORmax)<V_(DDPFtyp)<V_(DDmin) so is chosen to be asserted whenV_(DD)<V_(DDPFtyp)=V_(DDPORmax)+200 mV. This infers a V_(DD) slew ratelimitation which must be <200 mV/5 us to ensure enough time to detectthat power is failing before the supply drops too low and the reset isactivated. This requirement must be met in the application by provisionof adequate supply decoupling or other means to control the rate ofdescent of V_(DD). TABLE 391 Power failing detection target performanceParameter Conditions Min Typ Max Units Vthr T = 27° C. 2.1 2.2 2.3 V¹⁷Vhyst 16 mV IDD 5 μA Tspike 100 ns Vminr 0.5 V¹⁷These limits are after trimming and include an allowance for VDDramping.

2 bits of trimming (trim₁₋₀) will be provided to take up all of theerror in the bandgap voltage.

20.4 Ring Oscillator

SysClk is required to be in the range 7-14 MHz throughout the lifetimeof the circuit provided V_(DD) is maintained within the rangeV_(DDMIN)<V_(DD)<V_(DDMAX). The 2:1 range is derived from theprogramming time requirements of the TSMC Flash memory. If this range isexceeded, the useful lifetime of the Flash may be reduced.

The first version of the QA chip, without physical protection, does notrequire the addition of random jitter to the clock. However, it isrecommended that the ring oscillator be designed in such a way as toallow for the addition of jitter later on with minimal modification. Inthis way, the un-trimmed centre frequency would not be expected tochange.

The initial frequency error must be reduced to remain within the range10 MHz/1.41 to 10 MHz×1.41 allowing for variation in:

-   -   voltage    -   temperature    -   ageing    -   added jitter    -   errors in frequency measurement and setting accuracy

The range budget must be partitioned between these variables.

FIG. 411._Ring oscillator block diagram

The above arrangement allows the oscillator centre frequency to betrimmed since the bias current of the ring oscillator is controlled bythe DAC. SysClk is derived by dividing the oscillator frequency by 5which makes the oscillator smaller and allows the duty cycle of theclock to be better controlled.

20.4.1 DAC (Programmable Current Source)

Using V_(bg), this block sources a current that can be programmed by theTrim signal. 6 of the available 8 trim bits will be used (trim₇₋₂)giving a clock adjustment resolution of about 250 kHz. The range ofcurrent should be such that the ring oscillator frequency can beadjusted over a 4 to 1 range. TABLE 392 Programmable current sourcetarget performance Parameter Conditions Min Typ Max Units Iout Trim7-2 =0 5 μA Trim7-2 = 32 12.5 Trim7-2 = 63 20 Vrefin 1.23 V Rout Trim7-2 = 632.5 MΩ

20.4.2 Ring Oscillator Circuit TABLE 393 Ring oscillator targetperformance Parameter Conditions Min Typ Max Units Fosc¹⁸ 7 10 14 MHzIDD 10 μA KI 1 MHz/μA KVDD +200 KHz/V KT +30 KHz/oC Vstart 1.5 VK_(I) = control sensitivity, K_(VDD) = V_(DD) sensitivity, K_(T) =temperature sensitivityWith the figures above, K_(VDD) will give rise to a maximum variation of±50 kHz and K_(T) to ±1.8 MHz over the specified range of V_(DD) andtemperature.¹⁸Accounting for division by 520.4.3 Div5

The ring oscillator will be prescaled by 5 to obtain the nominal 10 MHzclock. An asynchronous design may be used to save power. Several dividedclock duty cycles are obtainable, eg 4:1, 3:2 etc. To ease timingrequirements for the standard cell logic block, the following clock willbe generated; most flip-flops will operate on the rising edge of theclock allowing negative edge clocking to meet memory timing. TABLE 394Div5 target performance Parameter Conditions Min Typ Max Units Fmax Vdd= 1.5 V 100 MHz IDD 10 μA20.5 Power on Reset

This block combines the overL (omitted from the current version), underLand MAURstOutL signals to provide the global reset. MAURstOutL isdelayed by one clock cycle to ensure a reset generated when this signalis asserted has at least this duration since the reset deasserts thesignal itself. It should be noted that the register, with active lowreset RN, is the only one in the QA chip not connected to RstL.

[4] TSMC, Oct. 1, 2000, SFC0008_(—)08B9_HE, 8K×8 Embedded Flash MemorySpecification, Rev 0.1.

[5] TSMC (design service division), Sep. 10, 2001, 0.25 um EmbeddedFlash Test Mode User Guide, V0.3.

[6] TSMC (EmbFlash product marketing), Oct. 19, 2001, 0.25 umApplication Note, V2.2.

[7] Artisan Components, January 1999, Process Perfect Library Databook2.5-Volt Standard Cells, Rev1.0.

Other Applcations for Protocols and QA Chips

1 Introduction

In its preferred form, the QA chip [1] is a programmable 32 bitmicroprocessor with security features (8,000 gates, 3 k bits of RAM and8 kbytes of flash memory for program and non-volatile data storage). Itis manufactured in a 0.25 um CMOS process.

Physically, the chip is mounted in a 5 pin SOT23 plastic package andcommunicates with external circuitry via a two pin serial bus.

The QA chip was designed to for authenticating consumable usage andperformance upgrades in printers and associated hardware.

Because of its core functionality and programmability the QA chip canalso be used in applications that differ significantly from its originalone. This document seeks to identify some of those areas.

3 Applications Overview

Applications include:

-   -   Regular EEPROM    -   Secure EEPROM    -   General purpose MPU with security features    -   Security coprocessor for microprocessor system    -   Security coprocessor for PC (with optional USB connection)    -   Resource dispenser—secure, web based transfer of a variable        quantity from “source” to “sink”    -   IDtag    -   Security pass inside offices    -   Set top box security    -   Car key    -   Car Petrol    -   Car manufacturer “genuine parts” detection, where the car        requires genuine (or authorised) parts to function.    -   Aeroplane control on motor-control servos to allow secure        external control on an aircraft in a hijack situation.    -   Security device for controlling access to and copying of audio,        video, and data (eg, preventing unauthorized downloading of        music to a device).        4 Exemplary Application Descriptions        4.1 Car Petrol

Using mechanisms and protocols similar to those described in relation toink refills, refilling of petrol can be controlled. An example of acommercial relationship this allows is selling a car at a discountedrate, but requiring that the car be refilled at designated servicestations. Similarly, prevention of unauthorized servicing can beachieved.

4.2 Car Keys

4.2.1 Basic Advantages Over Physical Keys

-   -   Keys and locks can be easily programmed & configured for use    -   Can only be duplicated/reprogrammed by an authorised individual    -   The same key can be used for physical entry/exit and remote        (radio-based) entry/exit    -   Inbuilt security features        4.2.2 Single Key for Multiple Vehicles

Useful when a family has more than one car.

-   -   Can be programmed so any keys fits any car.    -   Fewer number of duplicate keys.    -   Misplacing a key for a particular car—any key for any other car        can be used as oppose to duplicate of the same key.        4.2.3 Multiple Keys for a Single Vehicle        4.2.3.1 Same Company Car Being Driven by Multiple Drivers    -   Mileage can be logged per driver e.g. for accounting purposes.    -   Key permissions can be different per driver (e.g. boot/trunk        access may be disabled)        4.2.3.2 Same Family Car Being Driven by Children and Parents    -   Time/date restrictions can be applied to (e.g. children's) keys    -   Speeds above a specified limit (and duration of that speed) can        be logged for auditing purposes (may be less dangerous than        actually enforcing a speed limit)        4.2.4 No Problem if Key Lost

Can easily:

-   -   make a new key the same as lost one (existing copies of key will        still function)    -   reprogram the locks on car (and reprogram all non-lost keys to        match) so the lost key will no longer function        4.2.5 No Problem if Key Left in Car    -   Easy to create a one-time-use open-door-only key via roadside        assistance based on secret password information, driver's        license etc (prevents having to break into the car)        4.2.6 Car Rentals    -   Key can have an expiration date (e.g. some period past the        rental end-date)        4.2.7 Single Physical Key for All Locks in Car

A single physical key can open all locks (door, immobiliser, boot/trunk,glovebox etc.).

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1. A printer controller for supplying dot data to a printhead in apredetermined order, the printhead comprising at least a first printheadmodule having a plurality of rows of printing nozzles, the printercontroller being configured to order and time the supply of the dot datato the first printhead module such that a relative skew between adjacentrows of printing nozzles on the at least one printhead module, in adirection normal to a direction of printing, is at least partiallycompensated for.
 2. A printer controller according to claim 1, whereinthe printer controller is configured to at least partially compensatefor the relative skew between adjacent rows in each of a plurality ofsets of the adjacent rows.
 3. A printer controller according to claim 1,wherein the relative skew between each of the plurality of the sets ofthe adjacent rows is the same.
 4. A printer controller according toclaim 1, wherein the printer controller is configured to compensate forthe skew by introducing a relative delay into the dot data destined forat least one of the rows of printing nozzles.
 5. A printer controlleraccording to claim 4, wherein the printhead is configured to print thedots at a predetermined spacing across its width, and wherein the delayintroduced by the printer controller equates to an integral multiple ofthe spacing.
 6. A printer controller according to claim 5, wherein theprinthead defines a printable region between printing boundaries, andwherein nozzles of at least one of the rows of at least one of the atleast one printhead modules are positioned outside the printable regiondue to the skew between adjacent rows of the nozzles on the at least oneprinthead module, the printer controller being configured to introduce arelative delay into the dot data supplied to at least one of the rowssuch that the nozzles outside the printable region do not print.
 7. Aprinter controller according to claim 1, wherein the at least oneprinthead module includes at least one pair of adjacent rows of thenozzles such that each row of the pair is configured to print the sameink, the printhead being configured to provide the dot data to the pairof adjacent rows such that the dot data is shifted serially through thefirst of the rows then through the second of the rows, until the dotdata has been supplied to all the nozzles.
 8. A printer controlleraccording to claim 7, the printhead being configured to provide the dotdata to the pair of adjacent rows such that the dot data is shiftedserially through the first of the rows in a first direction then loopedback through the second of the rows in a second direction opposite thefirst, until the dot data has been supplied to all the nozzles.
 9. Aprinter controller according to claim 7, wherein the printhead isconfigured to print a series of printhead-width rows of the dots, andwherein the first and second rows are configured to print odd and evendots, respectively, of the printhead-width rows, the printheadcontroller being configured to supply the one or more first rows withodd dot data and the one or more second rows with even dot data.
 10. Aprinter controller according to claim 7, including a plurality of thepairs of rows, the printer controller being configured to supply the dotdata such that any relative skew between the first and second rows ofeach pair of rows, in a direction normal to a direction of printing, isat least partially compensated for.
 11. A printer controller accordingto claim 1, wherein each printhead module is configured to print aplurality of independent inks, and wherein the nozzles in each row areconfigured to print in one of the inks, the printhead controller beingconfigured to supply each of the inks to at least one row of at leastone of the printhead modules.
 12. A printer controller according toclaim 1, wherein the printhead is a pagewidth printhead.
 13. A printercontroller according to claim 1, wherein the printhead comprises aplurality of the printhead modules.
 14. A printer controller accordingto claim 13, wherein at least some of the printhead modules are ofmutually unequal length, the printer controller being configured toorder and time the supply of the dot data to the compensate for theunequal length.
 15. A printer controller according to claim 13,configured to at least partially compensate for any relative skewbetween adjacent rows of the nozzles on adjacent ones of the printheadmodules.
 16. A printer controller according to claim 1, beingselectively configurable to compensate at least partially for aplurality of potential relative skews.
 17. A printer controlleraccording to claim 1, being configured to compensate at least partly fora fixed amount of the skew.
 18. A printer engine comprising the printerengine controller and the printhead according to claim 5, wherein thenozzles of the printhead are disposed in a printable region betweenprinting boundaries of the printhead, and the printhead includes atleast one logical nozzle located outside the printable zone that canaccept data but is not capable of printing, the logical nozzles beingarranged to introduce a relative delay into the dot data supplied to atleast one of the rows, such that dot data is supplied to the correctnozzles for printing.